High-reliability symmetric charge pump

Abstract

The invention relates to a high-reliability symmetric charge pump circuit. According to the high-reliability symmetric charge pump circuit, two CTS charge pump branches are connected in parallel to form a charge pump of a symmetric structure, the two parallel charge pump circuits have the same parameters, and the clock phase of the first CTS charge pump branch is opposite to the clock phase of the second CTS charge pump branch. When the charge pump circuit works in a steady state, the bias voltages of all transistors in the circuit do not exceed VDD, the maximum bias voltage of the transistors is reduced by half, the problem that the bias voltage of the charge pump circuit is too large is solved, and the reliability of the circuit is improved.

Description

Technical Field

[0001] The present application relates to the technical field of charge pumps, and in particular to a highly reliable symmetrical charge pump. Background Art

[0002] In non-volatile memory, charge pump circuits are often used to provide the high voltage required for programming and erasing storage cells. Due to the influence of high voltage, the bias voltage of the transistor unit in the charge pump circuit is too large, and there is a risk of breakdown. Considering the reliability of the charge pump circuit, the circuit needs to be reinforced.

[0003] Figure 1 For the CTS charge pump circuit, Figure 2 The figure shows the phase relationship of the CTS charge pump input clock and the voltage of its main nodes when the circuit is working stably. The charge pump input voltage is VDD, the input clock high level is VDD, and the low level is 0. When the CTS charge pump circuit is working stably, the transistor bias voltage can reach twice the power supply voltage. If the bias voltage of the transistor is too large, it is very easy to break down, resulting in circuit failure. Summary of the invention

[0004] Based on this, it is necessary to provide a highly reliable symmetrical charge pump with advantages such as high reliability and low ripple voltage in order to solve the above technical problems.

[0005] A highly reliable symmetrical charge pump circuit comprises: two CTS charge pump branches connected in parallel, the parameters of the two CTS charge pump branches are the same, and the clock of the first CTS charge pump branch is in opposite phase to the clock of the second CTS charge pump branch.

[0006] In one embodiment, the first CTS charge pump branch includes an NMOS transistor N3, an NMOS transistor N1, a PMOS transistor P1, a PMOS transistor P3 and a capacitor C1.

[0007] The second CTS charge pump branch includes an NMOS transistor N4, an NMOS transistor N2, a PMOS transistor P2, a PMOS transistor P4 and a capacitor C2.

[0008] One end of the capacitor C1 receives the clock CLK, the gate of the NMOS tube N3, the gate of the PMOS tube P1, and the drain of the NMOS tube N1 are all connected to the other end of the capacitor C1, the drain of the NMOS tube N3 and the drain of the PMOS tube P1 are all connected to the gate of the NMOS tube N1, the source of the NMOS tube N1 and the source of the NMOS tube N3 are all connected to the signal input end, the drain of the PMOS tube P3 is connected to the drain of the NMOS tube N1; the drain of the PMOS tube P3 is connected to the gate of the PMOS tube P4, the drain of the PMOS tube P4 is connected to the gate of the PMOS tube P3, and the sources of the PMOS tubes P1, PMOS tubes P2, PMOS tubes P3, and PMOS tubes P4 are all connected to the signal output end.

[0009] One end of the capacitor C2 receives the inverted clock CLKB of the clock CLK, the gate of the NMOS tube N4, the gate of the PMOS tube P2, and the drain of the NMOS tube N2 are all connected to the other end of the capacitor C2, the drain of the NMOS tube N4 and the drain of the PMOS tube P2 are all connected to the gate of the NMOS tube N2, and the source of the NMOS tube N2 and the source of the NMOS tube N4 are all connected to the signal input end.

[0010] A cascaded symmetrical charge pump circuit comprises a plurality of the above-mentioned high-reliability symmetrical charge pump circuits, wherein the input end of the first-stage symmetrical charge pump circuit receives an input signal, the output of the first-stage symmetrical charge pump circuit serves as the input of the second-stage symmetrical charge pump circuit, the output of the second-stage symmetrical charge pump circuit serves as the input of the third-stage symmetrical charge pump circuit, and so on, the signal output end of the last-stage symmetrical charge pump circuit serves as the output end of the cascade circuit, the output end of the cascade circuit is connected to one end of a capacitor CL, and the other end of the capacitor CL is grounded; the first CTS charge pump branch of each symmetrical charge pump circuit uses the same clock signal CLK, and the second CTS charge pump branch uses the same clock signal CLKB, wherein the clock signal CLKB is in opposite phase to the clock signal CLK.

[0011] The above-mentioned highly reliable symmetrical charge pump, the highly reliable symmetrical charge pump circuit uses two CTS charge pump branches in parallel to form a charge pump with a symmetrical structure, the two parallel charge pump circuits have the same parameters, and the clock of the first CTS charge pump branch is in opposite phase to the clock of the second CTS charge pump branch. When working in steady state, the bias voltage of all transistors in the circuit will not exceed VDD, and the maximum bias voltage of the transistor is reduced by half, which solves the problem of excessive bias voltage of the charge pump circuit and improves the reliability of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 This is the schematic diagram of the CTS charge pump circuit; Figure 2 Schematic diagram of the CTS charge pump input clock phase relationship and key node voltage changes; Figure 3 A schematic diagram of a symmetrical charge pump circuit in one embodiment; Figure 4 A schematic diagram of the charge pump input clock phase relationship and voltage changes at key nodes in another embodiment; Figure 5 A cascaded symmetrical charge pump circuit in one embodiment. DETAILED DESCRIPTION

[0013] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0014] In one embodiment, Figure 3 As shown, a highly reliable symmetrical charge pump circuit is provided, which includes: two CTS charge pump branches connected in parallel, the parameters of the two CTS charge pump branches are the same, and the clock of the first CTS charge pump branch is in opposite phase to the clock of the second CTS charge pump branch.

[0015] Specifically, the charge pump circuit uses two CTS charge pump branches connected in parallel to form a symmetrical structure. The two parallel charge pump circuits have the same parameters, and the clock of the first CTS charge pump branch is in opposite phase to the clock of the second CTS charge pump branch. Figure 3 The PMOS tubes P3 and P4, PMOS tube P1 and NMOS tube N3, PMOS tube P2 and NMOS tube N4 respectively constitute a dynamic bias circuit, wherein the PMOS tubes P3 and P4 always select the higher voltage output of node 3 and node 4. By eliminating the voltage change of the key node, the bias voltage of each transistor will not exceed VDD, and the bias voltage of the transistor in the charge pump circuit is reduced, thereby improving the anti-shooting capability.

[0016] In the above-mentioned high-reliability symmetrical charge pump circuit, the high-reliability symmetrical charge pump circuit uses two CTS charge pump branches in parallel to form a charge pump with a symmetrical structure. The parameters of the two parallel charge pump circuits are the same, and the clock of the first CTS charge pump branch is opposite to the clock of the second CTS charge pump branch. When working in a steady state, the bias voltage of all transistors in the circuit will not exceed VDD, and the maximum bias voltage of the transistor is reduced by half, which solves the problem of excessive bias voltage of the charge pump circuit and improves the reliability of the circuit.

[0017] In one embodiment, the first CTS charge pump branch includes an NMOS transistor N3, an NMOS transistor N1, a PMOS transistor P1, a PMOS transistor P3 and a capacitor C1.

[0018] The second CTS charge pump branch includes an NMOS transistor N4, an NMOS transistor N2, a PMOS transistor P2, a PMOS transistor P4 and a capacitor C2.

[0019] One end of the capacitor C1 receives the clock CLK, the gate of the NMOS tube N3, the gate of the PMOS tube P1, and the drain of the NMOS tube N1 are all connected to the other end of the capacitor C1, the drain of the NMOS tube N3 and the drain of the PMOS tube P1 are all connected to the gate of the NMOS tube N1, the source of the NMOS tube N1 and the source of the NMOS tube N3 are all connected to the signal input end, the drain of the PMOS tube P3 is connected to the drain of the NMOS tube N1; the drain of the PMOS tube P3 is connected to the gate of the PMOS tube P4, the drain of the PMOS tube P4 is connected to the gate of the PMOS tube P3, and the sources of the PMOS tubes P1, PMOS tubes P2, PMOS tubes P3, and PMOS tubes P4 are all connected to the signal output end.

[0020] One end of the capacitor C2 receives the inverted clock CLKB of the clock CLK, the gate of the NMOS tube N4, the gate of the PMOS tube P2, and the drain of the NMOS tube N2 are all connected to the other end of the capacitor C2, the drain of the NMOS tube N4 and the drain of the PMOS tube P2 are all connected to the gate of the NMOS tube N2, and the source of the NMOS tube N2 and the source of the NMOS tube N4 are all connected to the signal input end.

[0021] Specific, high reliability symmetrical charge pump circuit such as Figure 3 As shown, the input node 5 is a signal input terminal, and its voltage is an input voltage; the output node 6 is a signal output terminal, and the voltage of the output node 6 is an output voltage.

[0022] In a circuit in which multiple high-reliability symmetrical charge pump circuits are cascaded, corresponding to the Nth stage of high-reliability symmetrical charge pump circuit, the voltage of input node 5 is the output voltage of the N-1th stage, and the voltage of output node 6 is the input voltage of the N+1th stage.

[0023] In the Nth level high-reliability symmetrical charge pump circuit, PMOS tubes P3 and P4, PMOS tube P1 and NMOS tube N3, PMOS tube P2 and NMOS tube N4 respectively form a dynamic bias circuit. Among them, PMOS tubes P3 and P4 always select the higher voltage output of node 3 and node 4. By eliminating the voltage change of the key node, the bias voltage of each transistor will not exceed VDD, solving the problem of excessive bias voltage of the charge pump circuit. The specific analysis is as follows: PMOS transistors P3 and P4 always select the higher voltage output of node 3 and node 4. When the voltage of node 3 is greater than the voltage of node 4, PMOS transistor P3 is turned on, PMOS transistor P4 is turned off, and the voltage of node 3 is transmitted to output node 6. When the voltage of node 4 is greater than the voltage of node 3, PMOS transistor P4 is turned on, PMOS transistor P3 is turned off, and the voltage of node 4 is transmitted to node 6.

[0024] When the charge pump is working in a stable state, in any time period, in a highly reliable symmetrical charge pump circuit, the voltage phases of nodes 1 and 3 are opposite to those of nodes 2 and 4. The voltage of input node 5 is NVDD, and the voltage of output node 6 is equal to the higher voltage of node 3 and node 4, that is, (N+1)VDD.

[0025] When CLK changes from 0 to 1 and CLKB changes from 1 to 0, the voltage at node 3 changes from NVDD to (N+1)VDD, N3 is turned on, PMOS tube P1 is turned off, and the voltage at input node 5 is transmitted to node 1, that is, the voltage at node 1 is NVDD and N1 is turned off.

[0026] The voltage at node 4 changes from (N+1)VDD to NVDD, the PMOS tube P2 is turned on, the NMOS tube N4 is turned off, and the voltage at the output node 6 is transmitted to node 2, that is, the voltage at node 2 is (N+1)VDD, the NMOS tube N2 is turned on, and the voltage at the input node 5 is transmitted to node 4.

[0027] The voltage of node 3 is (N+1)VDD, the voltage of node 4 is NVDD, PMOS tube P3 is turned on, PMOS tube P4 is turned off, and the voltage of node 3 is transmitted to output node 6, that is, the voltage of output node 6 is (N+1)VDD.

[0028] When the clock CLK changes from 1 to 0 and the clock CLKB changes from 0 to 1, the voltage of node 4 changes from NVDD to (N+1)VDD, the NMOS tube N4 is turned on, the PMOS tube P2 is turned off, and the voltage of the input node 5 is transmitted to the node 2, that is, the voltage of the node 2 is NVDD, and the NMOS tube N2 is turned off.

[0029] The voltage at node 3 changes from (N+1)VDD to NVDD, the PMOS tube P1 is turned on, the NMOS tube N3 is turned off, and the voltage at the output node 6 is transmitted to node 1, that is, the voltage at node 1 is (N+1)VDD, the NMOS tube N1 is turned on, and the voltage at the input node 5 is transmitted to node 3.

[0030] The voltage of node 4 is (N+1)VDD, the voltage of node 3 is NVDD, PMOS tube P4 is turned on, PMOS tube P3 is turned off, and the voltage of node 4 is transmitted to output node 6, that is, the voltage of output node 6 is (N+1)VDD.

[0031] The phase relationship of the charge pump input clock and the voltage changes of key nodes are shown in the figure. Figure 4 shown.

[0032] In summary, when the charge pump circuit is working in steady state, the bias voltage of all transistors is less than or equal to |VDD|. By reducing the bias voltage of the MOS tube in the circuit, the reliability of the charge pump circuit is improved, the anti-breakdown capability of the transistor is enhanced, and it has the advantages of low ripple voltage, etc.

[0033] It is worth noting that the performance parameters of NMOS tube N3 and NMOS tube N4 are the same, the performance parameters of NMOS tube N1 and NMOS tube N2 are the same, the performance parameters of PMOS tube P1 and PMOS tube P2 are the same, the performance parameters of PMOS tube P3 and PMOS tube P4 are the same, and the performance parameters of capacitor C1 and capacitor C2 are the same.

[0034] In one embodiment, Figure 5 As shown, a cascaded symmetrical charge pump circuit is provided, which includes a plurality of the above-mentioned high-reliability symmetrical charge pump circuits, the input end of the first-stage symmetrical charge pump circuit receives an input signal, the output of the first-stage symmetrical charge pump circuit serves as the input of the second-stage symmetrical charge pump circuit, the output of the second-stage symmetrical charge pump circuit serves as the input of the third-stage symmetrical charge pump circuit, and so on, the signal output end of the last-stage symmetrical charge pump circuit serves as the output end of the cascade circuit, the output end of the cascade circuit is connected to one end of a capacitor CL, and the other end of the capacitor CL is grounded; the first CTS charge pump branch of each symmetrical charge pump circuit uses the same clock signal CLK, and the second CTS charge pump branch uses the same clock signal CLKB, wherein the clock signal CLKB is in opposite phase to the clock signal CLK.

[0035] Specifically, the input voltage of the first-stage symmetrical charge pump circuit is VDD, the high level of the input clock is VDD, and the low level is 0.

[0036] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0037] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A highly reliable symmetrical charge pump circuit, characterized in that: The symmetrical charge pump circuit comprises: two CTS charge pump branches connected in parallel, the parameters of the two CTS charge pump branches are the same, and the clock of the first CTS charge pump branch is in opposite phase to the clock of the second CTS charge pump branch.

2. The high-reliability symmetrical charge pump circuit according to claim 1, characterized in that: The first CTS charge pump branch includes an NMOS transistor N3, an NMOS transistor N1, a PMOS transistor P1, a PMOS transistor P3 and a capacitor C1; The second CTS charge pump branch includes an NMOS transistor N4, an NMOS transistor N2, a PMOS transistor P2, a PMOS transistor P4 and a capacitor C2; One end of the capacitor C1 receives the clock CLK, the gate of the NMOS tube N3, the gate of the PMOS tube P1, and the drain of the NMOS tube N1 are all connected to the other end of the capacitor C1, the drain of the NMOS tube N3 and the drain of the PMOS tube P1 are all connected to the gate of the NMOS tube N1, the source of the NMOS tube N1 and the source of the NMOS tube N3 are all connected to the signal input end, the drain of the PMOS tube P3 is connected to the drain of the NMOS tube N1; the drain of the PMOS tube P3 is connected to the gate of the PMOS tube P4, the drain of the PMOS tube P4 is connected to the gate of the PMOS tube P3, and the sources of the PMOS tubes P1, PMOS tubes P2, PMOS tubes P3, and PMOS tubes P4 are all connected to the signal output end; One end of the capacitor C2 receives the inverted clock CLKB of the clock CLK, the gate of the NMOS tube N4, the gate of the PMOS tube P2, and the drain of the NMOS tube N2 are all connected to the other end of the capacitor C2, the drain of the NMOS tube N4 and the drain of the PMOS tube P2 are all connected to the gate of the NMOS tube N2, and the source of the NMOS tube N2 and the source of the NMOS tube N4 are all connected to the signal input end.

3. A cascaded symmetrical charge pump circuit, characterized in that: The cascaded symmetrical charge pump circuit includes several high-reliability symmetrical charge pump circuits according to claim 1, the input end of the first-stage symmetrical charge pump circuit receives an input signal, the output of the first-stage symmetrical charge pump circuit serves as the input of the second-stage symmetrical charge pump circuit, the output of the second-stage symmetrical charge pump circuit serves as the input of the third-stage symmetrical charge pump circuit, and so on, the signal output end of the last-stage symmetrical charge pump circuit serves as the output end of the cascade circuit, the output end of the cascade circuit is connected to one end of the capacitor CL, and the other end of the capacitor CL is grounded; the first CTS charge pump branch of each symmetrical charge pump circuit uses the same clock signal CLK, and the second CTS charge pump branch uses the same clock signal CLKB, wherein the clock signal CLKB is in opposite phase to the clock signal CLK.

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