Digital isolator based on charge detection and implementation method thereof

Abstract

The embodiment of the invention provides a digital isolator based on charge detection and an implementation method of the digital isolator based on charge detection, high-voltage capacitors with two channels independent of each other are adopted for isolation, rising edge oscillation signals and falling edge oscillation signals are transmitted respectively, and no matching requirement exists relative to a differential channel; the signal encoding side and the signal decoding side are both matched with mutually independent dual-channel charge detection circuits, the encoding side charge detection unit is used for controlling the voltage-controlled oscillation unit to work through charge detection, detecting continuous first preset number of pulses to turn over high level and terminating the work of the voltage-controlled oscillation unit, otherwise, the pulse is low level; and the decoding side charge detection unit is used for detecting continuous pulses with a second preset number and generating a setting / resetting signal for the RS trigger to recover the original signal. According to the mode, the influence of interference signals on the oscillation signal frequency is avoided, and the correctness and reliability of signal demodulation are greatly improved.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of isolators, and in particular to a digital isolator based on charge detection and an implementation method thereof. Background Art

[0002] Isolation technology is to completely isolate two independent systems in terms of electrical performance to prevent electrical energy leakage from causing circuit damage or safety accidents. Therefore, isolation chips with isolation technology are widely used in industrial automation control, motor drive, isolation bus, photovoltaic inverter, hybrid electric vehicle, etc.

[0003] According to the different isolation media, digital isolators can be divided into optocoupler isolators, magnetic isolators and capacitive isolators. The advantages of optocoupler isolators are simple structure and low cost, while the disadvantages are easy aging of the device, high transmission delay, slow speed, nonlinearity, etc., and they can only be used in occasions where isolation requirements are not high. With the development of integrated circuits, silicon-based technology has developed rapidly due to its high compatibility with CMOS processes. Isolation products represented by magnetic isolators and capacitive isolators have won wide attention. They are superior to optocoupler isolators in small size, high speed, low power consumption and great performance, and gradually occupy the market. Magnetic isolators are mainly highly integrated on-chip transformers that can transmit signals and power at the same time, but they have a large area and weak resistance to magnetic field interference. They are limited in applications that pursue small areas and low costs, and most of the isolator chip application environments have very harsh conditions such as strong magnetic fields, high surges, and large noise. Capacitive isolators use high-voltage capacitors to isolate small areas and have strong resistance to magnetic field interference, which meets application requirements, but cannot transmit signal power. Signal and noise transmission interference in the same channel is large, so solving signal errors caused by noise interference has attracted much attention.

[0004] The existing signal modulation schemes for capacitive isolation transmission mainly include pulse signal modulation schemes based on iCoupler technology, modulation schemes based on ordinary OOK technology (such as: high-speed capacitive isolation OOK signal modulation and demodulation circuits), and modulation schemes based on the combination of pulse signals and OOK technology (such as a digital isolator circuit based on Efficient-OOK).

[0005] like Figure 1 As shown in the figure, for the pulse signal modulation scheme based on iCoupler technology, the rising edge and the falling edge are modulated into single and double pulses respectively for distinguished transmission. The decoding circuit distinguishes the rising edge and the falling edge according to the number of single and double pulses. This method has low power consumption and low cost per channel. However, the single-channel transmission has poor noise suppression capability and is easily interfered with to form bit errors. Although the refresh circuit can be used to refresh the signal in real time to prevent bit errors, interference within the refresh time may also occur and cannot be completely avoided. In addition, the refresh circuit greatly increases the complexity of the circuit.

[0006] For the technical solution of OOK differential transmission, the "high-speed capacitor-isolated OOK signal modulation and demodulation circuit" uses a ring oscillation signal encoding method on the signal encoding side, and uses a fully differential frequency-selective amplifier circuit with a full-wave detector to detect the oscillation signal envelope to achieve signal decoding in the decoding solution. However, due to the use of differential capacitor transmission, the use of a bandpass amplifier structure and the sensitivity to signal frequency, frequency drift is prone to bit errors, and the fully differential signal modulation and demodulation method has extremely high requirements for circuit matching, and it is easy to amplify common-mode interference as a differential-mode signal, resulting in bit errors. Figure 2 As shown, the traditional OOK technology modulates the high level of the square wave control signal into an oscillating signal, and does not modulate the low level, and generates high and low levels according to the presence or absence of an oscillating signal. This technology has no effect when the interference signal appears in the oscillating signal, but will cause bit errors in the decoded signal when it appears during the low level period. The power consumption is high due to continuous oscillation during the high level period.

[0007] like Figure 3 As shown in the figure, “A digital isolator circuit based on Efficient-OOK” uses a combination of pulses and OOK to achieve signal modulation. Oscillators are set on both the encoding side and the decoding side, which increases the power consumption of the circuit. Although the transmission mode has been improved, edge recognition is first performed, and then the rising edge and falling edge are modulated into six pulses and four pulses respectively through the oscillation circuit. Then, a full-wave detector, a timer and an oscillator of the same frequency are matched on the decoding side. The rising edge and falling edge are identified based on the pulse width corresponding to the five pulses, thereby decoding the signal. However, the oscillators on both sides are always in working state, and the power consumption is still very high. Although dual-channel transmission is adopted, it is not differential transmission, so the common-mode noise interference cannot be shielded. If the noise appears near the four pulses representing the rising edge or the six pulses representing the falling edge, it will cause bit errors. Summary of the invention

[0008] To this end, an embodiment of the present invention provides a digital isolator based on charge detection and an implementation method thereof, so as to solve the technical problems that interference cannot be completely avoided and bit errors are easily formed in the current signal modulation of capacitive isolation transmission.

[0009] In order to achieve the above purpose, the embodiment of the present invention provides the following technical solutions:

[0010] According to a first aspect of an embodiment of the present invention, an embodiment of the present application provides a digital isolator based on charge detection, the digital isolator comprising:

[0011] A signal encoding module, used for receiving the encoding side square wave control signal and encoding it into a double-edge oscillation signal;

[0012] Dual isolation channels, used to transmit the double-edge oscillation signal to the decoding side;

[0013] A signal decoding module is used to receive dual isolation channel signals and decode them into original signals to obtain a decoding side square wave control signal;

[0014] The signal encoding module includes: an edge detection unit, a voltage-controlled oscillation unit, and a coding side charge detection unit; the edge detection unit is used to extract the first rising edge information and the first falling edge information of the coding side square wave control signal; the voltage-controlled oscillation unit is used to encode the first rising edge information and the first falling edge information into a rising edge oscillation signal and a falling edge oscillation signal respectively; the coding side charge detection unit is used to detect whether the number of continuous pulses of the rising edge oscillation signal and the falling edge oscillation signal is greater than a first preset number; when the number of continuous pulses of the rising edge oscillation signal is greater than the first preset number, the voltage-controlled oscillation unit is controlled to output the rising edge oscillation signal to the outside; when the number of continuous pulses of the falling edge oscillation signal is greater than the first preset number, the voltage-controlled oscillation unit is controlled to output the falling edge oscillation signal to the outside.

[0015] Furthermore, the signal encoding module further includes: a signal shaping unit, which is used to receive the encoding side square wave control signal, shape the encoding side square wave control signal and filter out interference signals.

[0016] Furthermore, the edge detection unit comprises:

[0017] A rising edge detection part, used for detecting the first rising edge information of the encoding side square wave control signal and generating a first single pulse signal; the first single pulse signal is input to the CLK input terminal of the first D flip-flop through the first input terminal of the first OR gate circuit, the Q output terminal of the first D flip-flop is connected to the D input terminal, the Q output terminal of the first D flip-flop is connected to the first input terminal of the voltage-controlled oscillation unit, and the R access terminal of the first D flip-flop is used for power-on reset;

[0018] A falling edge detection part, used for detecting the first falling edge information of the encoding side square wave control signal and generating a second single pulse signal; the second single pulse signal is input to the CLK input terminal of the second D flip-flop through the first input terminal of the second OR gate circuit, the Q output terminal of the second D flip-flop is connected to the D input terminal, the Q output terminal of the second D flip-flop is connected to the second input terminal of the voltage-controlled oscillation unit, and the R access terminal of the second D flip-flop is used for power-on reset;

[0019] The voltage-controlled oscillation unit is provided with a first output end corresponding to the first input end, a second output end corresponding to the second input end, and a third output end, the third output end is connected to the charge detection input end of the coding side charge detection unit, and the charge detection output end of the coding side charge detection unit is connected to the second input ends of the first OR gate circuit OR1 and the second OR gate circuit OR2.

[0020] Furthermore, the signal encoding module also includes a first high-pass filtering unit and a second high-pass filtering unit, the first high-pass filtering unit includes: a first capacitor C1 and a first resistor R1, the second high-pass filtering unit includes: a second capacitor C2 and a second resistor R2, the voltage-controlled oscillation unit is respectively connected to one end of the first capacitor C1 and the second capacitor C2 through a first output end and a second output end, the other ends of the first capacitor C1 and the second capacitor C2 respectively form the output ends of the first high-pass filtering unit and the second high-pass filtering unit, one end of the first resistor R1 and the second resistor R2 are respectively connected to the other end of the first capacitor C1 and the second capacitor C2, and the other ends of the first resistor R1 and the second resistor R2 are grounded.

[0021] Furthermore, the dual isolation channel includes: a first high-voltage isolation capacitor HC1, a second high-voltage isolation capacitor HC2, a third high-voltage isolation capacitor HC3 and a fourth high-voltage isolation capacitor HC4, the first high-voltage isolation capacitor HC1 and the third high-voltage isolation capacitor HC3 are connected in series to form a first isolation channel, the second high-voltage isolation capacitor HC2 and the fourth high-voltage isolation capacitor HC4 are connected in series to form a second isolation channel, the first high-voltage isolation capacitor HC1 and the third high-voltage isolation capacitor HC3 respectively form an input end and an output end of the first isolation channel to the outside, the second high-voltage isolation capacitor HC2 and the fourth high-voltage isolation capacitor HC4 respectively form an input end and an output end of the second isolation channel to the outside, the input end of the first isolation channel is connected to the output end of the first high-pass filtering unit, and the input end of the second isolation channel is connected to the output end of the second high-pass filtering unit.

[0022] Further, the signal decoding module includes: a first interface amplification unit, a second interface amplification unit, a first decoding side charge detection unit, a second decoding side charge detection unit, and an RS trigger; the output end of the first isolation channel is connected to the R input end of the RS trigger via the first interface amplification unit and the first decoding side charge detection unit in sequence, the output end of the second isolation channel is connected to the S input end of the RS trigger via the second interface amplification unit and the second decoding side charge detection unit in sequence, and the Q output end of the RS trigger forms the output end of the signal decoding module externally;

[0023] The rising edge oscillation signal in the dual isolation channel signal is input into the first decoding side charge detection unit via the first interface amplification unit, and the first decoding side charge detection unit is used to detect whether the number of continuous pulses of the rising edge oscillation signal is greater than the second preset number; when the number of continuous pulses of the rising edge oscillation signal is greater than the second preset number, the second rising edge information is input into the RS trigger through the R input terminal;

[0024] The falling edge oscillation signal in the dual isolation channel signal is input into the second decoding side charge detection unit via the second interface amplification unit, and the second decoding side charge detection unit is used to detect whether the number of continuous pulses of the falling edge oscillation signal is greater than the second preset number; when the number of continuous pulses of the falling edge oscillation signal is greater than the second preset number, the second falling edge information is input into the RS trigger through the S input terminal;

[0025] The RS trigger is used to obtain a decoding side square wave control signal based on the received second rising edge information and the received second falling edge information.

[0026] Furthermore, the first preset number and the second preset number are both 4.

[0027] Further, the first interface amplifying unit and the second interface amplifying unit both include: a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6 and a first Schmitt trigger SMT1, one end of the fifth resistor R5 and the sixth resistor R6 are grounded, one end of the third resistor R3 is connected in series with the other end of the fifth resistor R5, one end of the fourth resistor R4 is connected in series with the sixth resistor R6, and one end of the fifth resistor R5 is connected in series with the other end of the fifth resistor R6. 6, the other end of the third resistor R3 and the other end of the fourth resistor R4 are connected together, the sources of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are connected together and grounded, the gate of the first NMOS transistor MN1 is connected to the gate of the fourth NMOS transistor MN4, the gate of the second NMOS transistor MN2 is connected to a first connection point between the third resistor R3 and the fifth resistor R5, the first connection point externally forms a decoding side oscillation signal receiving end, the gate of the third NMOS transistor MN3 is connected to a second connection point between the fourth resistor R4 and the sixth resistor R6, the first PMOS The sources of the S transistor MP1, the second PMOS transistor MP2, the third PMOS transistor MP3, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, and the sixth PMOS transistor MP6 are connected to the other ends of the third resistor R3 and the fourth resistor R4, the drain of the first PMOS transistor MP1 is connected to the drain of the first NMOS transistor MN1, the gate of the first PMOS transistor MP1 is connected to the gate of the second PMOS transistor MP2, the drains of the second PMOS transistor MP2 and the third PMOS transistor MP3 are connected to the drain of the second NMOS transistor MN2 to form a first intersection, and the first intersection is connected to the gate of the first PMOS transistor MP1 and the gate of the first NMOS transistor MN1. The drains of the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are connected to the drain of the third NMOS tube MN3 and form a second intersection point, the gate of the fifth PMOS tube MP5 is connected to the gate of the sixth PMOS tube MP6, the second intersection point is connected to a fourth connection point between the gate of the fifth PMOS tube MP5 and the gate of the sixth PMOS tube MP6, the gate of the third PMOS tube MP3 is connected to the second intersection point, the gate of the fourth PMOS tube MP4 is connected to the first intersection point, and the drain of the sixth PMOS tube MP6 is connected to the drain of the fourth NMOS tube MN4.The input end of the first Schmitt trigger SMT1 is connected to a fifth connection point between the drain of the sixth PMOS transistor MP6 and the drain of the fourth NMOS transistor MN4.

[0028] Further, the encoding side charge detection unit, the first decoding side charge detection unit, and the second decoding side charge detection unit all include: a first inverter Inv1, a second inverter Inv2, a third inverter Inv3, a third D flip-flop Dff3, a fourth D flip-flop Dff4, a first transmission gate TG1, a second transmission gate TG2, a buffer Buffer, a seventh resistor R7, a third capacitor C3, a seventh PMOS tube MP7, and a second Schmitt trigger SMT2, wherein the input end of the first inverter Inv1 forms a charge detection input end externally, and the first inverter Inv1 and the second inverter Inv2 are connected in series, the output terminals of the first inverter Inv1 and the second inverter Inv2 are respectively connected to the CLK input terminals of the fourth D flip-flop Dff4 and the third D flip-flop Dff3, the D input terminal of the third D flip-flop Dff3 is connected to the first power supply, the D input terminal of the fourth D flip-flop Dff4 is grounded, the Q output terminals of the third D flip-flop Dff3 and the fourth D flip-flop Dff4 are respectively connected to the input terminals of the first transmission gate TG1 and the second transmission gate TG2, the first transmission gate TG1 and The output end of the second transmission gate TG2 is connected to the input end of the buffer Buffer, the second control end of the first transmission gate TG1 is connected to the first control end of the second transmission gate TG2, the second control end of the second transmission gate TG2 is connected to the first control end of the first transmission gate TG1, the output end of the first inverter Inv1 is connected to the first control end of the second transmission gate TG2, the output end of the second inverter Inv2 is connected to the first control end of the first transmission gate TG1, the output end of the buffer Buffer is connected to the gate of the seventh PMOS tube MP7 through the third inverter Inv3, the source of the seventh PMOS tube MP7 is connected to the second power supply, the drain of the seventh PMOS tube MP7 is grounded through the third capacitor C3, the output end of the buffer Buffer is connected to the ground end of the third capacitor C3 through the seventh resistor R7, the input end of the second Schmitt trigger SMT2 is connected to the sixth connection point between the drain of the seventh PMOS tube MP7 and the third capacitor C3, and the output end of the second Schmitt trigger SMT2 forms a charge detection output end to the outside.

[0029] According to a second aspect of an embodiment of the present invention, an embodiment of the present application provides a method for implementing a digital isolator based on charge detection, the method comprising:

[0030] The signal encoding module receives the encoding side square wave control signal and encodes it into a double-edge oscillation signal;

[0031] The double-edge oscillation signal is transmitted to the decoding side through a dual isolation channel;

[0032] The signal decoding module receives the dual isolation channel signals and decodes them into original signals to obtain a decoding side square wave control signal;

[0033] The signal encoding module includes: an edge detection unit, a voltage-controlled oscillation unit, and a coding side charge detection unit; the edge detection unit is used to extract the first rising edge information and the first falling edge information of the coding side square wave control signal; the voltage-controlled oscillation unit is used to encode the first rising edge information and the first falling edge information into a rising edge oscillation signal and a falling edge oscillation signal respectively; the coding side charge detection unit is used to detect whether the number of continuous pulses of the rising edge oscillation signal and the falling edge oscillation signal is greater than a first preset number; when the number of continuous pulses of the rising edge oscillation signal is greater than the first preset number, the voltage-controlled oscillation unit is controlled to output the rising edge oscillation signal to the outside; when the number of continuous pulses of the falling edge oscillation signal is greater than the first preset number, the voltage-controlled oscillation unit is controlled to output the falling edge oscillation signal to the outside.

[0034] Compared with the prior art, the embodiment of the present application provides a digital isolator based on charge detection and its implementation method, which adopts dual-channel independent high-voltage capacitor isolation to transmit rising edge oscillation signals and falling edge oscillation signals respectively, and has no matching requirements relative to differential channels; the signal encoding side and the signal decoding side are equipped with independent dual-channel charge detection circuits, and the charge detection unit on the encoding side is used to control the operation of the voltage-controlled oscillation unit through charge detection, and detects a continuous first preset number of pulses to flip the high level and terminate the operation of the voltage-controlled oscillation unit, otherwise it is a low level; the charge detection unit on the decoding side is used to detect a continuous second preset number of pulses and generate a set / reset signal for the RS trigger to restore the original signal. This method ignores the influence of interference signals on the frequency of the oscillation signal, greatly improves the accuracy and reliability of signal demodulation, and has greatly reduced power consumption compared to the existing OOK modulation technology, and the signal propagation delay and distortion are small, which can complete low-delay, low-distortion, low-power consumption, and high-speed transmission of signals. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the implementation methods of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for the implementation methods or the description of the prior art. Obviously, the drawings in the following description are only exemplary, and for ordinary technicians in this field, other implementation drawings can be derived from the provided drawings without creative work.

[0036] The structures, proportions, sizes, etc. illustrated in this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with the technology. They are not used to limit the conditions under which the present invention can be implemented, and therefore have no substantial technical significance. Any structural modification, change in proportion or adjustment of size shall still fall within the scope of the technical contents disclosed in the present invention without affecting the effects and purposes that can be achieved by the present invention.

[0037] Figure 1 A signal waveform diagram based on pulse coding technology and interference provided by an embodiment of the present invention;

[0038] Figure 2 The signal waveform diagram of the traditional OOK modulation and demodulation technology and interference provided by the embodiment of the present invention;

[0039] Figure 3 A signal waveform diagram of a signal modulation and demodulation using a combination of pulse and OOK provided in an embodiment of the present invention;

[0040] Figure 4 A schematic diagram of a circuit module structure of a digital isolator based on charge detection provided by an embodiment of the present invention;

[0041] Figure 5 A schematic diagram of the circuit principle for implementing the rising edge encoding technology of the encoding side square wave control signal provided by an embodiment of the present invention;

[0042] Figure 6 A schematic diagram of the circuit principle for implementing the falling edge encoding technology of the encoding side square wave control signal provided by an embodiment of the present invention;

[0043] Figure 7 A circuit diagram of a first interface amplifying unit and a second interface amplifying unit provided in an embodiment of the present invention;

[0044] Figure 8 A circuit diagram of a coding side charge detection unit, a first decoding side charge detection unit, and a second decoding side charge detection unit provided in an embodiment of the present invention;

[0045] Fig. 9 A signal transmission waveform diagram in a method for implementing a digital isolator based on charge detection provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0046] The following is a description of the implementation of the present invention by specific embodiments. People familiar with the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0047] The signal modulation technologies for capacitive isolation transmission mainly include ordinary OOK modulation and pulse signal modulation technology. Among them, the transmission method based on OOK modulation has higher reliability and does not require the refresh circuit in pulse signal modulation to ensure the accuracy of the signal. The circuit structure is greatly simplified. In order to optimize noise interference, most of them adopt differential dual-channel isolation capacitor transmission, and the signal demodulation side uses differential amplification to shield common-mode noise. In this way, there is always an oscillating signal during the high-level period of the signal, which consumes a lot of power, and the differential signal matching requirements are extremely high. Once mismatched, the common-mode signal will be converted into a differential signal and amplified by the differential amplifier to form a signal error.

[0048] The purpose of this application is to: address the technical problems that interference cannot be completely avoided and code errors are easily formed in the current signal modulation of capacitive isolation transmission, and to realize the function of a digital isolator based on charge detection.

[0049] In order to solve the above technical problems, Figure 4 As shown, an embodiment of the present application provides a digital isolator based on charge detection, which includes: a signal encoding module 1, a dual isolation channel 2 and a signal decoding module 3.

[0050] In the embodiment of the present invention, the signal encoding module 1 receives the encoding side square wave control signal and encodes it into a double-edge oscillating signal. Further, the signal encoding module 1 is used to modulate the input square wave control signal into a continuously oscillating high-frequency signal, which is convenient for transmission through high-voltage capacitor isolation. The output of the signal encoding module 1 is connected to the dual isolation channel 2; the signal decoding module 3 receives the dual isolation channel signal and decodes it into the original signal to obtain the decoding side square wave control signal.

[0051] Specifically, the signal encoding module 1 includes: an edge detection unit 11 , a voltage-controlled oscillation unit 12 , a coding-side charge detection unit 13 , and a signal shaping unit 14 .

[0052] First, the signal shaping unit 14 is used to receive the coding side square wave control signal, shape the coding side square wave control signal and filter out interference signals to prevent the input signal from causing coding confusion. The output end of the signal shaping unit 14 is connected to the input end of the edge detection unit 11, and the shaped and filtered coding side square wave control signal is input into the edge detection unit 11.

[0053] Further, the edge detection unit 11 is used to extract the first rising edge information and the first falling edge information of the square wave control signal on the encoding side. The voltage-controlled oscillation unit 12 is used to encode the first rising edge information and the first falling edge information into a rising edge oscillation signal and a falling edge oscillation signal, respectively, wherein the rising edge oscillation signal and the falling edge oscillation signal are both oscillation signals of a specific frequency. The charge detection unit 13 on the encoding side is used to detect whether the number of continuous pulses of the rising edge oscillation signal and the falling edge oscillation signal is greater than a first preset number; when the number of continuous pulses of the rising edge oscillation signal is greater than the first preset number, the voltage-controlled oscillation unit 12 is controlled to output a rising edge oscillation signal to the outside; when the number of continuous pulses of the falling edge oscillation signal is greater than the first preset number, the voltage-controlled oscillation unit 12 is controlled to output a falling edge oscillation signal to the outside.

[0054] In the embodiment of the present application, the first preset number can be 4. In this way, when the rising edge oscillation signal is greater than 4 consecutive pulses, the high level is flipped and the voltage-controlled oscillation unit 12 is turned off, and the charge is released after the voltage-controlled oscillation unit 12 is turned off, thereby generating a single pulse signal, and the single pulse signal is used to control the voltage-controlled oscillation unit 12 to output the rising edge oscillation signal to the outside. Similarly, when the falling edge oscillation signal is greater than 4 consecutive pulses, the high level is flipped and the voltage-controlled oscillation unit 12 is turned off, and the charge is released after the voltage-controlled oscillation unit 12 is turned off, thereby generating a single pulse signal, and the single pulse signal is used to control the voltage-controlled oscillation unit 12 to output the falling edge oscillation signal to the outside.

[0055] like Figure 5 and Figure 6 As shown, the edge detection unit 11 includes: a rising edge detection part 111 and a falling edge detection part 112.

[0056] Furthermore, the rising edge detection part 111 is used to detect the first rising edge information of the square wave control signal on the encoding side and generate a first single pulse signal; the first single pulse signal is input to the CLK input terminal of the first D flip-flop Dff1 through the first input terminal of the first OR gate circuit OR1, the Q output terminal of the first D flip-flop Dff1 is connected to the D input terminal, the Q output terminal of the first D flip-flop Dff1 is connected to the first input terminal of the voltage-controlled oscillation unit 12, and the R access terminal of the first D flip-flop Dff1 is used for power-on reset.

[0057] The falling edge detection part 112 is used to detect the first falling edge information of the square wave control signal on the encoding side and generate a second single pulse signal; the second single pulse signal is input to the CLK input terminal of the second D flip-flop Dff2 through the first input terminal of the second OR gate circuit OR2, the Q output terminal of the second D flip-flop Dff2 is connected to the D input terminal, the Q output terminal of the second D flip-flop Dff2 is connected to the second input terminal of the voltage-controlled oscillation unit 12, and the R access terminal of the second D flip-flop Dff2 is used for power-on reset.

[0058] As described above, in the embodiment of the present application, the edge detection unit 11 outputs a pulse signal and a pulse representing edge information which are combined through an OR gate as a rising edge trigger signal of the first D flip-flop and a falling edge trigger signal of the second D flip-flop, that is, as an oscillator start working signal, generating four continuous pulse oscillation signals corresponding to the edge information.

[0059] The voltage-controlled oscillation unit 12 is used to generate an oscillation signal and adjust the frequency according to the voltage. In the embodiment of the present application, only its on and off functions are used. The voltage-controlled oscillation unit 12 is provided with a first output terminal OUT1, a second output terminal OUT2 and a third output terminal OUT3. The first output terminal OUT1 corresponds to the first input terminal, the second output terminal OUT2 corresponds to the second input terminal, and the third output terminal OUT3 is connected to the charge detection input terminal of the encoding side charge detection unit 13. The charge detection output terminal of the encoding side charge detection unit 13 is connected to the second input terminal of the first OR gate circuit OR1 and the second OR gate circuit OR2.

[0060] refer to Figure 8 The encoding side charge detection unit 13 includes: a first inverter Inv1, a second inverter Inv2, a third inverter Inv3, a third D flip-flop Dff3, a fourth D flip-flop Dff4, a first transmission gate TG1, a second transmission gate TG2, a buffer Buffer, a seventh resistor R7, a third capacitor C3, a seventh PMOS tube MP7, and a second Schmitt trigger SMT2.

[0061] Further, the input end of the first inverter Inv1 forms a charge detection input end IN2 externally, the first inverter Inv1 and the second inverter Inv2 are connected in series, the output ends of the first inverter Inv1 and the second inverter Inv2 are respectively connected to the CLK input ends of the fourth D flip-flop Dff4 and the third D flip-flop Dff3, the D input end of the third D flip-flop Dff3 is connected to the first power supply VDD1, the D input end of the fourth D flip-flop Dff4 is grounded, the Q output ends of the third D flip-flop Dff3 and the fourth D flip-flop Dff4 are respectively connected to the input ends of the first transmission gate TG1 and the second transmission gate TG2, the output ends of the first transmission gate TG1 and the second transmission gate TG2 are connected to the input end of the buffer Buffer, the second control end CT2 of the first transmission gate TG1 is connected to the first control end CT3 of the second transmission gate TG2, the second control end CT4 of the second transmission gate TG2 is connected to the first control end CT1 of the first transmission gate TG1, the output end of the first inverter Inv1 is connected to the first control end CT3 of the second transmission gate TG2, and the output end of the second inverter Inv2 is connected to the first control end CT1 of the first transmission gate TG1. The output end of the buffer Buffer is connected to the gate of the seventh PMOS tube MP7 through the third inverter Inv3, the source of the seventh PMOS tube MP7 is connected to the second power supply VDD2, and the drain of the seventh PMOS tube MP7 is grounded through the third capacitor C3. The output end of the buffer Buffer is connected to the ground end of the third capacitor C3 through the seventh resistor R7. The input end of the second Schmitt trigger SMT2 is connected to the sixth connection point AP6 between the drain of the seventh PMOS tube MP7 and the third capacitor C3, and the output end of the second Schmitt trigger SMT2 forms a charge detection output end OUT5 to the outside.

[0062] As described above, the encoding side charge detection unit 13 is used to detect continuous pulse oscillation signals. The oscillation signal serves as the edge signal of the D flip-flop and the control signal of the TG transmission gate. The D flip-flop is only sensitive to the edge, and the TG transmission gate is only sensitive to the level. The charge is accumulated by continuously switching the capacitor to charge and discharge. When four consecutive pulse oscillation signals appear, it flips to a high level, otherwise the charge is released and the level is low.

[0063] refer to Figure 8, the charge detection input terminal IN2 of the charge detection unit 13 on the encoding side receives the output signal of the third output terminal OUT3 of the voltage-controlled oscillation unit 12 as the clock signal of the first D flip-flop Dff1 and the second D flip-flop Dff2, wherein the first D flip-flop Dff1 and the second D flip-flop Dff2 are both triggered by the rising edge. When no signal appears, the seventh resistor R7 turns off the seventh PMOS tube MP7, the current source I1 path is blocked, and the current source I2 outputs a low level for capacitor discharge. When the rising edge of the oscillation signal comes, the first D flip-flop Dff1 samples the power supply voltage and outputs a high level, the first transmission gate TG1 is turned on, and the second transmission gate TG2 is turned off. The high level passes through the buffer Buffer and the third inverter Inv3 to turn on the seventh PMOS tube MP7, and the current source I1 starts to charge the third capacitor C3. The charging current is the current difference between the current source I1 and the current source I2, and this current difference is also greater than the current value of the current source I2. When the falling edge of the input oscillation signal arrives, it passes through the first inverter Inv1 and becomes a rising edge to trigger the second D trigger Dff2, and samples the low level, the first transmission gate TG1 is closed, the second transmission gate TG2 is opened, and the low level passes through the buffer Buffer and the third inverter Inv3 to close the seventh PMOS tube MP7. At this time, the current source I2 discharges the third capacitor C3. Because the charging current (the current difference between the current source I1 and the current source I2) is greater than the discharge current (the current value of the current source I2), one cycle can complete partial charge accumulation. When the charge of four pulse cycles is accumulated continuously, the upper flip threshold of the second Schmitt trigger SMT2 can be reached, and a high level is output; at the end of four pulses, when no oscillation signal appears, the current source I2 starts to discharge the third capacitor C3. When the discharge drop potential is lower than the lower flip threshold of the second Schmitt trigger SMT2, a low level is output, and the charge detection is completed and a single pulse is output.

[0064] like Figure 4 As shown, the signal encoding module 1 also includes a first high-pass filtering unit 15 and a second high-pass filtering unit 16, and the first high-pass filtering unit 15 and the second high-pass filtering unit 16 are both used to filter out low-frequency interference signals. The first high-pass filtering unit 15 includes: a first capacitor C1 and a first resistor R1, and the second high-pass filtering unit 16 includes: a second capacitor C2 and a second resistor R2, and the voltage-controlled oscillation unit 12 is connected to one end of the first capacitor C1 and the second capacitor C2 through the first output end and the second output end, respectively, and the other ends of the first capacitor C1 and the second capacitor C2 form the output ends of the first high-pass filtering unit and the second high-pass filtering unit respectively to the outside, and one end of the first resistor R1 and the second resistor R2 are connected to the other end of the first capacitor C1 and the second capacitor C2 respectively, and the other ends of the first resistor R1 and the second resistor R2 are grounded.

[0065] In the embodiment of the present application, the dual isolation channel 2 is used to transmit the double-edge oscillation signal to the decoding side. The dual isolation channel 2 uses a high-voltage process isolation capacitor, which is a two-two series dual-channel isolation transmission path composed of four identical high-voltage capacitors, and transmits the corresponding rising and falling edge oscillation signals respectively.

[0066] like Figure 4 As shown, the dual isolation channel specifically includes: a first high-voltage isolation capacitor HC1, a second high-voltage isolation capacitor HC2, a third high-voltage isolation capacitor HC3 and a fourth high-voltage isolation capacitor HC4. The first high-voltage isolation capacitor HC1 and the third high-voltage isolation capacitor HC3 are connected in series to form a first isolation channel, and the second high-voltage isolation capacitor HC2 and the fourth high-voltage isolation capacitor HC4 are connected in series to form a second isolation channel. The first high-voltage isolation capacitor HC1 and the third high-voltage isolation capacitor HC3 respectively form an input end and an output end of the first isolation channel to the outside, and the second high-voltage isolation capacitor HC2 and the fourth high-voltage isolation capacitor HC4 respectively form an input end and an output end of the second isolation channel to the outside, and the input end of the first isolation channel is connected to the output end of the first high-pass filtering unit, and the input end of the second isolation channel is connected to the output end of the second high-pass filtering unit.

[0067] As described above, the signal encoding module 1 includes two separate channels, which are respectively used to generate four continuous pulse oscillation signals corresponding to the rising edge and four continuous pulse oscillation signals corresponding to the falling edge, and are independently transmitted through the first isolation channel 21 and the second isolation channel 22 of the dual isolation channel 2.

[0068] like Figure 4 As shown, the signal decoding module 3 includes: a first interface amplifying unit 31 , a second interface amplifying unit 32 , a first decoding side charge detecting unit 33 , a second decoding side charge detecting unit 34 , and an RS trigger 35 .

[0069] Furthermore, the output end of the first isolation channel 21 is connected to the R input end of the RS trigger 35 via the first interface amplification unit 31 and the first decoding side charge detection unit 33 in sequence. In this way, the rising edge oscillation signal in the dual isolation channel signal is input to the first decoding side charge detection unit 33 via the first interface amplification unit 31, and the first decoding side charge detection unit 33 is used to detect whether the number of continuous pulses of the rising edge oscillation signal is greater than the second preset number; when the number of continuous pulses of the rising edge oscillation signal is greater than the second preset number, the second rising edge information is input to the RS trigger through the R input end.

[0070] Similarly, the output end of the second isolation channel 22 is connected to the S input end of the RS trigger 35 via the second interface amplifier unit 32 and the second decoding side charge detection unit 34. In this way, the falling edge oscillation signal in the dual isolation channel signal is input to the second decoding side charge detection unit 34 via the second interface amplifier unit 32, and the second decoding side charge detection unit 34 is used to detect whether the number of continuous pulses of the falling edge oscillation signal is greater than the second preset number; when the number of continuous pulses of the falling edge oscillation signal is greater than the second preset number, the second falling edge information is input to the RS trigger 35 via the S input end.

[0071] In the embodiment of the present application, the second preset number can also be 4.

[0072] In the embodiment of the present application, the first interface amplifier unit 31 and the second interface amplifier unit 32 are used to amplify and shape the oscillation signal, respectively as the clock signal of the first decoding side charge detection unit 33 and the second decoding side charge detection unit 34 of the subsequent stage. The circuit structure of the first interface amplifier unit 31 and the second interface amplifier unit 32 is the same, both including a resistor voltage divider structure to control the common mode level, amplifying in a single-ended input and single-ended output mode to achieve rail-to-rail output, and shaping through a Schmitt trigger to facilitate subsequent decoding.

[0073] refer to Figure 7 The first interface amplifying unit 31 and the second interface amplifying unit 32 specifically include: a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, a fourth NMOS tube MN4, a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a fifth PMOS tube MP5, a sixth PMOS tube MP6 and a first Schmitt trigger SMT1.

[0074] In the embodiment of the present application, the third resistor R3, the fourth resistor R4, the fifth resistor R5, and the sixth resistor R6 control the common mode level of the input end, the second NMOS tube MN2 and the third NMOS tube MN3 are differential input tubes, and IN1 is an oscillation signal transmitted to the decoding side through the isolation channel; the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4, the fifth PMOS tube MP5, the sixth PMOS tube MP6 and the first NMOS tube MN1, the second NMOS tube MN2, the third NMOS tube MN3, and the fourth NMOS tube MN4 constitute a high-gain amplification structure with dual-end input and single-end output, which can realize rail-to-rail output of the signal, and then be shaped and output by the first Schmitt trigger SMT1.

[0075] Further, one end of the fifth resistor R5 and the sixth resistor R6 are grounded, one end of the third resistor R3 is connected in series with the other end of the fifth resistor R5, one end of the fourth resistor R4 is connected in series with the other end of the sixth resistor R6, and the other ends of the third resistor R3 and the fourth resistor R4 are connected together. The sources of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are connected together and grounded, the gate of the first NMOS transistor MN1 is connected to the gate of the fourth NMOS transistor MN4, the gate of the second NMOS transistor MN2 is connected to the first connection point AP1 between the third resistor R3 and the fifth resistor R5, the first connection point AP1 forms a decoding side oscillation signal receiving end IN1 externally, and the gate of the third NMOS transistor MN3 is connected to the second connection point AP2 between the fourth resistor R4 and the sixth resistor R6. The sources of the first PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4, the fifth PMOS tube MP5, and the sixth PMOS tube MP6 are connected to the other ends of the third resistor R3 and the fourth resistor R4, the drain of the first PMOS tube MP1 is connected to the drain of the first NMOS tube MN1, the gate of the first PMOS tube MP1 is connected to the gate of the second PMOS tube MP2, the drains of the second PMOS tube MP2 and the third PMOS tube MP3 are connected to the drain of the second NMOS tube MN2 and form a first intersection BP1, the first intersection BP1 is connected to the third connection point AP3 between the gate of the first PMOS tube MP1 and the gate of the second PMOS tube MP2, the fourth PMOS tube MP 4 and the drain of the fifth PMOS tube MP5 are connected to the drain of the third NMOS tube MN3 and form a second intersection BP2, the gate of the fifth PMOS tube MP5 is connected to the gate of the sixth PMOS tube MP6, the second intersection BP2 is connected to a fourth connection point AP4 between the gate of the fifth PMOS tube MP5 and the gate of the sixth PMOS tube MP6, the gate of the third PMOS tube MP3 is connected to the second intersection BP2, the gate of the fourth PMOS tube MP4 is connected to the first intersection BP1, the drain of the sixth PMOS tube MP6 is connected to the drain of the fourth NMOS tube MN4, and the input end of the first Schmitt trigger SMT1 is connected to a fifth connection point AP5 between the drain of the sixth PMOS tube MP6 and the drain of the fourth NMOS tube MN4.

[0076] refer to Figure 8The circuit structure of the first decoding side charge detection unit 33 and the second decoding side charge detection unit 34 is the same as the circuit structure of the encoding side charge detection unit 13. Similarly, the first decoding side charge detection unit 33 and the second decoding side charge detection unit 34 both include: a first inverter Inv1, a second inverter Inv2, a third inverter Inv3, a third D flip-flop Dff3, a fourth D flip-flop Dff4, a first transmission gate TG1, a second transmission gate TG2, a buffer Buffer, a seventh resistor R7, a third capacitor C3, a seventh PMOS tube MP7, and a second Schmitt trigger SMT2.

[0077] Further, the input end of the first inverter Inv1 forms a charge detection input end IN2 externally, the first inverter Inv1 and the second inverter Inv2 are connected in series, the output ends of the first inverter Inv1 and the second inverter Inv2 are respectively connected to the CLK input ends of the fourth D flip-flop Dff4 and the third D flip-flop Dff3, the D input end of the third D flip-flop Dff3 is connected to the first power supply VDD1, the D input end of the fourth D flip-flop Dff4 is grounded, the Q output ends of the third D flip-flop Dff3 and the fourth D flip-flop Dff4 are respectively connected to the input ends of the first transmission gate TG1 and the second transmission gate TG2, the output ends of the first transmission gate TG1 and the second transmission gate TG2 are connected to the input end of the buffer Buffer, the second control end CT2 of the first transmission gate TG1 is connected to the first control end CT3 of the second transmission gate TG2, the second control end CT4 of the second transmission gate TG2 is connected to the first control end CT1 of the first transmission gate TG1, the output end of the first inverter Inv1 is connected to the first control end CT3 of the second transmission gate TG2, and the output end of the second inverter Inv2 is connected to the first control end CT1 of the first transmission gate TG1. The output end of the buffer Buffer is connected to the gate of the seventh PMOS tube MP7 through the third inverter Inv3, the source of the seventh PMOS tube MP7 is connected to the second power supply VDD2, and the drain of the seventh PMOS tube MP7 is grounded through the third capacitor C3. The output end of the buffer Buffer is connected to the ground end of the third capacitor C3 through the seventh resistor R7. The input end of the second Schmitt trigger SMT2 is connected to the sixth connection point AP6 between the drain of the seventh PMOS tube MP7 and the third capacitor C3, and the output end of the second Schmitt trigger SMT2 forms a charge detection output end OUT5 to the outside.

[0078] As described above, the first decoding side charge detection unit 33 and the second decoding side charge detection unit 34 are used to detect continuous pulse oscillation signals. The oscillation signal serves as the edge signal of the D flip-flop and the control signal of the TG transmission gate. The D flip-flop is only sensitive to the edge, and the TG transmission gate is only sensitive to the level. The capacitor is charged and discharged through continuous switching actions to accumulate charge. When four consecutive pulse oscillation signals appear, it flips to a high level, otherwise the charge is released and the level is low.

[0079] refer to Figure 8 , the charge detection input terminal IN2 of the first decoding side charge detection unit 33 and the second decoding side charge detection unit 34 respectively receives the output signal of the fourth output terminal OUT4 of the first interface amplification unit 31 and the second interface amplification unit 32, as the clock signal of the third D flip-flop Dff3 and the fourth D flip-flop Dff4, wherein the third D flip-flop Dff3 and the fourth D flip-flop Dff4 are both triggered by the rising edge. When no signal appears, the seventh resistor R7 turns off the seventh PMOS tube MP7, the current source I1 path is blocked, and the current source I2 outputs a low level for capacitor discharge. When the rising edge of the oscillation signal comes, the third D flip-flop Dff3 samples the power supply voltage and outputs a high level, the first transmission gate TG1 is turned on, and the second transmission gate TG2 is turned off. The high level passes through the buffer Buffer and the third inverter Inv3 to turn on the seventh PMOS tube MP7, and the current source I1 starts to charge the third capacitor C3, and the charging current is the current difference between the current source I1 and the current source I2, and this current difference is also greater than the current value of the current source I2. When the falling edge of the input oscillation signal arrives, it passes through the first inverter Inv1 and becomes a rising edge to trigger the fourth D trigger Dff4, and samples the low level, the first transmission gate TG1 is closed, the second transmission gate TG2 is opened, and the low level passes through the buffer Buffer and the third inverter Inv3 to close the seventh PMOS tube MP7. At this time, the current source I2 discharges the third capacitor C3. Because the charging current (the current difference between the current source I1 and the current source I2) is greater than the discharge current (the current value of the current source I2), one cycle can complete partial charge accumulation. When the charge of four pulse cycles is accumulated continuously, the upper flip threshold of the second Schmitt trigger SMT2 can be reached, and a high level is output; at the end of four pulses, when no oscillation signal appears, the current source I2 starts to discharge the third capacitor C3. When the discharge potential is lower than the lower flip threshold of the second Schmitt trigger SMT2, a low level is output, and the charge detection is completed and a single pulse is output.

[0080] In addition, the signal decoding module 3 includes two signal channels, which respectively receive and process the oscillation signal corresponding to the rising edge and the oscillation signal corresponding to the falling edge, and combine the decoded output at the RS trigger input end. The RS trigger 35 is used to obtain the decoding side square wave control signal based on the received second rising edge information and the second falling edge information. The input end of the RS trigger 35 circuit is the output signal of the charge detection, which is used to restore the original square wave control signal by using the pulse signal obtained by the charge detection as the set / reset signal; the Q output end of the RS trigger 35 forms the output end of the signal decoding module 3 to the outside.

[0081] Compared with the prior art, the digital isolator based on charge detection provided by the embodiment of the present application adopts dual-channel independent high-voltage capacitor isolation to transmit rising edge oscillation signals and falling edge oscillation signals respectively, and has no matching requirements relative to differential channels; the signal encoding side and the signal decoding side are equipped with independent dual-channel charge detection circuits, and the charge detection unit on the encoding side is used to control the operation of the voltage-controlled oscillation unit through charge detection, and detects a continuous first preset number of pulses to flip the high level and terminate the operation of the voltage-controlled oscillation unit, otherwise it is a low level; the charge detection unit on the decoding side is used to detect a continuous second preset number of pulses and generate a set / reset signal for the RS trigger to restore the original signal. This method ignores the influence of interference signals on the frequency of oscillation signals, greatly improves the accuracy and reliability of signal demodulation, and has greatly reduced power consumption compared to existing OOK modulation technology, and has low signal propagation delay and distortion, which can complete low-delay, low-distortion, low-power consumption, and high-speed transmission of signals.

[0082] Corresponding to the above-disclosed digital isolator based on charge detection, an embodiment of the present invention further discloses a method for implementing a digital isolator based on charge detection. The following describes in detail a method for implementing a digital isolator based on charge detection disclosed in an embodiment of the present invention in combination with the above-described digital isolator based on charge detection.

[0083] The specific steps of a method for implementing a digital isolator based on charge detection provided in an embodiment of the present application are described in detail below.

[0084] like Figure 4 As shown, an implementation method of a digital isolator based on charge detection provided in an embodiment of the present application specifically includes: a signal encoding module 1 receives a square wave control signal on the encoding side and encodes it into a double-edge oscillation signal; a dual isolation channel 2 transmits the double-edge oscillation signal to the decoding side; a signal decoding module 3 receives the dual isolation channel signal and decodes it into the original signal to obtain a square wave control signal on the decoding side.

[0085] Further, at the encoding end, the signal shaping unit 14 receives the encoding side square wave control signal, shapes the encoding side square wave control signal and filters out the interference signal, and then inputs the shaped and filtered encoding side square wave control signal into the edge detection unit 11. The edge detection unit 11 extracts the first rising edge information and the first falling edge information of the encoding side square wave control signal and sends them to the voltage-controlled oscillation unit 12, and the voltage-controlled oscillation unit 12 encodes the first rising edge information and the first falling edge information into a rising edge oscillation signal and a falling edge oscillation signal respectively and sends them to the encoding side charge detection unit 13. The encoding side charge detection unit 13 detects whether the number of continuous pulses of the rising edge oscillation signal and the falling edge oscillation signal is greater than the first preset number; when the number of continuous pulses of the rising edge oscillation signal is greater than the first preset number, the voltage-controlled oscillation unit 12 is controlled to output the rising edge oscillation signal externally; when the number of continuous pulses of the falling edge oscillation signal is greater than the first preset number, the voltage-controlled oscillation unit 12 is controlled to output the falling edge oscillation signal externally.

[0086] refer to Figure 5 and Figure 6 In the embodiment of the present application, the signal encoding module includes two independent circuits, namely, a rising edge oscillation signal generating circuit and a falling edge oscillation signal generating circuit, and uses dual isolation channels for independent transmission. The rising edge detection part 111 in the rising edge oscillation signal generating circuit is used to detect the rising edge of the square wave signal and generate a single pulse, which is used as the clock signal of the first D flip-flop Dff1 through the first OR gate circuit OR1. The inverting output terminal of the first D flip-flop Dff1 (corresponding to Figure 5 The Q output terminal in the circuit) is connected to the input D input terminal. Since the R access terminal is connected to the power supply, the power-on reset signal is reset to zero during the initial power-on. At this time, the Q output terminal is at a low level and the Q output terminal is at a high level. After being triggered by a single pulse corresponding to the rising edge, the high level is sampled. At this time, the Q output terminal is at a low level and the Q output terminal is at a high level. The voltage-controlled oscillation unit 12 is started to generate a rising edge oscillation signal. The rising edge oscillation signal is input to the encoding side charge detection unit 13. When four consecutive pulse oscillation signals are detected, the charge accumulation is sufficient and flips to a high level. At this time, a rising edge appears in the output. The first D flip-flop Dff1 starts sampling a low level, and the Q output terminal becomes a low level, turning off the voltage-controlled oscillation unit 12. At this time, the encoding side charge detection unit 13 detects that there is no oscillation signal, starts to release the charge, and becomes a low level, completing the loop control. Similarly, the falling edge corresponding to the oscillation signal generating circuit, the falling edge detection part 112 is used to detect the falling edge of the square wave signal and generate a single pulse, which is used as the clock signal of the second D flip-flop Dff2 through the second OR gate circuit OR2. The inverting output terminal of the second D flip-flop Dff2 (corresponding to Figure 6The Q output terminal in the circuit is connected to the D input terminal. Since the R access terminal is connected to the power supply, the power-on reset signal is reset to zero during the initial power-on. At this time, the Q output terminal is low level and the Q output terminal is high level. After the single pulse trigger corresponding to the falling edge is triggered, the high level is sampled. At this time, the Q output terminal is low level and the Q output terminal is high level. The voltage-controlled oscillation unit 12 is started to generate a falling edge oscillation signal. The falling edge oscillation signal is input to the charge detection unit 13 on the encoding side. When four consecutive pulse oscillation signals are detected, the charge accumulation is sufficient and flips to a high level. At this time, a rising edge appears in the output. The second D trigger starts to sample a low level, and the Q output terminal becomes a low level. The voltage-controlled oscillation unit 12 is turned off. At this time, the charge detection circuit detects that there is no oscillation signal, starts to release the charge, and becomes a low level, completing the loop control. In this way, four continuous pulse oscillation signals corresponding to the rising edge and the falling edge of the two paths are completed and transmitted independently through the isolation channel.

[0087] like Figure 4 As shown, at the decoding end, the rising edge oscillation signal in the dual isolation channel signal is input into the first decoding side charge detection unit 33 via the first interface amplification unit 31, and the first decoding side charge detection unit 33 is used to detect whether the number of continuous pulses of the rising edge oscillation signal is greater than the second preset number; when the number of continuous pulses of the rising edge oscillation signal is greater than the second preset number, the second rising edge information is input into the RS trigger through the R input end. Similarly, the falling edge oscillation signal in the dual isolation channel signal is input into the second decoding side charge detection unit 34 via the second interface amplification unit 32, and the second decoding side charge detection unit 34 is used to detect whether the number of continuous pulses of the falling edge oscillation signal is greater than the second preset number; when the number of continuous pulses of the falling edge oscillation signal is greater than the second preset number, the second falling edge information is input into the RS trigger 35 through the S input end. Afterwards, the RS trigger 35 obtains the decoding side square wave control signal based on the received second rising edge information and second falling edge information.

[0088] Compared with the prior art, the implementation method of a digital isolator based on charge detection provided by the embodiment of the present application adopts dual-channel independent high-voltage capacitor isolation to transmit rising edge oscillation signals and falling edge oscillation signals respectively, and there is no matching requirement relative to the differential channel; the signal encoding side and the signal decoding side are equipped with independent dual-channel charge detection circuits, and the charge detection unit on the encoding side is used to control the operation of the voltage-controlled oscillation unit through charge detection, and detects a continuous first preset number of pulses to flip the high level and terminate the operation of the voltage-controlled oscillation unit, otherwise it is a low level; the charge detection unit on the decoding side is used to detect a continuous second preset number of pulses and generate a set / reset signal for the RS trigger to restore the original signal. This method ignores the influence of interference signals on the frequency of the oscillation signal, greatly improves the accuracy and reliability of signal demodulation, and has greatly reduced power consumption compared to the existing OOK modulation technology, and the signal propagation delay and distortion are small, which can complete low-delay, low-distortion, low-power consumption, and high-speed transmission of signals.

[0089] refer to Fig. 9 , where Vin is the input encoding side square wave control signal, Pulse_up is the pulse corresponding to the rising edge, Pulse_down is the pulse corresponding to the falling edge, TX1 is the rising edge oscillation signal, TX2 is the falling edge oscillation signal, RX1 is the isolation channel receiving signal corresponding to TX1, RX2 is the isolation channel receiving signal corresponding to TX2, RX3 is the output pulse signal of the first decoding side charge detection unit corresponding to the first isolation channel where RX1 is located, RX4 is the output pulse signal of the second decoding side charge detection unit corresponding to the second isolation channel where RX2 is located, RX3 and RX4 are used as RS trigger input terminal signals to decode and output the original square wave signal, and VOut is the output decoding side square wave control signal. From Fig. 9 It can be seen that no matter where the interference signal appears, the interference can be shielded and the signal decoding reliability is high;

[0090] Although the present invention has been described in detail above by general description and specific embodiments, it is obvious to those skilled in the art that some modifications or improvements can be made to the present invention. Therefore, these modifications or improvements made without departing from the spirit of the present invention all belong to the scope of protection claimed by the present invention.

Claims

1. A digital isolator based on charge detection, characterized in that: The digital isolator comprises: A signal encoding module, used for receiving the encoding side square wave control signal and encoding it into a double-edge oscillation signal; Dual isolation channels, used to transmit the double-edge oscillation signal to the decoding side; A signal decoding module is used to receive dual isolation channel signals and decode them into original signals to obtain a decoding side square wave control signal; The signal encoding module includes: an edge detection unit, a voltage-controlled oscillation unit, and a coding side charge detection unit; the edge detection unit is used to extract the first rising edge information and the first falling edge information of the coding side square wave control signal; the voltage-controlled oscillation unit is used to encode the first rising edge information and the first falling edge information into a rising edge oscillation signal and a falling edge oscillation signal respectively; the coding side charge detection unit is used to detect whether the number of continuous pulses of the rising edge oscillation signal and the falling edge oscillation signal is greater than a first preset number; when the number of continuous pulses of the rising edge oscillation signal is greater than the first preset number, the voltage-controlled oscillation unit is controlled to output the rising edge oscillation signal to the outside; when the number of continuous pulses of the falling edge oscillation signal is greater than the first preset number, the voltage-controlled oscillation unit is controlled to output the falling edge oscillation signal to the outside.

2. A digital isolator based on charge detection as claimed in claim 1, characterized in that: The signal encoding module further includes: a signal shaping unit, which is used to receive the encoding side square wave control signal, shape the encoding side square wave control signal and filter out interference signals.

3. A digital isolator based on charge detection as claimed in claim 2, characterized in that: The edge detection unit comprises: A rising edge detection part, used for detecting the first rising edge information of the encoding side square wave control signal and generating a first single pulse signal; the first single pulse signal is input to the CLK input terminal of the first D flip-flop through the first input terminal of the first OR gate circuit, the Q output terminal of the first D flip-flop is connected to the D input terminal, the Q output terminal of the first D flip-flop is connected to the first input terminal of the voltage-controlled oscillation unit, and the R access terminal of the first D flip-flop is used for power-on reset; A falling edge detection part, used for detecting the first falling edge information of the encoding side square wave control signal and generating a second single pulse signal; the second single pulse signal is input to the CLK input terminal of the second D flip-flop through the first input terminal of the second OR gate circuit, the Q output terminal of the second D flip-flop is connected to the D input terminal, the Q output terminal of the second D flip-flop is connected to the second input terminal of the voltage-controlled oscillation unit, and the R access terminal of the second D flip-flop is used for power-on reset; The voltage-controlled oscillation unit is provided with a first output end corresponding to the first input end, a second output end corresponding to the second input end, and a third output end, the third output end is connected to the charge detection input end of the coding side charge detection unit, and the charge detection output end of the coding side charge detection unit is connected to the second input ends of the first OR gate circuit OR1 and the second OR gate circuit OR2.

4. A digital isolator based on charge detection as claimed in claim 3, characterized in that: The signal encoding module also includes a first high-pass filtering unit and a second high-pass filtering unit, the first high-pass filtering unit includes: a first capacitor C1 and a first resistor R1, the second high-pass filtering unit includes: a second capacitor C2 and a second resistor R2, the voltage-controlled oscillation unit is respectively connected to one end of the first capacitor C1 and the second capacitor C2 through a first output end and a second output end, the other ends of the first capacitor C1 and the second capacitor C2 respectively form the output ends of the first high-pass filtering unit and the second high-pass filtering unit, one end of the first resistor R1 and the second resistor R2 are respectively connected to the other ends of the first capacitor C1 and the second capacitor C2, and the other ends of the first resistor R1 and the second resistor R2 are grounded.

5. A digital isolator based on charge detection as claimed in claim 4, characterized in that: The dual isolation channel includes: a first high-voltage isolation capacitor HC1, a second high-voltage isolation capacitor HC2, a third high-voltage isolation capacitor HC3 and a fourth high-voltage isolation capacitor HC4. The first high-voltage isolation capacitor HC1 and the third high-voltage isolation capacitor HC3 are connected in series to form a first isolation channel. The second high-voltage isolation capacitor HC2 and the fourth high-voltage isolation capacitor HC4 are connected in series to form a second isolation channel. The first high-voltage isolation capacitor HC1 and the third high-voltage isolation capacitor HC3 respectively form an input end and an output end of the first isolation channel to the outside. The second high-voltage isolation capacitor HC2 and the fourth high-voltage isolation capacitor HC4 respectively form an input end and an output end of the second isolation channel to the outside. The input end of the first isolation channel is connected to the output end of the first high-pass filtering unit, and the input end of the second isolation channel is connected to the output end of the second high-pass filtering unit.

6. A digital isolator based on charge detection as claimed in claim 5, characterized in that: The signal decoding module comprises: a first interface amplifying unit, a second interface amplifying unit, a first decoding side charge detection unit, a second decoding side charge detection unit, and an RS trigger; the output end of the first isolation channel is connected to the R input end of the RS trigger via the first interface amplifying unit and the first decoding side charge detection unit in sequence, the output end of the second isolation channel is connected to the S input end of the RS trigger via the second interface amplifying unit and the second decoding side charge detection unit in sequence, and the Q output end of the RS trigger forms the output end of the signal decoding module externally; The rising edge oscillation signal in the dual isolation channel signal is input into the first decoding side charge detection unit via the first interface amplification unit, and the first decoding side charge detection unit is used to detect whether the number of continuous pulses of the rising edge oscillation signal is greater than the second preset number; when the number of continuous pulses of the rising edge oscillation signal is greater than the second preset number, the second rising edge information is input into the RS trigger through the R input terminal; The falling edge oscillation signal in the dual isolation channel signal is input into the second decoding side charge detection unit via the second interface amplification unit, and the second decoding side charge detection unit is used to detect whether the number of continuous pulses of the falling edge oscillation signal is greater than the second preset number; when the number of continuous pulses of the falling edge oscillation signal is greater than the second preset number, the second falling edge information is input into the RS trigger through the S input terminal; The RS trigger is used to obtain a decoding side square wave control signal based on the received second rising edge information and the received second falling edge information.

7. A digital isolator based on charge detection as claimed in claim 6, characterized in that: The first preset number and the second preset number are both 4.

8. A digital isolator based on charge detection as claimed in claim 7, characterized in that: The first interface amplifying unit and the second interface amplifying unit both include: a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a first NMOS transistor MN1, a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, a fourth PMOS transistor MP4, a fifth PMOS transistor MP5, a sixth PMOS transistor MP6 and a first Schmitt trigger SMT1, one end of the fifth resistor R5 and the sixth resistor R6 are grounded, one end of the third resistor R3 is connected in series with the other end of the fifth resistor R5, one end of the fourth resistor R4 is connected in series with the other end of the sixth resistor R6 The third resistor R3 and the fourth resistor R4 are connected in series, the other ends of the third resistor R3 and the fourth resistor R4 are connected together, the sources of the first NMOS transistor MN1, the second NMOS transistor MN2, the third NMOS transistor MN3, and the fourth NMOS transistor MN4 are connected together and grounded, the gate of the first NMOS transistor MN1 is connected to the gate of the fourth NMOS transistor MN4, the gate of the second NMOS transistor MN2 is connected to the first connection point between the third resistor R3 and the fifth resistor R5, the first connection point forms a decoding side oscillation signal receiving end, the gate of the third NMOS transistor MN3 is connected to the second connection point between the fourth resistor R4 and the sixth resistor R6, the first PMOS transistor M The sources of the second PMOS tube MP1, the second PMOS tube MP2, the third PMOS tube MP3, the fourth PMOS tube MP4, the fifth PMOS tube MP5, and the sixth PMOS tube MP6 are connected to the other ends of the third resistor R3 and the fourth resistor R4, the drain of the first PMOS tube MP1 is connected to the drain of the first NMOS tube MN1, the gate of the first PMOS tube MP1 is connected to the gate of the second PMOS tube MP2, the drains of the second PMOS tube MP2 and the third PMOS tube MP3 are connected to the drain of the second NMOS tube MN2 to form a first intersection, and the first intersection is connected to the gate of the first PMOS tube MP1 and the The third connection point between the gates of the second PMOS tube MP2, the drains of the fourth PMOS tube MP4 and the fifth PMOS tube MP5 are connected to the drain of the third NMOS tube MN3 and form a second intersection, the gate of the fifth PMOS tube MP5 is connected to the gate of the sixth PMOS tube MP6, the second intersection is connected to the fourth connection point between the gates of the fifth PMOS tube MP5 and the gates of the sixth PMOS tube MP6, the gate of the third PMOS tube MP3 is connected to the second intersection, the gate of the fourth PMOS tube MP4 is connected to the first intersection, the drain of the sixth PMOS tube MP6 is connected to the drain of the fourth NMOS tube MN4,The input end of the first Schmitt trigger SMT1 is connected to a fifth connection point between the drain of the sixth PMOS transistor MP6 and the drain of the fourth NMOS transistor MN4.

9. A digital isolator based on charge detection as claimed in claim 8, characterized in that: The encoding side charge detection unit, the first decoding side charge detection unit, and the second decoding side charge detection unit all include: a first inverter Inv1, a second inverter Inv2, a third inverter Inv3, a third D flip-flop Dff3, a fourth D flip-flop Dff4, a first transmission gate TG1, a second transmission gate TG2, a buffer Buffer, a seventh resistor R7, a third capacitor C3, a seventh PMOS tube MP7, and a second Schmitt trigger SMT2. The input end of the first inverter Inv1 forms a charge detection input end externally. The first inverter Inv1 and the second inverter Inv2 are connected in series, the output terminals of the first inverter Inv1 and the second inverter Inv2 are respectively connected to the CLK input terminals of the fourth D flip-flop Dff3 and the third D flip-flop Dff4, the D input terminal of the third D flip-flop Dff3 is connected to the first power supply, the D input terminal of the fourth D flip-flop Dff4 is grounded, the Q output terminals of the third D flip-flop Dff3 and the fourth D flip-flop Dff4 are respectively connected to the input terminals of the first transmission gate TG1 and the second transmission gate TG2, the first transmission gate TG1 and the first The output end of the second transmission gate TG2 is connected to the input end of the buffer Buffer, the second control end of the first transmission gate TG1 is connected to the first control end of the second transmission gate TG2, the second control end of the second transmission gate TG2 is connected to the first control end of the first transmission gate TG1, the output end of the first inverter Inv1 is connected to the first control end of the second transmission gate TG2, the output end of the second inverter Inv2 is connected to the first control end of the first transmission gate TG1, the output end of the buffer Buffer is connected to the gate of the seventh PMOS tube MP7 through the third inverter Inv3, the source of the seventh PMOS tube MP7 is connected to the second power supply, the drain of the seventh PMOS tube MP7 is grounded through the third capacitor C3, the output end of the buffer Buffer is connected to the ground end of the third capacitor C3 through the seventh resistor R7, the input end of the second Schmitt trigger SMT2 is connected to the sixth connection point between the drain of the seventh PMOS tube MP7 and the third capacitor C3, and the output end of the second Schmitt trigger SMT2 forms a charge detection output end to the outside.

10. A method for implementing a digital isolator based on charge detection according to any one of claims 1 to 9, characterized in that: The method comprises: The signal encoding module receives the encoding side square wave control signal and encodes it into a double-edge oscillation signal; The double-edge oscillation signal is transmitted to the decoding side through a dual isolation channel; The signal decoding module receives the dual isolation channel signals and decodes them into original signals to obtain a decoding side square wave control signal; The signal encoding module includes: an edge detection unit, a voltage-controlled oscillation unit, and a coding side charge detection unit; the edge detection unit is used to extract the first rising edge information and the first falling edge information of the coding side square wave control signal; the voltage-controlled oscillation unit is used to encode the first rising edge information and the first falling edge information into a rising edge oscillation signal and a falling edge oscillation signal respectively; the coding side charge detection unit is used to detect whether the number of continuous pulses of the rising edge oscillation signal and the falling edge oscillation signal is greater than a first preset number; when the number of continuous pulses of the rising edge oscillation signal is greater than the first preset number, the voltage-controlled oscillation unit is controlled to output the rising edge oscillation signal to the outside; when the number of continuous pulses of the falling edge oscillation signal is greater than the first preset number, the voltage-controlled oscillation unit is controlled to output the falling edge oscillation signal to the outside.

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