Preparation method of novel power device and power device

Abstract

The invention discloses a preparation method of a novel power device and the power device, relates to the technical field of power semiconductor devices, and can solve the problem that the stress of Vds is too large when an SGT MOSFET device is quickly turned off, so that the stability of the device can be improved. The method comprises the following steps: etching a first surface of a first substrate to form a plurality of first grooves to obtain a first groove-shaped surface; after a first oxidation layer is oxidized on the first groove-shaped surface and a first groove oxidation surface is obtained, each first groove is filled with first polycrystalline silicon; after a first conducting layer is formed on the oxidation surface of the first groove, the first conducting layer is connected with each piece of first polycrystalline silicon; forming a second conductive layer on the second surface of the first substrate to obtain a capacitor structure; and connecting the capacitor structure with a source electrode of a pre-prepared device structure to obtain a target power device.

Description

Technical Field

[0001] The present application relates to the technical field of power semiconductor devices, and in particular to a preparation method of a novel power device and a power device. Background Art

[0002] Shielded Gate Trench (SGT) MOSFET device is an innovative trench power MOSFET with low on-resistance, low switching loss, and superior frequency characteristics. It can be used in core power key components such as mobile phone fast charging, motor drive and power management system. In addition, with the rise of electric vehicles, the demand for medium and low voltage MOSFET is increasing. SGT MOSFET helps improve system efficiency and power density in motor control and power battery systems.

[0003] In SGT MOSFET, by connecting the shield electrode to the source electrode, this design achieves the function of shielding the gate and drift region, thereby reducing the Miller capacitance and gate charge of the device and accelerating the switching speed of the device. However, this also causes the device to have excessive Vds stress under fast shutdown, resulting in the risk of device breakdown, damage or even burning. Summary of the invention

[0004] The present application provides a novel method for preparing a power device and a power device, which can solve the problem of excessive Vds stress during fast shutdown of an SGT MOSFET device, thereby improving the stability of the device.

[0005] In order to achieve the above objectives, this application adopts the following technical solutions: A first aspect of an embodiment of the present application provides a method for preparing a novel power device, the method comprising: After etching a first surface of the first substrate to form a plurality of first grooves, a first grooved surface is obtained; After the first oxide layer is oxidized on the first groove-shaped surface to obtain a first groove oxidized surface, first polysilicon is filled in each first groove; After forming a first conductive layer on the first trench oxidation surface, connecting the first conductive layer to each of the first polysilicon; After forming a second conductive layer on the second surface of the first substrate, a capacitor structure is obtained; The capacitor structure is connected to the source electrode of the pre-fabricated device structure to obtain a target power device.

[0006] As a possible implementation manner, after forming a first conductive layer on the oxidized surface of the first trench, the first conductive layer is connected to the first polysilicon; After the first groove is oxidized to form a first passivation layer, a plurality of first etching holes are formed in the first passivation layer to obtain a first etching layer, wherein each first etching hole is etched into the first polysilicon in each first groove; A first conductive layer is formed on the first etched layer, and the first conductive layer is connected to the first polysilicon in each first trench through the first etched hole.

[0007] As a possible implementation, the source includes a source pad, the source pad includes a contact hole, and the capacitor structure is connected to the source of the pre-fabricated device structure, including: The first conductive layer in the capacitor structure is connected to the source electrode through the contact hole.

[0008] As a possible implementation manner, before connecting the capacitor structure to the source of the pre-fabricated device structure, the method further includes: forming a gate and the source on the first surface of the second substrate; A drain is formed on the second surface of the second substrate.

[0009] As a possible implementation manner, forming the gate and the source on the first surface of the second substrate includes: After etching a plurality of second grooves on the first surface of the second substrate, a second grooved surface is obtained; After oxidizing the second groove-shaped surface to form a second oxide layer, second polysilicon is filled in the second groove to obtain a substrate structure; The gate and the source are formed on the substrate structure.

[0010] As a possible implementation manner, forming the gate and the source on the substrate structure includes: After etching the first surface of the substrate structure along each second groove position, an isolation layer is formed at the groove position to obtain an isolation surface; After forming a gate oxide layer on the isolation surface, filling gate polysilicon at the trench position on the gate oxide layer; The source is formed in the second substrate below the gate oxide layer.

[0011] As a possible implementation manner, forming the source electrode in the second substrate under the gate oxide layer includes: A first conductive type body region is first formed in the second substrate under the gate oxide layer by ion implantation, and a second conductive type doped region is formed on the first conductive type body region.

[0012] As a possible implementation manner, the method further includes: The capacitance of the capacitor structure is adjusted by adjusting the facing area of ​​the first conductive layer and the second conductive layer; Alternatively, the capacitance of the capacitor structure is adjusted by adjusting the thickness of the first substrate.

[0013] As a possible implementation manner, the first conductivity type is N-type, and the second conductivity type is P-type, or the first conductivity type is P-type, and the second conductivity type is N-type.

[0014] In a second aspect of the embodiment of the present application, a new type of power device is provided, wherein the power device comprises: A capacitor structure and a device structure, wherein a source electrode of the device structure is connected to the capacitor structure; The capacitor structure comprises: A first substrate, the first substrate comprising a first trench oxide surface and a plurality of first polysilicon; The first groove oxidized surface is a surface after a first oxide layer is oxidized on the first grooved surface after a first groove is formed by etching a plurality of first grooves on the first surface of the first substrate, and each first groove in the first groove oxidized surface includes a polysilicon; A first conductive layer, located on the oxidized surface of the first trench, the first conductive layer being connected to each of the first polysilicon; The second conductive layer is located on the second surface of the first substrate.

[0015] The beneficial effects brought by the technical solution provided by the embodiment of the present application include at least: The method for preparing a power device provided in an embodiment of the present application comprises the steps of: etching a first surface of a first substrate to form a plurality of first grooves to obtain a first groove-shaped surface; oxidizing a first oxide layer on the first groove-shaped surface to obtain a first groove oxidized surface, and then filling each first groove with first polysilicon; forming a first conductive layer on the first groove oxidized surface, and connecting the first conductive layer with each first polysilicon; and forming a second conductive layer on the second surface of the first substrate to obtain a capacitor structure; The capacitor structure is connected to the source of the pre-prepared device structure to obtain a target power device, which can increase the output capacitance of the device, reduce the Vds stress of the device under fast shutdown, and further improve the stability of the device. At the same time, the capacitor structure preparation process of the present application is simple. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A flow chart of a method for preparing a novel power device provided in an embodiment of the present application; Figure 2A schematic diagram of a longitudinal section of a device structure provided in an embodiment of the present application; Figure 3 A schematic diagram of a longitudinal section of a capacitor structure provided in an embodiment of the present application.

[0017] Reference numerals: 1-second oxide layer, 2-second polysilicon, 3-isolation layer, 4-gate polysilicon, 5-second passivation layer, 6-gate oxide layer, 7-source, 8-metal electrode, 9-drain, 10-second conductive layer, 11-first oxide layer, 12-first polysilicon, 13-first passivation layer, 14-first conductive layer. DETAILED DESCRIPTION

[0018] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0019] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.

[0020] It should be understood that when an element or layer is referred to as being “on,” “adjacent to,” “connected to,” or “coupled to” another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly adjacent to,” “directly connected to,” or “directly coupled to” another element or layer, there are no intervening elements or layers.

[0021] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present application in a schematic manner, and therefore the illustrations only show components related to the present application rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0022] The present application provides a method for preparing a novel power device, such as Figure 1 As shown, the method comprises the following steps: Step 101, after etching a first surface of a first substrate to form a plurality of first grooves, a first grooved surface is obtained; Step 102, after the first oxide layer is oxidized on the first groove-shaped surface to obtain a first groove oxidized surface, first polysilicon is filled in each first groove; Step 103, after forming a first conductive layer on the oxidized surface of the first trench, connecting the first conductive layer to each of the first polysilicon; Step 104: After forming a second conductive layer on the second surface of the first substrate, a capacitor structure is obtained; Step 105 : Connect the capacitor structure to the source of the pre-fabricated device structure to obtain a target power device.

[0023] The substrate is used as a carrier of the power device and mainly plays a supporting role. The substrate can be made of silicon, germanium or germanium silicon. In this embodiment, the substrate is preferably made of silicon, which is the most common, cheap and stable semiconductor material.

[0024] The substrate has a first surface and a second surface opposite to each other, wherein the first surface can be understood as the front side of the substrate, and the second surface can be understood as the back side of the substrate. The gate region and the source electrode in the device structure are formed on the first surface. The drain electrode in the device structure is formed on the second surface of the substrate.

[0025] Optionally, after forming the first conductive layer on the oxidized surface of the first trench in step 103, connecting the first conductive layer to each of the first polysilicon layers includes: After the first groove is oxidized to form a first passivation layer, a plurality of first etching holes are formed in the first passivation layer to obtain a first etching layer, wherein each first etching hole is etched into the first polysilicon in each first groove; A first conductive layer is formed on the first etched layer, and the first conductive layer is connected to the first polysilicon in each first trench through the first etched hole.

[0026] The capacitor structure can be prepared by the above method. The process for preparing the capacitor structure of the present application is simple and can be prepared by the existing preparation process of power devices.

[0027] It should be noted that the capacitor structure can also be connected to the source of other power devices, and can also increase the output capacitance of other power devices, thereby reducing the Vds stress of other power devices under fast shutdown.

[0028] Optionally, the source electrode includes a source pad, and the source pad includes a contact hole. The above step 104 connects the capacitor structure to the source electrode of the pre-prepared device structure to obtain the target power device, including: The first conductive layer in the capacitor structure is connected to the source electrode through the contact hole.

[0029] In addition, the method further comprises: The capacitance of the capacitor structure is adjusted by adjusting the facing area of ​​the first conductive layer and the second conductive layer; or, the capacitance of the capacitor structure is adjusted by adjusting the thickness of the first substrate.

[0030] The capacitance of the capacitor structure can be adjusted in the above manner, and the Vds stress of the device under fast shutdown can be adjusted, so that the SGT power device can be applied to a variety of scenarios.

[0031] Optionally, before executing the above step 104 of connecting the capacitor structure to the source of the pre-fabricated device structure, the method further includes: forming a gate and the source on the first surface of the second substrate; A drain is formed on the second surface of the second substrate.

[0032] Specifically, the forming of the gate and the source on the first surface of the second substrate includes: After etching a plurality of second grooves on the first surface of the second substrate, a second grooved surface is obtained; After oxidizing the second groove-shaped surface to form a second oxide layer, second polysilicon is filled in the second groove to obtain a substrate structure; The gate and the source are formed on the substrate structure.

[0033] Furthermore, the forming of the gate and the source on the substrate structure comprises: After etching the first surface of the substrate structure along each second groove position, an isolation layer is formed at the groove position to obtain an isolation surface; After forming a gate oxide layer on the isolation surface, filling gate polysilicon at the trench position on the gate oxide layer; The source is formed in the second substrate below the gate oxide layer.

[0034] In addition, forming the source electrode in the second substrate under the gate oxide layer includes: A first conductive type body region is first formed in the second substrate under the gate oxide layer by ion implantation, and a second conductive type doped region is formed on the first conductive type body region.

[0035] The first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0036] The method for preparing a power device provided in an embodiment of the present application comprises the steps of: etching a first surface of a first substrate to form a plurality of first grooves to obtain a first groove-shaped surface; oxidizing a first oxide layer on the first groove-shaped surface to obtain a first groove oxidized surface, and then filling each first groove with first polysilicon; forming a first conductive layer on the first groove oxidized surface, and connecting the first conductive layer with each first polysilicon; and forming a second conductive layer on the second surface of the first substrate to obtain a capacitor structure; The capacitor structure is connected to the source of the pre-prepared device structure to obtain a target power device, which can increase the output capacitance of the device, reduce the Vds stress of the device under fast shutdown, and further improve the stability of the device. At the same time, the capacitor structure preparation process of the present application is simple.

[0037] The embodiment of the present application provides a power device, which includes: a capacitor structure and a device structure, wherein a source of the device structure is connected to the capacitor structure, such as Figure 2 The schematic diagram of the device structure is shown in Figure 3 Shown is a schematic diagram of a capacitor structure.

[0038] The capacitor structure comprises: A first substrate, the first substrate comprising a first trench oxidation surface and a plurality of first polysilicon 12; The first groove oxidized surface is a surface obtained by etching a plurality of first grooves on the first surface of the first substrate to obtain a first grooved surface, and then oxidizing the first grooved surface to obtain a first oxide layer 11, and each first groove in the first groove oxidized surface includes a first polysilicon 12; A first conductive layer 14, located on the first trench oxidation surface, the first conductive layer 14 is connected to each of the first polysilicon 12; The second conductive layer 10 is located on the second surface of the first substrate.

[0039] Optionally, the capacitor structure further includes: A first passivation layer 13, wherein the first passivation layer 13 is formed on the oxidized surface of the first trench, and the first passivation layer 13 includes a plurality of first etching holes, each of which is etched into the first polysilicon 12 in each first trench; A first conductive layer 14 is located on the first passivation layer 13 , and the first conductive layer 14 is connected to the first polysilicon 12 in each first trench through the first etching hole.

[0040] Optionally, the source electrode 7 includes a source electrode pad, and the source electrode pad includes a contact hole, and the contact hole is used to connect the first conductive layer 14 in the capacitor structure with the source electrode 7.

[0041] Optionally, the device structure includes: A gate electrode and a source electrode 7, wherein the gate electrode and the source electrode 7 are located on the first surface of the second substrate; A drain electrode 9 is located on the second surface of the second substrate.

[0042] Optionally, the device structure further includes: a second grooved surface, wherein the second grooved surface is a surface formed by etching a plurality of second grooves on the first surface of the second substrate; A substrate structure, wherein the substrate structure is obtained by oxidizing the second groove-shaped surface to form a second oxide layer 1, and then filling the second groove with second polysilicon 2; The gate and the source 7 are formed on the substrate structure.

[0043] Optionally, the device structure further includes: An isolation surface, wherein the isolation surface is a surface after the first surface of the substrate structure is etched along each second groove position and an isolation layer 3 is formed at the groove position; A gate oxide layer 6 formed on the isolation layer 3; The gate polysilicon 4 is located at the groove position on the gate oxide layer 6; The source electrode 7 is formed in the second substrate below the gate oxide layer 6 .

[0044] Optionally, the power device further includes: A second passivation layer 5 is located on the gate oxide layer 6 and the gate polysilicon 4, wherein the second passivation layer 5 comprises a plurality of second etching holes, each of which is etched into the source electrode 7; The metal electrode 8 is located on the second passivation layer 5 , and the metal electrode 8 is connected to the source electrode 7 through the second etched hole.

[0045] Optionally, the first conductivity type is N-type and the second conductivity type is P-type, or the first conductivity type is P-type and the second conductivity type is N-type.

[0046] Regarding the specific limitations of the power device, reference may be made to the limitations of the method for preparing the novel power device in the embodiments of the present application, and no further details will be given here.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein by equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

[0048] In addition, those skilled in the art will appreciate that, although some embodiments herein include certain features included in other embodiments but not other features, the combination of features of different embodiments is meant to be within the scope of the present application and form different embodiments. For example, in the above claims, any one of the claimed embodiments may be used in any combination. The information disclosed in this background technology section is intended only to deepen the understanding of the overall background technology of the present application and should not be regarded as an admission or in any form of implication that the information constitutes prior art known to those skilled in the art.

Claims

1. A method for preparing a novel power device, characterized in that: The method comprises: After etching a first surface of the first substrate to form a plurality of first grooves, a first grooved surface is obtained; After the first groove-shaped surface is oxidized to form a first oxide layer, a first groove oxidized surface is obtained, and a first polysilicon is filled in each first groove; After forming a first conductive layer on the first trench oxidation surface, connecting the first conductive layer to each of the first polysilicon; After forming a second conductive layer on the second surface of the first substrate, a capacitor structure is obtained; Connecting the capacitor structure to a source electrode of a pre-prepared device structure to obtain a target power device; After forming a first conductive layer on the first trench oxidation surface, connecting the first conductive layer to each of the first polysilicon layers comprises: After the first groove is oxidized to form a first passivation layer, a plurality of first etching holes are formed in the first passivation layer to obtain a first etching layer, wherein each first etching hole is etched into the first polysilicon in each first groove; A first conductive layer is formed on the first etched layer, and the first conductive layer is connected to the first polysilicon in each first trench through the first etched hole.

2. The method according to claim 1, characterized in that The source electrode includes a source electrode pad, and the source electrode pad includes a contact hole. The capacitor structure is connected to the source electrode of the pre-fabricated device structure, including: The first conductive layer in the capacitor structure is connected to the source electrode through the contact hole.

3. The method according to claim 1, characterized in that Before connecting the capacitor structure to the source of the pre-fabricated device structure, the method further includes: forming a gate and the source on the first surface of the second substrate; A drain is formed on the second surface of the second substrate.

4. The method according to claim 3, characterized in that The forming of the gate and the source on the first surface of the second substrate comprises: After etching a plurality of second grooves on the first surface of the second substrate, a second grooved surface is obtained; After oxidizing the second groove-shaped surface to form a second oxide layer, second polysilicon is filled in the second groove to obtain a substrate structure; The gate and the source are formed on the substrate structure.

5. The method according to claim 4, characterized in that The step of forming the gate and the source on the substrate structure comprises: After etching the first surface of the substrate structure along each second groove position, an isolation layer is formed at the groove position to obtain an isolation surface; After forming a gate oxide layer on the isolation surface, filling gate polysilicon at the trench position on the gate oxide layer; The source is formed in the second substrate below the gate oxide layer.

6. The method according to claim 5, characterized in that The forming of the source electrode in the second substrate under the gate oxide layer comprises: A first conductive type body region is first formed in the second substrate under the gate oxide layer by ion implantation, and a second conductive type doped region is formed on the first conductive type body region.

7. The method according to claim 1, characterized in that The method further comprises: The capacitance of the capacitor structure is adjusted by adjusting the facing area of ​​the first conductive layer and the second conductive layer; Alternatively, the capacitance of the capacitor structure is adjusted by adjusting the thickness of the first substrate.

8. The method according to claim 6, characterized in that The first conductivity type is N type and the second conductivity type is P type, or the first conductivity type is P type and the second conductivity type is N type.

9. A power device, characterized in that: The power device comprises: A capacitor structure and a device structure, wherein a source electrode of the device structure is connected to the capacitor structure; The capacitor structure comprises: A first substrate, the first substrate comprising a first trench oxide surface and a plurality of first polysilicon; The first groove oxidized surface is a surface obtained by etching a plurality of first grooves on the first surface of the first substrate to obtain a first grooved surface, and then oxidizing the first grooved surface to obtain a first oxide layer, and each first groove in the first groove oxidized surface includes a polysilicon; A first conductive layer, located on the oxidized surface of the first trench, the first conductive layer being connected to each of the first polysilicon; A second conductive layer, located on the second surface of the first substrate; The capacitor structure further includes: A first passivation layer, wherein the first passivation layer is formed on the oxidized surface of the first trench, and the first passivation layer includes a plurality of first etching holes, each of which is etched into the first polysilicon in each first trench; A first conductive layer, wherein the first conductive layer is located on the first passivation layer, and the first conductive layer is connected to the first polysilicon in each first trench through the first etching hole.

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