Semiconductor device and preparation method

Abstract

The invention provides a semiconductor device and a preparation method thereof. The semiconductor device comprises a gallium nitride epitaxial wafer; the first dielectric layer, the second dielectric layer and the third dielectric layer are sequentially deposited on the upper surface of the gallium nitride epitaxial wafer, a grid electrode is arranged in the second dielectric layer, and a first source electrode field plate is arranged between the second dielectric layer and the third dielectric layer; the first drain electrode is deposited at one end of the upper surface of the gallium nitride epitaxial wafer, and the second drain electrode is arranged on the upper surface of the first drain electrode; the first source is deposited on the upper surface of one end, far away from the first drain, of the gallium nitride epitaxial wafer, and the second source is arranged on the upper surface of the first source; the second source field plate is deposited on the upper surface of the third dielectric layer; and the passivation layer is deposited on the upper surface of the third dielectric layer, and the lower surface of the passivation layer is in contact with the upper surfaces of the second source electrode field, the second drain electrode and the second source electrode. According to the invention, the breakdown voltage effect can be effectively improved, and the purpose of realizing a plurality of field plates without adding extra process levels can be achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a preparation method thereof. Background Art

[0002] In application areas such as wind power generation, photovoltaic energy storage, electric vehicles, chargers, etc., different forms of power conversion are key technologies. These power conversions include converting DC into AC, converting AC into DC, and converting DC at different voltage levels into each other.

[0003] Among the power conversion components, power switch semiconductor devices are key components. The switching speed, switching loss, breakdown voltage capability, size, and cost of power switch semiconductor devices are key factors affecting their commercial use. Simply put, the performance, price, and size of power switch semiconductor devices are the compromises that need to be considered during product design.

[0004] At present, power switch semiconductor devices can be simply divided into two categories: one is based on the first generation of semiconductor materials, such as IGBT, Power MOS, etc.; the other is based on the third generation of semiconductor materials, such as gallium nitride high electron mobility transistor (GaN HEMT), SiC MOS, etc. Among them, GaN HEMT is a very important type of power semiconductor device, which has a wide range of application scenarios in power electronics design, such as fast chargers for mobile devices, electric vehicle charging piles, etc.

[0005] There are three main technical routes for the design and manufacture of GaN HEMT semiconductor devices. One is to grow GaN epitaxy based on SiC substrate and then manufacture GaN HEMT semiconductor devices. It is expensive and mainly used in the field of radio frequency microwaves. One is to grow GaN epitaxy based on Si substrate and then manufacture GaN HEMT semiconductor devices. It is cheap and mainly used in the field of power electronics with a withstand voltage requirement of less than 650V. One is to grow GaN epitaxy based on sapphire substrate and then manufacture GaN HEMT semiconductor devices. It is cheap and can be used in the field of power electronics with a withstand voltage requirement of 1200V. It is a current research hotspot. Regardless of which of the above technical routes is used, the method of achieving high breakdown voltage and high reliability by suppressing the electric field peak in the channel of GaN HEMT semiconductor devices is very common, and field plate technology is a common device structure for suppressing the electric field peak, so the field plate structure design and manufacturing method of GaNHEMT semiconductor devices is a key technology.

[0006] In the prior art, most commercial GaN HEMT semiconductor devices use a combination of one gate field plate and one source field plate. This structural design and manufacturing process are simple, but the disadvantage is that it is difficult to achieve a higher breakdown voltage. In order to further suppress the electric field peak in the channel of the GaN HEMT semiconductor device and achieve a higher breakdown voltage, the prior art chooses to use a combination of one gate field plate and multiple source field plates. This combination has two disadvantages: 1. Additional process levels need to be added to achieve multiple field plates; 2. The simple combination of multiple source field plates cannot effectively suppress the peak electric field and cannot achieve the effect of increasing the breakdown voltage. Summary of the invention

[0007] Based on this, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to at least solve the above-mentioned deficiencies in the prior art.

[0008] In a first aspect, the present invention provides a semiconductor device, comprising:

[0009] GaN epitaxial wafers;

[0010] A first dielectric layer, a second dielectric layer and a third dielectric layer are sequentially deposited on the upper surface of the gallium nitride epitaxial wafer, a gate is provided in the second dielectric layer, the bottom of the gate penetrates the first dielectric layer and contacts the upper surface of the gallium nitride epitaxial wafer, a first source field plate is provided between the second dielectric layer and the third dielectric layer, wherein the first dielectric layer, the second dielectric layer, the first source field plate and the gallium nitride epitaxial wafer constitute a semiconductor structure MIS1, and the threshold voltage of the semiconductor structure MIS1 is 30-50%*Vbr, where Vbr represents the breakdown voltage design value of the semiconductor device;

[0011] A first drain electrode and a second drain electrode, wherein the first drain electrode is deposited on one end of the upper surface of the gallium nitride epitaxial wafer, and the second drain electrode is arranged on the upper surface of the first drain electrode;

[0012] A first source electrode and a second source electrode, wherein the first source electrode is deposited on an upper surface of the gallium nitride epitaxial wafer away from an end of the first drain electrode, and the second source electrode is disposed on an upper surface of the first source electrode;

[0013] A second source field plate is deposited on the upper surface of the third dielectric layer, wherein the first dielectric layer, the second dielectric layer, the third dielectric layer, the second source field plate and the gallium nitride epitaxial wafer constitute a semiconductor structure MIS2, and the threshold voltage of the semiconductor structure MIS2 is 70-90%*Vbr;

[0014] A passivation layer is deposited on the upper surface of the third dielectric layer, and the lower surface of the passivation layer is in contact with the upper surfaces of the second source field, the second drain and the second source.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: a semiconductor structure MIS1 is formed by a first source field plate, a first dielectric layer, a second dielectric layer and a gallium nitride epitaxial wafer, so that the breakdown voltage of the semiconductor structure MISI is greater than the design breakdown voltage of GaN HEMT, and a metal dielectric semiconductor structure MIS2 is formed by a second source field plate, a first dielectric layer, a second dielectric layer, a third dielectric layer and a gallium nitride epitaxial wafer, and the threshold voltage of the metal dielectric semiconductor structure MIS2 is the design breakdown voltage of GaN HEMT, thereby effectively improving the effect of the breakdown voltage, and being able to simultaneously form a first source field plate, a first source and a first drain, and being able to simultaneously form a second source field plate, a second source and a second drain, thereby achieving the purpose of realizing multiple field plates without adding additional process levels.

[0016] Furthermore, a side wall of the first drain electrode contacts with a side wall of the first dielectric layer and a side wall of the second dielectric layer, and a side wall of the second drain electrode contacts with a side wall of the second dielectric layer and a side wall of the third dielectric layer.

[0017] Furthermore, a side wall of the first source electrode contacts with a side wall of the first dielectric layer and a side wall of the second dielectric layer, and a side wall of the second source electrode contacts with a side wall of the second dielectric layer and a side wall of the third dielectric layer.

[0018] Furthermore, the gallium nitride epitaxial wafer includes a sapphire substrate and a gallium nitride epitaxial layer, and the gallium nitride epitaxial layer is arranged on the upper surface of the sapphire substrate.

[0019] Furthermore, the first dielectric layer, the second dielectric layer and the third dielectric layer are all made of silicon dioxide or silicon nitride, and the thickness of the first dielectric layer, the second dielectric layer and the third dielectric layer is 10 nm to 200 nm.

[0020] Furthermore, a protruding structure is provided on the upper surface of the second dielectric layer, and a side wall of the first source field plate is in contact with a side wall of the protruding structure.

[0021] Furthermore, the upper surface of the third dielectric layer is arranged in a step-type structure, and the side wall of the second source field plate is in contact with a side wall of the step-type structure.

[0022] Furthermore, a gate groove for passing the gate is provided on the first dielectric layer, the length of the gate groove is greater than 1 μm, the gate is composed of nickel and gold or titanium-tungsten alloy and gold, and the thickness of the gate is 100 nm to 1000 nm.

[0023] Furthermore, a third source field plate is deposited on the upper surface of the passivation layer, and the first source field plate, the second source field plate, the third source field plate and the gallium nitride epitaxial wafer constitute a semiconductor structure MIS3, and a threshold voltage of the semiconductor structure MIS3 is 80-90%*Vbr.

[0024] In a second aspect, the present invention further provides a method for preparing a semiconductor device, which is used to prepare the semiconductor device as described above, and the method comprises:

[0025] Providing a gallium nitride epitaxial wafer;

[0026] Depositing a first dielectric layer on the gallium nitride epitaxial wafer, depositing a gate metal film on the first dielectric layer, and performing a stripping process on the gate metal film to obtain a gate;

[0027] Depositing a second dielectric layer on the upper surface of the gate, etching two ends of the second dielectric layer to obtain two etched areas, depositing a first drain and a first source on the two etched areas by a low-temperature ohmic process, and depositing a first source field plate on the second dielectric layer;

[0028] Depositing a third dielectric layer on the upper surfaces of the first drain, the first source, and the first source field plate, and etching two opening areas at both ends of the third dielectric layer;

[0029] Forming a second drain electrode in one of the opening regions, forming a second source electrode in another of the opening regions, and forming a second source field plate on the upper surface of the third dielectric layer by metal evaporation or electroplating, wherein the second drain electrode is in contact with the first drain electrode, and the second source electrode is in contact with the first source electrode;

[0030] A passivation layer is deposited on the second drain, the second source, the third dielectric layer, and the second source field plate. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 is a schematic structural diagram of a semiconductor device in a first embodiment of the present invention;

[0032] Figure 2 is a schematic structural diagram of a gallium nitride epitaxial wafer of a semiconductor device in a first embodiment of the present invention;

[0033] Figure 3 It is a schematic diagram of the structure of preparing the gate trench of the semiconductor device in the first embodiment of the present invention;

[0034] Figure 4 It is a schematic diagram of the preparation structure of the first source, the first drain and the first source field plate of the semiconductor device in the first embodiment of the present invention;

[0035] Figure 5 It is a schematic diagram of the preparation structure of the second source field plate of the semiconductor device in the first embodiment of the present invention;

[0036] Figure 6 is a schematic structural diagram of a semiconductor device in a second embodiment of the present invention;

[0037] Figure 7 FIG. 4 is a flow chart of a method for manufacturing a semiconductor device in a third embodiment of the present invention.

[0038] Description of main component symbols:

[0039] 100, GaN epitaxial wafer; 101, sapphire substrate; 102, GaN epitaxial layer; 113, first dielectric layer; 112, second dielectric layer; 111, third dielectric layer; 103, first drain; 104, second drain; 106, first source; 107, second source; 108, gate; 109, second source field plate; 110, second source field plate; 105, passivation layer;

[0040] 200, gate groove; 211, third source field plate.

[0041] The following specific implementation manner will further illustrate the present invention in conjunction with the above-mentioned drawings. DETAILED DESCRIPTION

[0042] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0043] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0044] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0045] Embodiment 1

[0046] See also Figures 1 to 5 , shown is a semiconductor device in the first embodiment of the present invention, including a gallium nitride epitaxial wafer 100, a first dielectric layer 113, a second dielectric layer 112, a third dielectric layer 111, a first drain 103, a second drain 104, a first source 106, a second source 107, a second source field plate 110 and a passivation layer 105.

[0047] The first dielectric layer 113, the second dielectric layer 112 and the third dielectric layer 111 are sequentially deposited on the upper surface of the gallium nitride epitaxial wafer 100, a gate electrode 108 is provided in the second dielectric layer 112, the bottom of the gate electrode 108 penetrates the first dielectric layer 113 and contacts the upper surface of the gallium nitride epitaxial wafer 100, a first source field plate 109 is provided between the second dielectric layer 112 and the third dielectric layer 111, wherein the first dielectric layer 113, the second dielectric layer 112, the first source field plate 110 and the gallium nitride epitaxial wafer 100 form a semiconductor structure MIS1, the threshold voltage of the semiconductor structure MIS1 is 30-50%*Vbr, Vbr represents the breakdown voltage design value of the semiconductor device, the first drain electrode 103 is deposited at one end of the upper surface of the gallium nitride epitaxial wafer 100, and the second drain electrode 109 is deposited at one end of the upper surface of the gallium nitride epitaxial wafer 100. The first source 106 is deposited on the upper surface of the gallium nitride epitaxial wafer 100 away from the first drain 103, the second source 107 is arranged on the upper surface of the first source 106, and the second source field plate 110 is deposited on the upper surface of the third dielectric layer 111, wherein the first dielectric layer 113, the second dielectric layer 112, the third dielectric layer 111, the second source field plate 110 and the gallium nitride epitaxial wafer 100 constitute a semiconductor structure MIS2, the threshold voltage of the semiconductor structure MIS2 is 70-90%*Vbr, the passivation layer 105 is deposited on the upper surface of the third dielectric layer 111, and the lower surface of the passivation layer 105 is in contact with the upper surfaces of the second source field plate 110, the second drain 107 and the second source 104.

[0048] It should be noted that the gate 108 is first manufactured on the GaN epitaxial wafer 100 , and then the first source 106 and the first drain 103 are manufactured at a low temperature to prevent the high temperature process from damaging the gate 108 metal.

[0049] It is worth noting that a protruding structure is provided on the upper surface of the second dielectric layer 112, and the sidewall of the first source field plate 109 contacts one sidewall of the protruding structure. The upper surface of the third dielectric layer 111 is arranged in a stepped structure, and the sidewall of the second source field plate 110 contacts one sidewall of the stepped structure.

[0050] In addition, it can be understood that a second dielectric layer 112 is formed on the gate electrode 108, and an opening area of ​​the first source electrode 106 and the first drain electrode 103 is formed on the second dielectric layer 112 by dry etching, and then the first source electrode 106 and the first drain electrode 103 are prepared in the opening area. In order to form a good metal semiconductor, the second dielectric layer 112 needs to be overetched, and a part of the thickness is also etched on the gallium nitride epitaxial wafer 100. In the process of preparing the first source 106 and the first drain 103, the first source 106 and the first drain 103 are prepared by a low temperature ohmic process, the purpose is to protect the prepared gate 108 metal from being damaged by high temperature, and the first source 106, the first drain 103 and the first source field plate 109 are prepared in the same process step, the first source 106, the first drain 103 and the first source field plate 109 are made of titanium and aluminum. In this embodiment, the thickness of the first source field plate 109 is 400nm of titanium and aluminum. In other optional embodiments, the first source field plate 109 is made of titanium and gold. In order to achieve a high breakdown voltage of the GaN HEMT, the distance between the gate 108 and the first source 106 is required to be 1.5μm, and the distance between the gate 108 and the first drain 103 is required to be 18μm. In other optional embodiments, the distance between the gate 108 and the first source 106 is greater than 1μm, and the distance between the gate 108 and the first drain 103 is greater than 15μm.

[0051] It should be noted that the first source field plate 109, the second dielectric layer 112, the first dielectric layer 113 and the gallium nitride epitaxial wafer 100 form a metal-dielectric-semiconductor structure MIS1, and the threshold voltage of the MIS1 structure is required to be 30-50% of the design value of the breakdown voltage of the GaN HEMT, and the breakdown voltage of the MIS1 structure is greater than 50% of the design value of the breakdown voltage of the GaN HEMT. Because the second dielectric layer 112 and the first dielectric layer 113 are composed of insulating materials with a high critical breakdown electric field, the breakdown voltage of the MIS structure can easily meet the requirement of being greater than 50% of the design value of the breakdown voltage of the GaN HEMT, so the design of the threshold voltage of the MIS structure is given priority in the device structure design. The second source field plate 110, the third dielectric layer 111, the second dielectric layer 112, the first dielectric layer 113, and the gallium nitride epitaxial wafer 100 form a metal-dielectric-semiconductor structure MIS2, and the threshold voltage of the MIS2 structure is required to be 70-90% of the design value of the breakdown voltage of the GaN HEMT, and the breakdown voltage of the MIS2 structure is greater than 100% of the design value of the breakdown voltage of the GaN HEMT. Because the third dielectric layer 111, the second dielectric layer 112, and the first dielectric layer 113 are composed of insulating materials with equal high critical breakdown electric fields, the breakdown voltage of the MIS structure can easily meet the requirement of being greater than 100% of the design value of the breakdown voltage of the GaN HEMT, so the design of the threshold voltage of the MIS structure is given priority in the device structure design.

[0052] It is worth noting that the opening area of ​​the second source 107 and the second drain 104 is formed on the third dielectric layer 111 by dry etching, and the etching depth is required to penetrate the third dielectric layer 111, and then the second source 107, the second drain 104 and the second source field plate 110 are formed on the third dielectric layer 111 by metal evaporation or electroplating, wherein the second source 107 and the second drain 104 are in the opening area, and this layer of metal can be called interconnection metal in the process flow, which plays the role of interconnecting different layers of metal outside the active area.

[0053] In addition, the passivation layer 105 can protect the metal of the second source 107, the second drain 104 and the second source field plate 110 from being damaged. In the present embodiment, the passivation layer 105 is made of silicon nitride and is prepared by low-pressure chemical vapor deposition. In other optional embodiments, the passivation layer 105 is one of silicon dioxide or silicon nitride, and the passivation layer 105 is made by one of plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD).

[0054] Specifically, the side wall of the first drain 103 contacts the side wall of the first dielectric layer 113 and the second dielectric layer 112, the side wall of the second drain 106 contacts the side wall of the second dielectric layer 112 and the third dielectric layer 111, the side wall of the first source 106 contacts the side wall of the first dielectric layer 113 and the second dielectric layer 112, and the side wall of the second source 107 contacts the side wall of the second dielectric layer 112 and the third dielectric layer 111.

[0055] It should be noted that, in the present embodiment, the gallium nitride epitaxial wafer 100 includes a sapphire substrate 101 and a gallium nitride epitaxial layer 102. The gallium nitride epitaxial layer 102 is arranged on the upper surface of the sapphire substrate 101. The gallium nitride epitaxial wafer 100 of the sapphire substrate 101 is prepared by metal organic chemical vapor deposition. In other optional embodiments, the gallium nitride epitaxial layer 102 is composed of a nucleation layer, a buffer layer, a channel layer, a barrier layer and a cap layer.

[0056] Specifically, in this embodiment, the first dielectric layer 113, the second dielectric layer 112, and the third dielectric layer 111 are all silicon nitride, and the thickness of the first dielectric layer 113, the second dielectric layer 112, and the third dielectric layer 111 is 40 nm. In other optional embodiments, the first dielectric layer 113, the second dielectric layer 112, and the third dielectric layer 111 are all one of silicon dioxide or silicon nitride, and the thickness of the first dielectric layer 113, the second dielectric layer 112, and the third dielectric layer 111 is 10 nm to 200 nm. In addition, the first dielectric layer 113, the second dielectric layer 112, and the third dielectric layer 111 can be a single-layer dielectric, or a multi-layer dielectric of different materials formed by multiple substrate processes.

[0057] It should be noted that, in the present embodiment, the first dielectric layer 13, the second dielectric layer 112 and the third dielectric layer 111 are obtained by depositing silicon nitride dielectric using LPCVD. In other optional embodiments, the first dielectric layer 13, the second dielectric layer 112 and the third dielectric layer 111 can be prepared using one of low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD).

[0058] Specifically, in this embodiment, a gate groove 200 for passing the gate 108 is provided on the first dielectric layer 113, the length of the gate groove 200 is 1.5 μm, the gate 108 is composed of nickel and gold or titanium tungsten alloy and gold, and the thickness of the gate 108 is 400 nm. In other optional embodiments, the length of the gate groove 200 is greater than 1.0 μm, and the thickness of the gate 108 is 100 nm to 1000 nm.

[0059] It should be noted that a hole is opened on the first dielectric layer 113 to manufacture the gate groove 200. The size and position of the gate groove 200 are determined by the photomask. The gate groove 200 on the first dielectric layer 113 is realized by anisotropic dry etching. The type of the gate 108 determines whether the gate groove 200 penetrates the first dielectric layer 113. If the Schottky gate type is selected, the gate 108 is required to be in contact with the gallium nitride epitaxial wafer 100, that is, the gate groove 200 is etched through the first dielectric layer 113; if the metal-dielectric layer-semiconductor gate type is selected, a dielectric layer of a certain thickness is required between the gate 108 and the gallium nitride epitaxial wafer 100, that is, the gate groove is not etched through the first dielectric layer 113.

[0060] It is worth noting that a gate metal film is deposited on the first dielectric layer 113 by a magnetron sputtering process or a metal evaporation process, and then a gate metal is formed by dry etching or a lift-off stripping process. The gate metal is composed of multiple layers of metal. In this embodiment, the gate metal is composed of nickel and gold, that is, the gate 108 is composed of nickel and gold. In other optional embodiments, the gate metal is composed of titanium-tungsten alloy and gold, that is, the gate 108 is composed of titanium-tungsten alloy and gold. Then, the gate 108 is obtained by performing metal evaporation on the gate metal and then performing a lift-off stripping process.

[0061] Embodiment 2

[0062] Please refer to Figure 6 , shown is a semiconductor device in a second embodiment of the present invention. The difference between the semiconductor device in this embodiment and the semiconductor device in the first embodiment is that a third source field plate 211 is deposited on the upper surface of the passivation layer 105 .

[0063] The first source field plate 109, the second source field plate 110, the third source field plate 211 and the gallium nitride epitaxial wafer 100 form a semiconductor structure MIS3, the threshold voltage of the semiconductor structure MIS3 is 80-90%*Vbr, and the MIS3 structure can also realize the design of GaN HEMT devices with a breakdown voltage greater than 1200V.

[0064] Among them, the relationship between the threshold voltage value of the MIS structure with different source field plate compositions and the design Vbr of the GaN HEMT device is shown in Table 1:

[0065] Table 1

[0066]

[0067] In Table 1, the MIS1 threshold voltage corresponds to the first source field plate 109 in the first embodiment, the MIS2 threshold voltage corresponds to the second source field plate 110 in the first embodiment, and the MIS3 threshold voltage corresponds to the third source field plate 211 in the second embodiment.

[0068] In summary, the semiconductor device in the above embodiment of the present invention forms a semiconductor structure MIS1 through the first source field plate 109, the first dielectric layer 113, the second dielectric layer 112 and the gallium nitride epitaxial wafer 100, so that the breakdown voltage of the semiconductor structure MIS1 is greater than the design value of the breakdown voltage of the GaN HEMT, and the second source field plate 110, the first dielectric layer 113, the second dielectric layer 112, the third dielectric layer 111 and the gallium nitride epitaxial wafer 100 form a metal dielectric semiconductor structure MIS2, and the threshold voltage of the metal dielectric semiconductor structure MIS2 is the design value of the breakdown voltage of the GaN HEMT, thereby effectively improving the effect of the breakdown voltage, and simultaneously forming the first source field plate 109, the first source 106 and the first drain 103, and simultaneously forming the second source field plate 110, the second source 107 and the second drain 104, thereby achieving the purpose of realizing multiple field plates without adding additional process layers.

[0069] Embodiment 3

[0070] See also Figure 7 , shown is a method for preparing a semiconductor device in a third embodiment of the present invention, which is used to prepare the semiconductor device in the above embodiment, and the method includes steps S1 to S6:

[0071] S1, providing a gallium nitride epitaxial 100;

[0072] S2, depositing a first dielectric layer 113 on the gallium nitride epitaxial wafer, depositing a gate metal film on the first dielectric layer 113, and performing a stripping process on the gate metal film to obtain a gate 108;

[0073] S3, depositing a second dielectric layer 112 on the upper surface of the gate, etching two ends of the second dielectric layer 112 to obtain two etched regions, depositing a first drain 103 and a first source 106 in the two etched regions by a low-temperature ohmic process, and depositing a first source field plate 109 on the second dielectric layer 112;

[0074] S4, depositing a third dielectric layer 111 on the upper surfaces of the first drain 103, the first source 106 and the first source field plate 109, and etching two opening areas at both ends of the third dielectric layer 111;

[0075] S5, forming a second drain electrode 104 in one of the opening regions, forming a second source electrode 107 in another of the opening regions, and forming a second source field plate 110 on the upper surface of the third dielectric layer 111 by metal evaporation or electroplating, wherein the second drain electrode 104 is in contact with the first drain electrode 103, and the second source electrode 107 is in contact with the first source electrode 106;

[0076] S6 , depositing a passivation layer 105 on the second drain 104 , the second source 107 , the third dielectric layer 111 and the second source field plate 110 .

[0077] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0078] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A semiconductor device, characterized in that: include: GaN epitaxial wafers; A first dielectric layer, a second dielectric layer and a third dielectric layer are sequentially deposited on the upper surface of the gallium nitride epitaxial wafer, a gate is provided in the second dielectric layer, the bottom of the gate penetrates the first dielectric layer and contacts the upper surface of the gallium nitride epitaxial wafer, a first source field plate is provided between the second dielectric layer and the third dielectric layer, wherein the first dielectric layer, the second dielectric layer, the first source field plate and the gallium nitride epitaxial wafer constitute a semiconductor structure MIS1, and the threshold voltage of the semiconductor structure MIS1 is 30-50%*Vbr, where Vbr represents the breakdown voltage design value of the semiconductor device; A first drain electrode and a second drain electrode, wherein the first drain electrode is deposited on one end of the upper surface of the gallium nitride epitaxial wafer, and the second drain electrode is arranged on the upper surface of the first drain electrode; A first source electrode and a second source electrode, wherein the first source electrode is deposited on an upper surface of the gallium nitride epitaxial wafer away from an end of the first drain electrode, and the second source electrode is disposed on an upper surface of the first source electrode; A second source field plate is deposited on the upper surface of the third dielectric layer, wherein the first dielectric layer, the second dielectric layer, the third dielectric layer, the second source field plate and the gallium nitride epitaxial wafer constitute a semiconductor structure MIS2, and the threshold voltage of the semiconductor structure MIS2 is 70-90%*Vbr; A passivation layer is deposited on the upper surface of the third dielectric layer, and the lower surface of the passivation layer is in contact with the upper surfaces of the second source field, the second drain and the second source.

2. The semiconductor device according to claim 1, wherein: The sidewall of the first drain electrode contacts the sidewalls of the first dielectric layer and the second dielectric layer, and the sidewall of the second drain electrode contacts the sidewalls of the second dielectric layer and the third dielectric layer.

3. The semiconductor device according to claim 1, wherein: The sidewall of the first source electrode contacts the sidewalls of the first dielectric layer and the second dielectric layer, and the sidewall of the second source electrode contacts the sidewalls of the second dielectric layer and the third dielectric layer.

4. The semiconductor device according to claim 1, wherein: The gallium nitride epitaxial wafer comprises a sapphire substrate and a gallium nitride epitaxial layer, and the gallium nitride epitaxial layer is arranged on the upper surface of the sapphire substrate.

5. The semiconductor device according to claim 1, wherein: The first dielectric layer, the second dielectric layer and the third dielectric layer are all made of silicon dioxide or silicon nitride, and the thickness of the first dielectric layer, the second dielectric layer and the third dielectric layer is 10 nm to 200 nm.

6. The semiconductor device according to claim 1, wherein: A protruding structure is provided on the upper surface of the second dielectric layer, and a side wall of the first source field plate is in contact with a side wall of the protruding structure.

7. The semiconductor device according to claim 1, wherein: The upper surface of the third dielectric layer is arranged in a step-type structure, and the side wall of the second source field plate contacts a side wall of the step-type structure.

8. The semiconductor device according to claim 1, wherein: A gate groove for passing the gate is provided on the first dielectric layer. The length of the gate groove is greater than 1 μm. The gate is composed of nickel and gold or titanium-tungsten alloy and gold. The thickness of the gate is 100 nm to 1000 nm.

9. The semiconductor device according to claim 1, wherein: A third source field plate is deposited on the upper surface of the passivation layer. The first source field plate, the second source field plate, the third source field plate and the gallium nitride epitaxial wafer constitute a semiconductor structure MIS3. The threshold voltage of the semiconductor structure MIS3 is 80-90%*Vbr.

10. A method for preparing a semiconductor device, used for preparing the semiconductor device according to any one of claims 1 to 9, characterized in that: The method comprises: Providing a gallium nitride epitaxial wafer; Depositing a first dielectric layer on the gallium nitride epitaxial wafer, depositing a gate metal film on the first dielectric layer, and performing a stripping process on the gate metal film to obtain a gate; Depositing a second dielectric layer on the upper surface of the gate, etching two ends of the second dielectric layer to obtain two etched areas, depositing a first drain and a first source on the two etched areas by a low-temperature ohmic process, and depositing a first source field plate on the second dielectric layer; Depositing a third dielectric layer on the upper surfaces of the first drain, the first source, and the first source field plate, and etching two opening areas at both ends of the third dielectric layer; Forming a second drain electrode in one of the opening regions, forming a second source electrode in another of the opening regions, and forming a second source field plate on the upper surface of the third dielectric layer by metal evaporation or electroplating, wherein the second drain electrode is in contact with the first drain electrode, and the second source electrode is in contact with the first source electrode; A passivation layer is deposited on the second drain, the second source, the third dielectric layer, and the second source field plate.

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