SGT device

Abstract

An SGT device includes a drift region, a channel region on a surface of the drift region, and a plurality of gate trenches through the channel region. And in the primitive cell region, a source field plate and a gate conductive material layer are simultaneously formed in the gate trench, the side surface of the gate conductive material layer also covers the top region of the drift region at the bottom of the channel region, and the gate conductive material layer forms the gate field plate for transversely depleting the top region of the drift region during reverse biasing. In the source electrode field plate leading-out region, a source electrode field plate is formed in the grid electrode groove and is not provided with a grid electrode conductive material layer, a first compensation region is formed in the interface region of the channel region and the drift region at the bottom, and compensation injection impurities are added in the first compensation region so as to improve the depletion capability of the top region of the drift region. According to the invention, the doping concentration of the drift region in the primitive cell region is relatively high, so that the specific on-resistance of the device is reduced, the weakness of the top region of the drift region in the source field plate extraction region is eliminated, and the withstand voltage of the device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a shielded gate trench (SGT) device. Background Art

[0002] Compared with traditional trench MOSFET, SGT MOSFET adds a source field plate in the drift region. Through the lateral depletion of the drift region by the source field plate, the doping concentration of the drift region can be greatly increased without reducing the breakdown voltage, thereby reducing the specific on-resistance. At the same time, for SGT MOSFET, due to the shielding of the gate by the source field plate, its gate-drain capacitance Cgd is also greatly reduced, and its switching speed is also greatly improved.

[0003] Therefore, SGT MOSFET is replacing trench MOSFET in more and more occasions and becoming the mainstream of power devices.

[0004] The source field plate is usually located directly below the device cell of an SGT MOSFET.

[0005] like Figure 1 As shown in FIG. 1 , it is a schematic diagram of the structure of a device unit in the primitive cell region of an existing SGT MOSFET; Figure 2A FIG. 1 is a schematic diagram of a first structure of a lead-out region of a source field plate 104 of an existing SGT MOSFET; taking an N-type device as an example, the existing SGT MOSFET includes:

[0006] The heavily doped N-type substrate 101 is such as a silicon substrate, and the substrate 101 is connected to the drain. In order to reduce the back diffusion of the substrate 101, an arsenic substrate 101 is usually selected. In order to reduce the resistance of the substrate 101, the higher the doping concentration of the substrate 101, the better, and the thinner the thickness of the substrate 101, the better. The thinned substrate 101 serves as a drain region. The back of the drain region will form a drain composed of a back metal layer.

[0007] The drift region 102 , the doping concentration and thickness of the drift region 102 determine the breakdown voltage of the device; the drift region 102 can be uniformly doped or variably doped.

[0008] The source field plate 104 is usually made of polysilicon.

[0009] The shielding dielectric layer 3 between the source field plate 104 and the inner surface of the gate trench is the isolation layer, and the material is usually SiO2; the depth of the source field plate 104 and the thickness of the shielding dielectric layer 3 determine the breakdown voltage of the device. The higher the breakdown voltage of the device, the deeper the source field plate 104 is. The depth of the source field plate 104 is the longitudinal dimension of the source field plate 104, and the thickness of the shielding dielectric layer 3 is also thicker; for a 100V SGT MOSFET, the depth of the source field plate 104 is usually between 5 and 6μm, and the thickness of the shielding dielectric layer 3 is usually between 10 and 20μm. between.

[0010] A gate conductive material layer 105 such as a polysilicon gate and a gate oxide layer 106 are formed in the gate trench. Figure 1 In the embodiment, the gate structure is a top-bottom structure, the gate conductive material layer 105 is located on the top of the source field plate 104, and there is an inter-gate dielectric layer 112 therebetween, and the inter-gate dielectric layer 112 is usually an oxide layer.

[0011] A P-type doped channel region 107 is formed on the top of the drift region 102, and a source region 108 is formed on the top surface of the channel region 107. A contact hole, i.e., a through hole (CT) 109, is formed on the top of the source region 108, which passes through the interlayer film 111, and the contact hole 109 on the top of the source region 108 also passes through the source region 108 and contacts the channel region 107. Usually, the position where the contact hole 109 is formed on the top of the source region 108 is in the middle of the mesa region (mesa) between the gate trenches. In order to ensure that the contact hole 109 formed on the top of the source region 108 and the channel region 107 can form a good ohmic contact, a through hole injection is usually added directly below the contact hole 109 formed on the top of the source region 108 to form a heavily doped P-type layer. The injection impurities of the through hole injection are usually BF2, the injection energy is between 10keV and 50keV, and the injection dose is usually 1e14cm -2 ~5e15cm -2 between.

[0012] The top of the source region 108 is formed with a contact hole 109 and is connected to the source electrode formed by the front metal layer 110. The gate conductive material layer 105 is also connected to the gate electrode (not shown) formed by the front metal layer 110. Figure 1 Only the front metal layer 110 corresponding to the source is shown, and the front metal layer 110 corresponding to the gate is not shown. Figure 1 At the corresponding cross-sectional position. When a positive voltage is applied to the gate, the channel is inverted and current flows from the source to the drain.

[0013] For SGT MOSFET, its source field plate 104 needs to be connected to the source. The source field plate 104 is usually connected in the following two ways:

[0014] like Figure 2A , which is a schematic diagram of the first structure of the source field plate lead-out region of the existing SGT MOSFET; in the source field plate lead-out region, the gate trench does not have a gate conductive material layer 105. In the first structure, the source field plate 104 and Figure 1 The source field plate 104 in the original cell region shown is formed by the same process, undergoes the same deposition and back etching process, and has the same position of the top surface. In the source field plate lead-out region, the top area of ​​the source field plate 104 will be filled with a dielectric layer 113, and the dielectric layer 113 can be implemented by an interlayer film 111, or can be formed by a dielectric growth process independent of the interlayer film 111. The source field plate 104 in the source field plate lead-out region will be connected to the source through a deep contact hole (deep CT) 114 passing through the interlayer film 111 and the dielectric layer 113. In the source field plate lead-out region, there is usually no source injection, that is, no source region 108 is formed. The source field plate 104 in the original cell region and the source field plate 104 in the source field plate lead-out region will contact each other and be connected to the source through the deep contact hole 114 at the top of the source field plate 104 in the source field plate lead-out region.

[0015] like Figure 2B , which is a schematic diagram of a second structure of the source field plate lead-out region of an existing SGT MOSFET; Figure 2B In the example, the source field plate in the source field plate lead-out region is individually indicated by reference numeral 104a, and Figure 1 Different from the source field plate 104 of FIG. 1 , the top surface of the source field plate 104 a is flush with the gate trench, that is, it is not etched back below the top surface of the gate trench. Thus, the top of the source field plate 104 a is directly connected to the source through a contact hole 109 .

[0016] The structures of the original cell region and the source field plate lead-out region are connected in parallel, and both need to withstand the breakdown voltage of the device; when bearing the breakdown voltage, the source and gate are both at 0 potential; the drain is at high voltage.

[0017] In the original cell region, because of the existence of the gate, it can also be considered that the gate forms a field plate, namely, the gate field plate. The depth of the gate field plate is shallower than that of the source field plate 104. For a 100V device, the depth of the gate conductive material layer 105, namely, the longitudinal extension dimension, is usually between 0.6μm and 1.0μm. The thickness of the gate layer 106 is thinner than that of the shielding dielectric layer 104. For a 100V device, the thickness of the gate layer 106 is usually between The gate conductive material layer 105 also has a lateral depletion effect on the drift region 102, which can reduce the electric field strength at the bottom of the channel region 107. The progress of SGT technology requires continuous reduction of the on-resistance and increase of the doping concentration of the drift region 102. The higher the doping concentration of the drift region 102, the greater the electric field strength at the bottom of the channel. As for the source field plate lead-out region, because there is no gate field plate, the electric field strength at the bottom of the channel will increase, which makes it easier to form a weak point. Summary of the invention

[0018] The technical problem to be solved by the present invention is to provide an SGT device, which can ensure that the doping concentration of the drift region in the original cell region is high so as to reduce the specific on-resistance of the device while eliminating the weakness of the top area of ​​the drift region in the source field plate lead-out region and thereby improve the withstand voltage of the device.

[0019] In order to solve the above technical problems, the SGT device provided by the present invention includes:

[0020] A drift region doped with a first conductivity type.

[0021] A second conductivity type doped channel region is formed above the top surface of the drift region.

[0022] A plurality of gate trenches are provided, wherein the gate trenches vertically penetrate the channel region and bottom regions of the gate trenches enter the drift region.

[0023] The SGT device is divided into the primary cell region and the source field plate lead-out region.

[0024] In the original cell region, a source field plate and a gate conductive material layer are simultaneously formed in the gate groove, a shielding dielectric layer is separated between the source field plate and the inner surface of the corresponding gate groove, an inter-gate dielectric layer is separated between the source field plate and the gate conductive material layer, and a gate dielectric layer is separated between the gate conductive material layer and the side of the corresponding gate groove; the depth of the gate conductive material layer is greater than the depth of the channel region, and the surface of the channel region covered by the side of the gate conductive material layer is used to form a conductive channel; the gate conductive material layer also covers the top area of ​​the drift region located at the bottom of the channel region, and when reverse biased, the gate conductive material layer forms a gate field plate that laterally depletes the top area of ​​the drift region.

[0025] In the source field plate lead-out region, a source field plate is formed in the gate trench, and a shielding dielectric layer is provided between the source field plate and the inner surface of the corresponding gate trench.

[0026] The source field plate in the cell region is in contact with the source field plate in the source field plate lead-out region and is connected to a source electrode composed of a front metal layer through a contact structure on the top of the source field plate in the source field plate lead-out region.

[0027] The gate trench of the source field plate lead-out region does not include the gate conductive material layer and thus does not have the gate field plate; the source field plate lead-out region also includes a first compensation region, the first compensation region is located at the interface region between the channel region and the drift region at the bottom, and second conductive type compensating injection impurities are added to the first compensation region, the compensating injection impurities increase the depletion ability of the channel region to the top region of the drift region to compensate for the reduction in depletion ability of the top region of the drift region when the source field plate lead-out region does not have the gate field plate.

[0028] A further improvement is that, at the interface region, the compensation implanted impurities in the first compensation region are completely located in the drift region or extend into both the channel region and the drift region.

[0029] A further improvement is that the compensating implanted impurities extending into the drift region reduce the net doping concentration of the first conductivity type in the drift region.

[0030] A further improvement is that the ion implantation of the compensatory implanted impurities includes one implantation or multiple implantations with different energies.

[0031] A further improvement is that when the ion implantation of the compensatory impurity is a single implantation, the implantation energy includes 40keV and the implantation dose includes 2e15cm -2 .

[0032] A further improvement is that when the ion implantation of the compensatory impurity is performed for multiple times with different energies, a combination of low energy and high dose and high energy and low dose is adopted, the implantation energy corresponding to the low energy and high dose is lower than the implantation energy of the high energy and low dose, but the implantation dose amount corresponding to the low energy and high dose is higher than the implantation dose of the high energy and low dose.

[0033] A further improvement is that the number of times of ion implantation of the compensatory impurity is twice, and the process conditions of the first implantation are that the implantation energy is 40keV and the implantation dose is 1e15cm -2 The process conditions for the second implantation are as follows: the implantation energy is 200 keV and the implantation dose is 1e12 cm -2 .

[0034] A further improvement is that, in the original cell region, a source region heavily doped with the first conductivity type is self-alignedly formed in the surface region of the channel region on both sides of the gate trench.

[0035] In the source field plate lead-out region, the source region is not formed in the surface area of ​​the channel region at both sides of the gate trench.

[0036] The ion implantation of the compensating impurity implantation adopts the mask definition of the source region, and the photoresist used for the ion implantation of the compensating impurity implantation has opposite polarity to the photoresist used for the ion implantation of the source region.

[0037] A further improvement is that the top surface of the source field plate in the source field plate lead-out region is lower than the top surface of the gate trench, a first dielectric layer is filled in the gate trench above the top surface of the source field plate, an interlayer film is formed above the top surface of the gate trench, and the contact structure is a deep contact hole, which passes through the interlayer film and the first dielectric layer.

[0038] Alternatively, the top surface of the source field plate is flush with the top surface of the gate trench, an interlayer film is formed on the top surface of the gate structure, and the contact structure is a contact hole that passes through the interlayer film.

[0039] A further improvement is that the material of the source field plate includes polysilicon.

[0040] A further improvement is that the material of the shielding dielectric layer includes an oxide layer.

[0041] A further improvement is that, at the bottom of the gate dielectric layer, from the bottom of the gate trench upward, the thickness of the shielding dielectric layer is evenly distributed or the thickness gradually decreases.

[0042] A further improvement is that, when the thickness of the shielding dielectric layer gradually decreases from the bottom of the gate trench upward, the doping concentration of the drift region gradually increases, so as to reduce the specific on-resistance of the device.

[0043] A further improvement is that, in the original cell region, the gate structure is a top-bottom structure, and the gate conductive material layer is located on top of the source field plate.

[0044] Alternatively, in the original cell region, the gate structure is a left-right structure, and the gate conductive material layer is located at the left and right sides of the top region of the source field plate.

[0045] A further improvement is that the SGT device is an SGT MOSFET, and a drain region heavily doped with the first conductivity type is formed at the bottom of the drift region.

[0046] A further improvement is that the SGT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the SGT device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0047] The present invention sets a first compensation area in the source field plate lead-out region, and the first compensation area adds compensating injection impurities of the second conductive type. The compensating injection impurities can increase the depletion capacity of the top area of ​​the drift region, so as to compensate for the weakening of the depletion capacity of the top area of ​​the drift region due to the lack of a gate field plate in the source field plate lead-out region, and can ensure that the doping concentration of the drift region in the original cell region is high while reducing the electric field strength of the top area of ​​the drift region in the source field plate lead-out region during reverse bias, thereby eliminating the weakness of the top area of ​​the drift region in the source field plate lead-out region caused by the high doping concentration of the drift region and the lack of a gate field plate in the source field plate lead-out region, and ultimately improve the withstand voltage of the device. Therefore, the present invention can ensure that the doping concentration of the drift region in the original cell region is high, thereby reducing the specific on-resistance of the device, while eliminating the weakness of the top area of ​​the drift region in the source field plate lead-out region and thereby improving the withstand voltage of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments:

[0049] Figure 1 It is a schematic diagram of the structure of a device unit in the original cell region of an existing SGT MOSFET;

[0050] Figure 2A It is a schematic diagram of the first structure of the source field plate lead-out region of the existing SGT MOSFET;

[0051] Figure 2B It is a second structural schematic diagram of the source field plate lead-out region of the existing SGT MOSFET;

[0052] Figure 3 1 is a schematic structural diagram of a device unit in a primitive cell region of an SGT device in a first embodiment of the present invention;

[0053] Figure 4 1 is a schematic structural diagram of the source field plate lead-out region of the SGT device of the first embodiment of the present invention;

[0054] Figure 5 It is a schematic structural diagram of a device unit in the primary cell region of the SGT device according to the second embodiment of the present invention. DETAILED DESCRIPTION

[0055] like Figure 3 , which is a schematic diagram of the structure of a device unit in the primitive cell region of the SGT device of the first embodiment of the present invention; Figure 4 FIG. 1 is a schematic diagram of the structure of the source field plate lead-out region of the SGT device of the first embodiment of the present invention; the SGT device of the first embodiment of the present invention comprises:

[0056] The drift region 2 is doped with a first conductivity type.

[0057] A second conductivity type doped channel region 7 is formed on the top surface of the drift region 2 .

[0058] A plurality of gate trenches are provided, wherein the gate trenches vertically penetrate the channel region 7 and the bottom regions of the gate trenches enter into the drift region 2 .

[0059] The SGT device is divided into the primary cell region and the source field plate lead-out region.

[0060] like Figure 3 As shown, in the original cell region, a source field plate 4 and a gate conductive material layer 5 are simultaneously formed in the gate trench, a shielding dielectric layer 3 is separated between the source field plate 4 and the inner surface of the corresponding gate trench, an inter-gate dielectric layer 12 is separated between the source field plate 4 and the gate conductive material layer 5, and a gate dielectric layer 6 is separated between the gate conductive material layer 5 and the side of the corresponding gate trench; the depth of the gate conductive material layer 5 is greater than the depth of the channel region 7, and the surface of the channel region 7 covered by the side of the gate conductive material layer 5 is used to form a conductive channel; the gate conductive material layer 5 also covers the top area of ​​the drift region 2 located at the bottom of the channel region 7, and when reverse biased, the gate conductive material layer 5 forms a gate field plate that laterally depletes the top area of ​​the drift region 2, that is, at the bottom of the channel region 7, the gate conductive material layer 5 serves as a gate field plate.

[0061] In the embodiment of the present invention, the material of the source field plate 4 includes polysilicon. The material of the gate conductive material layer 5 includes polysilicon.

[0062] The material of the shielding dielectric layer 3 includes an oxide layer. The thickness of the shielding dielectric layer 3 is evenly distributed.

[0063] The material of the gate dielectric layer 6 includes an oxide layer.

[0064] The material of the inter-gate dielectric layer 12 includes an oxide layer.

[0065] In the embodiment of the present invention, in the original cell region, the gate structure is a top-bottom structure, and the gate conductive material layer 5 is located on the top of the source field plate 4. In other embodiments, it can also be: in the original cell region, the gate structure is a left-right structure, and the gate conductive material layer 5 is located on the left and right sides of the top area of ​​the source field plate 4.

[0066] like Figure 4 As shown, in the source field plate lead-out region, a source field plate 4 is formed in the gate trench, and a shielding dielectric layer 3 is provided between the source field plate 4 and the inner surface of the corresponding gate trench.

[0067] The source field plate 4 in the cell region contacts the source field plate 4 in the source field plate lead-out region and is connected to the source electrode composed of the front metal layer 10 through the contact structure on the top of the source field plate 4 in the source field plate lead-out region. Figure 3 and Figure 4 The front metal layer 10 shown in the figure is used as a source. The front metal layer 10 is also patterned to form a gate. The top of the gate conductive material layer 5 is connected to the gate through a contact hole 9. The front metal layer 10 corresponding to the gate is not Figure 3 and Figure 4 The corresponding section position.

[0068] The gate trench of the source field plate lead-out region does not include a gate conductive material layer 5 and thus does not have a gate field plate; the source field plate lead-out region also includes a first compensation region 13, the first compensation region 13 is located at the interface region between the channel region 7 and the drift region 2 at the bottom, and the first compensation region 13 is added with compensating injection impurities of the second conductivity type, and the compensating injection impurities increase the depletion ability of the channel region 7 to the top region of the drift region 2 to compensate for the reduction in depletion ability to the top region of the drift region 2 when the source field plate lead-out region does not have a gate field plate.

[0069] In the embodiment of the present invention, at the interface region, the compensating injection impurities in the first compensation region 13 are completely located in the drift region 2 or extend to both the channel region 7 and the drift region 2. The specific distribution of the compensating injection impurities in the first compensation region 13 is directly related to the injection energy of the ion injection of the compensating injection impurities, and the thermal process that the compensating injection impurities undergo will also affect the distribution of the compensating injection impurities. The compensating injection impurities extending into the drift region 2 reduce the net doping concentration of the first conductivity type in the drift region 2, that is, can reduce the doping concentration of the first conductivity type in the top region of the drift region 2 in the source field plate lead-out region. The drift region 2 is usually composed of an epitaxial layer doped with a first conductive type formed on a semiconductor substrate. The doping concentration of the drift region 2 can be set according to the requirements in the original cell region. By increasing the doping concentration of the drift region 2, the specific on-resistance of the device can be reduced. At the same time, a first compensation region 13 is set separately in the source field plate region to reduce the doping concentration at the surface of the top area of ​​the drift region 2 in the source field plate region, thereby eliminating the weaknesses caused by the excessive doping concentration at the surface of the top area of ​​the drift region 2 in the source field plate region and the excessive electric field strength at the surface of the top area of ​​the drift region 2 in the source field plate region due to the absence of a gate field plate.

[0070] In the embodiment of the present invention, the ion implantation for compensating the implantation of impurities includes one implantation or multiple implantations with different energies.

[0071] In some embodiments, when the ion implantation of the compensatory implanted impurities is a single implantation, the implantation energy includes 40 keV, and the implantation dose includes 2e15 cm -2 .

[0072] In some embodiments, when the ion implantation of the compensatory impurity is multiple implantations with different energies, a combination of low energy high dose and high energy low dose is used, and the implantation energy corresponding to the low energy high dose is lower than the implantation energy of the high energy low dose, but the implantation dose corresponding to the low energy high dose is higher than the implantation dose of the high energy low dose. Further, the number of times of the ion implantation of the compensatory impurity includes two times, and the process conditions of the first implantation are that the implantation energy includes 40keV, and the implantation dose includes 1e15cm -2 The process conditions for the second implantation are as follows: the implantation energy is 200 keV and the implantation dose is 1e12 cm -2 .

[0073] like Figure 3 As shown, in the original cell region, a source region 8 heavily doped with the first conductivity type is self-alignedly formed in the surface region of the channel region 7 on both sides of the gate trench.

[0074] In the source field plate lead-out region, no active region 8 is formed in the surface area of ​​the channel region 7 on both sides of the gate trench. The source region 8 is connected to the source through the contact hole 9 at the top, and the contact hole 9 at the top of the source region 8 also passes through the source region 8 and contacts the channel region 7 at the bottom.

[0075] The ion implantation of the compensating impurity injection adopts the mask definition of the source region 8, and the photoresist used for the ion implantation of the compensating impurity injection is opposite to the polarity of the photoresist used for the ion implantation of the source region 8. For example: the ion implantation of the source region 8 adopts positive photoresist. At this time, after exposure using the mask of the source region 8, the original cell region will be opened, and the source field plate lead-out region will be covered by the positive photoresist; the ion implantation of the compensating impurity injection adopts negative photoresist, the original cell region will be covered by the positive photoresist, and the source field plate lead-out region will be opened.

[0076] The ion implantation of the compensating implant impurity can be performed after the formation of the epitaxial layer of the drift region 2 and before the ion implantation of the source region 8, or it can be performed after the ion implantation of the source region 8. When the ion implantation of the compensating implant impurity is performed after the ion implantation of the source region 8, the compensating implant impurity undergoes less thermal processes in the subsequent process.

[0077] like Figure 4 As shown, in the embodiment of the present invention, the top surface of the source field plate 4 in the source field plate lead-out region is lower than the top surface of the gate trench, the first dielectric layer 15 is filled in the gate trench above the top surface of the source field plate 4, an interlayer film 11 is formed above the top surface of the gate trench, and the contact structure is a deep contact hole 14, which passes through the interlayer film 11 and the first dielectric layer 15. Figure 4 In the example, the source field plate 4 in the source field plate lead-out region and the source field plate 4 in the original cell region are formed simultaneously using the same process, and both undergo the same back etching process to lower the top surface.

[0078] In other embodiments, the top surface of the source field plate 4 is flush with the top surface of the gate trench, an interlayer film 11 is formed on the top surface of the gate structure, and the contact structure is a contact hole 9 that passes through the interlayer film 11 .

[0079] In an embodiment of the present invention, the SGT device is an SGT MOSFET, and a drain region 1 heavily doped with a first conductivity type is formed at the bottom of a drift region 2. In some embodiments, the drain region 1 is directly formed by thinning a semiconductor substrate heavily doped with the first conductivity type, such as a silicon substrate. In some embodiments, the drain region can also be formed by back ion implantation of heavily doped with the first conductivity type into the thinned semiconductor substrate.

[0080] In the embodiment of the present invention, the SGT device is an N-type device, the first conductivity type is N-type, the second conductivity type is P-type, and the implanted impurities of the ion implantation of the compensatory implanted impurities include boron. In other embodiments, the SGT device can also be a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

[0081] In an embodiment of the present invention, a first compensation region 13 is set in the source field plate lead-out region. The first compensation region 13 adds compensating injection impurities of the second conductive type. The compensating injection impurities can increase the depletion capacity of the top region of the drift region 2, thereby compensating for the weakening of the depletion capacity of the top region of the drift region 2 due to the lack of a gate field plate in the source field plate lead-out region. While ensuring that the doping concentration of the drift region 2 in the original cell region is relatively high, the electric field strength of the top region of the drift region 2 in the source field plate lead-out region is reduced during reverse bias, thereby eliminating the weakness of the top region of the drift region 2 in the source field plate lead-out region caused by the high doping concentration of the drift region 2 and the lack of a gate field plate in the source field plate lead-out region, thereby ultimately improving the withstand voltage of the device. Therefore, in an embodiment of the present invention, while ensuring that the doping concentration of the drift region 2 in the original cell region is relatively high, thereby reducing the specific on-resistance of the device, the weakness of the top region of the drift region 2 in the source field plate lead-out region is eliminated, thereby improving the withstand voltage of the device.

[0082] like Figure 5 As shown, it is a schematic diagram of the structure of the device unit of the primary cell region of the SGT device of the second embodiment of the present invention; the difference from the SGT device of the first embodiment of the present invention is that in the SGT device of the second embodiment of the present invention, at the bottom of the gate dielectric layer 6, from the bottom of the gate trench upward, the thickness of the shielding dielectric layer 3a gradually decreases. Figure 5 The shielding dielectric layer 3a is divided into a first shielding dielectric layer 3a1 and a second shielding dielectric layer 3a2, and the thickness of the second shielding dielectric layer 3a2 is thinner than that of the first shielding dielectric layer 3a1. The setting of gradually decreasing thickness of the shielding dielectric layer 3a is conducive to making the electric field strength of the drift region 2 at various positions on the side of the gate trench more uniform.

[0083] Furthermore, as the thickness of the shielding dielectric layer 3 gradually decreases from the bottom of the gate trench upward, the doping concentration of the drift region 2 gradually increases, so as to reduce the specific on-resistance of the device.

[0084] The present invention can reduce the position of the source field plate lead-out region, because there is no problem of increased electric field strength at the bottom of the channel caused by the gate field plate. Taking an N-type device as an example, at the source lead-out position, i.e., the source field plate lead-out region, a P-type ion injection is added by adding a mask (Mask) such as the same mask as the ion injection of the source region. The P-type ion injection area is located in the first compensation region 13. The depth of the first compensation region 13 is deeper than the depth of the channel region 7. The function is to reduce the doping concentration of the drift region 2 in contact with the channel region 7, thereby reducing the electric field strength. In addition, the injection position corresponding to the first compensation region 13 is not in the original cell region of the device, but only in the source lead-out terminal and its vicinity, so the impact on the on-resistance of the device can be ignored.

[0085] The present invention has been described in detail above through specific embodiments, but these do not constitute limitations of the present invention. Without departing from the principle of the present invention, those skilled in the art may also make many variations and improvements, which should also be considered as the protection scope of the present invention.

Claims

1. An SGT device, characterized in that: include: a drift region doped with a first conductivity type; a second conductivity type doped channel region formed above a top surface of the drift region; A plurality of gate trenches, wherein the gate trenches vertically penetrate the channel region and the bottom regions of the gate trenches enter the drift region; The SGT device is divided into the primary cell region and the source field plate lead-out region; In the primitive cell region, a source field plate and a gate conductive material layer are simultaneously formed in the gate trench, a shielding dielectric layer is separated between the source field plate and the inner surface of the corresponding gate trench, an inter-gate dielectric layer is separated between the source field plate and the gate conductive material layer, and a gate dielectric layer is separated between the gate conductive material layer and the side surface of the corresponding gate trench; the depth of the gate conductive material layer is greater than the depth of the channel region, and the surface of the channel region covered by the side surface of the gate conductive material layer is used to form a conductive channel; The gate conductive material layer also laterally covers the top region of the drift region at the bottom of the channel region, and when reverse biased, the gate conductive material layer forms a gate field plate that laterally depletes the top region of the drift region; In the source field plate lead-out region, a source field plate is formed in the gate trench, and a shielding dielectric layer is separated between the source field plate and the inner surface of the corresponding gate trench; The source field plate in the original cell region is in contact with the source field plate in the source field plate lead-out region and is connected to a source electrode composed of a front metal layer through a contact structure on the top of the source field plate in the source field plate lead-out region; The gate trench of the source field plate lead-out region does not include the gate conductive material layer and thus does not have the gate field plate; the source field plate lead-out region also includes a first compensation region, the first compensation region is located at the interface region between the channel region and the drift region at the bottom, and second conductive type compensating injection impurities are added to the first compensation region, the compensating injection impurities increase the depletion ability of the channel region to the top region of the drift region to compensate for the reduction in depletion ability of the top region of the drift region when the source field plate lead-out region does not have the gate field plate.

2. The SGT device according to claim 1, characterized in that: At the interface region, the compensation implantation impurities in the first compensation region are completely located in the drift region or extend into both the channel region and the drift region.

3. The SGT device according to claim 2, characterized in that: The compensating implanted impurities extending into the drift region reduce a net doping concentration of the first conductivity type in the drift region.

4. The SGT device according to claim 2, characterized in that: The ion implantation of the compensatory implanted impurities includes one implantation or multiple implantations with different energies.

5. The SGT device according to claim 4, characterized in that: When the ion implantation of the compensatory implanted impurities is a single implantation, the implantation energy includes 40keV and the implantation dose includes 2e15cm -2 .

6. The SGT device according to claim 4, characterized in that: When the ion implantation of the compensatory impurity is multiple implantations with different energies, a combination of low energy and high dose and high energy and low dose is adopted, the implantation energy corresponding to the low energy and high dose is lower than the implantation energy of the high energy and low dose, but the implantation dose amount corresponding to the low energy and high dose is higher than the implantation dose of the high energy and low dose.

7. The SGT device according to claim 6, characterized in that: The number of times of ion implantation of the compensatory impurity is twice, and the process conditions of the first implantation are that the implantation energy is 40keV and the implantation dose is 1e15cm -2 The process conditions for the second implantation are as follows: the implantation energy is 200 keV and the implantation dose is 1e12 cm -2 .

8. The SGT device according to claim 1, characterized in that: In the original cell region, a source region heavily doped with a first conductivity type is self-alignedly formed in the surface region of the channel region on both sides of the gate trench; In the source field plate lead-out region, the source region is not formed in the surface region of the channel region on both sides of the gate trench; The ion implantation of the compensating impurity implantation adopts the mask definition of the source region, and the photoresist used for the ion implantation of the compensating impurity implantation has opposite polarity to the photoresist used for the ion implantation of the source region.

9. The SGT device according to claim 1, characterized in that: The top surface of the source field plate of the source field plate lead-out region is lower than the top surface of the gate trench, a first dielectric layer is filled in the gate trench above the top surface of the source field plate, an interlayer film is formed on the top surface of the gate trench, and the contact structure is a deep contact hole, and the deep contact hole passes through the interlayer film and the first dielectric layer; Alternatively, the top surface of the source field plate is flush with the top surface of the gate trench, an interlayer film is formed on the top surface of the gate structure, and the contact structure is a contact hole that passes through the interlayer film.

10. The SGT device according to claim 1, characterized in that: The material of the source field plate includes polysilicon.

11. The SGT device according to claim 1, characterized in that: The material of the shielding dielectric layer includes an oxide layer.

12. The SGT device according to claim 11, characterized in that: At the bottom of the gate dielectric layer, from the bottom of the gate trench upward, the thickness of the shielding dielectric layer is evenly distributed or the thickness gradually decreases.

13. The SGT device according to claim 12, characterized in that: When the thickness of the shielding dielectric layer gradually decreases from the bottom of the gate trench upward, the doping concentration of the drift region gradually increases, so as to reduce the specific on-resistance of the device.

14. The SGT device according to claim 1, characterized in that: In the primitive cell region, the gate structure is a top-bottom structure, and the gate conductive material layer is located on top of the source field plate; Alternatively, in the original cell region, the gate structure is a left-right structure, and the gate conductive material layer is located at the left and right sides of the top region of the source field plate.

15. The SGT device according to claim 1, characterized in that: The SGT device is an SGT MOSFET, and a drain region heavily doped with a first conductivity type is formed at the bottom of the drift region.

16. The SGT device according to any one of claims 1 to 15, characterized in that: The SGT device is an N-type device, the first conductivity type is N-type, and the second conductivity type is P-type; or, the SGT device is a P-type device, the first conductivity type is P-type, and the second conductivity type is N-type.

Images