Semiconductor structure and manufacturing method thereof

Abstract

The embodiment of the invention relates to the field of semiconductors, and provides a semiconductor structure and a manufacturing method thereof, the semiconductor structure comprises a substrate, the substrate comprises a semiconductor substrate and a semiconductor layer located on the surface of the semiconductor substrate, and the forbidden bandwidth of the material of the semiconductor layer is smaller than that of the material of the semiconductor substrate; the gate structure is located on the top surface of the semiconductor layer; the source-drain doped region is located in the substrate on the two opposite sides of the gate structure, the source-drain doped region comprises a groove, and the bottom surface of the groove is lower than the bottom surface of the semiconductor layer; and the metal semiconductor compound layer is located at the bottom of the groove of the source-drain doped region, and the top surface of the metal semiconductor compound layer is lower than the bottom surface of the semiconductor layer. The reliability of the semiconductor structure can be improved.

Description

Technical Field

[0001] The present disclosure relates to the semiconductor field, and in particular to a semiconductor structure and a method for manufacturing the same. Background Art

[0002] Memory is a memory component used to store programs and various data information. The random access memory (RAM) used in general computer systems can be divided into two types: dynamic random access memory (DRAM) and static random access memory (SRAM). Dynamic random access memory is a commonly used semiconductor memory device in computers, consisting of many repeated storage units.

[0003] Currently, when a metal semiconductor compound layer (such as a metal silicide layer) is formed, the reliability of the semiconductor structure is affected. Summary of the invention

[0004] The embodiments of the present disclosure provide a semiconductor structure and a method for manufacturing the same, which can at least improve the reliability of the semiconductor structure.

[0005] According to some embodiments of the present disclosure, on the one hand, the embodiments of the present disclosure provide a semiconductor structure, comprising: a substrate, the substrate comprising a semiconductor substrate and a semiconductor layer located on the surface of the semiconductor substrate, wherein the bandgap width of the material of the semiconductor layer is smaller than the bandgap width of the material of the semiconductor substrate; a gate structure, the gate structure is located on the top surface of the semiconductor layer; a source-drain doping region, the source-drain doping region is located in the substrate on opposite sides of the gate structure, the source-drain doping region comprises a groove, the bottom surface of the groove is lower than the bottom surface of the semiconductor layer; a metal semiconductor compound layer, the metal semiconductor compound layer is located at the bottom of the groove in the source-drain doping region, and the top surface of the metal semiconductor compound layer is lower than the bottom surface of the semiconductor layer.

[0006] In some embodiments, in a direction perpendicular to the substrate, a distance between a top surface of the metal semiconductor compound layer and a bottom surface of the semiconductor layer is 4-8 nm.

[0007] In some embodiments, it also includes: a dielectric layer covering the source and drain doping regions; a contact plug penetrating the dielectric layer and partially located in the groove and electrically connected to the metal semiconductor compound layer.

[0008] In some embodiments, the method further includes: an isolation layer, a portion of which is located between the contact plug and the dielectric layer, another portion of which is located between the contact plug and the substrate, and the other portion of which at least covers the sidewall of the semiconductor layer.

[0009] In some embodiments, the isolation layer has a thickness of 1-3 nm.

[0010] In some embodiments, the contact plug includes a diffusion barrier layer and a metal conductive layer, wherein the diffusion barrier layer surrounds a bottom and a sidewall of the metal conductive layer.

[0011] In some embodiments, the source and drain doping regions include a lightly doped region and a heavily doped region that are in contact with each other, the lightly doped region is located within the orthographic projection of the gate structure on the substrate, and the heavily doped region extends from within the orthographic projection to outside the orthographic projection; the groove is located in the heavily doped region.

[0012] In some embodiments, the gate structure includes a gate stack and a spacer structure covering the sidewalls of the gate stack; in a direction perpendicular to the substrate, the lightly doped region partially overlaps with the gate stack, and the lightly doped region partially overlaps with the spacer structure.

[0013] In some embodiments, the material of the semiconductor substrate includes silicon, the material of the semiconductor layer includes silicon germanium, and the material of the metal semiconductor compound layer does not include germanium.

[0014] According to some embodiments of the present disclosure, on the other hand, the embodiments of the present disclosure further provide a method for manufacturing a semiconductor structure, comprising: providing a substrate, the substrate comprising a semiconductor substrate and a semiconductor layer located on the surface of the semiconductor substrate, wherein the bandgap width of the material of the semiconductor layer is smaller than the bandgap width of the material of the semiconductor substrate; forming a gate structure, the gate structure being located on the top surface of the semiconductor layer; forming source-drain doping regions, the source-drain doping regions being located in the substrate on opposite sides of the gate structure; forming grooves in the source-drain doping regions, the bottom of the grooves being lower than the bottom surface of the semiconductor layer; forming a metal semiconductor compound layer, the metal semiconductor compound layer being located at the bottom of the grooves, and the top surface of the metal semiconductor compound layer being lower than the bottom surface of the semiconductor layer.

[0015] In some embodiments, before forming the metal semiconductor compound layer, the method further includes: forming a dielectric layer, wherein the dielectric layer covers the source and drain doping regions; and etching the dielectric layer and the substrate to form a contact hole, wherein the contact hole includes the groove.

[0016] In some embodiments, after forming the metal semiconductor compound layer, the method further includes: forming a contact plug in the contact hole, wherein the contact plug is electrically connected to the metal semiconductor compound layer.

[0017] In some embodiments, forming the contact plug in the contact hole includes: forming a diffusion barrier layer, the diffusion barrier layer conformally covering the sidewalls of the contact hole and the metal semiconductor compound layer; forming a metal conductive layer, the metal conductive layer covering the diffusion barrier layer and filling the contact hole.

[0018] In some embodiments, before forming the contact plug in the contact hole, the method further includes: forming an isolation layer on the sidewall of the contact hole, wherein at least a portion of the isolation layer covers the sidewall of the semiconductor layer exposed by the contact hole.

[0019] In some embodiments, forming the metal semiconductor compound layer includes: forming a metal layer, wherein the metal layer is located in the groove, and the top surface of the metal layer is lower than the bottom surface of the semiconductor layer; using an annealing process to allow the material of the metal layer to react with the material of the semiconductor substrate to form the metal semiconductor compound layer; and removing the unreacted metal layer.

[0020] The technical solution provided by the embodiments of the present disclosure has at least the following advantages: by setting a semiconductor layer, and setting the band gap width of the semiconductor layer material to be smaller than the band gap width of the semiconductor substrate material, the semiconductor layer is used as a channel of the semiconductor structure, thereby improving the performance of the semiconductor structure; by setting a gate structure and a source-drain doping region to form a transistor, a metal semiconductor compound layer is set, the metal semiconductor compound layer is located at the bottom of the groove of the source-drain doping region, and the top surface of the metal semiconductor compound layer is lower than the bottom surface of the semiconductor layer; the resistance of the semiconductor structure can be reduced by the metal semiconductor compound layer; by setting the top surface of the metal semiconductor compound layer to be lower than the bottom surface of the semiconductor layer, the metal semiconductor compound layer can be avoided from contacting the semiconductor layer, thereby avoiding the material of the metal semiconductor compound layer from reacting with the material of the semiconductor layer, thereby improving the reliability of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 A schematic structural diagram of a first semiconductor structure provided in an embodiment of the present disclosure;

[0023] Figure 2 A schematic structural diagram of a second semiconductor structure provided in an embodiment of the present disclosure;

[0024] Figure 3 A schematic structural diagram of a third semiconductor structure provided by an embodiment of the present disclosure;

[0025] Figures 4 to 10 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0026] At present, when forming a metal semiconductor compound layer, the material in the metal semiconductor compound layer will react with the material in certain semiconductor layers, resulting in the formation of holes in the semiconductor structure. In this way, in the subsequent process of forming other structures, the materials of other structures will penetrate through the holes, affecting the reliability of the semiconductor structure. For example, when the metal semiconductor compound layer is cobalt silicide and the material of the semiconductor layer is silicon germanium, when forming metal silicide of cobalt, the metal cobalt will react with the germanium in the semiconductor layer to generate holes. When subsequently forming a diffusion barrier layer (for example, titanium nitride), titanium will diffuse into the holes, affecting the reliability of the semiconductor structure.

[0027] The present disclosure implements a semiconductor structure, which is provided by setting a semiconductor layer, and setting the band gap width of the semiconductor layer material to be smaller than the band gap width of the semiconductor substrate material, so that the semiconductor layer is used as a channel of the semiconductor structure, thereby improving the performance of the semiconductor structure, and by setting a gate structure and a source-drain doping region to form a transistor, and by setting a metal semiconductor compound layer, the metal semiconductor compound layer is located at the bottom of the groove of the source-drain doping region, and the top surface of the metal semiconductor compound layer is lower than the bottom surface of the semiconductor layer, the resistance of the semiconductor structure can be reduced by the metal semiconductor compound layer, and by setting the top surface of the metal semiconductor compound layer to be lower than the bottom surface of the semiconductor layer, the metal semiconductor compound layer can be prevented from contacting the semiconductor layer, thereby preventing the material of the metal semiconductor compound layer from reacting with the material of the semiconductor layer, thereby improving the reliability of the semiconductor structure.

[0028] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0029] refer to Figures 1 to 3 , Figure 1 A schematic structural diagram of a first semiconductor structure provided in an embodiment of the present disclosure; Figure 2 A schematic structural diagram of a second semiconductor structure provided in an embodiment of the present disclosure; Figure 3 A schematic structural diagram of a third semiconductor structure provided in an embodiment of the present disclosure.

[0030] refer to Figure 1 In some embodiments, the semiconductor structure may include: a base 100, the base 100 includes a semiconductor substrate 101 and a semiconductor layer 102 located on the surface of the semiconductor substrate 101, wherein the bandgap width of the material of the semiconductor layer 102 is smaller than the bandgap width of the material of the semiconductor substrate 101.

[0031] The semiconductor structure may further include: a gate structure 110 , and the gate structure 110 is located on the top surface of the semiconductor layer 102 .

[0032] The semiconductor structure may further include: source-drain doped regions 120 , which are located in the substrate 100 on opposite sides of the gate structure 110 . The source-drain doped regions 120 include grooves 121 , and the bottom surface of the grooves 121 is lower than the bottom surface of the semiconductor layer 102 .

[0033] The semiconductor structure may further include: a metal semiconductor compound layer 130 , the metal semiconductor compound layer 130 is located at the bottom of the groove 121 of the source / drain doping region 120 , and the top surface of the metal semiconductor compound layer 130 is lower than the bottom surface of the semiconductor layer 102 .

[0034] By setting a semiconductor layer 102 and setting the bandgap width of the semiconductor layer 102 material to be smaller than the bandgap width of the semiconductor substrate 101 material, the semiconductor layer 102 is used as a channel of the semiconductor structure, so that the performance of the semiconductor structure can be improved. By setting a gate structure 110 and a source-drain doping region 120 to form a transistor, a metal semiconductor compound layer 130 is set, and the metal semiconductor compound layer 130 is located at the bottom of the groove 121 of the source-drain doping region 120, and the top surface of the metal semiconductor compound layer 130 is lower than the bottom surface of the semiconductor layer 102. The resistance of the semiconductor structure can be reduced by the metal semiconductor compound layer 130. By setting the top surface of the metal semiconductor compound layer 130 to be lower than the bottom surface of the semiconductor layer 102, the metal semiconductor compound layer 130 can be prevented from contacting the semiconductor layer 102, so that the material of the metal semiconductor compound layer 130 can be prevented from reacting with the material of the semiconductor layer 102, so that the reliability of the semiconductor structure can be improved.

[0035] In some embodiments, the material of the semiconductor substrate 101 may include semiconductor materials, such as but not limited to silicon. In some embodiments, the semiconductor substrate 101 may include: a basic semiconductor, a compound semiconductor, or an alloy semiconductor. For example, the basic semiconductor includes silicon; the compound semiconductor includes silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium antimonide; the alloy semiconductor includes gallium arsenic phosphide, gallium indium phosphide, gallium in arsenide, indium gallium arsenide phosphide, aluminum indium arsenide, and / or aluminum gallium arsenide. In some embodiments, the semiconductor substrate 101 may also be a silicon-on-insulator structure.

[0036] In addition, the semiconductor substrate 101 may be doped according to design requirements (eg, a P-type substrate or an N-type substrate). In some embodiments, the semiconductor substrate 101 may be doped with P-type doping ions (eg, boron ions, aluminum ions) or N-type doping ions (eg, phosphorus ions, arsenic ions).

[0037] Taking the semiconductor substrate 101 as silicon, for example, the semiconductor layer 102 may be made of germanium or silicon germanium, etc. The semiconductor substrate 101 may also be made of other semiconductor materials, and the semiconductor layer 102 may also be made of other materials with a smaller bandgap than the semiconductor substrate 101 .

[0038] refer to Figure 2 In some embodiments, the gate structure 110 may include: a gate stack 1101 and a spacer structure 113 covering the sidewalls of the gate stack 1101. The gate stack 1101 includes: a gate dielectric layer 112, a work function layer 11, a gate conductive layer 111 and a gate cap layer 12 stacked in sequence.

[0039] In some embodiments, the gate conductive layer 111 may include: a first conductive layer 13, a gate barrier layer 14, and a second conductive layer 15. The first conductive layer 13 is a transition layer between the second conductive layer 15 and the work function layer 11, which reduces the material difference between the film layers of the gate structure 110 and can improve the reliability of the semiconductor structure; the gate barrier layer 14 is used to isolate the second conductive layer 15 from the first conductive layer 13, thereby preventing the metal ions in the second conductive layer 15 from diffusing into the first conductive layer 13, thereby improving the reliability of the semiconductor structure; the second conductive layer 15 can improve the conductivity of the gate conductive layer 111 and can improve the signal transmission rate.

[0040] In some embodiments, the material of the first conductive layer 13 may be polysilicon, polysilicon doped with dopant ions, or other semiconductor materials.

[0041] In some embodiments, the material of the gate barrier layer 14 may be titanium nitride (TiN), tungsten nitride (WN), titanium silicon nitride (TiSiN), or the like.

[0042] In some embodiments, the material of the second conductive layer 15 can be a metal with good conductivity, such as tungsten, copper or silver.

[0043] The work function layer 11 is used to adjust the work function in the gate structure 110, so as to adjust the threshold voltage of the transistor. In some embodiments, the gate structure 110 is used as a gate structure of a PMOS (P-type Metal-Oxide-Semiconductor) tube, and the work function layer 11 may include a first barrier layer, a first work function adjustment layer, and a second barrier layer. In some embodiments, the gate structure 110 is used as a gate structure of an NMOS (N-type Metal-Oxide-Semiconductor) tube, and the work function layer 11 may include: a second work function adjustment layer and a third barrier layer.

[0044] In the case where the gate structure 110 is used as a gate structure of a PMOS tube, the material of the first work function regulating layer in the work function layer 11 may include aluminum oxide, but is not limited thereto. In the case where the gate structure 110 is used as a gate structure of an NMOS tube, the material of the second work function regulating layer in the work function layer 11 may include lanthanum oxide, but is not limited thereto. The materials of the first barrier layer, the second barrier layer, and the third barrier layer may be titanium nitride (TiN), but are not limited thereto.

[0045] In some embodiments, the gate dielectric layer 112 may include: a first gate dielectric layer 1121 and a second gate dielectric layer 1122 which are stacked, wherein the dielectric constant of the second gate dielectric layer 1122 is greater than the dielectric constant of the first gate dielectric layer 1121, the material of the first gate dielectric layer 1121 may be silicon oxide, and the material of the second gate dielectric layer 1122 may be hafnium oxide. By setting the second gate dielectric layer 1122 to have a high relative dielectric constant, the transistor size is reduced, the thickness of the gate dielectric layer 112 is reduced, and the distance between the gate structure 110 and the source-drain doped region 120 is reduced. By setting the second gate dielectric layer 1122 with a high relative dielectric constant, the gate leakage current and the source-drain leakage current can be reduced.

[0046] It should be noted that the relative dielectric constant here is a physical parameter that characterizes the dielectric properties or polarization properties of a dielectric material. Its value is equal to the ratio of the capacitance of a capacitor made with a preset material as the medium to the capacitance of a capacitor of the same size made with a vacuum as the medium.

[0047] It is understandable that the gate dielectric layer 112 may also include a single dielectric layer, for example, only a silicon oxide layer or a hafnium oxide layer.

[0048] In some embodiments, the gate cap layer 12 is a protective layer on the top surface of the gate conductive layer 111 , and the material of the gate cap layer 12 may include insulating materials such as silicon nitride and silicon oxynitride.

[0049] In some embodiments, the spacing structure 113 may include: a first protection layer 1131, the first protection layer 1131 covers the sidewall of the gate conductive layer 111; a second protection layer 1132, the second protection layer 1132 covers the side of the first protection layer 1131 away from the gate conductive layer 111; a third protection layer 1133, the third protection layer 1133 covers the side of the second protection layer 1132 away from the first protection layer 1131. By setting the spacing structure 113 to be composed of the first protection layer 1131, the second protection layer 1132 and the third protection layer 1133, the insulation performance of the spacing structure 113 can be increased, thereby preventing short circuits between adjacent gate conductive layers 111.

[0050] In some embodiments, the material of the first protective layer 1131 may be silicon nitride, the material of the second protective layer 1132 may be silicon oxide, and the material of the third protective layer 1133 may be silicon nitride. That is, the spacing structure 113 may be a NON (nitride layer-oxide layer-nitride layer) structure. By setting an oxide layer between the two nitride layers, the insulation performance of the spacing structure 113 can be improved, and the parasitic capacitance between adjacent gate conductive layers 111 can be reduced. The material of the nitride layer is relatively hard, and by setting two nitride layers, the morphology of the spacing structure 113 can be improved.

[0051] In some embodiments, the material of the first protective layer 1131, the material of the second protective layer 1132 and the material of the third protective layer 1133 may also be other insulating materials, and the material of the first protective layer 1131, the material of the second protective layer 1132 and the material of the third protective layer 1133 may be the same or different.

[0052] In some embodiments, the gate dielectric layer 112 includes: a first gate dielectric layer 1121 and a second gate dielectric layer 1122, the first protection layer 1131 can cover the top surface of the first gate dielectric layer 1121, and the second protection layer 1132 can cover the sidewalls of the first gate dielectric layer 1121. In some embodiments, the gate dielectric layer 112 includes: a first gate dielectric layer 1121 and a second gate dielectric layer 1122, and the first protection layer 1131 can cover the sidewalls of the first gate dielectric layer 1121.

[0053] In some embodiments, the source-drain doping region 120 includes a lightly doped region 122 and a heavily doped region 123 that are in contact with each other, the lightly doped region 122 is located within the orthographic projection of the gate structure 110 on the substrate 100, the heavily doped region 123 extends from within the orthographic projection to outside the orthographic projection, and the groove 121 is located in the heavily doped region 123.

[0054] In some embodiments, the gate structure 110 includes a gate stack 1101 and a spacer structure 113. In a direction perpendicular to the substrate 100, the lightly doped region 122 partially overlaps with the gate stack 1101, and the lightly doped region 122 partially overlaps with the spacer structure 113. In other words, the orthographic projection of the lightly doped region 122 on the surface of the substrate 100 partially overlaps with the orthographic projection of the gate stack 1101 on the surface of the substrate 100, and partially overlaps with the orthographic projection of the spacer structure 113 on the surface of the substrate 100.

[0055] In some embodiments, in a direction perpendicular to the substrate 100, the distance between the top surface of the metal semiconductor compound layer 130 and the bottom surface of the semiconductor layer 102 is 4-8 nm, for example, 5 nm, 5.5 nm, 6 nm or 7 nm. It can be understood that the smaller the distance between the top surface of the metal semiconductor compound layer 130 and the bottom surface of the semiconductor layer 102, the worse the ability to avoid the reaction between the metal semiconductor compound layer 130, and the larger the distance between the top surface of the metal semiconductor compound layer 130 and the bottom surface of the semiconductor layer 102, the deeper the metal semiconductor compound layer 130 is located in the substrate 100, which will affect the performance of the semiconductor structure. Therefore, by setting the distance between the top surface of the metal semiconductor compound layer 130 and the bottom surface of the semiconductor layer 102 to 4-8 nm, it is possible to ensure that there is a certain distance between the metal semiconductor compound layer 130 and the semiconductor layer 102, while avoiding the metal semiconductor compound layer 130 from being too deep in the substrate 100, thereby avoiding affecting the performance of the semiconductor structure.

[0056] If the distance between the top surface of the metal semiconductor compound layer 130 and the bottom surface of the semiconductor layer 102 is less than 4nm, the reaction between the metal semiconductor compound layer 130 and the semiconductor layer 102 may not be avoided well. If the distance between the top surface of the metal semiconductor compound layer 130 and the bottom surface of the semiconductor layer 102 is greater than 8nm, the depth of the substrate 100 that needs to be etched when forming the metal semiconductor compound layer 130 is deeper, which will affect the reliability of the formed semiconductor structure.

[0057] In some embodiments, the width of the formed metal semiconductor compound layer 130 may also be controlled, for example, the width of the formed metal semiconductor compound layer 130 may be controlled to be 15-25 nm, such as 16 nm, 18 nm, 20 nm or 22 nm.

[0058] It can be understood that if the width of the metal semiconductor compound layer 130 is less than 15nm, the ability to reduce the resistance of the semiconductor structure is poor. If the width of the metal semiconductor compound layer 130 is greater than 25nm, the ability to reduce the possibility of reaction between the metal semiconductor compound layer 130 and the semiconductor layer 102 is poor.

[0059] It should be noted that the width here refers to the maximum width of the metal semiconductor compound layer in the direction from the gate stack 1101 to the spacer structure 113 .

[0060] In some embodiments, the material of the semiconductor substrate 101 includes silicon, the material of the semiconductor layer 102 includes germanium silicon, and the material of the metal semiconductor compound layer 130 does not include germanium. That is, when the metal semiconductor compound layer 130 is formed, the material of the semiconductor layer 102 does not participate in the reaction, so no holes are formed in the semiconductor layer 102.

[0061] In some embodiments, the semiconductor structure may further include: a dielectric layer 140, covering the source-drain doped region 120; and a contact plug 150, penetrating the dielectric layer 140 and partially located in the groove 121, and electrically connected to the metal semiconductor compound layer 130. The dielectric layer 140 is provided to fill the gap between adjacent gate structures 110, so as to facilitate the subsequent formation of other structures. The contact plug 150 is provided and electrically connected to the metal semiconductor compound layer 130 through the contact plug 150, so as to facilitate the transmission of signals to the metal semiconductor compound layer 130 through the contact plug 150, and further transmit signals to the source-drain doped region 120, or facilitate the extraction of signals in the metal semiconductor compound layer 130.

[0062] In some embodiments, the material of the dielectric layer 140 may be an insulating material such as silicon oxide or silicon nitride.

[0063] In some embodiments, the contact plug 150 may include: a diffusion barrier layer 151 and a metal conductive layer 152, wherein the diffusion barrier layer 151 surrounds the bottom and sidewalls of the metal conductive layer 152. The metal conductive layer 152 is the portion of the contact plug 150 used to transmit signals, and the diffusion barrier layer 151 is used to prevent metal ions in the metal conductive layer 152 from diffusing into the substrate 100 or the adjacent gate structure 110, thereby improving the reliability of the semiconductor structure.

[0064] refer to Figure 3 In some embodiments, the structure of the semiconductor structure may further include an isolation layer 160, a portion of which is located between the contact plug 150 and the dielectric layer 140, another portion of which is located between the contact plug 150 and the substrate 100, and another portion of which at least covers the sidewall of the semiconductor layer 102. The isolation layer 160 may be provided to further isolate the semiconductor layer 102 from the metal semiconductor compound layer 130, thereby further preventing the semiconductor layer 102 from reacting with the metal semiconductor compound layer 130, and thereby further improving the performance of the semiconductor structure.

[0065] In some embodiments, the thickness of the isolation layer 160 is 1-3 nm, for example, 1.3 nm, 1.7 nm, 2 nm, 2.5 nm or 2.8 nm, etc. The thicker the isolation layer 160 is, the stronger the ability to prevent the semiconductor layer 102 from reacting with the metal semiconductor compound layer 130 is. However, the thickness of the isolation layer 160 will affect the subsequent formation of the contact plug 150 and the resistance of the contact plug 150. Therefore, by setting the thickness of the isolation layer 160 to 1-3 nm, the ability to prevent the semiconductor layer 102 from reacting with the metal semiconductor compound layer 130 can be improved while avoiding the impact on the contact plug 150.

[0066] If the thickness of the isolation layer 160 is less than 1 nm, the effect of improving the reaction between the semiconductor layer 102 and the metal semiconductor compound layer 130 is poor. If the thickness of the isolation layer 160 is greater than 3 nm, the size of the contact plug 150 formed subsequently will be reduced, and the resistance of the contact plug 150 will be increased.

[0067] It should be noted that the thickness of the isolation layer 160 here is an average dimension in a direction from the dielectric layer 140 to the contact plug 150 .

[0068] In the embodiment of the present disclosure, a semiconductor layer 102 is provided, and the bandgap width of the semiconductor layer 102 material is provided to be smaller than the bandgap width of the semiconductor substrate 101 material, so that the semiconductor layer 102 is used as a channel of the semiconductor structure, thereby improving the performance of the semiconductor structure. A gate structure 110 and a source-drain doping region 120 are provided to form a transistor, and a metal semiconductor compound layer 130 is provided. The metal semiconductor compound layer 130 is located at the bottom of the groove 121 of the source-drain doping region 120, and the top surface of the metal semiconductor compound layer 130 is lower than the bottom surface of the semiconductor layer 102. The resistance of the semiconductor structure can be reduced by the metal semiconductor compound layer 130. By setting the top surface of the metal semiconductor compound layer 130 lower than the bottom surface of the semiconductor layer 102, the metal semiconductor compound layer 130 can be prevented from contacting the semiconductor layer 102, thereby preventing the material of the metal semiconductor compound layer 130 from reacting with the material of the semiconductor layer 102, thereby improving the reliability of the semiconductor structure.

[0069] Another embodiment of the present disclosure further provides a method for manufacturing a semiconductor structure, which can be used to form the above-mentioned semiconductor structure. The method for manufacturing a semiconductor structure provided by another embodiment of the present disclosure will be described below in conjunction with the accompanying drawings. It should be noted that the same or corresponding parts of the aforementioned embodiments can refer to the corresponding description of the aforementioned embodiments and will not be repeated below.

[0070] refer to Figures 4 to 10 , Figures 4 to 10A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided in one embodiment of the present disclosure.

[0071] In some embodiments, a method for manufacturing a semiconductor structure may include:

[0072] Providing a substrate 100, the substrate 100 includes a semiconductor substrate 101 and a semiconductor layer 102 located on a surface of the semiconductor substrate 101, wherein a bandgap width of a material of the semiconductor layer 102 is smaller than a bandgap width of a material of the semiconductor substrate 101;

[0073] forming a gate structure 110 , wherein the gate structure 110 is located on a top surface of the semiconductor layer 102 ;

[0074] forming source-drain doped regions 120 , wherein the source-drain doped regions 120 are located in the substrate 100 at two opposite sides of the gate structure 110 ;

[0075] A groove 121 is formed in the source-drain doping region 120 , wherein the bottom surface of the groove 121 is lower than the bottom surface of the semiconductor layer 102 ;

[0076] A metal semiconductor compound layer 130 is formed. The metal semiconductor compound layer 130 is located at the bottom of the groove 121 of the source / drain doping region 120 , and the top surface of the metal semiconductor compound layer 130 is lower than the bottom surface of the semiconductor layer 102 .

[0077] By providing a base 100 including a semiconductor layer 102 and a semiconductor substrate 101, and setting the bandgap width of the semiconductor layer 102 material to be smaller than the bandgap width of the semiconductor substrate 101 material, the semiconductor layer 102 is used as a channel of the semiconductor structure, so that the performance of the semiconductor structure can be improved. By forming a gate structure 110 and a source-drain doping region 120 to form a transistor, by forming a metal semiconductor compound layer 130, the metal semiconductor compound layer 130 is located at the bottom of the groove 121 of the source-drain doping region 120, and the top surface of the metal semiconductor compound layer 130 is lower than the bottom surface of the semiconductor layer 102, the resistance of the semiconductor structure can be reduced by the metal semiconductor compound layer 130, and by setting the top surface of the metal semiconductor compound layer 130 to be lower than the bottom surface of the semiconductor layer 102, the metal semiconductor compound layer 130 can be prevented from contacting the semiconductor layer 102, so that the material of the metal semiconductor compound layer 130 can be prevented from reacting with the material of the semiconductor layer 102, so that the reliability of the semiconductor structure can be improved.

[0078] refer to Figures 4 to 6In some embodiments, before forming the metal semiconductor compound layer 130, the manufacturing method further includes: forming a dielectric layer 140, the dielectric layer 140 covers the source and drain doped regions 120; etching the dielectric layer 140 and the substrate 100 to form a contact hole 170, the contact hole 170 includes a groove 121. By forming the dielectric layer 140, the dielectric layer 140 covers the source and drain doped regions 120, that is, the dielectric layer 140 is located on opposite sides of the gate structure 110, and the formation of the dielectric layer 140 can facilitate the formation of the contact hole 170 and the groove 121. By forming the contact hole 170 and the groove 121, the subsequent formation of the metal semiconductor compound layer 130 can be facilitated.

[0079] refer to Figure 7 In some embodiments, before forming the contact plug 150 in the contact hole 170, the manufacturing method further includes: forming an isolation layer 160 on the sidewall of the contact hole 170, at least a portion of the isolation layer 160 covers the sidewall of the semiconductor layer 102 exposed by the contact hole 170. By forming the isolation layer 160, the semiconductor layer 102 can be further isolated from the metal semiconductor compound layer 130, thereby further preventing the semiconductor layer 102 from reacting with the metal semiconductor compound layer 130, thereby further improving the performance of the semiconductor structure.

[0080] refer to Figure 8 and Fig. 9 , forming a metal semiconductor compound layer 130. In some embodiments, forming the metal semiconductor compound layer 130 includes: forming a metal layer 180, the metal layer 180 is located in the groove 121, and the top surface of the metal layer 180 is lower than the bottom surface of the semiconductor layer 102; using an annealing process to react the material of the metal layer 180 with the material of the semiconductor substrate 101 to form the metal semiconductor compound layer 130; and removing the unreacted metal layer 180. The metal layer 180 reacts with the semiconductor substrate 101 through the annealing process to generate the metal semiconductor compound layer 130, thereby reducing the resistance of the source-drain doping region 120 and improving the reliability of the semiconductor structure.

[0081] In some embodiments, the annealing process may include: performing a first rapid thermal annealing treatment to transform a portion of the semiconductor substrate 101 and the metal layer 180 into an initial metal semiconductor compound layer; performing a second rapid thermal annealing treatment to transform the initial metal semiconductor compound layer into the metal semiconductor compound layer 130 .

[0082] Taking the case where the material of the metal layer 180 is cobalt and the material of the semiconductor substrate 101 is silicon as an example, a first rapid thermal annealing treatment is performed, and the cobalt metal reacts with the single crystal silicon of the semiconductor substrate 101 to generate an initial metal semiconductor compound layer in a high resistance state, such as cobalt silicon; then, a second rapid thermal annealing treatment is performed, and the initial metal semiconductor compound layer in a high resistance state can be converted into a metal semiconductor compound layer 130 in a low resistance state, such as cobalt disilicide, through the second rapid thermal annealing treatment; thereafter, the unreacted cobalt metal can be removed by selective wet etching. It can be understood that the above-mentioned cobalt metal and single crystal silicon materials are only examples for the convenience of explanation, and do not limit the materials of the metal layer 180 and the materials of the semiconductor substrate 101, and can be adjusted according to actual conditions.

[0083] In some embodiments, before performing the first rapid thermal annealing treatment, the above-mentioned manufacturing method can also form a barrier layer on the surface of the metal layer 180, thereby preventing the metal layer from flowing during the two rapid thermal annealing treatments and preventing the metal ions in the metal layer 180 from diffusing to other places. The barrier layer can be removed simultaneously when the metal layer 180 is removed after the two rapid thermal annealing treatments.

[0084] refer to Fig.10 In some embodiments, after forming the metal semiconductor compound layer 130, the manufacturing method may further include: forming a contact plug 150 in the contact hole 170, wherein the contact plug 150 is electrically connected to the metal semiconductor compound layer 130. The contact plug 150 is formed to transmit a signal to the metal semiconductor compound layer 130 through the contact plug 150, and then transmit a signal to the source-drain doped region 120, or to facilitate the extraction of a signal in the metal semiconductor compound layer 130.

[0085] In some embodiments, forming the contact plug 150 in the contact hole 170 includes: forming a diffusion barrier layer 151, the diffusion barrier layer 151 conformally covers the sidewall of the contact hole 170 and the metal semiconductor compound layer 130; forming a metal conductive layer 152, the metal conductive layer 152 covers the diffusion barrier layer 151 and fills the contact hole 170. The metal conductive layer 152 is formed to transmit signals, and the diffusion barrier layer 151 is formed to prevent metal ions in the metal conductive layer 152 from diffusing into the substrate 100 or the adjacent gate structure 110, thereby improving the reliability of the semiconductor structure.

[0086] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for implementing the present disclosure, and in practical applications, various changes can be made to them in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure, so the protection scope of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising a semiconductor substrate and a semiconductor layer located on a surface of the semiconductor substrate, wherein the bandgap width of a material of the semiconductor layer is smaller than the bandgap width of a material of the semiconductor substrate; A gate structure, wherein the gate structure is located on a top surface of the semiconductor layer; Source-drain doped regions, the source-drain doped regions are located in the substrate at two opposite sides of the gate structure, the source-drain doped regions include grooves, and the bottom surface of the grooves is lower than the bottom surface of the semiconductor layer; A metal semiconductor compound layer is located at the bottom of the groove in the source-drain doping region, and the top surface of the metal semiconductor compound layer is lower than the bottom surface of the semiconductor layer.

2. The semiconductor structure according to claim 1, characterized in that: In a direction perpendicular to the substrate, a distance between a top surface of the metal semiconductor compound layer and a bottom surface of the semiconductor layer is 4-8 nm.

3. The semiconductor structure according to claim 1 or 2, characterized in that: Also includes: A dielectric layer covering the source and drain doped regions; The contact plug penetrates the dielectric layer and is partially located in the groove, and is electrically connected to the metal semiconductor compound layer.

4. The semiconductor structure according to claim 3, characterized in that: Also includes: An isolation layer, a portion of which is located between the contact plug and the dielectric layer, another portion of which is located between the contact plug and the substrate, and the another portion of which at least covers the sidewall of the semiconductor layer.

5. The semiconductor structure according to claim 4, characterized in that: The thickness of the isolation layer is 1-3 nm.

6. The semiconductor structure according to claim 3, characterized in that: The contact plug includes: A diffusion barrier layer and a metal conductive layer, wherein the diffusion barrier layer surrounds a bottom and a side wall of the metal conductive layer.

7. The semiconductor structure according to claim 1 or 2, characterized in that: The source-drain doping region comprises a lightly doped region and a heavily doped region that are in contact with each other, the lightly doped region is located within the orthographic projection of the gate structure on the substrate, and the heavily doped region extends from within the orthographic projection to outside the orthographic projection; The groove is located in the heavily doped region.

8. The semiconductor structure according to claim 7, characterized in that: The gate structure includes a gate stack and a spacer structure covering a sidewall of the gate stack; In a direction perpendicular to the substrate, the lightly doped region partially overlaps with the gate stack, and the lightly doped region partially overlaps with the spacing structure.

9. The semiconductor structure according to claim 1 or 2, characterized in that: The material of the semiconductor substrate includes silicon, the material of the semiconductor layer includes silicon germanium, and the material of the metal semiconductor compound layer does not include germanium.

10. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a semiconductor substrate and a semiconductor layer located on a surface of the semiconductor substrate, wherein a bandgap width of a material of the semiconductor layer is smaller than a bandgap width of a material of the semiconductor substrate; forming a gate structure, wherein the gate structure is located on a top surface of the semiconductor layer; forming source-drain doped regions, wherein the source-drain doped regions are located in the substrate at opposite sides of the gate structure; forming a groove in the source-drain doping region, wherein the bottom of the groove is lower than the bottom surface of the semiconductor layer; A metal semiconductor compound layer is formed, wherein the metal semiconductor compound layer is located at the bottom of the groove, and the top surface of the metal semiconductor compound layer is lower than the bottom surface of the semiconductor layer.

11. The method for manufacturing a semiconductor structure according to claim 10, characterized in that: Before forming the metal semiconductor compound layer, the method further comprises: forming a dielectric layer, wherein the dielectric layer covers the source and drain doped regions; The dielectric layer and the substrate are etched to form a contact hole, wherein the contact hole includes the groove.

12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: After forming the metal semiconductor compound layer, the method further comprises: A contact plug is formed in the contact hole, and the contact plug is electrically connected to the metal semiconductor compound layer.

13. The method for manufacturing a semiconductor structure according to claim 12, characterized in that: Forming the contact plug in the contact hole comprises: forming a diffusion barrier layer, wherein the diffusion barrier layer conformally covers the sidewalls of the contact hole and the metal semiconductor compound layer; A metal conductive layer is formed, the metal conductive layer covers the diffusion barrier layer and fills the contact hole.

14. The method for manufacturing a semiconductor structure according to claim 12 or 13, characterized in that: Before forming the contact plug in the contact hole, the method further includes: An isolation layer is formed on the sidewall of the contact hole, and at least a portion of the isolation layer covers the sidewall of the semiconductor layer exposed by the contact hole.

15. The method for manufacturing a semiconductor structure according to claim 10, characterized in that: Forming the metal semiconductor compound layer comprises: forming a metal layer, wherein the metal layer is located in the groove, and a top surface of the metal layer is lower than a bottom surface of the semiconductor layer; Using an annealing process to make the material of the metal layer react with the material of the semiconductor substrate to form the metal semiconductor compound layer; The unreacted metal layer is removed.

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