Array substrate, preparation method thereof and display panel

Abstract

The invention provides an array substrate and a preparation method thereof, and a display panel, the array substrate comprises a substrate, and a first conductive layer, an active layer, a second conductive layer and a third conductive layer which are arranged on the substrate, a source electrode contact part of the active layer is connected with a source electrode of the first conductive layer, the second conductive layer comprises a grid electrode arranged corresponding to a channel part, and the third conductive layer is arranged on the first conductive layer. The pixel electrode of the third conductive layer is connected with the drain electrode contact part of the active layer, and at least one of the first conductive layer and the second conductive layer further comprises a common electrode arranged opposite to the pixel electrode; therefore, the source electrode and the shading electrode are arranged on the same layer, and the common electrode and the grid electrode and / or the shading electrode are arranged on the same layer, so that the number of used photomasks can be reduced, and the cost is reduced.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate and a preparation method thereof, and a display panel. Background Art

[0002] In the field of display technology, a thin film transistor (TFT) array substrate is an important component of a display panel. The manufacture of a thin film transistor array substrate involves the use of multiple photo masks, which results in a complex manufacturing process and high cost. Summary of the invention

[0003] The present application provides an array substrate and a manufacturing method thereof, and a display panel, so as to reduce the number of photomasks used in the manufacturing process of a thin film transistor array substrate and reduce costs.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] The present application provides an array substrate, which includes:

[0006] substrate;

[0007] A first conductive layer, disposed on one side of the substrate, the first conductive layer comprising a source electrode and a light shielding electrode disposed at intervals;

[0008] an active layer, arranged on a side of the first conductive layer away from the substrate, the active layer comprising a channel portion, a source contact portion and a drain contact portion, the channel portion being connected between the source contact portion and the drain contact portion; in a thickness direction of the array substrate, the channel portion is arranged corresponding to the light shielding electrode, and the source contact portion is connected to the source;

[0009] A second conductive layer is disposed on a side of the active layer away from the substrate, the second conductive layer comprising a gate disposed corresponding to the channel portion;

[0010] A third conductive layer is disposed on a side of the second conductive layer away from the substrate, the third conductive layer comprising a pixel electrode connected to the drain contact portion;

[0011] Wherein, at least one of the first conductive layer and the second conductive layer further includes a common electrode arranged opposite to the pixel electrode.

[0012] In the array substrate provided in the embodiment of the present application, at least one of the first conductive layer and the second conductive layer includes at least a transparent conductive sublayer, and the transparent conductive sublayer forms the common electrode.

[0013] In the array substrate provided in the embodiment of the present application, the material of the transparent conductive sublayer includes indium tin oxide.

[0014] In the array substrate provided in the embodiment of the present application, the second conductive layer includes the transparent conductive sublayer, and the transparent conductive sublayer also forms the gate.

[0015] In the array substrate provided in the embodiment of the present application, the second conductive layer further includes at least one metal sublayer arranged on a side of the transparent conductive sublayer away from the substrate, and the metal sublayer and the transparent conductive sublayer form the gate.

[0016] In the array substrate provided in the embodiment of the present application, the first conductive layer includes the transparent conductive sublayer and at least one metal sublayer arranged on the side of the transparent conductive sublayer away from the substrate, and the metal sublayer and the transparent conductive sublayer form the source and the light-shielding electrode.

[0017] In the array substrate provided in the embodiment of the present application, in the thickness direction of the array substrate, the distance between the gate and the substrate is greater than the distance between the common electrode and the substrate.

[0018] In the array substrate provided in the embodiment of the present application, the array substrate further includes:

[0019] a first insulating layer, located between the substrate and the first conductive layer, wherein the first insulating layer is provided with a first via hole at a position corresponding to the source electrode, and the source contact portion is connected to the source electrode through the first via hole;

[0020] a second insulating layer, located between the active layer and the second conductive layer, the second insulating layer comprising a first insulating portion arranged corresponding to the gate;

[0021] The third insulating layer is located between the second conductive layer and the third conductive layer. The third insulating layer is provided with a second via hole at a position corresponding to the drain contact portion. The pixel electrode is connected to the drain contact portion through the second via hole.

[0022] The present application also provides a method for preparing an array substrate, which includes:

[0023] Providing a substrate, preparing a first conductive layer on one side of the substrate, wherein the first conductive layer includes a source electrode and a light shielding electrode that are spaced apart;

[0024] An active layer is prepared on a side of the first conductive layer away from the substrate, and a part of the active layer is connected to the source electrode;

[0025] A second conductive layer is prepared on a side of the active layer away from the substrate, the second conductive layer includes a gate arranged corresponding to a portion of the active layer and a common electrode arranged at intervals from the gate, and the active layer is conductorized with the gate as a shield, so that the active layer forms a channel portion, a source contact portion and a drain contact portion, the channel portion is connected between the source contact portion and the drain contact portion, and in the thickness direction of the array substrate, the channel portion is arranged corresponding to the light shielding electrode, and the source contact portion is connected to the source;

[0026] A third conductive layer is prepared on a side of the second conductive layer away from the substrate, wherein the third conductive layer includes a pixel electrode connected to the drain contact portion, and the pixel electrode is arranged opposite to the common electrode.

[0027] An embodiment of the present application further provides a display panel, which includes the array substrate described in one of the aforementioned embodiments.

[0028] The beneficial effects of the present application are as follows: in the array substrate and its preparation method, and the display panel provided by the present application, the array substrate includes a substrate and a first conductive layer, an active layer, a second conductive layer, and a third conductive layer arranged on the substrate, the source contact portion of the active layer is connected to the source of the first conductive layer, the second conductive layer includes a gate arranged corresponding to the channel portion, the pixel electrode of the third conductive layer is connected to the drain contact portion of the active layer, and at least one of the first conductive layer and the second conductive layer also includes a common electrode arranged opposite to the pixel electrode; in this way, by arranging the source electrode and the light-shielding electrode on the same layer, and arranging the common electrode and the gate and / or the light-shielding electrode on the same layer, the number of photomasks used can be reduced and the cost can be reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0030] Figure 1 As a preface to an embodiment of the present application, an array substrate is provided.

[0031] Figure 2 A schematic cross-sectional structure diagram of an array substrate provided in an embodiment of the present application.

[0032] Figure 3 Another schematic diagram of the cross-sectional structure of the array substrate provided in an embodiment of the present application.

[0033] Figure 4A schematic diagram of another cross-sectional structure of an array substrate provided in an embodiment of the present application.

[0034] Figure 5 A schematic diagram of a process for preparing an array substrate provided in an embodiment of the present application.

[0035] Figures 6a to 6f for Figure 5 Method for preparing array substrate Figure 2 Schematic diagram of the film layer structure obtained in each step of the array substrate.

[0036] Figures 7a to 7f for Figure 5 Method for preparing array substrate Figure 3 Schematic diagram of the film layer structure obtained in each step of the array substrate.

[0037] Figure 8 Another schematic diagram of the process of preparing an array substrate provided in an embodiment of the present application.

[0038] Figures 9a to 9f for Figure 8 Method for preparing array substrate Figure 4 Schematic diagram of the film layer structure obtained in each step of the array substrate. DETAILED DESCRIPTION

[0039] The description of the following embodiments is with reference to the attached diagrams to illustrate specific embodiments that the present application can be implemented. The directional terms mentioned in the present application, such as [up], [down], [front], [back], [left], [right], [inside], [outside], [side], etc., are only with reference to the directions of the attached drawings. Therefore, the directional terms used are used to illustrate and understand the present application, rather than to limit the present application. In the figures, units with similar structures are represented by the same reference numerals. In the accompanying drawings, the thickness of some layers and regions is exaggerated for clear understanding and ease of description. That is, the size and thickness of each component shown in the drawings are arbitrarily shown, but the present application is not limited to this.

[0040] Reference Figure 1As a preface to an embodiment of the present application, an array substrate is provided. The array substrate includes a substrate 10' and a light shielding electrode 21', an active layer 30', a gate 41', a source 22', a drain, a common electrode 42' and a pixel electrode 51' arranged on the substrate 10'. A first insulating layer 11' is arranged between the light shielding electrode 21' and the active layer 30'. A second insulating layer 12' is arranged between the active layer 30' and the gate 41'. The active layer 30' includes a channel portion, a source contact portion and a drain contact portion, and the channel portion is located between the source contact portion and the drain contact portion. The gate 41' and the second insulating layer 12' are both arranged corresponding to the channel portion. A third insulating layer 13' is provided between the gate 41' and the source 22' and the drain. The source 22' is connected to the source contact portion through a via hole on the third insulating layer 13', and the drain is connected to the drain contact portion through a via hole on the third insulating layer 13'. A passivation layer 14' and a planarization layer 15' are provided between the source 22', the drain and the common electrode 42'. A fourth insulating layer 16' is provided between the common electrode 42' and the pixel electrode 51'. The pixel electrode 51' is connected to the drain through the fourth insulating layer 16', the planarization layer 15' and the via hole on the passivation layer 14'.

[0041] exist Figure 1 In the array substrate shown in the figure, the light shielding electrode 21' needs to use a photomask, the active layer 30' needs to use a photomask, the gate 41' and the first insulating layer 11' need to use a photomask, the second insulating layer 12' needs to use a photomask, the source 22' and the drain need to use a photomask, the passivation layer 14' needs to use a photomask, the flat layer 15' needs to use a photomask, the common electrode 42' needs to use a photomask, the fourth insulating layer 16' needs to use a photomask, and the pixel electrode 51' needs to use a photomask. In this way, the preparation is as follows Figure 1 The array substrate shown requires a total of 10 photomasks, which results in a complicated manufacturing process and high cost.

[0042] To this end, the present application provides an array substrate and a method for preparing the same, as well as a display panel.

[0043] Please refer to Figure 1 and Figure 2 , Figure 2A schematic cross-sectional structure diagram of an array substrate provided in an embodiment of the present application. The array substrate 100 includes a substrate 10 and a first conductive layer 20, an active layer 30, a second conductive layer 40, and a third conductive layer 50 arranged on the substrate 10. The first conductive layer 20 is arranged on one side of the substrate 10, and the first conductive layer 20 includes a source electrode 21 and a light shielding electrode 22 arranged at intervals. The active layer 30 is arranged on a side of the first conductive layer 20 away from the substrate 10, and the active layer 30 includes a channel portion 32, a source contact portion 31, and a drain contact portion 33, and the channel portion 32 is connected between the source contact portion 31 and the drain contact portion 33.

[0044] In the thickness direction of the array substrate 100, the channel portion 32 is arranged corresponding to the light shielding electrode 22, and the source contact portion 31 is connected to the source 21. The second conductive layer 40 is arranged on the side of the active layer 30 away from the substrate 10, and the second conductive layer 40 includes a gate 41 arranged corresponding to the channel portion 32. The third conductive layer 50 is arranged on the side of the second conductive layer 40 away from the substrate 10, and the third conductive layer 50 includes a pixel electrode 51 connected to the drain contact portion 33. At least one of the first conductive layer 20 and the second conductive layer 40 further includes a common electrode 42 arranged opposite to the pixel electrode 51. When the common electrode 42 is formed by the first conductive layer 20, the common electrode 42 is arranged in the same layer as the light shielding electrode 22; when the common electrode 42 is formed by the second conductive layer 40, the common electrode 42 is arranged in the same layer as the gate 41.

[0045] Optionally, at least one of the first conductive layer 20 and the second conductive layer 40 includes at least a transparent conductive sublayer 401, and the transparent conductive sublayer 401 forms the common electrode 42, that is, the common electrode 42 is formed by the transparent conductive sublayer 401 in the first conductive layer 20 and / or the second conductive layer 40, so that the common electrode 42 can be light-transmissive and conductive. The material of the transparent conductive sublayer 401 includes a transparent conductive material such as indium tin oxide (ITO).

[0046] In this embodiment, the source 21 and the light-shielding electrode 22 are arranged on the same layer, and the common electrode 42 and the gate 41 and / or the light-shielding electrode 22 are arranged on the same layer. In this way, the source 21 and the light-shielding electrode 22 can be formed using the same photomask, and the common electrode 42 and the gate 41 or the light-shielding electrode 22 can be formed using the same photomask, thereby reducing the number of photomasks used and reducing costs.

[0047] In one embodiment, referring to Figure 1The second conductive layer 40 includes the transparent conductive sublayer 401 , and the transparent conductive sublayer 401 also forms the gate 41 , that is, the transparent conductive sublayer 401 is formed with the gate 41 and the common electrode 42 spaced apart from the gate 41 .

[0048] Specifically, refer to Figure 1 , the array substrate 100 further includes a transistor disposed on the substrate 10. The transistor may be a thin film transistor. The transistor includes the source 21, the active layer 30 and the gate 41. The active layer 30 is disposed on a side of the source 21 away from the substrate 10, and the gate 41 is disposed on a side of the active layer 30 away from the substrate 10. The active layer 30 includes a channel portion 32 and a source contact portion 31 located on one side of the channel portion 32. Of course, the active layer 30 further includes a drain contact portion 33 located on a side of the channel portion 32 away from the source contact portion 31, that is, the drain contact portion 33 and the source contact portion 31 are located on opposite sides of the channel portion 32, and the channel portion 32 is connected between the source contact portion 31 and the drain contact portion 33. The gate 41 is disposed opposite to the channel portion 32 , and an orthographic projection of the gate 41 on the substrate 10 coincides with an orthographic projection of the channel portion 32 on the substrate 10 .

[0049] Optionally, the substrate 10 may be a rigid substrate or a flexible substrate; when the substrate 10 is a rigid substrate, it may include a rigid substrate such as a glass substrate, a quartz substrate or a silicon wafer; when the substrate 10 is a flexible substrate, it may include a flexible substrate such as a polyimide (PI) film or an ultra-thin glass film. When the substrate 10 is a polyimide, moisture or oxygen may more easily penetrate into the substrate 10 compared to a glass substrate. To prevent this, a buffer layer having a single-layer or multi-layer structure including silicon oxide or silicon nitride may be provided on the substrate 10.

[0050] The first conductive layer 20 is disposed on the substrate 10. The first conductive layer 20 includes a source electrode 21 and a light shielding electrode 22 that are spaced and insulated. The light shielding electrode 22 is at least disposed corresponding to the channel portion 32 to shield the channel portion 32 from light and reduce the photogenerated leakage current of the transistor. The material of the first conductive layer 20 includes a material with low resistance and light shielding performance such as Al, Ti, Mo, Cu, Ni or an alloy thereof.

[0051] The array substrate 100 further includes a first insulating layer 11 located between the first conductive layer 20 and the active layer 30. The first insulating layer 11 covers the first conductive layer 20 and the substrate 10. The first insulating layer 11 is provided with a first via hole 111 at a position corresponding to the source electrode 21. The first via hole 111 penetrates the first insulating layer 11 and exposes at least a portion of the source electrode 21. The source contact portion 31 is connected to the source electrode 21 through the first via hole 111, that is, a portion of the source contact portion 31 is located in the first via hole 111 and connected to the source electrode 21.

[0052] The film thickness of the first insulating layer 11 ranges from 3000 angstroms to 5000 angstroms, such as 3000 angstroms, 3500 angstroms, 4000 angstroms, 4500 angstroms, 5000 angstroms, etc. The material of the first insulating layer 11 includes an inorganic material, for example, the first insulating layer 11 can be a plurality of layers or a single layer including at least one of tetraethyl orthosilicate, silicon nitride, and silicon oxide.

[0053] The active layer 30 is disposed on a side of the first insulating layer 11 away from the substrate 10. The source contact portion 31 and the drain contact portion 33 of the active layer 30 are formed by conducting the semiconductor material forming the active layer 30, so that the source contact portion 31 and the drain contact portion 33 of the active layer 30 form conductors. The source contact portion 31 is located on a portion of the first insulating layer 11 and in the first via hole 111. The source contact portion 31 located in the first via hole 111 covers the hole wall of the first via hole 111 and the source electrode 21 exposed by the first via hole 111, so as to be connected to the source electrode 21.

[0054] The active layer 30 has a thickness ranging from 100 angstroms to 500 angstroms, such as 100 angstroms, 200 angstroms, 220 angstroms, 250 angstroms, 280 angstroms, 300 angstroms, 350 angstroms, 380 angstroms, 400 angstroms, 500 angstroms, etc. The active layer 30 is made of semiconductor materials such as polysilicon and metal oxides.

[0055] The array substrate 100 further includes a second insulating layer 12 between the active layer 30 and the gate 41. The second insulating layer 12 is disposed on a side of the active layer 30 away from the substrate 10, and is disposed corresponding to the channel portion 32. The material of the second insulating layer 12 includes an inorganic material, for example, the second insulating layer 12 may be a plurality of layers or a single layer including at least one of tetraethyl orthosilicate, silicon nitride, and silicon oxide.

[0056] The second conductive layer 40 is disposed on a side of the second insulating layer 12 away from the substrate 10, and the second conductive layer 40 includes a gate 41 of the transistor, and the gate 41 is disposed corresponding to the second insulating layer 12. The second conductive layer 40 also includes a common electrode 42 spaced apart from the gate 41, and the common electrode 42 is disposed in the same layer as the gate 41. The second insulating layer 12 includes a first insulating portion 121 disposed corresponding to the gate 41 and a second insulating portion 122 disposed corresponding to the common electrode 42. In the thickness direction of the array substrate 100, the distance between the gate 41 and the substrate 10 is greater than the distance between the common electrode 42 and the substrate 10.

[0057] It should be noted that "arranged in the same layer" in this application means that in the preparation process, a film layer formed of the same material is patterned to obtain at least two different structures, and the at least two different structures are arranged in the same layer. For example, the gate 41 and the common electrode 42 of this embodiment are obtained by patterning the same transparent conductive sublayer 401, and the gate 41 and the common electrode 42 are arranged in the same layer.

[0058] Optionally, when the material of the transparent conductive sublayer 401 is indium tin oxide, when preparing the gate 41 and the common electrode 42, magnetron sputtering, vacuum evaporation and other deposition processes can be adopted, thereby eliminating the need for physical vapor deposition (PVD) deposition, thereby reducing the number of machines required for the physical vapor deposition process. In this way, while reducing the number of photomasks used and reducing costs, the number of machines required for the physical vapor deposition process can also be reduced to further reduce costs.

[0059] In this way, by setting the source 21 and the light-shielding electrode 22 on the same layer, and setting the common electrode 42 and the gate 41 on the same layer, the source 21 and the light-shielding electrode 22 can be formed using the same photomask, and the gate 41 and the common electrode 42 can be formed using the same photomask, thereby reducing the number of photomasks used and reducing costs.

[0060] The array substrate 100 further includes a third insulating layer 13 located between the second conductive layer 40 and the third conductive layer 50. The third insulating layer 13 is provided with a second via hole 131 at a position corresponding to the drain contact portion 33. The pixel electrode 51 is connected to the drain contact portion 33 through the second via hole 131, that is, part of the pixel electrode 51 is located in the second via hole 131 and connected to the drain contact portion 33. The third insulating layer 13 covers part of the first insulating layer 11, part of the active layer 30, the gate 41, and the common electrode 42.

[0061] More specifically, the third insulating layer 13 covers the upper surface and side walls of the gate 41, the side walls of the first insulating portion 121, the upper surface and side walls of the source contact portion 31, the upper surface and side walls of the drain contact portion 33, the upper surface and side walls of the common electrode 42, the side walls of the second insulating portion 122 and a portion of the first insulating layer 11.

[0062] The material of the third insulating layer 13 includes an inorganic material. For example, the third insulating layer 13 may be a plurality of layers or a single layer including at least one of tetraethyl orthosilicate, silicon nitride, and silicon oxide.

[0063] Among them, for the convenience of description, the present application defines that the surface of each structure away from the substrate 10 is the upper surface, the surface opposite to the upper surface is the lower surface, and the sidewall connects the upper surface and the lower surface. For example, the surface of the gate 41 away from the substrate 10 is the upper surface of the gate 41, the surface opposite to the upper surface of the gate 41 is the lower surface of the gate 41, the lower surface of the gate 41 is in contact with the first insulating portion 121, and the sidewall of the gate 41 connects the upper surface and the lower surface.

[0064] The pixel electrode 51 is disposed on a side of the third insulating layer 13 away from the substrate 10. The third insulating layer 13 is provided with a second via hole 131 at a position corresponding to the drain contact portion 33. The second via hole 131 penetrates the third insulating layer 13 and exposes at least a portion of the drain contact portion 33. Part of the pixel electrode 51 is located in the second via hole 131 and is connected to the drain contact portion 33 exposed by the second via hole 131. The pixel electrode 51 includes a plurality of electrode portions 511, and a slit 512 is provided between adjacent electrode portions 511. The material of the pixel electrode 51 includes a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO) or indium oxide (In2O3).

[0065] In this embodiment, the source 21 and the light-shielding electrode 22 require a photomask, the first insulating layer 11 requires a photomask, the active layer 30 requires a photomask, the second insulating layer 12, the gate 41 and the common electrode 42 require a photomask, the third insulating layer 13 requires a photomask, and the pixel electrode 51 requires a photomask. Thus, a total of 6 photomasks are required to form the array substrate 100 of the present application.

[0066] Compared to Figure 1 The example array substrate requires 10 photomasks. Figure 2The array substrate 100 of the example only needs 6 photomasks, which reduces the number of photomasks used, thereby reducing costs. Moreover, when preparing the gate 41 and the common electrode 42, magnetron sputtering, vacuum evaporation and other processes can be used for deposition, so there is no need to use physical vapor deposition, which can reduce the number of machines required for the physical vapor deposition process. In this way, while reducing the number of photomasks used and reducing costs, it can also reduce the number of machines required for the physical vapor deposition process, thereby further reducing costs.

[0067] In one embodiment, continue to refer to Figure 2 The array substrate 100 has a display area AA and a binding area BA located on one side of the display area AA, the display area AA is used to display images, and the binding area BA is used to bind a driving chip or a flexible circuit board, etc. The source electrode 21, the light shielding electrode 22, the active layer 30, the gate 41, the common electrode 42 and the pixel electrode 51 are all located in the display area AA.

[0068] The second conductive layer 40 further includes a signal line 43 located in the binding area BA, and the second insulating layer 12 further includes a third insulating portion 123 disposed corresponding to the signal line 43. The third conductive layer 50 further includes a binding terminal 52 located in the binding area BA, and the third insulating layer 13 is provided with a third via 132 at a position corresponding to the signal line 43, and part of the binding terminal 52 is located in the third via 132 and connected to the signal line 43. The third insulating layer 13 also covers part of the upper surface and sidewall of the signal line 43 and the sidewall of the third insulating portion 123.

[0069] In one embodiment, referring to Figures 1 to 3 , Figure 3 This is another cross-sectional structural diagram of an array substrate provided in an embodiment of the present application. Figure 3 ,and Figure 2 The difference between the exemplary embodiments is that the second conductive layer 40 also includes at least one metal sublayer 402 arranged on the side of the transparent conductive sublayer 401 away from the substrate 10, the metal sublayer 402 and the transparent conductive sublayer 401 form the gate 41, and the transparent conductive sublayer 401 is the top film layer of the common electrode 42, that is, the common electrode 42 is formed by the transparent conductive sublayer 401 and does not include the metal sublayer 402.

[0070] Specifically, the second conductive layer 40 includes a transparent conductive sublayer 401 and a metal sublayer 402, and the number of the metal sublayers 402 can be multiple. For example, the second conductive layer 40 includes two metal sublayers 402, wherein the material of the first metal sublayer is copper, and the material of the second metal sublayer is molybdenum, titanium or molybdenum-titanium alloy, and the first metal sublayer is located between the second metal sublayer and the transparent conductive sublayer 401, so that the second conductive layer 40 is formed by stacking three sublayers.

[0071] The transparent conductive sublayer 401 and the metal sublayer 402 together form the gate 41, the transparent conductive sublayer 401 forms the common electrode 42, and the metal sublayer 402 does not form the common electrode 42, that is, the gate 41 is formed by the transparent conductive sublayer 401 and the metal sublayer 402, and the common electrode 42 is formed by the transparent conductive sublayer 401. In other words, the gate 41 is formed by multiple sublayers, and the common electrode 42 is formed by a single sublayer.

[0072] Optionally, a half-tone mask (HTM) is used to perform a yellow light process on the second conductive layer 40 to form the gate 41 and the common electrode 42. Specifically, the transparent conductive sublayer 401 and the metal sublayer 402 are subjected to a yellow light process using a half-tone mask, including first etching the transparent conductive sublayer 401 and the metal sublayer 402 to form a gate pattern and a common electrode pattern. At this time, the gate pattern and the common electrode pattern both include the transparent conductive sublayer 401 and the metal sublayer 402, and then the gate pattern and the common electrode pattern are etched for a second time to form the gate 41, while removing the metal sublayer 402 in the common electrode pattern and exposing the transparent conductive sublayer 401 to form the common electrode 42. For other descriptions, please refer to the above embodiment, which will not be repeated here.

[0073] In one embodiment, referring to Figures 1 to 4 , Figure 4 This is another cross-sectional structural diagram of an array substrate provided in an embodiment of the present application. Figure 4 ,and Figure 3 The difference of the exemplary embodiment is that the common electrode 42 and the light shielding electrode 22 are arranged in the same layer, that is, the common electrode 42 is formed by the first conductive layer 20 .

[0074] Specifically, the first conductive layer 20 includes the transparent conductive sublayer 401 and at least one metal sublayer 402 arranged on the side of the transparent conductive sublayer 401 away from the substrate 10, the metal sublayer 402 and the transparent conductive sublayer 401 form the source 21 and the light-shielding electrode 22, and the transparent conductive sublayer 401 is the top film layer of the common electrode 42.

[0075] Optionally, the number of the metal sublayers 402 can be multiple, for example, the first conductive layer 20 includes two metal sublayers 402, wherein the material of the first metal sublayer is copper, and the material of the second metal sublayer is molybdenum, titanium or molybdenum-titanium alloy, and the first metal sublayer is located between the second metal sublayer and the transparent conductive sublayer 401, so that the first conductive layer 20 can be formed by stacking three sublayers.

[0076] The transparent conductive sublayer 401 and the metal sublayer 402 jointly form the source 21 and the light-shielding electrode 22. The transparent conductive sublayer 401 forms the common electrode 42, and the metal sublayer 402 does not form the common electrode 42. That is, the source 21 and the light-shielding electrode 22 are formed by the transparent conductive sublayer 401 and the metal sublayer 402, and the common electrode 42 is formed by the transparent conductive sublayer 401. In other words, the source 21 and the light-shielding electrode 22 are formed by multiple sublayers, and the common electrode 42 is formed by a single sublayer.

[0077] Optionally, a half-tone photomask is used to perform a yellow light process on the first conductive layer 20 to form the source electrode 21, the light shielding electrode 22 and the common electrode 42. Specifically, the transparent conductive sublayer 401 and the metal sublayer 402 are subjected to a yellow light process using a half-tone photomask, including first etching the transparent conductive sublayer 401 and the metal sublayer 402 to form a source electrode pattern, a light shielding electrode pattern and a common electrode pattern. At this time, the source electrode pattern, the light shielding electrode pattern and the common electrode pattern all include the transparent conductive sublayer 401 and the metal sublayer 402, and then the source electrode pattern, the light shielding electrode pattern and the common electrode pattern are etched for a second time to form the source electrode 21 and the light shielding electrode 22, and at the same time, the metal sublayer 402 in the common electrode pattern is removed and the transparent conductive sublayer 401 is exposed to form the common electrode 42. For other descriptions, please refer to the above embodiment, which will not be repeated here.

[0078] In one embodiment, the present application also provides a method for preparing an array substrate, referring to Figures 1 to 6f , Figure 5 A schematic diagram of a process for preparing an array substrate provided in an embodiment of the present application is provided. Figures 6a to 6f for Figure 5Method for preparing array substrate Figure 2 Schematic diagram of the film structure obtained by each step of the array substrate. Figure 5 , the array substrate preparation method comprises the following steps:

[0079] S601: providing a substrate 10, and preparing a first conductive layer 20 on one side of the substrate 10, wherein the first conductive layer 20 includes a source electrode 21 and a light shielding electrode 22 that are spaced apart from each other;

[0080] Specifically, refer to Figure 6a , providing a substrate 10, the substrate 10 is divided into a display area AA and a binding area BA located on one side of the display area AA, depositing a first conductive film on the substrate 10, and performing a yellow light process on the first conductive film using a first photomask to form a first conductive layer 20, the first conductive layer 20 includes a source electrode 21 and a light shielding electrode 22 arranged at intervals. The material of the first conductive layer 20 includes a material with low resistance and light shielding performance such as Al, Ti, Mo, Cu, Ni or an alloy thereof.

[0081] S602: preparing an active layer 30 on a side of the first conductive layer 20 away from the substrate 10, and a portion of the active layer 30 is connected to the source electrode 21;

[0082] Specifically, refer to Figure 6b , a first insulating film is deposited on the first conductive layer 20 and the substrate 10 , and a second photomask is used to perform a yellow light process on the first insulating film to form a first insulating layer 11 , wherein the first insulating layer 11 forms a first via hole 111 at a position corresponding to the source electrode 21 .

[0083] Reference Figure 6c , depositing a semiconductor film on the first insulating layer 11 , and performing a yellow light process on the semiconductor film using a third photomask to form the active layer 30 . Part of the active layer 30 is connected to the source electrode 21 through the first via hole 111 .

[0084] S603: preparing a second conductive layer 40 on a side of the active layer 30 away from the substrate 10, wherein the second conductive layer 40 includes a gate 41 arranged corresponding to a portion of the active layer and a common electrode 42 arranged spaced apart from the gate 41, and using the gate 41 as a shield, the active layer 30 is conductively formed so that the active layer 30 forms a channel portion 32, a source contact portion 31 and a drain contact portion 33, wherein the channel portion 32 is connected between the source contact portion 31 and the drain contact portion 33, and in the thickness direction of the array substrate 100, the channel portion 32 is arranged corresponding to the light shielding electrode 22, and the source contact portion 31 is connected to the source 21;

[0085] Specifically, refer to Figure 6d , depositing a second insulating film and a transparent conductive sublayer on the active layer 30, and performing a yellow light process on the second insulating film and the transparent conductive sublayer using a fourth photomask to form the second insulating layer 12 and the second conductive layer 40, wherein the material of the transparent conductive sublayer includes indium tin oxide, etc. The second conductive layer 40 includes a gate 41 arranged corresponding to the channel portion 32 and a common electrode 42 arranged spaced apart from the gate 41, and the second insulating layer 12 includes a first insulating portion 121 arranged corresponding to the gate 41, and a second insulating portion 122 arranged corresponding to the common electrode 42.

[0086] The active layer 30 is conductorized with the gate 41 and the first insulating portion 121 as shielding, so that the active layer 30 forms a channel portion 32, a source contact portion 31 and a drain contact portion 33, and the channel portion 32 is connected between the source contact portion 31 and the drain contact portion 33. In the thickness direction of the array substrate 100, the channel portion 32 is arranged corresponding to the light-shielding electrode 22, and the source contact portion 31 is connected to the source 21.

[0087] S604 : preparing a third conductive layer 50 on a side of the second conductive layer 40 away from the substrate 10 , wherein the third conductive layer 50 includes a pixel electrode 51 connected to the drain contact portion 33 , and the pixel electrode 51 is arranged opposite to the common electrode 42 .

[0088] Reference Figure 6e , depositing a third insulating film on the gate 41, and performing a yellow light process on the third insulating film using a fifth photomask to form a third insulating layer 13. The third insulating layer 13 forms a second via hole 131 at a position corresponding to the drain contact portion 33, and the second via hole 131 penetrates the third insulating layer 13 and exposes at least a portion of the drain contact portion 33.

[0089] Reference Figure 6f , depositing a second conductive film on the third insulating layer 13, and performing a yellow light process on the second conductive film using a sixth photomask to form the third conductive layer 50. The third conductive layer 50 includes a pixel electrode 51 connected to the drain contact portion 33, and the pixel electrode 51 is arranged opposite to the common electrode 42.

[0090] Thus, in the array substrate manufacturing method of this embodiment, a total of 6 photomasks are needed to form the array substrate 100 of the present application. Figure 1 The array substrate 100 of the example requires 10 photomasks, Figure 2The array substrate 100 of the example only needs 6 photomasks, which reduces the number of photomasks used, thereby reducing costs. Moreover, when preparing the gate 41 and the common electrode 42, magnetron sputtering, vacuum evaporation and other processes can be used for deposition, so there is no need to use physical vapor deposition, thereby reducing the number of machines required for the physical vapor deposition process. In this way, while reducing the number of photomasks used and reducing costs, the cost can be further reduced by reducing the number of machines required for the physical vapor deposition process.

[0091] In one embodiment, referring to Figures 1 to 7f , Figures 7a to 7f for Figure 5 Method for preparing array substrate Figure 3 Schematic diagram of the film structure obtained by each step of the array substrate. Figure 5 and Figures 7a to 7f , the array substrate preparation method comprises the following steps:

[0092] S701: providing a substrate 10, and preparing a first conductive layer 20 on one side of the substrate 10, wherein the first conductive layer 20 includes a source electrode 21 and a light shielding electrode 22 which are spaced apart from each other;

[0093] Specifically, refer to Figure 7a , providing a substrate 10, the substrate 10 is divided into a display area AA and a binding area BA located on one side of the display area AA, depositing a first conductive film on the substrate 10, and performing a yellow light process on the first conductive film using a first photomask to form a first conductive layer 20, the first conductive layer 20 includes a source electrode 21 and a light shielding electrode 22 arranged at intervals. The material of the first conductive layer 20 includes a material with low resistance and light shielding performance such as Al, Ti, Mo, Cu, Ni or an alloy thereof.

[0094] S702: preparing an active layer 30 on a side of the first conductive layer 20 away from the substrate 10, and a portion of the active layer 30 is connected to the source electrode 21;

[0095] Specifically, refer to Figure 7b , a first insulating film is deposited on the first conductive layer 20 and the substrate 10 , and a second photomask is used to perform a yellow light process on the first insulating film to form a first insulating layer 11 , wherein the first insulating layer 11 forms a first via hole 111 at a position corresponding to the source electrode 21 .

[0096] Reference Figure 7c , depositing a semiconductor film on the first insulating layer 11 , and performing a yellow light process on the semiconductor film using a third photomask to form the active layer 30 . Part of the active layer 30 is connected to the source electrode 21 through the first via hole 111 .

[0097] S703: preparing a second conductive layer 40 on a side of the active layer 30 away from the substrate 10, wherein the second conductive layer 40 includes a gate 41 arranged corresponding to a portion of the active layer 30 and a common electrode 42 arranged spaced apart from the gate 41, and using the gate 41 as a shield, the active layer 30 is conductorized to form a channel portion 32, a source contact portion 31, and a drain contact portion 33 in the active layer 30, wherein the channel portion 32 is connected between the source contact portion 31 and the drain contact portion 33, and in the thickness direction of the array substrate 100, the channel portion 32 is arranged corresponding to the light shielding electrode 22, and the source contact portion 31 is connected to the source 21;

[0098] Specifically, refer to Figure 7d , a second insulating film, a transparent conductive sublayer 401 and at least one metal sublayer 402 are sequentially deposited on the active layer 30, and a fourth photomask is used to perform a yellow light process on the second insulating film, the transparent conductive sublayer 401 and the metal sublayer 402 to form the second insulating layer 12 and the second conductive layer 40, wherein the material of the transparent conductive sublayer 401 includes indium tin oxide, etc., and the metal sublayer is formed of a material including molybdenum, titanium, copper or molybdenum-titanium alloy, etc. The fourth photomask is a halftone photomask, etc.

[0099] The transparent conductive sublayer 401 and the metal sublayer 402 together form the gate 41, the transparent conductive sublayer 401 forms the common electrode 42, and the metal sublayer 402 does not form the common electrode 42, that is, the gate 41 is formed by the transparent conductive sublayer 401 and the metal sublayer 402, and the common electrode 42 is formed by the transparent conductive sublayer 401. In other words, the gate 41 is formed by multiple sublayers, and the common electrode 42 is formed by a single sublayer.

[0100] Specifically, a half-tone photomask is used to perform a yellow light process on the transparent conductive sublayer 401 and the metal sublayer 402, including a first etching of the transparent conductive sublayer 401 and the metal sublayer 402 to form a gate pattern and a common electrode pattern. At this time, the gate pattern and the common electrode pattern both include the transparent conductive sublayer 401 and the metal sublayer 402, and then the gate pattern and the common electrode pattern are etched for a second time to form a gate 41, while removing the metal sublayer 402 in the common electrode pattern and exposing the transparent conductive sublayer 401 to form the common electrode 42.

[0101] The active layer 30 is conductorized with the gate 41 and the first insulating portion 121 as shielding, so that the active layer 30 forms a channel portion 32, a source contact portion 31 and a drain contact portion 33, and the channel portion 32 is connected between the source contact portion 31 and the drain contact portion 33. In the thickness direction of the array substrate 100, the channel portion 32 is arranged corresponding to the light-shielding electrode 22, and the source contact portion 31 is connected to the source 21.

[0102] S604 : preparing a third conductive layer 50 on a side of the second conductive layer 40 away from the substrate 10 , wherein the third conductive layer 50 includes a pixel electrode 51 connected to the drain contact portion 33 , and the pixel electrode 51 is arranged opposite to the common electrode 42 .

[0103] Reference Figure 7e , depositing a third insulating film on the gate 41, and performing a yellow light process on the third insulating film using a fifth photomask to form a third insulating layer 13. The third insulating layer 13 forms a second via hole 131 at a position corresponding to the drain contact portion 33, and the second via hole 131 penetrates the third insulating layer 13 and exposes at least a portion of the drain contact portion 33.

[0104] Reference Figure 7f , depositing a second conductive film on the third insulating layer 13, and performing a yellow light process on the second conductive film using a sixth photomask to form the third conductive layer 50. The third conductive layer 50 includes a pixel electrode 51 connected to the drain contact portion 33, and the pixel electrode 51 is arranged opposite to the common electrode 42.

[0105] Thus, in the array substrate manufacturing method of this embodiment, a total of 6 photomasks are needed to form the array substrate 100 of the present application. Figure 1 The array substrate 100 of the example requires 10 photomasks, Figure 3 The array substrate 100 of the example only needs 6 photomasks, which reduces the number of photomasks used, thereby reducing costs. Moreover, when preparing the gate 41 and the common electrode 42, magnetron sputtering, vacuum evaporation and other processes can be used for deposition, so there is no need to use physical vapor deposition, thereby reducing the number of machines required for the physical vapor deposition process. In this way, while reducing the number of photomasks used and reducing costs, the cost can be further reduced by reducing the number of machines required for the physical vapor deposition process.

[0106] In one embodiment, referring to Figures 1 to 9f , Figure 8 Another schematic diagram of a process for preparing an array substrate provided in an embodiment of the present application is shown in FIG. Figures 9a to 9f for Figure 8Method for preparing array substrate Figure 4 Schematic diagram of the film structure obtained by each step of the array substrate. Figure 8 and Figures 9a to 9f , the array substrate preparation method comprises the following steps:

[0107] S701: providing a substrate 10, and preparing a first conductive layer 20 on one side of the substrate 10, wherein the first conductive layer 20 includes a source electrode 21, a light shielding electrode 22, and a common electrode 42 which are arranged at intervals;

[0108] Specifically, refer to Figure 9a , providing a substrate 10, the substrate 10 is divided into a display area AA and a binding area BA located on one side of the display area AA, depositing a transparent conductive sublayer 401 and at least one metal sublayer 402 on the substrate 10, using a first photomask to perform a yellow light process on the transparent conductive sublayer 401 and the metal sublayer 402 to form the second insulating layer 12 and the first conductive layer 20, the material of the transparent conductive sublayer 401 includes indium tin oxide, etc., and the material of the metal sublayer includes a single layer or a stacked layer of molybdenum, titanium, copper or molybdenum-titanium alloy, etc. The first photomask is a halftone photomask, etc.

[0109] The transparent conductive sublayer 401 and the metal sublayer 402 jointly form the source 21 and the light-shielding electrode 22. The transparent conductive sublayer 401 forms the common electrode 42, and the metal sublayer 402 does not form the common electrode 42. That is, the source 21 and the light-shielding electrode 22 are formed by the transparent conductive sublayer 401 and the metal sublayer 402, and the common electrode 42 is formed by the transparent conductive sublayer 401. In other words, the source 21 and the light-shielding electrode 22 are formed by multiple sublayers, and the common electrode 42 is formed by a single sublayer.

[0110] Specifically, a half-tone photomask is used to perform a yellow light process on the transparent conductive sublayer 401 and the metal sublayer 402, including a first etching of the transparent conductive sublayer 401 and the metal sublayer 402 to form a source pattern, a light-shielding electrode pattern and a common electrode pattern. At this time, the source pattern, the light-shielding electrode pattern and the common electrode pattern all include the transparent conductive sublayer 401 and the metal sublayer 402, and then the source pattern, the light-shielding electrode pattern and the common electrode pattern are etched for a second time to form the source 21 and the light-shielding electrode 22, and at the same time, the metal sublayer 402 in the common electrode pattern is removed and the transparent conductive sublayer 401 is exposed to form the common electrode 42.

[0111] S702: preparing an active layer 30 on a side of the first conductive layer 20 away from the substrate 10, and a portion of the active layer 30 is connected to the source electrode 21;

[0112] Specifically, refer to Figure 9b , a first insulating film is deposited on the first conductive layer 20 and the substrate 10 , and a second photomask is used to perform a yellow light process on the first insulating film to form a first insulating layer 11 , wherein the first insulating layer 11 forms a first via hole 111 at a position corresponding to the source electrode 21 .

[0113] Reference Fig.9c , depositing a semiconductor film on the first insulating layer 11 , and performing a yellow light process on the semiconductor film using a third photomask to form the active layer 30 . Part of the active layer 30 is connected to the source electrode 21 through the first via hole 111 .

[0114] S703: preparing a second conductive layer 40 on a side of the active layer 30 away from the substrate 10, wherein the second conductive layer 40 includes a gate electrode 41 disposed corresponding to a portion of the active layer, and using the gate electrode 41 as a shield, the active layer 30 is conductively formed so that the active layer 30 forms a channel portion 32, a source contact portion 31, and a drain contact portion 33, wherein the channel portion 32 is connected between the source contact portion 31 and the drain contact portion 33, and in the thickness direction of the array substrate 100, the channel portion 32 is disposed corresponding to the light shielding electrode 22, and the source contact portion 31 is connected to the source 21;

[0115] Specifically, refer to Figure 9d , depositing a second insulating film and a first conductive film on the active layer 30, and performing a yellow light process on the second insulating film and the first conductive film using a fourth photomask to form the second insulating layer 12 and the second conductive layer 40, wherein the material of the first conductive film includes copper, molybdenum, titanium or molybdenum-titanium alloy, etc. The second conductive layer 40 includes a gate 41 corresponding to the channel portion 32, and the second insulating layer 12 includes a first insulating portion 121 corresponding to the gate 41.

[0116] The active layer 30 is conductorized with the gate 41 and the first insulating portion 121 as shielding, so that the active layer 30 forms a channel portion 32, a source contact portion 31 and a drain contact portion 33, and the channel portion 32 is connected between the source contact portion 31 and the drain contact portion 33. In the thickness direction of the array substrate 100, the channel portion 32 is arranged corresponding to the light-shielding electrode 22, and the source contact portion 31 is connected to the source 21.

[0117] S704 : preparing a third conductive layer 50 on a side of the second conductive layer 40 away from the substrate 10 , wherein the third conductive layer 50 includes a pixel electrode 51 connected to the drain contact portion 33 , and the pixel electrode 51 is arranged opposite to the common electrode 42 .

[0118] Reference Fig.9e , depositing a third insulating film on the gate 41, and performing a yellow light process on the third insulating film using a fifth photomask to form a third insulating layer 13. The third insulating layer 13 forms a second via hole 131 at a position corresponding to the drain contact portion 33, and the second via hole 131 penetrates the third insulating layer 13 and exposes at least a portion of the drain contact portion 33.

[0119] Reference Figure 9f , depositing a second conductive film on the third insulating layer 13, and performing a yellow light process on the second conductive film using a sixth photomask to form the third conductive layer 50. The third conductive layer 50 includes a pixel electrode 51 connected to the drain contact portion 33, and the pixel electrode 51 is arranged opposite to the common electrode 42.

[0120] Thus, in the array substrate manufacturing method of this embodiment, a total of 6 photomasks are needed to form the array substrate 100 of the present application. Figure 1 The array substrate 100 of the example requires 10 photomasks, Figure 4 The array substrate 100 of the example only needs 6 photomasks, which reduces the number of photomasks used, thereby reducing costs. Moreover, when preparing the gate 41 and the common electrode 42, magnetron sputtering, vacuum evaporation and other processes can be used for deposition, so there is no need to use physical vapor deposition, thereby reducing the number of machines required for the physical vapor deposition process. In this way, while reducing the number of photomasks used and reducing costs, the cost can be further reduced by reducing the number of machines required for the physical vapor deposition process.

[0121] Based on the same inventive concept, an embodiment of the present application further provides a display panel, wherein the display panel comprises the array substrate 100 of one of the aforementioned embodiments. The display panel comprises a liquid crystal display panel and the like.

[0122] According to the above embodiments, it can be seen that:

[0123] The present application provides an array substrate and a preparation method thereof, and a display panel, wherein the array substrate includes a substrate and a first conductive layer, an active layer, a second conductive layer, and a third conductive layer arranged on the substrate, the source contact portion of the active layer is connected to the source of the first conductive layer, the second conductive layer includes a gate arranged corresponding to the channel portion, the pixel electrode of the third conductive layer is connected to the drain contact portion of the active layer, and at least one of the first conductive layer and the second conductive layer also includes a common electrode arranged opposite to the pixel electrode; in this way, by arranging the source electrode and the light-shielding electrode in the same layer, and arranging the common electrode and the gate and / or the light-shielding electrode in the same layer, the number of photomasks used can be reduced and the cost can be reduced.

[0124] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0125] The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. An array substrate, characterized in that: include: substrate; A first conductive layer, disposed on one side of the substrate, the first conductive layer comprising a source electrode and a light shielding electrode disposed at intervals; an active layer, disposed on a side of the first conductive layer away from the substrate, the active layer comprising a channel portion, a source contact portion and a drain contact portion, the channel portion being connected between the source contact portion and the drain contact portion; In the thickness direction of the array substrate, the channel portion is arranged corresponding to the light shielding electrode, and the source contact portion is connected to the source electrode; A second conductive layer is disposed on a side of the active layer away from the substrate, the second conductive layer comprising a gate disposed corresponding to the channel portion; A third conductive layer is disposed on a side of the second conductive layer away from the substrate, the third conductive layer comprising a pixel electrode connected to the drain contact portion; Wherein, at least one of the first conductive layer and the second conductive layer further includes a common electrode arranged opposite to the pixel electrode.

2. The array substrate according to claim 1, characterized in that: At least one of the first conductive layer and the second conductive layer includes at least a transparent conductive sublayer, and the transparent conductive sublayer forms the common electrode.

3. The array substrate according to claim 2, characterized in that: The material of the transparent conductive sublayer includes indium tin oxide.

4. The array substrate according to claim 2, characterized in that: The second conductive layer includes the transparent conductive sublayer, and the transparent conductive sublayer also forms the gate.

5. The array substrate according to claim 4, characterized in that: The second conductive layer further includes at least one metal sublayer disposed on a side of the transparent conductive sublayer away from the substrate, and the metal sublayer and the transparent conductive sublayer form the gate.

6. The array substrate according to claim 2, characterized in that: The first conductive layer includes the transparent conductive sublayer and at least one metal sublayer arranged on a side of the transparent conductive sublayer away from the substrate, and the metal sublayer and the transparent conductive sublayer form the source electrode and the light shielding electrode.

7. The array substrate according to any one of claims 1 to 6, characterized in that: In a thickness direction of the array substrate, a distance between the gate and the substrate is greater than a distance between the common electrode and the substrate.

8. The array substrate according to any one of claims 1 to 6, characterized in that: The array substrate further includes: a first insulating layer, located between the substrate and the first conductive layer, wherein the first insulating layer is provided with a first via hole at a position corresponding to the source electrode, and the source contact portion is connected to the source electrode through the first via hole; a second insulating layer, located between the active layer and the second conductive layer, the second insulating layer comprising a first insulating portion arranged corresponding to the gate; The third insulating layer is located between the second conductive layer and the third conductive layer. The third insulating layer is provided with a second via hole at a position corresponding to the drain contact portion. The pixel electrode is connected to the drain contact portion through the second via hole.

9. A method for preparing an array substrate, characterized in that: include: Providing a substrate, preparing a first conductive layer on one side of the substrate, wherein the first conductive layer includes a source electrode and a light shielding electrode that are spaced apart; An active layer is prepared on a side of the first conductive layer away from the substrate, and a part of the active layer is connected to the source electrode; A second conductive layer is prepared on a side of the active layer away from the substrate, the second conductive layer includes a gate arranged corresponding to a portion of the active layer and a common electrode arranged at intervals from the gate, and the active layer is conductorized with the gate as a shield, so that the active layer forms a channel portion, a source contact portion and a drain contact portion, the channel portion is connected between the source contact portion and the drain contact portion, and in the thickness direction of the array substrate, the channel portion is arranged corresponding to the light shielding electrode, and the source contact portion is connected to the source; A third conductive layer is prepared on a side of the second conductive layer away from the substrate, wherein the third conductive layer includes a pixel electrode connected to the drain contact portion, and the pixel electrode is arranged opposite to the common electrode.

10. A display panel, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 8.

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