Array substrate, display panel and display device

Abstract

The invention provides an array substrate, a display panel and a display device.The array substrate comprises a substrate, a first wire, a test end, a first ground wire, a second ground wire and an electrostatic ring, the first wire, the test end, the first ground wire, the second ground wire and the electrostatic ring are arranged on the substrate, and the substrate is provided with a display area and a peripheral area surrounding the display area; the test end, the first grounding wire, the second grounding wire and the electrostatic ring are arranged in the peripheral area; the first wire comprises a plurality of first signal wires and / or a plurality of data wires, the electrostatic rings comprise a plurality of first electrostatic rings and / or a plurality of second electrostatic rings, the first end of any first electrostatic ring is connected with one first signal wire, the second end of any first electrostatic ring is connected with a first grounding wire, the first end of any second electrostatic ring is connected with one data wire, and the second end of any second electrostatic ring is connected with the first grounding wire. The test end is connected with the second grounding wire. Compared with the prior art, the display flicker of a low-frequency or broadband display product caused by the fluctuation of the common voltage signal is avoided, and the display quality is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and more specifically, to an array substrate, a display panel, and a display device. Background Art

[0002] In the field of display technology, electrostatic discharge (ESD) protection is a key link to ensure product quality and reliability. In order to effectively reduce the impact of ESD on product quality, related technologies disclose a solution in which an electrostatic ring is designed on the display panel, and key signal lines such as GOA line and Data line are connected to the common signal line through the electrostatic ring, so as to achieve the dispersion and release of ESD.

[0003] However, in low-frequency and broadband display products, the stability of the public signal is crucial to ensure display quality and avoid display anomalies. Although traditional ESD solutions can effectively disperse static electricity, when the GOA line or Data line disperses static electricity, the public signal may be disturbed and slightly fluctuate, resulting in flickering, which seriously affects the display quality of the product. Summary of the invention

[0004] The purpose of the present disclosure is to provide an array substrate, a display panel and a display device to solve the technical problem in the related art that electrostatic interference causes display flickering and affects display quality.

[0005] In order to achieve the above objectives, the present invention adopts the following technical solutions:

[0006] In a first aspect, the present disclosure provides an array substrate, comprising a base substrate, a first wiring, a test terminal, a first grounding wire, a second grounding wire and an electrostatic ring arranged on the base substrate, wherein the base substrate has a display area and a peripheral area surrounding the display area, and the test terminal, the first grounding wire, the second grounding wire and the electrostatic ring are arranged in the peripheral area;

[0007] The first routing line includes multiple first signal lines and / or multiple data lines, the electrostatic ring includes multiple first electrostatic rings and / or multiple second electrostatic rings, the first end of any first electrostatic ring is connected to a first signal line, and the second end is connected to the first ground line, the first end of any second electrostatic ring is connected to a data line, and the second end is connected to the first ground line, and the test end is connected to the second ground line.

[0008] Optionally, the peripheral area includes a first side area and a second side area located on opposite sides of the display area in the first direction, and multiple first signal lines are arranged in the first side area and the second side area, and the first grounding line includes a first sub-grounding line and a second sub-grounding line, the first sub-grounding line is arranged in the first side area, and the second sub-grounding line is arranged in the second side area, and the multiple first signal lines in the first side area are connected to the first sub-grounding line via the first electrostatic ring, and the multiple first signal lines in the second side area are connected to the second sub-grounding line via the first electrostatic ring.

[0009] Optionally, the peripheral area further includes a binding area and a non-binding area located on two opposite sides of the display area in the second direction, and the first sub-grounding line and the second sub-grounding line both extend to the non-binding area and are connected in the non-binding area.

[0010] Optionally, the array substrate also includes a first common electrode line, which is arranged around the display area. In the direction from the display area toward the first side area or the second side area, the first common electrode line, the first sub-ground line or the second sub-ground line, and the first signal line are arranged in sequence.

[0011] Optionally, the array substrate also includes a second common electrode line, which is arranged around the display area. In the direction from the display area toward the first side area or the second side area, the first common electrode line, the first sub-ground line or the second sub-ground line, the first signal line, the second common electrode line, and the second ground line are arranged in sequence.

[0012] Optionally, the peripheral area also includes a binding area and a non-binding area located on opposite sides of the display area in the second direction, the non-binding area includes a second electrostatic ring area, the second electrostatic ring is arranged in the second electrostatic ring area, and the data line extends to the second electrostatic ring area and is connected to the first end of the second electrostatic ring.

[0013] Optionally, the first common electrode line and the second common electrode line are connected via a connecting line extending along a first direction, and the first ground line is cross-connected with the second end of the second electrostatic ring at the position of the first common electrode line.

[0014] Optionally, the binding area includes a first electrostatic ring area, the first electrostatic ring is arranged in the first electrostatic ring area, the first signal line extends to the binding area and is connected to the first end of the first electrostatic ring through a first connecting line, the first grounding line extends to the binding area and is connected to the second end of the first electrostatic ring, and in the direction from the display area toward the binding area, the first common electrode line, the first grounding line, and the first electrostatic ring area are arranged in sequence, and the orthographic projection of the first connecting line on the substrate does not overlap with the orthographic projections of the first common electrode line and the first grounding line on the substrate.

[0015] Optionally, the first ground wire extends to the binding area and forms a first connection end, and the first connection end is used to connect to the ground signal output terminal in the flexible circuit board. The second ground wire extends to the binding area and forms a second connection end, and the second connection end is used to connect to the test signal output terminal in the flexible circuit board.

[0016] Optionally, the array substrate further comprises a gate layer, a first insulating layer, an active layer, a source-drain metal layer, a light-emitting layer, a common electrode layer, a second insulating layer and a pixel electrode layer sequentially stacked on the base substrate;

[0017] The first grounding line includes a first metal line arranged in the same layer as the gate layer and a second metal line arranged in the same layer as the source and drain metal layer, the orthographic projection of the first metal line on the base substrate overlaps with the orthographic projection of the second metal line on the base substrate, and the first metal line and the second metal line are connected through a first via on the first insulating layer.

[0018] Optionally, the array substrate also includes a first short-circuit ring and a second short-circuit ring, and the electrostatic ring also includes a third electrostatic ring and a fourth electrostatic ring, the first short-circuit ring is connected to the second end of each first electrostatic ring, and the first short-circuit ring is connected to the first ground wire via the third electrostatic ring; the second short-circuit ring is connected to the second end of each second electrostatic ring, and the second short-circuit ring is connected to the first ground wire via the fourth electrostatic ring.

[0019] Optionally, a line width of the first ground line and / or the second ground line is less than or equal to 10 microns.

[0020] Optionally, the second ground line includes a third sub-ground line and a fourth sub-ground line, and the second ground line is provided in both the first side area and the second side area. The test end includes a first data signal test end, a second data signal test end, a third data signal test end and a control signal test end. Two of the test ends are respectively connected to the third sub-ground line and the fourth sub-ground line in the first side area, and the other two of the test ends are respectively connected to the third sub-ground line and the fourth sub-ground line in the second side area. The first data signal test end, the second data signal test end and the third data signal test end are configured to input data signals in a test phase and to input ground signals in a non-test phase. The control signal test end is configured to input a first level signal in a test phase and to input a second level signal in a non-test phase.

[0021] A second aspect of the present disclosure provides a display panel, comprising the array substrate as described above.

[0022] A third aspect of the present disclosure provides a display device, comprising the display panel as described above.

[0023] The beneficial effects of the present disclosure are as follows:

[0024] In the array substrate of the disclosed embodiment, a first grounding wire is added in the peripheral area of ​​the display area, and the electrostatic ring is connected to the first grounding wire. Such a configuration can, on the one hand, avoid interference with the common voltage signal when the data line or the first signal line outputs different voltage signals or disperses different static electricity, avoid display flickering caused by fluctuations in the common voltage signal in low-frequency or broadband display products, and improve display quality. On the other hand, the connection between the second grounding wire and the test end can meet the testing requirements of the product in the production stage and the grounding requirements of the product after production. By adding the first grounding wire, the grounding of the electrostatic ring can be achieved without affecting the original second grounding wire. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The specific implementation methods of the present disclosure are further described in detail below with reference to the accompanying drawings.

[0026] Figure 1 It is a schematic diagram of the principle of connecting a data line and an electrostatic ring in the related art;

[0027] Figure 2 for Figure 1 Schematic diagram of the working principle of the electrostatic ring corresponding to the data line in the middle;

[0028] Figure 3 A schematic plan view of an array substrate provided in an embodiment of the present disclosure;

[0029] Figure 4A schematic diagram of wiring distribution of an array substrate provided in an embodiment of the present disclosure;

[0030] Figure 5 A schematic diagram of the film layer structure of an array substrate provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0032] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0033] In the related art, in order to effectively reduce the impact of ESD on product quality, the solution of connecting key signal lines such as data line, first signal line (GOA line) and test terminal (CT line) to the electrostatic ring is generally adopted, wherein the first signal line specifically refers to the routing of the input signal of the gate driver on array (GOA) in the display panel. The input signal of the GOA unit includes but is not limited to the clock signal, the frame start signal, etc. Correspondingly, the first signal line includes the clock signal line, the frame start signal line, etc. Please refer to Figure 1 , Figure 1 FIG. 1 is a schematic diagram showing the principle of connecting a data line to an electrostatic ring in the related art. Figure 1As shown, in the related art, each data line is connected to an electrostatic ring (ESD ring), and the electrostatic rings of each data line are connected to each other through a shorting ring (Shorting ring), and then connected to the common electrode signal line (VCOM) through an independent electrostatic ring. Figure 1 The principle shown is the same, that is, each first signal line is also connected to an electrostatic ring, and the electrostatic rings of each first signal line are also connected to each other through a short-circuit ring, and then connected to the common electrode signal line (VCOM) through an independent electrostatic ring.

[0034] Taking the data line as an example, the principle of using the static ring to protect the data line from static electricity is as follows: Figure 2 As shown, Figure 2 The left side is the equivalent circuit of the data line corresponding to the electrostatic ring, and the right side is the film layer structure of the data line corresponding to the electrostatic ring. Figure 2 The first pattern represents the gate layer, i.e., the Gate layer; the second pattern represents the source / drain metal layer, i.e., the S / D layer; and the third pattern represents the semiconductor active layer, i.e., the Active layer. A gate is formed on the Gate layer, a source and a drain are formed on the S / D layer, and an active part is formed on the Active layer. The source and the drain are both connected to the active part. The gate, the source, and the drain form a transistor. Figure 2 As shown, when ESD charges gather on the common electrode line VCOM and the potential is higher than the first voltage Vth, the gate of the second transistor T2 controlled by the common electrode line VCOM is opened, the source and drain of the second transistor T2 are turned on, and the charges are evenly dispersed to the gate, source, GOAline and other signal lines of the transistor, achieving the function of dispersing charges; when the ESD charges are large enough, the charges conducted to the gate, source, and GOAline can turn on the first transistor T1, forming an electrostatic loop. On the contrary, when ESD charges gather on the gate, source, GOAline and other signal lines, and the potential is greater than the first voltage Vth of the first transistor T1, the first transistor T1 is turned on, the source and drain are turned on, and the charges are transferred to the common electrode line VCOM and the gate and source of the transistor. When the ESD charges are large enough, the charges conducted to the gate, source, and common electrode line VCOM can turn on the first transistor T2, forming an electrostatic loop.

[0035] When the above solution is applied to conventional display products (such as display products with a refresh rate greater than or equal to 60Hz), there will be no obvious display problems. However, in low-frequency (for example, refresh rates as low as 20Hz, 10Hz, 5Hz, 1Hz, etc.) and broadband display products, the product itself has a relatively high stability requirement for the stability of the VCOM signal. Figure 1Although the traditional ESD connection method shown can effectively disperse static electricity, when the data line and the first signal line output different voltage signals or disperse ESD static electricity, the VCOM signal may be disturbed and fluctuate slightly. This fluctuation is particularly obvious in the low-frequency display mode because it will aggravate the brightness difference between the positive and negative frames, resulting in increased screen flicker, thereby reducing the product's display quality and user experience.

[0036] Therefore, how to ensure the ESD protection effect while maintaining the stability of the VCOM signal, especially in low-frequency and broadband display products, has become an urgent problem to be solved.

[0037] In order to solve the above technical problems, the present disclosure provides an array substrate, a display panel and a display device. Figure 3 to Figure 4 , Figure 3 A schematic plan view of an array substrate provided in an embodiment of the present disclosure is shown in FIG. Figure 4 A schematic diagram of the structure of an array substrate provided in an embodiment of the present disclosure, Figure 5 A schematic diagram of the film layer structure of an array substrate provided in an embodiment of the present disclosure.

[0038] like Figures 3 to 5 As shown, the array substrate includes a base substrate 10, a first wiring, a test terminal 30, a first grounding wire 40, a second grounding wire 50 and an electrostatic ring arranged on the base substrate 10, the base substrate 10 has a display area AA and a peripheral area surrounding the display area AA, and the test terminal 30, the first grounding wire 40, the second grounding wire 50 and the electrostatic ring are arranged in the peripheral area;

[0039] The first routing includes multiple first signal lines 210 and / or multiple data lines 220, the electrostatic ring includes multiple first electrostatic rings 610 and / or multiple second electrostatic rings 620, the first end of any first electrostatic ring 610 is connected to a first signal line 210, and the second end is connected to the first ground line 40, the first end of any second electrostatic ring 620 is connected to a data line 220, and the second end is connected to the first ground line 40, and the test end 30 is connected to the second ground line 50.

[0040] Compared with the related art, the array substrate provided by the embodiment of the present disclosure adds a first grounding wire in the peripheral area of ​​the display area, and the electrostatic ring is connected to the first grounding wire. Such a configuration can, on the one hand, avoid interference with the common voltage signal when the data line or the first signal line outputs different voltage signals or disperses different static electricity, and avoid flickering of low-frequency or broadband display products due to fluctuations in the common voltage signal. On the other hand, the connection between the second grounding wire and the test end can meet the testing requirements of the product in the production stage and the grounding requirements of the product after production is completed. By adding the first grounding wire, the grounding of the electrostatic ring can be achieved without affecting the original second grounding wire.

[0041] In a possible implementation, the array substrate also includes a short-circuit ring, the short-circuit ring includes a first short-circuit ring 710 and a second short-circuit ring 720, the electrostatic ring also includes a third electrostatic ring 630 and a fourth electrostatic ring 640, the first short-circuit ring 710 is connected to the second end of each first electrostatic ring 610, and the first short-circuit ring 710 is connected to the first ground wire 40 via the third electrostatic ring 630; the second short-circuit ring 720 is connected to the second end of each second electrostatic ring 620, and the second short-circuit ring 720 is connected to the first ground wire 40 via the fourth electrostatic ring 640.

[0042] like Figure 4 As shown, in the embodiment of the present disclosure, each first electrostatic ring 610 is connected together via the first short-circuit ring 710, and the first short-circuit ring 710 is connected to an independent electrostatic ring (that is, the third electrostatic ring 630), and the independent third electrostatic ring 630 is connected to the first grounding wire 40, so that each first electrostatic ring 710 can be connected to the first grounding wire 40 via the first short-circuit ring 710 and the third electrostatic ring 630. Correspondingly, in the embodiment of the present disclosure, each second electrostatic ring 620 is connected together via the second short-circuit ring 720, and the second short-circuit ring 720 is connected to an independent electrostatic ring (that is, the fourth electrostatic ring 640), and the independent fourth electrostatic ring 640 is connected to the first grounding wire 40, so that each second electrostatic ring 720 can be connected to the first grounding wire 40 via the second short-circuit ring 720 and the fourth electrostatic ring 640. The independent electrostatic ring in the embodiment of the present disclosure means that the electrostatic ring is not connected to the first signal line 210 or the data line 220 . For example, for the third electrostatic ring 630 , independent means that the third electrostatic ring 630 is not connected to any first signal line 210 .

[0043] It can be understood that the first electrostatic ring 610, the second electrostatic ring 620, the third electrostatic ring 630, and the fourth electrostatic ring 640 in the embodiment of the present disclosure are divided based on their different connection relationships with other structures and different objects of action. For example, the first electrostatic ring 610 is connected to the first signal line 210, and is an electrostatic ring for electrostatically protecting the first signal line 210. The second electrostatic ring 620 is connected to the data line 220, and is an electrostatic ring for electrostatically protecting the data line 220. In specific implementation, the first electrostatic ring 610, the second electrostatic ring 620, the third electrostatic ring 630, and the fourth electrostatic ring 640 can be implemented using electrostatic rings of the same structure or using electrostatic rings of different structures.

[0044] For example, Figure 4 As shown, the structures of the first electrostatic ring 610 and the second electrostatic ring 620 are different, wherein the second electrostatic ring 620 can be understood as a basic electrostatic ring unit, and the first electrostatic ring 610 can be understood as being formed by two basic electrostatic ring units connected in series. Such a setting can enhance the dispersion of static electricity, that is, static electricity needs to pass through four transistors before it can diffuse from one end to the other end, such as diffusing from the first routing line to the first ground line 40.

[0045] In a possible implementation, the peripheral area includes a first side area 110 and a second side area 120 located on opposite sides of the display area AA in the first direction, and a binding area 130 and a non-binding area 140 located on opposite sides of the display area in the second direction. The first signal line is arranged in the first side area 110 and the second side area 120, the data driving circuit is bound in the binding area 130, which is also called the DP (Data Pad, data binding side) side, and the non-binding area 140 opposite to the DP side is also called the DPO (Data Pad Opposite, data binding opposite side) side.

[0046] Optionally, the first direction is perpendicular to the second direction. Exemplarily, in the horizontal plane where the array substrate is located, the first direction is the horizontal direction X, and the second direction is the horizontal direction Y. In this case, the first side region 110 is the left peripheral region of the display area AA, the second side region 120 is the right peripheral region of the display area AA, the binding region 130 is the lower peripheral region of the display area AA, and the non-binding region 140 is the upper peripheral region of the display area AA.

[0047] In a possible implementation, the array substrate includes a plurality of gate lines and a plurality of data lines 220, each gate line is connected to a row of sub-pixels to provide a row drive signal for the row of sub-pixels, and each data line 220 is connected to a column of sub-pixels to provide a data drive signal for the column of sub-pixels. The connection relationship between the gate line and the data line 220 and the sub-pixels is a mature technology in the art and will not be described in detail in the embodiments of the present disclosure.

[0048] In addition, the peripheral area of ​​the array substrate also includes a gate drive circuit, namely a GOA circuit. The GOA circuit includes multiple cascaded GOA units. Each GOA unit is connected to a gate line to provide the required voltage for the gate line. The input signal line of the GOA circuit is also the GOA line, which is referred to as the first signal line 210 in the embodiment of the present disclosure.

[0049] It can be understood that the GOA circuit can be either a unilateral driving circuit or a bilateral driving circuit. The unilateral driving circuit means that the GOA circuit is only arranged on one side of the display area AA, such as only arranging the GOA circuit in the first side area 110 on the left side of AA, in which case each gate line is driven only by the GOA unit in the first side area 110; the bilateral driving circuit means that the GOA circuit is designed on both the left and right sides of the AA area, that is, the GOA circuit is arranged in both the first side area 110 and the second side area 120, in which case each gate line is driven simultaneously by two GOA units on the left and right sides. In the disclosed embodiment, the GOA circuit is described as a bilateral driving circuit as an example.

[0050] In the disclosed embodiment, electrostatic protection is provided for the first signal line 210 and the data line 220. Specifically, the first routing includes a plurality of first signal lines 210 and a plurality of data lines 220, one first signal line 210 is connected to a first electrostatic ring 610, and electrostatic protection is provided for the first signal line 210 through the first electrostatic ring 610, and one data line 220 is connected to a second electrostatic ring 620, and electrostatic protection is provided for the data line 220 through the second electrostatic ring 620.

[0051] In a possible implementation, the GOA circuit is a bilateral driving circuit, and multiple first signal lines 210 are arranged in the first side area 110 and the second side area 120, the first ground line 40 includes a first sub-ground line and a second sub-ground line, the first sub-ground line is arranged in the first side area 110, and the second sub-ground line is arranged in the second side area 120, the multiple first signal lines 210 in the first side area 110 are connected to the first sub-ground line via the first electrostatic ring 610, and the multiple first signal lines 210 in the second side area 120 are connected to the second sub-ground line via the first electrostatic ring 610.

[0052] In the present disclosure, Figure 3 to Figure 4 As shown, a plurality of first signal lines 210 are arranged in the first side area 110 and the second side area 120. In order to realize the grounding of the first signal lines 210 on the left and right sides, a grounding line is added in each of the first side area 110 and the second side area 120, which are the first sub-grounding line and the second sub-grounding line respectively. Such a setting can ensure that the charge distribution on the left and right sides of the array substrate is more balanced. When static electricity is generated on the array substrate, the first sub-grounding line and the second sub-grounding line can disperse the static electricity simultaneously and evenly to prevent static electricity from accumulating on the array substrate, thereby reducing the interference of static electricity on the display effect.

[0053] It can be understood that in the embodiment of the present disclosure, the setting of the second sub-grounding line in the second side area 120 is the same as the setting of the first sub-grounding line in the first side area 110. It can also be understood that the second sub-grounding line and the first sub-grounding line are symmetrically distributed with the display area AA as the center. The specific arrangement of the second sub-grounding line in the embodiment of the present disclosure will not be described in detail, and reference can be made to the description of the first sub-grounding line.

[0054] Optionally, both the first sub-grounding line and the second sub-grounding line extend to the non-binding area 140 and are connected in the non-binding area 140 .

[0055] In the disclosed embodiment, the first sub-grounding wire and the second sub-grounding wire are connected together, so that the static electricity in the first wiring can be diffused outward from both ends, and it is less likely to heat up and burn when encountering a large current.

[0056] In a possible implementation, the array substrate also includes a first common electrode line 810, which is arranged around the display area AA. In the direction of the display area AA toward the first side area 110 or the second side area 120, the first common electrode line 810, the first sub-ground line or the second sub-ground line, and the first signal line 210 are arranged in sequence.

[0057] Specifically, in the first side area 110, in the direction from the display area AA toward the first side area 110, the first common electrode line 810, the first sub-grounding line, and the first signal line 210 are sequentially arranged in parallel. Similarly, in the second side area 120, in the direction from the display area AA toward the second side area 120, the first common electrode line 810, the second sub-grounding line, and the first signal line 210 are sequentially arranged in parallel.

[0058] Optionally, the array substrate also includes a second common electrode line 820, which is arranged around the display area AA. In the direction of the display area AA toward the first side area 110 or the second side area 120, the first common electrode line 810, the first sub-ground line or the second sub-ground line, the first signal line 210, the second common electrode line 820, and the second ground line 50 are arranged in sequence.

[0059] Specifically, Figure 3 As shown, in the first side region 110, along the direction away from the display area AA, the first common electrode line 810, the first sub-ground line, the first signal line 210, the second common electrode line 820, and the second ground line 50 are sequentially arranged at intervals, and further, each line (including the first common electrode line 810, the first sub-ground line, the first signal line 210, the second common electrode line 820, and the second ground line 50) is arranged in parallel along the first direction X and extends along the second direction Y in the first side region 110. Similarly, in the second side region 120, along the direction away from the display area AA, the first common electrode line 810, the second sub-ground line, the first signal line 210, the second common electrode line 820, and the second ground line 50 are sequentially arranged at intervals, and further, each line is arranged in parallel along the first direction X and extends along the second direction Y in the second side region 120.

[0060] Optional, such as Figure 3 As shown, the first common electrode line 810 can also be understood as an inner common electrode line, and the second common electrode line 820 can also be understood as an outer common electrode line. The first common electrode line 810 and the second common electrode line 820 are connected together by a connecting line 830 extending along the first direction X, and the first ground line 40 (including the first sub-ground line and the second sub-ground line) and each first signal line 210 are arranged between the first common electrode line 810 and the second common electrode line 820.

[0061] In a possible implementation, the non-binding area 140 includes a second electrostatic ring area 1410 , the second electrostatic ring 620 is disposed in the second electrostatic ring area 1410 , and the data line 220 extends to the second electrostatic ring area 1410 and is connected to the first end of the second electrostatic ring 620 .

[0062] In the disclosed embodiment, the second end of each second electrostatic ring 620 is connected to the first grounding wire 40, specifically through the second short-circuit ring 720 and the fourth electrostatic ring 640. Since each second electrostatic ring 620 is connected together through the second short-circuit ring 720 and connected to the fourth electrostatic ring 620, the grounding of each second electrostatic ring 620 can be achieved by only connecting the fourth electrostatic ring 620 to the first grounding wire 40.

[0063] For example, Figure 4 As shown, in the second electrostatic ring area 1410, each second electrostatic ring 620 and the fourth electrostatic ring 640 are spaced apart and arranged in parallel along the first direction X, and the fourth electrostatic ring 640 is arranged between the second electrostatic ring 620 and the first common electrode line 810, that is, the fourth electrostatic ring 640 is close to the first common electrode line 810. With such an arrangement, when the fourth electrostatic ring 640 is connected to the first ground line 40, unnecessary cross-wires can be reduced and the wiring is simple.

[0064] In a possible implementation, the array substrate also includes a gate layer (Gate) 101, a first insulating layer (GI) 102, an active layer (Active) 103, a source / drain metal layer (S / D) 104, a light-emitting layer, a common electrode layer, a second insulating layer and a pixel electrode layer stacked in sequence on the base substrate 10, the first ground line 40 includes a first metal line arranged in the same layer as the gate layer and a second metal line arranged in the same layer as the source / drain metal layer, the orthographic projection of the first metal line on the base substrate overlaps with the orthographic projection of the second metal line on the base substrate 10, and the first metal line and the second metal line are connected through a first via on the first insulating layer.

[0065] Please refer to Figure 5 , Figure 5 is a schematic diagram of the film layer structure of the array substrate in the thickness direction, such as Figure 5 As shown, in the display area AA, a plurality of gates 1011 are formed on the gate layer 101, a plurality of active portions 1031 are formed on the active layer 103, a source electrode 1041 and a drain electrode 1042 are formed on the source-drain metal layer 104, and the gates 1011, the active portions 1031, the source electrode 1041, and the drain electrode 1042 at corresponding positions form a transistor T0, and the transistor T0 is used to drive the corresponding light-emitting unit to emit light. In addition, a plurality of light-emitting units are formed on the light-emitting layer, a plurality of common electrodes are formed on the common electrode layer, a plurality of pixel electrodes are formed on the pixel electrode layer, and the light-emitting layer, the common electrode layer, the second insulating layer, and the pixel electrode layer are not formed. Figure 5 The gate 1011 is connected to the gate line, the source 1041 is connected to the data line 220, and the drain 1042 is connected to the pixel electrode. Optionally, the gate line and the gate 1011 are arranged in the same layer, and the data line 220 and the source 1041 and the drain 1042 are arranged in the same layer.

[0066] It can be understood that, in some embodiments, the gate 1011 is located on the side of the active layer 103 away from the base substrate 10, that is, a top gate structure; in other embodiments, the gate 1011 is located on the side of the active layer 103 close to the base substrate 10, that is, a bottom gate structure, which is not limited in this application. In addition, the film layer structure for realizing driving and display in the array substrate, including but not limited to the specific structure of the gate layer 101, the first insulating layer 102, the active layer 103, the source and drain metal layer 104, the light-emitting layer, the common electrode layer, and the pixel electrode layer, can also adopt the mature structure already in the relevant technology, which is not limited in this disclosure.

[0067] Optional, such as Figure 4 As shown, Figure 4 The first filling pattern represents the gate layer 101, the second filling pattern represents the source-drain metal layer 104, the third filling pattern represents the active layer 103, and the fourth filling pattern represents the gate layer 101 and the source-drain metal layer 104. In the embodiment of the present disclosure, the first grounding wire 40 is made of the Gate&S / D layer, that is, the first grounding wire 40 is a double-layer structure made of the gate layer 101 and the source-drain metal layer 104, and the first metal wire in the Gate layer and the second metal wire in the S / D layer can be connected together through the vias in the GI layer.

[0068] Optionally, the first common electrode line 810 and the second common electrode line 820 are also made of the Gate & S / D layer, that is, the first common electrode line 810 / the second common electrode line 820 is a two-layer structure, one layer is located in the Gate layer, and one layer is located in the S / D layer, and the first common electrode line 810 / the second common electrode line 820 in the Gate layer and the S / D layer are connected together through the via hole in the GI layer. In addition, since the first common electrode line 810 and the second common electrode line 820 are arranged in different layers from the common electrode, the first common electrode line 810 and the second common electrode line 820 can be connected to the common electrode in the common electrode layer through the via hole.

[0069] Optionally, the first signal line 210 is also made of the Gate & S / D layer, and the first signal line 210 in the Gate layer and the S / D layer are connected together through vias in the GI layer.

[0070] Optionally, in the peripheral area of ​​the display area AA, the structure of the second electrostatic ring 620 is as follows: Figure 2 As shown, it includes two transistors T1 and T2 connected together, and the transistors T1 and T2 and the transistor T0 in the display area can be formed in the same process. It can be understood that the embodiment of the present disclosure does not limit the specific structure of the first electrostatic ring, the second electrostatic ring, the third electrostatic ring and the fourth electrostatic ring, and the specific structure of each electrostatic ring and how it is connected to the data line and the first signal line do not affect the protection scope of the present invention.

[0071] Optionally, the first common electrode line 810 and the second common electrode line 820 are connected via a connecting line 830 extending along the first direction X, and the first ground line 410 and the second end of the second electrostatic ring 620 are cross-connected at the position of the first common electrode line 810 .

[0072] Among them, the first sub-grounding wire and the second end of the second electrostatic ring 620 are connected by cross-line at the position of the first common electrode line 810, specifically: the first sub-grounding wire and the fourth electrostatic ring 640 are connected by cross-line at the position of the first common electrode line 810, thereby realizing the connection between the first sub-grounding wire and each second electrostatic ring 620.

[0073] In the embodiment of the present disclosure, since the first sub-grounding line is located outside the first common electrode line 810 and the fourth electrostatic ring 640 is located inside the first common electrode line 810, the fourth electrostatic ring 640 needs to be connected to the first sub-grounding line through an interlayer jumper. Figure 4 As shown, at the position of area Q10, the first common electrode line 810 includes an end portion formed on the gate layer 101, and the first sub-grounding line is connected to the fourth electrostatic ring 640 through a third connecting line 930 formed on the source-drain metal layer 104 and a fourth connecting line 940 formed on the gate layer 101, wherein the orthographic projection of the third connecting line 930 on the substrate 10 intersects with the first common electrode line 810, that is, it crosses the first common electrode line 810, specifically, the first end of the third connecting line 930 located on the outside of the first common electrode line 810 is connected to the first sub-grounding line on the source-drain metal layer 104, and the second end of the third connecting line 930 located on the inside of the first common electrode line 810 is connected to the fourth connecting line 940 through a via on the first insulating layer 102. Optionally, the first common electrode line 820 and the first sub-ground line extend to above the first routing line 210 and the second electrostatic ring area 1410, the fourth connecting line 940 extends from the fourth electrostatic ring 640 to above the second electrostatic ring area 1410, and the third connecting line 930 connects the first sub-ground line with the fourth electrostatic ring 640 above the first routing line 210 and the second electrostatic ring area 1410. Such a setting can reduce the straight line between the first signal line 210 and the fourth electrostatic ring 640, reduce signal interference and simplify wiring complexity.

[0074] In a possible implementation, the first electrostatic ring 610 is disposed in the binding area 130, and the first sub-grounding line extends from the first side area 110 to the binding area 130 and is connected to the first electrostatic ring 610 in the binding area 130. Similarly, the second sub-grounding line extends from the second side area 120 to the binding area 130 and is connected to the first electrostatic ring 610 in the binding area 130.

[0075] Optionally, the binding area 130 includes a first electrostatic ring area 1310, the first electrostatic ring 610 is arranged in the first electrostatic ring area 1310, the first signal line 210 extends to the binding area 130 and is connected to the first end of the first electrostatic ring 610 through the first connecting line 910, the first grounding line 40 extends to the binding area 130 and is connected to the second end of the first electrostatic ring 610, and in the direction of the display area AA toward the binding area 130, the first common electrode line 810, the first grounding line 40, and the first electrostatic ring area 1310 are arranged in sequence, and the orthographic projection of the first connecting line 910 on the base substrate 10 does not overlap with the orthographic projection of the first common electrode line 810 and the first grounding line 40 on the base substrate 10.

[0076] In the embodiment of the present disclosure, the connection between the second end of each first electrostatic ring 610 and the first grounding wire 40 is specifically achieved through the first short-circuit ring 710 and the third electrostatic ring 630. Since the first electrostatic rings 610 are connected together through the first short-circuit ring 710 and connected to the third electrostatic ring 630, the connection between each first electrostatic ring 610 and the first grounding wire 40 can be achieved by only connecting the third electrostatic ring 630 to the first grounding wire 40.

[0077] For example, Figure 4 As shown, in the first electrostatic ring area 1310, each of the first electrostatic rings 610 and the third electrostatic ring 630 is spaced and arranged in parallel along the first direction X. When the first signal line 210 extends to the binding area 130 and is connected to the first end of the first electrostatic ring 610, taking the first signal line 210 in the first side area 110 as an example, at this time, the first signal line 210 extends to the binding area 130 and is connected to the first end of the first electrostatic ring 610, including: the first signal line 210 extends to the edge area adjacent to the binding area 130 and the first side area 110, in the binding area 130, the first signal line 210 includes an end extending along the first direction X, and the first end of each first electrostatic ring 610 is connected to the end of each first signal line 210 in the binding area 130 through an interlayer jumper. For example, Figure 4As shown, the first end of each first electrostatic ring 610 is connected to the end of each first signal line 210 in the binding area 130 through the first connecting line 910 and the second connecting line 920, wherein the first connecting line 910 is located in the source-drain metal layer 104, and the second connecting line 920 is located in the gate layer 101. In the source-drain metal layer 104, one end of the first connecting line 910 is connected to the first end of the first electrostatic ring 610, and in the gate layer 101, one end of the second connecting line 920 is connected to the end of the first signal line 210 extending to the binding area 130, and the other end of the first connecting line 910 and the other end of the second connecting line 920 are connected together through a via on the first insulating layer (GI) 102, thereby realizing inter-layer cross-line connection.

[0078] Among them, the first common electrode line 810, the first ground line 40, the first electrostatic ring area 1310. The first signal line 210 is sequentially arranged in the direction from the display area AA toward the binding area 130, and the orthographic projection of the first connecting line 910 on the base substrate 10 does not overlap with the orthographic projection of the first common electrode line 810 and the first ground line 40 on the base substrate 10. For example, Figure 4 As shown, the second end of each first electrostatic ring 610 extends to above the first electrostatic ring area 1310 and is connected to the first short-circuit ring 710 arranged above the first electrostatic ring area 1310. The first connecting line 910 is arranged below the first electrostatic ring area 1310, and the first end of each first electrostatic ring 610 is connected to the first signal line 210 via the first connecting line 910. Compared with the scheme of setting the first grounding line 40 below the first electrostatic ring area 1310, such a setting can reduce unnecessary cross-line overlap when the first electrostatic ring 610 is connected to the first signal line 210 via the first connecting line 910, thereby reducing the risk of electrostatic breakdown.

[0079] In a possible implementation, the first grounding wire 40 extends to the binding area 130 and forms a first connection end, and the first connection end is used to connect to the ground signal output end in the flexible circuit board FPC, and the second grounding wire 50 extends to the binding area 130 and forms a second connection end, and the second connection end is used to connect to the test signal output end in the flexible circuit board FPC. In the embodiment of the present disclosure, the flexible circuit board FPC can output a ground signal to the first grounding wire 40 through the ground signal output end, and can output a test signal to the second grounding wire 50 through the test signal output end.

[0080] In a possible implementation, a line width of the first ground line 40 and / or the second ground line 50 is less than or equal to 10 micrometers.

[0081] Optionally, the line width of the first ground line 40 is less than or equal to 10 micrometers, that is, the line widths of the first sub-ground line and the second sub-ground line are both less than or equal to 10 micrometers.

[0082] Optionally, the line width of the second ground line 50 is less than or equal to 10 microns.

[0083] It is understandable that the line width of the first ground line 40 and / or the second ground line 50 can also be other values, and can be designed according to the frame size requirements of the display panel. Among them, the smaller the width of the first side area 110 and the second side area 120, the more conducive to achieving a narrow frame of the display panel. In the display panel, the line width of the first common electrode line 810 and the second common electrode line 820 is usually 100 to 300 microns, and the line width of each first signal line 210 is usually 15 to 50 microns. Although the first ground line 40 is added to the first side area 110 and the second side area 120 in the embodiment of the present disclosure, due to the small line width of the first ground line 40, it is negligible relative to the overall line width of the first signal line 210, the first common electrode line 810 and the second common electrode line 820. Therefore, the embodiment of the present disclosure has little effect on the narrow frame of the display panel and can be ignored.

[0084] In a possible implementation, the second ground line 50 includes a third sub-ground line 510 and a fourth sub-ground line 520, and the second ground line 50 is provided in both the first side area 110 and the second side area 120. The test terminal 30 includes a first data signal test terminal DR, a second data signal test terminal DG, a third data signal test terminal DB and a control signal test terminal SW. Two of the test terminals 50 are respectively connected to the third sub-ground line 510 and the fourth sub-ground line 520 in the first side area 110, and the other two test terminals are respectively connected to the third sub-ground line 510 and the fourth sub-ground line 520 in the second side area 120. The first data signal test terminal DR, the second data signal test terminal DG, and the third data signal test terminal DB are configured to output a test data signal in a test phase and output a ground signal in a non-test phase. The control signal test terminal SW is configured to output a first level signal in a test phase and input a second level signal in a non-test phase.

[0085] In the embodiment of the present disclosure, the second ground line 50 is arranged at the outermost side of the display area AA, and includes two sub-ground lines. Among them, the first ends of the third sub-ground line 510 and the fourth sub-ground line 520 in the first side area 110 are respectively connected to the first data signal test terminal DR and the second data signal test terminal DG, and the first ends of the third sub-ground line 510 and the fourth sub-ground line 520 in the second side area 120 are respectively connected to the third data signal test terminal DB and the control signal test terminal SW. In addition, the second ends of the third sub-ground line 510 and the fourth sub-ground line 520 in the first side area 110 and the second end of the third sub-ground line 510 in the second side area 120 are respectively connected to the R sub-pixel data line, the G sub-pixel data line, and the B sub-pixel data line of the display panel, for outputting the test data signal to the corresponding sub-pixel; the second end of the fourth sub-ground line 520 in the second side area 120 is connected to the SW switch, for controlling the conduction state of the SW switch, wherein the SW switch can control the conduction state between the second ground line 50 and each column of sub-pixel data lines.

[0086] During the test process of the display panel, the control signal test terminal SW outputs a first level signal (for example, a high level signal), the first data signal test terminal DR, the second data signal test terminal DG, and the third data signal test terminal DB output a test data signal, and the first level signal and the data signal are transmitted to the display panel via the second ground line 50, so that the display panel displays normally, so as to detect whether the display panel has any defects; when the display panel is completed, the control signal test terminal SW outputs a second level signal (for example, a low level signal VGL), the first data signal test terminal DR, the second data signal test terminal DG, and the third data signal test terminal DB output a ground signal, wherein when the control signal test terminal SW outputs a low level signal, the SW switch is completely turned off, which can avoid interference with normal display. Among them, the control signal test terminal SW is used to output a control signal, which can control the output of the second ground line 50 (including the third sub-ground line 510 and the fourth sub-ground line 520 in the first side area 110 and the second side area 120). When the control signal is a first level signal, the SW switch is turned on, and the second ground line 50 can output a test data signal to the display panel. When the control signal is a second level signal, the SW switch is turned off, and the path for the second ground line 50 to output the test data signal to the display panel is disconnected.

[0087] In the embodiment of the present disclosure, the first data signal test terminal DR, the second data signal test terminal DG, the third data signal test terminal DB and the control signal test terminal SW are arranged in the binding area 130 below the display area AA, and the second grounding line 50 extends to the edge area of ​​the binding area 130 close to the first side area 110, and is connected to the first data signal test terminal DR, the second data signal test terminal DG, the third data signal test terminal DB and the control signal test terminal SW through an interlayer crossing line in the edge area. Exemplarily, the second grounding line 50 is a two-layer structure made of Gate&S / D layers, and the first data signal test terminal DR, the second data signal test terminal DG, the third data signal test terminal DB and the control signal test terminal SW are formed in the source and drain metal layer 104, and the second grounding line 50 is connected to the corresponding test terminal through a connecting line formed on the gate layer 101. In addition, the first data signal test terminal DR, the second data signal test terminal DG, the third data signal test terminal DB and the control signal test terminal SW are connected to the test signal output terminal in the flexible circuit board FPC in the binding area 130, and the flexible circuit board FPC outputs different signals to each test terminal through the test signal output terminal, such as selectively outputting test data signals, first level signals, second level signals, ground signals, etc. to different test terminals at different stages.

[0088] During the production of the display panel, the second ground line 50 needs to serve as a test signal line for inputting a test signal. Therefore, the first electrostatic ring 610 , the second electrostatic ring 620 , the third electrostatic ring 630 and the fourth electrostatic ring 630 cannot be directly connected to the second ground line 50 .

[0089] Based on the same inventive concept, a second aspect of the present disclosure provides a display panel, comprising the array substrate as described above.

[0090] The display panel may be an organic light-emitting diode (OLED) display panel. It is understandable that the display panel may be set to other types according to actual needs, for example, the display panel may be a quantum dot light-emitting diode (QLED) display panel or a micro light-emitting diode (Micro LED) display panel.

[0091] Based on the same inventive concept, the third aspect of the present disclosure provides a display device, including the display panel as described above. Exemplarily, the display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., which is not limited in this embodiment.

[0092] Obviously, the above embodiments of the present disclosure are merely examples for clearly illustrating the present disclosure, and are not limitations on the implementation methods of the present disclosure. For ordinary technicians in this field, other different forms of changes or modifications can be made on the basis of the above description. It is impossible to list all the implementation methods here. All obvious changes or modifications derived from the technical solution of the present disclosure are still within the protection scope of the present disclosure.

Claims

1. An array substrate, characterized in that: The invention comprises a base substrate, a first wiring, a test terminal, a first grounding wire, a second grounding wire and an electrostatic ring arranged on the base substrate, wherein the base substrate has a display area and a peripheral area surrounding the display area, and the test terminal, the first grounding wire, the second grounding wire and the electrostatic ring are arranged in the peripheral area; The first routing line includes multiple first signal lines and / or multiple data lines, the electrostatic ring includes multiple first electrostatic rings and / or multiple second electrostatic rings, the first end of any first electrostatic ring is connected to a first signal line, and the second end is connected to the first ground line, the first end of any second electrostatic ring is connected to a data line, and the second end is connected to the first ground line, and the test end is connected to the second ground line.

2. The array substrate according to claim 1, characterized in that: The peripheral area includes a first side area and a second side area located on opposite sides of the display area in a first direction, a plurality of first signal lines are arranged in the first side area and the second side area, the first grounding line includes a first sub-grounding line and a second sub-grounding line, the first sub-grounding line is arranged in the first side area, and the second sub-grounding line is arranged in the second side area, the plurality of first signal lines in the first side area are connected to the first sub-grounding line via the first electrostatic ring, and the plurality of first signal lines in the second side area are connected to the second sub-grounding line via the first electrostatic ring.

3. The array substrate according to claim 2, characterized in that: The peripheral area further includes a binding area and a non-binding area located at two opposite sides of the display area in the second direction, and the first sub-grounding line and the second sub-grounding line both extend to the non-binding area and are connected in the non-binding area.

4. The array substrate according to claim 2, characterized in that: The array substrate also includes a first common electrode line, which is arranged around the display area. In the direction from the display area toward the first side area or the second side area, the first common electrode line, the first sub-ground line or the second sub-ground line, and the first signal line are arranged in sequence.

5. The array substrate according to claim 4, characterized in that: The array substrate also includes a second common electrode line, which is arranged around the display area. In the direction from the display area toward the first side area or the second side area, the first common electrode line, the first sub-ground line or the second sub-ground line, the first signal line, the second common electrode line, and the second ground line are arranged in sequence.

6. The array substrate according to claim 5, characterized in that: The peripheral area also includes a binding area and a non-binding area located on opposite sides of the display area in the second direction, the non-binding area includes a second electrostatic ring area, the second electrostatic ring is arranged in the second electrostatic ring area, and the data line extends to the second electrostatic ring area and is connected to the first end of the second electrostatic ring.

7. The array substrate according to claim 6, characterized in that: The first common electrode line and the second common electrode line are connected via a connecting line extending along a first direction, and the first ground line is cross-wired with the second end of the second electrostatic ring at the position of the first common electrode line.

8. The array substrate according to claim 6, characterized in that: The binding area includes a first electrostatic ring area, the first electrostatic ring is arranged in the first electrostatic ring area, the first signal line extends to the binding area and is connected to the first end of the first electrostatic ring through a first connecting line, the first grounding line extends to the binding area and is connected to the second end of the first electrostatic ring, and in the direction from the display area toward the binding area, the first common electrode line, the first grounding line, and the first electrostatic ring area are arranged in sequence, and the orthographic projection of the first connecting line on the substrate does not overlap with the orthographic projections of the first common electrode line and the first grounding line on the substrate.

9. The array substrate according to claim 5, characterized in that: The first grounding wire extends to the binding area and forms a first connection end, and the first connection end is used to connect to the ground signal output terminal in the flexible circuit board. The second grounding wire extends to the binding area and forms a second connection end, and the second connection end is used to connect to the test signal output terminal in the flexible circuit board.

10. The array substrate according to claim 1, characterized in that: The array substrate further comprises a gate layer, a first insulating layer, an active layer, a source-drain metal layer, a light-emitting layer, a common electrode layer, a second insulating layer and a pixel electrode layer which are sequentially stacked on the base substrate; The first grounding line includes a first metal line arranged in the same layer as the gate layer and a second metal line arranged in the same layer as the source and drain metal layer, the orthographic projection of the first metal line on the base substrate overlaps with the orthographic projection of the second metal line on the base substrate, and the first metal line and the second metal line are connected through a first via on the first insulating layer.

11. The array substrate according to claim 1, characterized in that: The array substrate further includes a first short-circuit ring and a second short-circuit ring, the electrostatic ring further includes a third electrostatic ring and a fourth electrostatic ring, the first short-circuit ring is connected to the second end of each first electrostatic ring, and the first short-circuit ring is connected to the first ground line via the third electrostatic ring; The second short-circuit ring is connected to the second end of each second electrostatic ring, and the second short-circuit ring is connected to the first ground line via the fourth electrostatic ring.

12. The array substrate according to claim 1, characterized in that: The line width of the first ground line and / or the second ground line is less than or equal to 10 micrometers.

13. The array substrate according to claim 2, characterized in that: The second ground line includes a third sub-ground line and a fourth sub-ground line, and the second ground line is arranged in both the first side area and the second side area. The test end includes a first data signal test end, a second data signal test end, a third data signal test end and a control signal test end. Two of the test ends are respectively connected to the third sub-ground line and the fourth sub-ground line in the first side area, and the other two of the test ends are respectively connected to the third sub-ground line and the fourth sub-ground line in the second side area. The first data signal test end, the second data signal test end and the third data signal test end are configured to input data signals in a test phase and input ground signals in a non-test phase. The control signal test end is configured to input a first level signal in a test phase and input a second level signal in a non-test phase.

14. A display panel, characterized in that: It comprises the array substrate as claimed in any one of claims 1 to 13.

15. A display device, characterized in that: Comprising the display panel as claimed in claim 14.

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