Channel type power device layout structure and semiconductor device

Abstract

The invention provides a channel type power device layout structure and a semiconductor device, the channel type power device layout structure is provided with at least one layout area, and each layout area is provided with at least one layout unit. Each layout unit comprises a plurality of snake-shaped channels which are arranged in parallel and at intervals and contact channels which are arranged between every two adjacent snake-shaped channels. According to the technical scheme, no extra wafer area is occupied, no extra process is added, internal stress balance of the layout area can be achieved, the problem of wafer warping in the device manufacturing process is solved, the product yield is improved, the existing Taiko process and other process cost for improving wafer warping can be omitted, and the production cost is reduced. Meanwhile, wasting of wafer edge materials is avoided, and the number of effective crystal grains on the wafer is relatively increased.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor device design, and particularly to a layout structure of a trench-type power device and a semiconductor device. Background Art

[0002] As a power device, a trench power MOSFET has characteristics of high breakdown voltage, low on-resistance, high conversion efficiency, and fast switching speed, and is widely used in various electronic devices.

[0003] Currently, in the layout design of trench-type power devices, the common surface shapes of the cell pattern are: "field" shape (as shown in Figure 1A ), "pin" shape (as shown in Figure 1B ), and strip shape (as shown in Figure 1C ). Among them, in the "field" shape and "pin" shape layouts, the trench 100 is arranged around the contact hole CT to form a closed hole structure, which is prone to the problem of electrical coupling imbalance. Therefore, currently, the strip layout structure is widely used in product design to avoid such problems.

[0004] However, referring to FIG. 2, in the current strip layout, due to the single trench direction design, there is stress imbalance, and when the strip layout structure is used in multiple layout areas on the wafer, this stress imbalance problem is often amplified, resulting in warping deformation of the wafer 1. This will greatly increase the risk of wafer breakage and fragmentation during the back thinning process of the wafer 1, thereby affecting the product yield, increasing the production cost, and delaying the product development progress at the same time.

[0005] Regarding the wafer warping problem caused by the strip layout, the current improvement method is to adopt the Taiko process. When the back thinning of the wafer 1 is performed, only the central region of the wafer 1 is thinned, so as to leave a ring of wafer material with a normal thickness (i.e., the Taiko ring) in the edge region (about 3 mm wide) of the wafer 1, thereby controlling the bending degree of the wafer material in the central region and avoiding wafer warping.

[0006] Obviously, the solution of combining the strip layout with the Taiko process has the following disadvantages:

[0007] 1. It wastes the wafer edge material, affects the number of effective dies on the wafer, and thus increases the production cost.

[0008] 2. The thicknesses of the wafer edge and the central position are different, resulting in different surface stresses in the two regions, and thus causing differences in the performance of the chips manufactured in the edge and the center.

[0009] 3. Wafers processed by the Taiko process are not compatible with some subsequent processes, resulting in these subsequent processes being unable to or requiring special treatment of such wafers, thereby causing process costs. Summary of the invention

[0010] The object of the present invention is to provide a trench type power device layout structure and a semiconductor device, which can improve the problem of wafer warping in the device manufacturing process.

[0011] To achieve the above object, the present invention provides a trench type power device layout structure, which has at least one layout area, each of which has at least one layout unit, and each layout unit includes:

[0012] A plurality of serpentine channels arranged in parallel and spaced apart; and,

[0013] A contact channel, wherein the contact channel includes a first contact channel segment and at least one second contact channel segment, wherein the first contact channel segment extends in a direction parallel to the overall extension direction of the serpentine channel and is arranged between two adjacent serpentine channels, and the second contact channel segment extends in a direction perpendicular to the first contact channel segment and is arranged between two adjacent serpentine channels.

[0014] Optionally, the serpentine channel has a first channel segment and a second channel segment which are arranged alternately and connected end to end, the first channel segment is arranged parallel to the extension direction of the entire serpentine channel, and the second channel segment is arranged perpendicular to the extension direction.

[0015] Optionally, in each of the layout units or in each of the layout areas or in the entire wafer, the ratio of the total area of ​​the first channel segment to the total area of ​​the second channel segment is 1:1.

[0016] Optionally, the first channel segment at any position and the second channel segment connected end to end together form a first rectangle opening toward the first contact channel segment, and the second contact channel segment is arranged in the first rectangle along a direction perpendicular to the first contact channel segment.

[0017] Optionally, when N serpentine channels are arranged in the layout unit based on one or two of the two mirror-symmetrical serpentine channels, there are 2 N An optional arrangement mode, wherein the arrangement mode of the N serpentine channels arranged in the layout unit is selected from the 2 N One of the possible arrangements.

[0018] Optionally, each of the layout areas has a layout unit; or, at least one of the layout areas is divided into at least two layout units, two adjacent layout units are spliced ​​together and the extension directions of the serpentine channels of the two adjacent layout units are different.

[0019] Optionally, the extension directions of the serpentine channels of two adjacent layout units are perpendicular to each other.

[0020] Optionally, each of the layout areas is in the shape of a second rectangle, wherein:

[0021] At least one of the layout areas is divided into two triangular layout units spliced ​​together by the diagonal line of the second rectangle, and when the characteristic dimensions of all the serpentine channels are the same, the area ratio of the two triangular layout units is 1:1;

[0022] Alternatively, at least one of the layout areas is divided into three layout units that are sequentially spliced ​​together by two straight lines parallel to the long side or the wide side of the second rectangle, and when the characteristic dimensions of all the serpentine channels are the same, the area ratio of the three layout units is 1:2:1;

[0023] Alternatively, at least one of the layout areas is divided into four layout units that are sequentially spliced ​​together by four straight lines that form a windmill structure, two of the four straight lines are parallel to the long sides of the second rectangle, and the other two are parallel to the wide sides of the second rectangle, and when the characteristic dimensions of all serpentine channels are the same, the area ratio of the four layout units is 1:1:1:1.

[0024] Optionally, the number of layout units contained in two adjacent layout areas is the same and the arrangement of the layout units is the same; or, the number of layout units contained in two adjacent layout areas is the same, and the extension directions of the serpentine channels of the layout units at the corresponding same arrangement positions are different.

[0025] Optionally, each of the layout areas further has a gate lead-out area, and the gate lead-out area is arranged at the center or peripheral edge or corner of the layout area.

[0026] Optionally, the gate lead-out regions of each layout area are arranged at the same position, or the layout areas are arranged in a matrix on the wafer according to the cutting paths of the wafer, and the gate lead-out regions of adjacent layout areas are arranged at similar corners of adjacent layout areas.

[0027] Based on the same inventive concept, the present invention further provides a semiconductor device having a device body, wherein the device body has the layout structure of the channel-type power device as described in the present invention.

[0028] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0029] 1. Each layout unit has multiple pairs of serpentine channels arranged in parallel and spaced apart, and a contact channel arranged between two adjacent serpentine channels. In addition to having the same extension direction as the conventional strip channel, the serpentine channel also has a turning direction (equivalent to a combination of channel segments extending in different directions). Therefore, it can achieve internal stress balance in the layout area where it is located, and achieve stress balance in different directions of the wafer, thereby improving the problem of wafer warping in the device manufacturing process and improving product yield.

[0030] 2. Since the problem of wafer warpage in the device manufacturing process can be improved through layout structure design, the cost of other processes used to improve wafer warpage, such as the existing Taiko process, can be saved, while avoiding the waste of wafer edge materials and relatively increasing the number of effective grains (Die) on the wafer.

[0031] 3. The layout structure of the trench-type power device mainly improves the channel layout and the contact channel layout, and will not occupy additional area of ​​the wafer.

[0032] 4. Each layout area is divided into multiple layout units. The layout units of adjacent layout areas are arranged differently, which can further reduce the cumulative effect of a single layout with uneven stress on the wafer, so that the overall stress of the wafer remains balanced, thereby maximally improving the problem of wafer warping in the device manufacturing process from the perspective of layout structure design. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0034] Figures 1A to 1C These are three example structural diagrams of existing trench-type power device layout structures.

[0035] Figure 2A It is a schematic diagram of wafer warpage during the device manufacturing process based on the existing trench-type power device layout structure design.

[0036] Figure 2B This is a schematic diagram of the cross-sectional structure of the wafer after Taiko process processing.

[0037] Figure 3 It is a schematic diagram of a layout unit in the layout structure of a trench-type power device according to the first embodiment of the present invention.

[0038] FIG. 4 is a schematic diagram of the layout structure of each layout area in the layout structure of a trench-type power device according to the first embodiment of the present invention.

[0039] Figure 5 is based on Figure 3Schematic diagram of wafer warpage during device manufacturing under the layout structure design of trench power devices.

[0040] Figures 6A to 6B It is a schematic diagram of an example structure of two layout areas in the layout structure of a trench-type power device according to the second embodiment of the present invention.

[0041] Figures 6C to 6E These are three exemplary structural schematic diagrams of the combination and arrangement of layout units in each layout area in the layout structure of a trench power device according to the second embodiment of the present invention.

[0042] Figures 7A to 7B It is a schematic diagram of an example structure of two layout areas in the layout structure of a trench-type power device according to the third embodiment of the present invention.

[0043] Figures 7C to 7E These are three exemplary structural schematic diagrams of the combination and arrangement of layout units in each layout area in the layout structure of a trench power device in the third embodiment of the present invention.

[0044] Figures 8A to 8B It is a schematic diagram of an example structure of two layout areas of the layout structure of a trench-type power device according to the fourth embodiment of the present invention.

[0045] Figures 8C to 8E Schematic diagrams of several exemplary structures of the combination and arrangement of layout units in each layout area of ​​the layout structure of a trench-type power device according to the fourth embodiment of the present invention.

[0046] Fig. 9 It is a schematic diagram of optional arrangement of layout units with N=2 and N=3 serpentine channels in the layout structure of a trench-type power device in other embodiments of the present invention. DETAILED DESCRIPTION

[0047] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0048] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0049] First embodiment

[0050] Please refer to Figure 3 and Figure 4A This embodiment provides a trench-type power device layout structure, which has a plurality of layout areas, each of which has a layout unit 2, and the layout unit 2 includes a plurality of serpentine channels and a plurality of contact channels 21, wherein the serpentine channels are arranged in parallel and spaced apart, and the directions of two adjacent serpentine channels 20A and 20B are opposite. The contact channel 21 is arranged between two adjacent serpentine channels.

[0051] It should be understood that the biggest difference between the serpentine channel and the strip channel in the prior art is that it is not a single-direction channel, but has a turn, so it can improve the stress imbalance problem existing in the strip channel layout, thereby improving the wafer warpage problem in the device manufacturing process, such as Figure 5 shown.

[0052] In this embodiment, the key dimensions of each serpentine channel are the same. Each serpentine channel has a first channel section 201 and a second channel section 202 arranged alternately and connected end to end, the first channel section 201 is arranged parallel to the extension direction of the entire serpentine channel, and the second channel section 202 is arranged perpendicular to the extension direction of the entire serpentine channel.

[0053] As an example, each layout area is a second rectangle with a length of L and a width of W, the overall extension direction of the serpentine channel and the first channel segment 201 are parallel to the long side L of the second rectangle, and the second channel segment 202 is parallel to the wide side W of the second rectangle.

[0054] Optionally, in the layout unit, in each layout area, or even in the entire wafer, the ratio of the sum of the areas of the first channel segment 201 to the sum of the areas of the second channel segment 202 is 1:1. Thus, by staggered distribution of the first channel segment 201 and the second channel segment 202, the stresses generated in different directions of the layout structure can offset each other, avoiding the stress accumulation effect generated by the layout unit on the wafer, so that the overall stress of the wafer is balanced, and the wafer warpage defect is improved. It should be understood that in other embodiments of the present invention, even if the ratio of the sum of the areas of the first channel segment 201 to the sum of the areas of the second channel segment 202 in the layout unit, in each layout area, or even in the entire wafer is not 1:1, due to the use of the serpentine channel design, the stresses generated in different directions of the layout structure can be offset to a certain extent, improving the stress accumulation effect generated by the layout unit on the wafer, thereby improving the overall stress of the wafer, and improving the wafer warpage defect to a certain extent.

[0055] As an example, see Figure 3Each contact channel 21 includes a first contact channel segment 211 and at least one second contact channel segment 212. The first contact channel segment 211 is arranged along the symmetry axis of two adjacent serpentine channels 20A and 20B, and each second contact channel segment 212 is arranged at each maximum distance position between the two adjacent serpentine channels along a direction perpendicular to the first contact channel segment 211 (that is, arranged in each first rectangle 22), and spans the first contact channel segment 211. The first channel segment 201 at any position of each serpentine channel and the second channel segment 202 connected to it form together a first rectangle 22 of the first contact channel segment 211 opening toward the contact channel 22. At this time, since any two adjacent serpentine channels are distributed in an axisymmetric (or mirror-symmetrical) manner, the first rectangles 22 formed at the same position relative to any two adjacent serpentine channels are aligned, and the spacing L1 between the first channel segments 201 of the two adjacent serpentine channels at the first rectangle 22 is also the maximum distance between the two adjacent serpentine channels, and the line width L2 of the opening 221 formed between the first rectangles 22 is also the minimum distance between the two adjacent serpentine channels.

[0056] In this example, two adjacent serpentine channels 20A and 20B can be regarded as a group of serpentine channel pairs. The layout unit is composed of multiple groups of serpentine channel pairs arranged in parallel and spaced apart. The minimum distance between any two adjacent serpentine channels is the same, and the maximum distance between any two adjacent serpentine channels is also the same, thereby achieving equal spacing and equal line width distribution of the serpentine channels in the layout unit.

[0057] The first contact channel segment 211 passes through each opening 221, and its head end can be aligned with the head end of the serpentine channel 20A, 20B, and its tail end can be aligned with the tail end of the serpentine channel 20A, 20B. The line width of the first contact channel segment 211 and the line width of the second contact channel segment 212 can be the same or different.

[0058] The layout structure design of the contact channel 21 can reuse the area defined by the serpentine channel and provide a larger process window, thereby helping to reduce the difficulty of the process manufacturing of the contact channel 21 and provide reliable electrical connection for the corresponding structure of the device.

[0059] In this example, each layout area can be arranged in a matrix on the wafer 1 according to the wafer's cutting path. Each layout area can correspond to a die, and the interval between adjacent layout areas is the cutting path between the dies. Figure 4A , the layout units in each layout area are the same, and the extension direction of their serpentine channels is the same ( Figure 4A In another example, the serpentine channel extends longitudinally, but in other examples, the serpentine channel can also extend transversely. Figure 4B, each layout area has a layout unit and the structure of each layout unit is basically the same, but the extension direction of the serpentine channels in adjacent layout areas is perpendicular, so the layout areas in the same column and the same row are cross-arranged in the manner of longitudinal extension or transverse extension of the serpentine channels. In this example, the layout units with transverse extension of the serpentine channels and the layout units with longitudinal extension of the serpentine channels are criss-crossed, and the stresses they generate can restrain and offset each other, which can further reduce the cumulative effect of the arrangement of a single layout with uneven stress on the wafer, so that the overall stress of the wafer is balanced, thereby maximizing the improvement of the problem of wafer warping during the device manufacturing process from the perspective of layout structure design without changing the process and increasing the cost, thereby improving the wafer yield and reducing the fragmentation rate.

[0060] It should be understood that the shapes, extension directions and other features of the layout area, serpentine channel and contact channel in the above examples are only used as an example, and do not mean that the technical solution of the present invention is limited to this. For example, in another embodiment of the present invention, the extension direction of the serpentine channel as a whole can also be arranged parallel to the wide side of the second rectangle; for another example, in another embodiment of the present invention, the contact channel only has the first contact channel section 211. For another example, in another embodiment of the present invention, the distribution density of the serpentine channels in different layout areas is different.

[0061] As can be seen from the above, the layout structure of the channel-type power device of this embodiment has at least one serpentine channel pair and a contact channel arranged between two adjacent serpentine channels in each layout unit. In addition to the extension direction being the same as that of the conventional strip-type channel, the serpentine channel also has a turning direction, so that the internal stress balance of the layout area where it is located can be achieved, and the stress in different directions (such as the horizontal and vertical directions) of the wafer can be balanced or offset, thereby improving the problem of wafer warpage in the device manufacturing process, improving the product yield, and reducing the fragmentation rate. Moreover, the cost of other processes for improving wafer warpage, such as the existing Taiko process, can be saved, while avoiding the waste of wafer edge materials, and the number of effective grains (Die) on the wafer can be relatively increased. In addition, the layout structure of the channel-type power device mainly improves the channel layout and the contact channel layout, and does not occupy additional area of ​​the wafer.

[0062] Second embodiment

[0063] In the first embodiment, the layout area (corresponding to the die) designed with a single serpentine channel extension direction has limited ability to balance the stress of the wafer.

[0064] Based on this, this embodiment provides a trench type power device layout structure, please refer to Fig. 6A and Figure 6B, which has at least one layout area, and the at least one layout area is divided into two areas symmetrical about the dividing line along a corresponding straight line (i.e., a dividing line), each area is provided with a layout unit, and the basic structure of each layout unit is similar to that of the layout unit in the first embodiment, and each has a plurality of serpentine channels arranged in parallel and spaced apart, and a contact channel provided between two adjacent serpentine channels. However, the extension directions of the serpentine channels of the two layout units in the layout area are different.

[0065] Therefore, the overall layout structure of the layout area is formed by splicing these two layout units together at the dividing line. The layout structure design can further balance the stress of the layout area itself, thereby reducing the cumulative effect of the arrangement of the layout units on the entire wafer, so that the overall stress of the wafer remains balanced.

[0066] It should be understood that the extending direction of the dividing line can be arbitrary. For example, when each layout area is a second rectangle, the dividing line can be the midline of the long side of the second rectangle, the midline of the wide side of the second rectangle, or the diagonal line of the second rectangle. Optionally, the extending directions of the serpentine channels of the two layout units in the layout area are perpendicular to each other.

[0067] As an example, see Fig. 6A , at least one layout area 2-1 is divided into two triangular layout units 2A and 2B along a diagonal line of the second rectangle, and when the characteristic dimensions of all serpentine channels are the same, the areas of the two triangular layout units 2A and 2B can be 1:1. The serpentine channel of the layout unit 2A extends in the longitudinal direction (that is, the extension direction of the serpentine channel is the longitudinal direction), such as Fig. 6A As shown by the longitudinal arrow at the dividing line, the serpentine channel of the layout unit 2B extends in the horizontal direction (that is, the extension direction of the serpentine channel is in the horizontal direction), as shown in FIG. Fig. 6A As shown by the horizontal arrow at the dividing line.

[0068] As another example, see Figure 6B , at least one layout area 2-2 is divided into two triangular layout units 2A and 2B along a diagonal line of the second rectangle, and when the characteristic dimensions of all serpentine channels are the same, the area ratio of the two triangular layout units 2A and 2B is 1:1. Among them, the serpentine channel of the layout unit 2A extends in the horizontal direction (that is, the extension direction of the serpentine channel is the horizontal direction), such as Figure 6B As shown by the horizontal arrow at the dividing line, the serpentine channel of the layout unit 2B extends in the longitudinal direction (that is, the extension direction of the serpentine channel is the longitudinal direction), as shown in FIG. Figure 6B As shown by the vertical arrow at the dividing line.

[0069] Obviously, the number of layout units contained in layout area 2-1 and layout area 2-2 is the same, but the layout units with the same serpentine channel extension direction (or even basically the same structure) are arranged in different positions. On the whole wafer, each layout area can be arranged in a matrix on wafer 1 according to the cutting path of the wafer, each layout area can correspond to a die, the interval between adjacent layout areas is the cutting path between the die, and the layout structure of each layout area can be the same as that of layout area 2-1 or layout area 2-2. Therefore, in each layout unit, in each layout area, and even in the whole wafer, the ratio of the sum of the areas of the first channel segment 201 to the sum of the areas of the second channel segment 202 is 1:1.

[0070] It should be understood that in other embodiments of the present invention, affected by the characteristic dimensions of different serpentine channels and the dimensions of layout units, the areas of layout units 2A and 2B in the above examples may not be 1:1. Due to the use of the serpentine channel design, the stresses generated by the layout structure in different directions can offset each other to a certain extent, thereby improving the stress accumulation effect caused by the arrangement of layout units on the wafer, thereby improving the overall stress of the wafer and improving the wafer warping defect to a certain extent.

[0071] In an example, see Figure 6C Each layout area uses Fig. 6A The layout structure of the layout area 2-1 shown, whereby the number of layout units contained in each layout area is the same, and the arrangement of each layout unit is the same, that is, the layout units with the same serpentine channel extension direction (or even basically the same structure) in different layout areas are arranged at the same positions corresponding to these layout areas.

[0072] In another example, see Fig.6D , each layout area uses Figure 6B The layout structure of the layout area 2-2 shown, whereby the number of layout units contained in each layout area is the same, and the arrangement of each layout unit is the same, that is, the layout units with the same serpentine channel extension direction (or even basically the same structure) in different layout areas are arranged at the same corresponding positions in these layout areas.

[0073] In another example, see Fig. 6E The area of ​​each layout area and the number of layout units contained therein are the same, but the layout units with the same serpentine channel extension direction (or even basically the same structure) in two adjacent layout areas are arranged in different positions. Fig. 6A The layout structure of the layout area 2-1 is shown, and the other layout area adopts Figure 6BThe layout structure of the layout area 2-2 shown makes the serpentine channel extension direction of the layout unit at the same arrangement position corresponding to the two adjacent layout areas perpendicular. Therefore, the layout areas in the same column and the same row are cross-arranged in the manner of the layout area 2-1 and the layout area 2-2, and the stresses generated by them can restrict and offset each other, which can further reduce the cumulative effect of the layout of a single layout unit with uneven stress on the wafer, so that the overall stress of the wafer is balanced, thereby maximally improving the problem of wafer warping during the manufacturing process of the device from the perspective of layout structure design without changing the process and increasing the cost, thereby improving the wafer yield and reducing the fragmentation rate.

[0074] Optionally, each layout area further has a gate lead-out area 23, and the gate lead-out area 23 of each layout area is arranged at the center or peripheral edge or corner of the layout area. The setting position of the gate lead-out area 23 of each layout area can be the same, for example FIG. 6A to FIG. 6E In the example shown, the gate lead-out region 23 of each layout area is arranged at the same position, and is arranged at the same corner of each layout area; for another example, 7A to 7E In the example shown, the gate lead-out region 23 of each layout area is arranged at the same position, that is, at the middle position of the same peripheral edge corresponding to each layout area; for another example, FIG. 8A to FIG. 8E In the example shown, the gate lead-out region 23 of each layout area is set at the same position, and is set at the center of each layout area. In other examples, the gate lead-out regions 23 of at least two layout areas may be set at different positions. For example, when these layout areas are arranged in a matrix according to the cutting path of the wafer, the gate lead-out regions 23 of adjacent layout areas are set at similar corners of the adjacent layout areas.

[0075] Compared with the first embodiment, the trench power device layout structure of this embodiment can reduce the stress accumulation effect caused by the arrangement of a single layout unit on the wafer, so that the overall stress of the wafer is further balanced and the wafer warping defect is further improved.

[0076] Third embodiment

[0077] In the second embodiment, the corresponding layout area has two layout units with serpentine channels extending in different directions, and its ability to balance the stress of the wafer is still limited.

[0078] Based on this, this embodiment provides a trench type power device layout structure, please refer to Fig. 7A and Figure 7B , which has at least one layout area, and the at least one layout area is divided into three areas along two corresponding straight lines (i.e., dividing lines) that have no intersection in the layout area, and a layout unit (i.e., Fig. 7A and Figure 7B2A to 2C), the basic structure of each layout unit is similar to that of the layout unit in the first embodiment, and has a plurality of serpentine channels arranged in parallel and spaced apart, and a contact channel arranged between two adjacent serpentine channels.

[0079] The layout structure of the layout area is formed by sequentially splicing the three layout units 2A-2C together at the corresponding dividing lines, and the extension directions of the serpentine channels of the adjacent and spliced ​​layout units are different.

[0080] The layout structure design can further balance the stress of the layout area itself, thereby reducing the cumulative effect of the layout unit arrangement on the entire wafer, so that the overall stress of the wafer remains balanced.

[0081] It should be understood that the extension direction of the two dividing lines can be any appropriate direction. For example, when each layout area is the second rectangle mentioned above, the dividing line can be a trisection line (i.e., two straight lines perpendicular to the long side and used to divide the second rectangle into three equal parts) or a quadrant (i.e., three straight lines perpendicular to the long side and used to divide the second rectangle into four equal parts) of the long side of the second rectangle, or a trisection line or a quadrant line of the wide side of the second rectangle, or other oblique lines that are not parallel to the long side and the wide side. The areas of the three layout units 2A to 2C can be the same or different, and the key parameters such as the distribution density and line width of the serpentine channels in the three layout units 2A to 2C can be the same or different. Preferably, the ratio of the sum of the areas of the first channel segments to the sum of the areas of the second channel segments in the three layout units 2A to 2C is 1:1, thereby achieving stress balance in different directions to the greatest extent possible.

[0082] Optionally, the extension directions of the serpentine channels of two adjacent and spliced ​​layout units in the layout area are perpendicular to each other.

[0083] As an example, see Fig. 7A , at least one layout area 2-3 is divided into three rectangular layout units 2A, 2B, and 2C along the two quadrants on the leftmost and rightmost sides of the wide side of the second rectangle, that is, the boundary line between the layout units 2A and 2B is the quadrant on the leftmost side of the wide side of the second rectangle, and the boundary line between the layout units 2B and 2C is the quadrant on the rightmost side of the wide side of the second rectangle, and when the characteristic dimensions of all serpentine channels are the same, the area ratio of the layout units 2A, 2B, and 2C is 1:2:1. Among them, the serpentine channels of the layout units 2A and 2C are all extended in the longitudinal direction (that is, the extension direction of the serpentine channels is the longitudinal direction), such as Fig. 7A As shown by the longitudinal arrows near the two dividing lines, the serpentine channel of the layout unit 2B extends in the horizontal direction (that is, the extension direction of the serpentine channel is in the horizontal direction), as shown in FIG. Fig. 7A It is shown as the horizontal line segment connecting the two vertical arrows in .

[0084] As another example, see Figure 7B , at least one layout area 2-4 is divided into three rectangular layout units 2A, 2B, and 2C along the leftmost quadrants and the rightmost quadrants of the wide side of the second rectangle, that is, the boundary line between the layout units 2A and 2B is the leftmost quadrant of the wide side of the second rectangle, and the boundary line between the layout units 2B and 2C is the rightmost quadrant of the wide side of the second rectangle, and when the characteristic dimensions of all serpentine channels are the same, the area ratio of the layout units 2A, 2B, and 2C is 1:2:1. Among them, the serpentine channels of the layout units 2A and 2C extend in the horizontal direction (that is, the extension direction of the serpentine channels is horizontal), such as Figure 7B As shown by the horizontal arrows at the two dividing lines, the serpentine channel of the layout unit 2B extends in the longitudinal direction (that is, the extension direction of the serpentine channel is the longitudinal direction), as shown in FIG. Figure 7B The stress is shown by the vertical arrows in .

[0085] Obviously, the three areas divided by layout area 2-3 and layout area 2-4 have the same area, and the number of layout units contained therein is the same (all 3), but the layout units are arranged differently, that is, the serpentine channel extension directions of the layout units arranged at the same positions corresponding to layout area 2-3 and layout area 2-4 are different. On the whole wafer, each layout area can be arranged in a matrix on wafer 1 according to the cutting path of the wafer, and each layout area can correspond to a die. The interval between adjacent layout areas is the cutting path between the die, and the layout structure of each layout area can be the same as that of layout area 2-3 or layout area 2-4. Therefore, in each layout unit, in each layout area, and even in the whole wafer, the ratio of the sum of the areas of the first channel segment 201 to the sum of the areas of the second channel segment 202 is 1:1. However, it should be understood that in other embodiments of the present invention, affected by the characteristic dimensions of different serpentine channels and the dimensions of the layout units, the area ratio of the three layout units of the layout area 2-3 or the layout area 2-4 in the above example may not be 1:2:1, and the ratio of the sum of the areas of the first channel segment 201 to the sum of the areas of the second channel segment 202 may not be 1:1. However, it can also improve the overall stress of the wafer to a certain extent, thereby improving the wafer warping defect to a certain extent.

[0086] In an example, see Figure 7C , each layout area adopts Fig. 7A The layout structure of the layout area 2-3 shown, whereby the number of layout units contained in each layout area is the same and the arrangement of each layout unit is also the same, that is, the layout units with the same serpentine channel extension direction (or even basically the same structure) in different layout areas are arranged at the same corresponding positions in these layout areas.

[0087] In another example, see Fig.7D , each layout area adopts Figure 7B The layout structure of the layout areas 2-4 shown, whereby the number of layout units contained in each layout area is the same, and the arrangement of each layout unit is also the same, that is, the layout units with the same serpentine channel extension direction (or even basically the same structure) in different layout areas are arranged at the same positions corresponding to these layout areas.

[0088] In another example, see Fig. 7E The three areas divided from each layout area are set one by one. The number of layout units contained in two adjacent layout areas is the same, but the layout units with the same serpentine channel extension direction (or even the same structure) in the adjacent layout areas are arranged in different positions. For example, one of the two adjacent layout areas adopts Fig. 7A The layout structure of the layout area 2-3 shown in the figure, and the other layout area uses Figure 7B The layout structure of the layout area 2-4 shown makes the extension direction of the serpentine channel of the layout unit at the same arrangement position corresponding to two adjacent layout areas perpendicular. Therefore, the layout areas in the same column and the same row are cross-arranged in the manner of layout area 2-3 and layout area 2-4, and the stresses generated by them can restrain and offset each other, which can further reduce the cumulative effect of the layout of a single layout unit with uneven stress on the wafer, so that the overall stress of the wafer is balanced, thereby maximally improving the problem of wafer warping during the manufacturing process of the device from the perspective of layout structure design without changing the process and increasing the cost, thereby improving the wafer yield and reducing the fragmentation rate.

[0089] Compared with the second embodiment, the layout structure of the trench power device in this embodiment has more detailed layout areas, so it can further reduce the stress accumulation effect caused by the arrangement of a single layout unit on the wafer, so that the overall stress of the wafer is further balanced and the wafer warping defect is further improved.

[0090] Fourth embodiment

[0091] In the second embodiment and the third embodiment, the number of layout units divided in the corresponding layout area is relatively small, and the ability to balance the stress of the wafer is still limited.

[0092] Based on this, this embodiment provides a trench type power device layout structure, please refer to Fig. 8A and Figure 8B , which has at least one layout area, and the at least one layout area is divided into four areas along two corresponding straight lines (i.e., dividing lines, such as two diagonal lines of the second rectangle) that have an intersection in the layout area or four straight lines that form a windmill structure in the layout area or other forms of straight line combinations, and a layout unit (i.e., Fig. 8A and Figure 8B 2A to 2D), the basic structure of each layout unit is similar to that of the layout unit in the first embodiment, and has a plurality of serpentine channels arranged in parallel and spaced apart, and a contact channel arranged between two adjacent serpentine channels.

[0093] The layout structure of the layout area is formed by sequentially splicing the four layout units 2A-2D together at the corresponding dividing lines, and the extension directions of the serpentine channels of the adjacent and spliced ​​layout units are different (for example, perpendicular to each other).

[0094] The layout structure design can further balance the stress of the layout area itself, thereby reducing the cumulative effect of the layout unit arrangement on the entire wafer, so that the overall stress of the wafer remains balanced.

[0095] It should be understood that the extension direction of these dividing lines can be any appropriate direction. For example, when each layout area is a second rectangle and there are four dividing lines, two of them can be two straight lines on both sides of the midline of the long side of the second rectangle, and the other two can be two straight lines on both sides of the midline of the wide side of the second rectangle. They can also be other oblique lines that are parallel to the long side or the wide side or are not parallel to both the long side and the wide side. The areas of the four layout units 2A to 2D can be the same or different, and the key parameters such as the distribution density and line width of the serpentine channels in the four layout units 2A to 2D can be the same or different. Preferably, the ratio of the sum of the areas of the first channel segments to the sum of the areas of the second channel segments in the four layout units 2A to 2D is 1:1, thereby achieving stress balance in different directions to the greatest extent possible.

[0096] Optionally, the extension directions of the serpentine channels of two adjacent and spliced ​​layout units in the layout area are perpendicular to each other.

[0097] As an example, see Fig. 8AAt least one layout area 2-5 is divided into four layout units 2A, 2B, 2C, and 2D that are sequentially spliced ​​together along four straight lines that form a windmill structure. Two of the four straight lines are parallel to the long sides of the second rectangle and are located on both sides of the midline of the long sides of the second rectangle. The other two are parallel to the wide sides of the second rectangle and are located on both sides of the midline of the wide sides of the second rectangle. The center of the windmill structure is the center of the layout area, and a gate lead-out area 23 is also provided at this position. When the characteristic dimensions of all serpentine channels are the same, the area ratio of the layout units 2A, 2B, 2C, and 2D is 1:1:1:1. Among them, the serpentine channels of layout units 2A and 2C are extended in the longitudinal direction (that is, the extension direction of the serpentine channels is longitudinal), and the serpentine channels of layout units 2B and 2D are extended in the transverse direction (that is, the extension direction of the serpentine channels is transverse), that is, the extension directions of the serpentine channels of adjacent and spliced ​​layout units are perpendicular, and the extension directions of the serpentine channels of the four layout units 2A, 2B, 2C, and 2D are arranged in a clockwise direction. As a result, layout units 2A, 2B, 2C, and 2D restrict each other, balance the stress of the layout area itself, and then reduce the cumulative effect of the layout units on the entire wafer, so that the overall stress of the wafer remains balanced.

[0098] As another example, see Figure 8B , at least one layout area 2-6 is divided into four layout units 2A, 2B, 2C, and 2D that are sequentially spliced ​​together along four straight lines that form a windmill structure, two of the four straight lines are parallel to the long sides of the second rectangle and are located on both sides of the midline of the long sides of the second rectangle, and the other two are parallel to the wide sides of the second rectangle and are located on both sides of the midline of the wide sides of the second rectangle, and when the characteristic dimensions of all serpentine channels are the same, the area ratio of the layout units 2A, 2B, 2C, and 2D is 1:1:1:1. Among them, the serpentine channels of the layout units 2A and 2C are extended in the horizontal direction (that is, the extension direction of the serpentine channels is the horizontal direction), and the serpentine channels of the layout units 2B and 2D are extended in the longitudinal direction (that is, the extension direction of the serpentine channels is the longitudinal direction), that is, the extension directions of the serpentine channels of the adjacent and spliced ​​layout units are perpendicular, and the extension directions of the serpentine channels of the four layout units 2A, 2B, 2C, and 2D are arranged in the counterclockwise direction. Therefore, the layout units 2A, 2B, 2C, and 2D restrict each other, balancing the stress of the layout area itself, thereby reducing the cumulative effect of the arrangement of the layout units on the entire wafer, so that the overall stress of the wafer remains balanced.

[0099] Obviously, the four areas divided from layout area 2-5 and layout area 2-6 can correspond one to one and have the same area, and the number of layout units contained therein is the same (all 4), but the arrangement of the layout units is different. For example, layout unit 2A of layout area 2-5 corresponds to and is the same as layout unit 2B of layout area 2-6, layout unit 2B of layout area 2-5 corresponds to and is the same as layout unit 2A of layout area 2-6, layout unit 2C of layout area 2-5 corresponds to and is the same as layout unit 2D of layout area 2-6, and layout unit 2D of layout area 2-5 corresponds to and is the same as layout unit 2C of layout area 2-6, that is, the serpentine channel extension directions of the layout units arranged at the same arrangement positions corresponding to layout area 2-5 and layout area 2-6 are different. On the whole wafer, each layout area can be arranged in a matrix on wafer 1 according to the wafer cutting path, each layout area can correspond to a die, the interval between adjacent layout areas is the cutting path between the die, and the layout structure of each layout area can be the same as that of layout area 2-5 or layout area 2-6. Therefore, in each layout unit, each layout area, and even in the whole wafer, the ratio of the sum of the areas of the first channel segment 201 to the sum of the areas of the second channel segment 202 is 1:1.

[0100] In an example, see Figure 8C , each layout area adopts Fig. 8A The layout structure of the layout areas 2-5 shown, whereby the number of layout units contained in each layout area is the same and the arrangement of each layout unit is also the same, that is, the layout units with the same serpentine channel extension direction (or even basically the same structure) in different layout areas are arranged at the same corresponding positions in these layout areas.

[0101] In another example, see Fig.8D , each layout area adopts Figure 8B The layout structure of the layout areas 2-6 shown, whereby the number of layout units contained in each layout area is the same and the arrangement of each layout unit is also the same, that is, the layout units with the same serpentine channel extension direction (or even basically the same structure) in different layout areas are arranged at the same corresponding positions in these layout areas.

[0102] In another example, see Fig. 8E The four areas divided by each layout area correspond to each other. The number of layout units in two adjacent layout areas is the same, but the layout units with the same serpentine channel extension direction (or even the same structure) in the adjacent layout areas are arranged in different positions. One of the two adjacent layout areas adopts Fig. 8A The layout structure of the layout area 2-5 is shown, and the other layout area uses Figure 8BThe layout structure of the layout area 2-6 shown makes the extension direction of the serpentine channel of the layout unit at the same arrangement position corresponding to two adjacent layout areas perpendicular. Therefore, the layout areas in the same column and the same row are arranged crosswise in the manner of the layout area 2-5 and the layout area 2-6, and the stresses generated by them can restrain and offset each other, which can further reduce the cumulative effect of the layout of a single layout unit with uneven stress on the wafer, so that the overall stress of the wafer is balanced, thereby maximally improving the problem of wafer warping during the manufacturing process of the device from the perspective of layout structure design without changing the process and increasing the cost, thereby improving the wafer yield and reducing the fragmentation rate.

[0103] Compared with the second and third embodiments, the layout structure of the trench power device in this embodiment has more detailed layout areas, so it can further reduce the stress accumulation effect caused by the arrangement of a single layout unit on the wafer, so that the overall stress of the wafer is further balanced and the wafer warping defect is further improved.

[0104] It should be understood that the above second to fourth embodiments only list the cases where a layout area is divided into two, three and four areas. The more partitions there are in the layout area, the higher the stress equalization effect is, and the area ratios in these embodiments are only used as an example, and do not indicate that the technical solution of the present invention is limited to this. Therefore, in other embodiments of the present invention, if the process permits, the area ratios of the partitions in each layout area can be other values, and no specific examples are given here. In addition, a layout area can be divided into as many and sequentially spliced ​​areas as possible, and the extension directions of the serpentine channels of the layout units in the adjacent and spliced ​​areas are different, thereby achieving a more detailed stress equalization effect in the layout area.

[0105] and, Figure 4B , Fig. 6E , Fig. 7E and Fig. 8E The examples shown all use two layout areas to arrange the layout structures on the wafer, but the technical solution of the present invention is not limited to this. Based on the design requirements of devices with different performances, three or more layout areas can be arranged on the wafer to achieve stress balance on the wafer while manufacturing different power devices on the wafer. Fig. 6E The layout structure of one of the four layout areas 2-1 or one of the layout areas 2-2 is replaced by Fig. 7E The layout structure of layout area 2-3 or layout area 2-4 or Fig. 8E The layout structure of the layout area 2-5 or 2-6 is realized, thereby realizing the arrangement of the three layout area structures. Fig. 6E One of the four layout areas, area 2-1, is replaced by Fig. 7EThe layout structure of layout area 2-3 or layout area 2-4 will Fig. 6E The layout structure of one of the four layout areas 2-2 is replaced by Fig. 8E The layout structure of layout area 2-5 or layout area 2-6 is realized, thereby realizing the arrangement of four layout area structures.

[0106] In addition, the layout area in the above embodiments is rectangular, and the various areas divided by the layout area are triangular or rectangular. These are just examples, and the technical solution of the present invention is not limited to this. In other examples of the present invention, the layout area containing at least one layout unit can also be a polygon other than a rectangle, such as a hexagon, an octagon or a rhombus, and each layout unit in the layout area (for example Fig. 8A The shape of 2A to 2D) in FIG. 2A to 2D depends on the shape and combination of the dividing lines, and may also be any other suitable shape other than a rectangle or a triangle, such as a pentagon, a hexagon, an octagon or a rectangle, and at least one dividing line may not be a straight line, but a broken line or a smooth curve.

[0107] It is worth noting that in each of the above embodiments, a pair of serpentine channels (i.e., a pair of serpentine channels) are mirror-symmetrical (i.e., the overall extension directions are parallel and the directions are opposite). Figure 3 20A and 20B) in the figure are used to design the serpentine channels of each layout unit, so that the structure of each layout unit is composed of multiple groups of serpentine channel pairs arranged in parallel and spaced apart, but the technical solution of the present invention is not limited to this. Please refer to Fig. 9 , based on one or both of the two serpentine channels a and b that are mirror-symmetrical (i.e., the overall extension directions are parallel and the directions are opposite), when designing the N serpentine channels required in each layout unit, there can be 2 N For example, when a layout unit only needs two (i.e., N=2) serpentine channels extending in the longitudinal direction and spaced apart, the optional arrangements that can be provided are "aa", "ab", "ba", and "bb", a total of 2 2 = 4, among which the optional arrangements with axial symmetry are "ab" and "ba", a total of 2 2-2 = 2 types, that is, the arrangement of the two serpentine channels in the final designed layout unit is one of "aa", "ab", "ba", and "bb", and the contact channel is arranged between two adjacent serpentine channels, and the first contact channel section of the contact channel extends in a direction parallel to the extension direction of the serpentine channel as a whole and is arranged between the corresponding two adjacent serpentine channels. The first channel section of the serpentine channel at any position and the second channel section connected end to end together form a first rectangle with an opening toward the first contact channel section, and each second contact channel section extends in a direction perpendicular to the first contact channel section and is arranged between the two adjacent serpentine channels. Therefore, for the layout unit adopting the "aa" or "bb" layout, the second contact channel sections corresponding to the two serpentine channels are arranged alternately on the first contact channel section, and for the layout unit adopting the "ab" or "ba" layout, the second contact channel sections corresponding to the two serpentine channels are arranged aligned on the first contact channel section.

[0108] For another example, when only three (i.e., N=3) serpentine channels extending in the longitudinal direction and arranged at intervals are required in a layout unit based on serpentine channels a and b, the optional arrangements that can be provided are "aaa", "aab", "aba", "abb", "baa", "bab", "bba", "bbb", a total of 2 3 = 8 types, among which the specific structures of "baa", "bab", "bba", and "bbb" can be based on Fig. 9 The structures of the serpentine channels a and b given in the paper are objectively combined, so Fig. 9 In this case, the optional arrangements with axial symmetry are "aab", "aba", "abb", "baa", "bab", "bba", a total of 2 3 -2 = 6. Thus, for a layout unit with an "aa" or "bb" layout, the second contact channel segments corresponding to two adjacent serpentine channels constituting the "aa" or "bb" layout are arranged alternately on the first contact channel segment, and for a layout unit with an "ab" or "ba" layout, the second contact channel segments corresponding to two adjacent serpentine channels constituting the "ab" or "ba" layout are arranged aligned on the first contact channel segment.

[0109] In summary, no matter the N serpentine channels in the layout unit are selected from the corresponding 2 NWhich of the optional arrangement modes is that each contact channel of the layout unit is arranged between two corresponding adjacent serpentine channels, and the first contact channel section of each contact channel extends in a direction parallel to the overall extension direction of the serpentine channel and is arranged between two corresponding adjacent serpentine channels, the first channel section at any position of each serpentine channel of the two adjacent serpentine channels and the second channel section connected end to end thereof together form a first rectangle opening toward the first contact channel section, and the corresponding second contact channel section is arranged in the first rectangle along a direction perpendicular to the first contact channel section.

[0110] Based on the same inventive concept, an embodiment of the present invention further provides a semiconductor device having a device body (e.g., a corresponding structure obtained by cutting a wafer), and the device has a trench-type power device layout structure as described in any of the above embodiments. Therefore, the semiconductor device has the beneficial effects brought about by the trench-type power device layout structure. The internal structure of the device body can be any suitable internal structure of a trench-type power MOS device in the art, which will not be described in detail here.

[0111] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A trench type power device layout structure, characterized in that: It has at least one layout area, each of which has at least one layout unit, and each layout unit includes: A plurality of serpentine channels arranged in parallel and spaced apart; and, A contact channel, wherein the contact channel includes a first contact channel segment and at least one second contact channel segment, wherein the first contact channel segment extends in a direction parallel to the overall extension direction of the serpentine channel and is arranged between two adjacent serpentine channels, and the second contact channel segment extends in a direction perpendicular to the first contact channel segment and is arranged between two adjacent serpentine channels.

2. The trench type power device layout structure according to claim 1, characterized in that: The serpentine channel comprises a first channel section and a second channel section which are arranged alternately and connected end to end. The first channel section is arranged parallel to the extension direction of the entire serpentine channel, and the second channel section is arranged perpendicular to the extension direction.

3. The trench type power device layout structure according to claim 2, characterized in that: In each of the layout units or in each of the layout areas or in the entire wafer, the ratio of the total area of ​​the first channel segment to the total area of ​​the second channel segment is 1:

1.

4. The trench type power device layout structure according to claim 2, characterized in that: The first channel segment at any position and the second channel segment connected end to end together form a first rectangle opening toward the first contact channel segment, and the second contact channel segment is arranged in the first rectangle along a direction perpendicular to the first contact channel segment.

5. The trench type power device layout structure according to claim 1, characterized in that: When N serpentine channels are arranged in the layout unit based on one or two of the two mirror-symmetrical serpentine channels, there are 2 N An optional arrangement mode, wherein the arrangement mode of the N serpentine channels arranged in the layout unit is selected from the 2 N One of the possible arrangements.

6. The trench type power device layout structure according to any one of claims 1 to 5, characterized in that: Each of the layout areas has a layout unit; or, at least one of the layout areas is divided into at least two layout units, two adjacent layout units are spliced ​​together and the overall extension directions of the serpentine channels of the two adjacent layout units are different.

7. The trench type power device layout structure according to claim 6, characterized in that: The overall extending directions of the serpentine channels of the two adjacent layout units are perpendicular to each other.

8. The trench type power device layout structure according to claim 6, characterized in that: Each of the layout areas is a second rectangle, wherein: At least one of the layout areas is divided into two triangular layout units spliced ​​together by the diagonal line of the second rectangle, and when the characteristic dimensions of all the serpentine channels are the same, the area ratio of the two triangular layout units is 1:1; Alternatively, at least one of the layout areas is divided into three layout units that are sequentially spliced ​​together by two straight lines parallel to the long side or the wide side of the second rectangle, and when the characteristic dimensions of all the serpentine channels are the same, the area ratio of the three layout units is 1:2:1; Alternatively, at least one of the layout areas is divided into four layout units that are sequentially spliced ​​together by four straight lines that form a windmill structure, two of the four straight lines are parallel to the long sides of the second rectangle, and the other two are parallel to the wide sides of the second rectangle, and when the characteristic dimensions of all serpentine channels are the same, the area ratio of the four layout units is 1:1:1:

1.

9. The trench type power device layout structure according to claim 6, characterized in that: The number of layout units contained in two adjacent layout areas is the same and the arrangement of the layout units is the same; or, the number of layout units contained in two adjacent layout areas is the same and the extension directions of the serpentine channels of the layout units at the corresponding same arrangement positions are different.

10. The trench type power device layout structure according to claim 6, characterized in that: Each of the layout areas also has a gate lead-out area, and the gate lead-out area is arranged at the center or peripheral edge or corner of the layout area.

11. The trench type power device layout structure according to claim 10, characterized in that: The gate lead-out regions of each layout area are arranged at the same position, or the layout areas are arranged in a matrix on the wafer according to the wafer cutting paths, and the gate lead-out regions of adjacent layout areas are arranged at similar corners of adjacent layout areas.

12. A semiconductor device, characterized in that: A device body is provided, wherein the device body has a layout structure of a channel-type power device as claimed in any one of claims 1 to 11.

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