Chip self-checking method, system and device under low power consumption condition and medium

Abstract

The invention discloses a chip self-checking method, system and device under a low-power-consumption condition and a medium. The chip self-checking method under the low-power-consumption condition comprises the steps that the operation power consumption of a chip is obtained in real time; when the operation power consumption is lower than a preset threshold value, obtaining a current operation state of the chip and a chip self-checking task; obtaining each sub-self-inspection task based on the chip self-inspection task; performing current chip self-checking processing based on the current running state and the chip self-checking task; and after the current chip self-checking processing is completed, obtaining a new running state and residual chip self-checking tasks, and continuing chip self-checking processing based on the new running state and the residual chip self-checking tasks until all sub-self-checking tasks are completed. Therefore, when the operation power consumption is lower than the preset threshold value, chip self-inspection is carried out according to the currently obtained operation state and the chip self-inspection task, chip self-inspection can be carried out under the condition of low power consumption, and then the power consumption of chip self-inspection is effectively reduced.

Description

Technical Field

[0001] The present invention relates to the field of chip self-checking technology, and in particular to a chip self-checking method, system, equipment and medium under low power consumption conditions. Background Art

[0002] With the continuous updating of chip hardware, the chip power consumption standards are getting higher and higher, which not only reduces the service life of the chip, but also increases the power consumption of the chip, thereby increasing the chip operating costs. Therefore, low-power operation of the chip has always been a research goal of technical personnel in this field. When the chip performs self-test, it is often necessary to conduct a comprehensive inspection of the various operating functions and operating states of the chip, which makes it difficult to reduce the power consumption during chip self-test. Therefore, how to improve the power saving effect during chip self-test is the current research goal.

[0003] The traditional chip self-test method is to perform functional self-test on each chip operating function of the chip based on the chip self-test running program. However, this self-test running program can only ensure that the chip completes the self-test task, but cannot ensure that the chip runs at low power consumption, resulting in poor power saving effect of chip self-test. Summary of the invention

[0004] The present invention provides a chip self-check method, system, device and medium under low power consumption conditions to solve the above technical problems and effectively reduce the power consumption of chip self-check.

[0005] In order to solve the above technical problems, the present invention provides a chip self-test method under low power consumption conditions, comprising:

[0006] Obtain the operating power consumption of the chip in real time;

[0007] When the operating power consumption is lower than a preset threshold, the current operating status of the chip and the chip self-check task are obtained;

[0008] Obtain each sub-self-check task based on the chip self-check task;

[0009] Perform current chip self-check processing based on current running status and chip self-check tasks;

[0010] After completing the current chip self-test processing, obtain the new running state and the remaining chip self-test tasks, and continue the chip self-test processing based on the new running state and the remaining chip self-test tasks until all sub-self-test tasks are completed.

[0011] The beneficial effects of the present invention are:

[0012] The present invention obtains the current operating state and chip self-test tasks of the chip when the operating power consumption of the chip is lower than a preset threshold, performs current chip self-test processing based on the current operating state and the chip self-test tasks, and after completing the current chip self-test processing, continues to perform chip self-test processing based on the acquired new operating state and the remaining chip self-test tasks until all sub-self-test tasks are completed. Therefore, the present invention performs chip self-test according to the currently acquired operating state and chip self-test tasks when the operating power consumption is lower than the preset threshold, and can perform chip self-test under low power consumption conditions, thereby effectively reducing the power consumption of the chip self-test.

[0013] As a preferred solution, the current chip self-checking process based on the current running state and the chip self-checking task includes:

[0014] Based on the current running state, obtaining current chip power consumption information and current running process;

[0015] Based on the chip self-check task, obtain the self-check process of each sub-self-check task to obtain the respective self-check processes;

[0016] Based on each inspection process, query the average power consumption information corresponding to each inspection process in the historical self-inspection database;

[0017] Based on the average power consumption information corresponding to each inspection process, the current chip power consumption information and the current running process, in each inspection process, the current self-inspection process is selected;

[0018] Perform current chip self-test based on the current self-test process.

[0019] As a preferred solution, the obtaining of current chip power consumption information and current operation process based on the current operation state includes:

[0020] Based on the current running state, obtaining the current power consumption value and the current running task of the chip;

[0021] Based on the current running task, obtain the current running process;

[0022] Based on the current running process, query the average unit power consumption value and the average running time of the current running process in the historical database;

[0023] Adjust the average unit power consumption value based on the current power consumption value to obtain the current average unit power consumption value;

[0024] Based on the current average unit power consumption value and the average operating time, current chip power consumption information is obtained.

[0025] As a preferred solution, the step of obtaining the self-test process of each sub-self-test task based on the chip self-test task includes:

[0026] Obtaining respective inspection targets based on the chip self-inspection task; wherein the respective inspection targets correspond to the respective sub-self-inspection tasks one by one;

[0027] Based on the respective inspection targets, query the task flow of each sub-self-inspection task in the self-inspection database respectively;

[0028] Get the average task power consumption of each task process;

[0029] For each sub-self-check task, a task flow with the lowest average task power consumption is selected from among the task flows corresponding to the sub-self-check task as the self-check flow of the sub-self-check task.

[0030] As a preferred solution, the method of querying average power consumption information corresponding to each inspection process in a historical self-inspection database based on each inspection process includes:

[0031] For each self-check process, in the historical self-check database, obtain each historical self-check log of the self-check process, the historical self-check power consumption of each historical self-check log, and the historical self-check duration of each historical self-check log;

[0032] Based on the historical self-check duration of each historical self-check log, calculate the average self-check duration of the self-check process;

[0033] Based on the historical self-test power consumption of each historical self-test log, calculate the average self-test power consumption of the self-test process;

[0034] The average self-checking time and the average self-checking power consumption are used as the average power consumption information corresponding to the self-checking process.

[0035] As a preferred solution, based on the average power consumption information corresponding to each inspection process, the current chip power consumption information and the current running process, in each inspection process, the current self-inspection process is screened, including:

[0036] Get the process content of the currently running process;

[0037] Extract the running process features corresponding to the process content;

[0038] Based on each inspection process, the self-inspection process content of each inspection process is obtained to obtain the content of each inspection process;

[0039] Extracting the self-inspection process features corresponding to the contents of each inspection process to obtain the respective inspection process features corresponding to the respective inspection processes;

[0040] Calculate the similarity between each running process feature and each self-check process feature respectively;

[0041] Among the self-inspection process features, the self-inspection process features with similarity greater than the similarity threshold are taken as candidate features;

[0042] In each self-inspection process, the self-inspection process corresponding to the candidate feature is used as a candidate self-inspection process;

[0043] Based on the current power consumption information and the average power consumption information corresponding to each candidate self-check process, calculating the power consumption deviation value between each candidate self-check process and the currently running process;

[0044] A candidate self-check process with the largest power consumption deviation value is selected as the current self-check process.

[0045] As a preferred solution, after completing the current chip self-check process and before obtaining the new running state and the remaining chip self-check tasks, it also includes:

[0046] Record the operation log information of the current running process;

[0047] Get the current self-check process content of the current self-check process;

[0048] Based on the operation log information and the current self-check process content, obtaining the remaining self-check process content of the current self-check process;

[0049] Using the current self-inspection process including the remaining self-inspection process content as a new self-inspection process;

[0050] Generate new sub-self-check tasks based on the new self-check process;

[0051] Each sub-self-check task is updated based on the new sub-self-check task.

[0052] Accordingly, in order to solve the above technical problems, the present invention also provides a chip self-checking system under low power consumption conditions, comprising: a power consumption acquisition module, a data acquisition module and a chip self-checking module;

[0053] Wherein, the power consumption acquisition module is used to acquire the operating power consumption of the chip in real time;

[0054] The data acquisition module is used to acquire the current operating state of the chip and the chip self-check task when the operating power consumption is lower than a preset threshold; and obtain each sub-self-check task based on the chip self-check task;

[0055] The chip self-check module is used to perform current chip self-check processing based on the current running state and chip self-check tasks;

[0056] The chip self-test module is also used to obtain a new operating state and remaining chip self-test tasks after completing the current chip self-test processing, and continue the chip self-test processing based on the new operating state and the remaining chip self-test tasks until all sub-self-test tasks are completed.

[0057] The present invention also provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of the chip self-test method under low power consumption conditions as described in any one of the above items are implemented.

[0058] The present invention also provides a storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the chip self-test method under low power consumption conditions as described in any one of the above items are implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figure 1 : A schematic flow chart of an embodiment of a chip self-test method under low power consumption conditions provided by the present invention;

[0060] Figure 2 : A schematic structural diagram of an embodiment of a chip self-checking system under low power consumption conditions provided by the present invention;

[0061] Figure 3 : An internal structure diagram of a terminal device provided for an embodiment of the present invention. DETAILED DESCRIPTION

[0062] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0063] The chip self-test method under low power consumption provided by an embodiment of the present invention is applied to a chip self-test system under low power consumption. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of the present application; the terms used in the specification of the application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application; the terms "including" and "having" in the specification and claims of the present application and the above-mentioned drawings and any variations thereof are intended to cover non-exclusive inclusions. The terms "first", "second", etc. in the specification and claims of the present application or the above-mentioned drawings are used to distinguish different objects, not to describe a specific order.

[0064] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0065] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the accompanying drawings.

[0066] With the continuous updating of chip hardware, the chip power consumption standards are getting higher and higher, which not only reduces the service life of the chip, but also increases the power consumption of the chip, thereby increasing the chip operating costs. Therefore, low-power operation of the chip has always been a research goal of technical personnel in this field. When the chip performs self-test, it is often necessary to conduct a comprehensive inspection of the various operating functions and operating states of the chip, which makes it difficult to reduce the power consumption during chip self-test. Therefore, how to improve the power saving effect during chip self-test is the current research goal.

[0067] The traditional chip self-test method is to perform functional self-test on each chip operating function of the chip based on the chip self-test running program. However, this self-test running program can only ensure that the chip completes the self-test task, but cannot ensure that the chip runs at low power consumption, resulting in poor power saving effect of chip self-test.

[0068] Embodiment 1

[0069] In order to solve the above technical problems, the present invention provides a chip self-test method, system, device and medium under low power consumption conditions, which effectively reduces the power consumption of chip self-test.

[0070] Please refer to Figure 1 , which is a flow chart of an embodiment of a chip self-test method under low power consumption conditions provided by an embodiment of the present invention.

[0071] like Figure 1 As shown, the chip self-test method under low power consumption conditions includes steps 101 to 105, specifically:

[0072] Step 101: Obtain the operating power consumption of the chip in real time;

[0073] Step 102: When the operating power consumption is lower than a preset threshold, the current operating state of the chip and the chip self-check task are obtained;

[0074] Step 103: obtaining each sub-self-check task based on the chip self-check task;

[0075] Step 104: performing a current chip self-check process based on the current running state and the chip self-check task;

[0076] Step 105: After completing the current chip self-test processing, obtain the new operating state and the remaining chip self-test tasks, and continue the chip self-test processing based on the new operating state and the remaining chip self-test tasks until all sub-self-test tasks are completed.

[0077] The present invention obtains the current operating state and chip self-test tasks of the chip when the operating power consumption of the chip is lower than a preset threshold, performs current chip self-test processing based on the current operating state and the chip self-test tasks, and after completing the current chip self-test processing, continues to perform chip self-test processing based on the acquired new operating state and the remaining chip self-test tasks until all sub-self-test tasks are completed. Therefore, the present invention performs chip self-test according to the currently acquired operating state and chip self-test tasks when the operating power consumption is lower than the preset threshold, and can perform chip self-test under low power consumption conditions, thereby effectively reducing the power consumption of the chip self-test.

[0078] The chip self-test method under low power consumption provided by the embodiment of the present application can be applied to the application environment of chip self-test. The method can be applied to a terminal, a server, or a system including a terminal and a server, and implemented through the interaction between the terminal and the server. Among them, the terminal can be, but is not limited to, various personal computers, laptops, smart phones, tablet computers, etc.

[0079] In this embodiment, the application environment of the chip self-test method under low power consumption conditions is a chip under low power consumption conditions, wherein the low power consumption condition is an artificially preset chip operation mode or a chip in low power consumption operation caused by other conditions.

[0080] In this embodiment, the remaining chip self-test tasks are all unfinished sub-self-test tasks.

[0081] Furthermore, when the operating power consumption is lower than a preset threshold, the chip self-check is stopped.

[0082] Furthermore, in step 102, the current operating state of the chip is collected by a detection device disposed on the chip, wherein the current operating state of the chip is the current power load percentage of the chip.

[0083] In this embodiment, obtaining the current operating status of the chip includes: detecting the current power output rate of the chip, and collecting the full power output rate of the chip, and then calculating the ratio between the current power output rate and the full power output rate to obtain the current power load percentage of the chip, and using the current power load percentage as the current operating status of the chip.

[0084] Further, in step 103, the sub-self-test tasks are obtained based on the chip self-test task, specifically, the chip self-test task is split into sub-self-test tasks of respective test targets.

[0085] Further, in step 104, the current chip self-checking process is performed based on the current running state and the chip self-checking task, including:

[0086] Based on the current running state, obtaining current chip power consumption information and current running process;

[0087] Based on the chip self-check task, obtain the self-check process of each sub-self-check task to obtain the respective self-check processes;

[0088] Based on each inspection process, query the average power consumption information corresponding to each inspection process in the historical self-inspection database;

[0089] Based on the average power consumption information corresponding to each inspection process, the current chip power consumption information and the current running process, in each inspection process, the current self-inspection process is selected;

[0090] Perform current chip self-test based on the current self-test process.

[0091] In this embodiment, each sub-self-test task corresponds to a self-test target, that is, the chip self-test task includes multiple sub-self-test tasks corresponding to the self-test targets. Based on the chip self-test task, the self-test process of each sub-self-test task is obtained to obtain each self-test process, specifically: in the historical self-test database, the task execution process of each sub-self-test task is queried to obtain the self-test process of each sub-self-test task to obtain each self-test process.

[0092] In this embodiment, each self-test process includes the normal operation process of the chip and the detection process of the chip. The self-test process of the sub-self-test task obtained by the present invention is the normal operation process of the chip. The normal operation process is the operation process when the chip runs each chip program, which is the same as the operation process of a conventional chip.

[0093] In this embodiment, the current chip power consumption information is based on the average unit power consumption value per unit time of the chip (i.e., the current power output rate of the chip) multiplied by the average running time of the current running process of the chip to obtain the target output power value of the chip. The target output power value is the output power of the total process when the chip is running the current running process.

[0094] Further, based on the current running state, obtaining current chip power consumption information and current running process includes:

[0095] Based on the current running state, obtaining the current power consumption value and the current running task of the chip;

[0096] Based on the current running task, obtain the current running process;

[0097] Based on the current running process, query the average unit power consumption value and the average running time of the current running process in the historical database;

[0098] Adjust the average unit power consumption value based on the current power consumption value to obtain the current average unit power consumption value;

[0099] Based on the current average unit power consumption value and the average operating time, current chip power consumption information is obtained.

[0100] In this embodiment, the current power consumption value is the instantaneous power consumption value corresponding to the current operating state obtained by the chip. Since the average unit power consumption value represents the average chip instantaneous power consumption value at each moment, the instantaneous power consumption value obtained at this time is the current actual chip instantaneous power consumption value.

[0101] In this embodiment, the average unit power consumption value is adjusted based on the current power consumption value to obtain the current average unit power consumption value, specifically: the average value between the current actual chip instantaneous power consumption value and the average unit power consumption value is calculated to obtain the current average unit power consumption value.

[0102] In this embodiment, the current chip power consumption information is obtained based on the current average unit power consumption value and the average operating time, specifically: the average operating time is multiplied by the current average unit power consumption value to obtain the current chip power consumption information.

[0103] The present invention adjusts the current average unit power consumption value of the chip by actually obtaining the current actual chip instantaneous power consumption value, obtains the current chip power consumption information of the chip, and improves the accuracy of the current chip power consumption information of the identified chip.

[0104] Furthermore, the self-checking process of each sub-self-checking task is obtained based on the chip self-checking task, including:

[0105] Obtaining respective inspection targets based on the chip self-inspection task; wherein the respective inspection targets correspond to the respective sub-self-inspection tasks one by one;

[0106] Based on the respective inspection targets, query the task flow of each sub-self-inspection task in the self-inspection database respectively;

[0107] Get the average task power consumption of each task process;

[0108] For each sub-self-check task, a task flow with the lowest average task power consumption is selected from among the task flows corresponding to the sub-self-check task as the self-check flow of the sub-self-check task.

[0109] In this embodiment, each self-check target corresponds to a chip operation program, and each chip operation program corresponds to one or more chip operation processes.

[0110] In this embodiment, each task flow is one or more chip operation flows corresponding to the chip operation program. The average task power consumption is the average value of each historical operation power consumption of each task flow.

[0111] The present invention reduces the task power consumption of the self-check process corresponding to each sub-self-check task by selecting the task flow with the lowest task power consumption as the self-check flow of the sub-self-check task, thereby improving the task power consumption saving degree of each sub-self-check task.

[0112] Further, the querying of average power consumption information corresponding to each inspection process in a historical self-inspection database based on each inspection process includes:

[0113] For each self-check process, in the historical self-check database, obtain each historical self-check log of the self-check process, the historical self-check power consumption of each historical self-check log, and the historical self-check duration of each historical self-check log;

[0114] Based on the historical self-check duration of each historical self-check log, calculate the average self-check duration of the self-check process;

[0115] Based on the historical self-test power consumption of each historical self-test log, calculate the average self-test power consumption of the self-test process;

[0116] The average self-checking time and the average self-checking power consumption are used as the average power consumption information corresponding to the self-checking process.

[0117] In this embodiment, the historical self-check database includes the corresponding relationship between the power consumption information of the chip self-checking each time the sub-self-checking task is executed and the sub-self-checking task. Based on the above corresponding relationship, the average power consumption information corresponding to each self-checking process is calculated.

[0118] In this embodiment, the historical self-test power consumption is the total operating power consumption required for the chip to run the self-test process stored in the historical self-test log; the historical self-test duration is the total duration required for the chip to run the self-test process.

[0119] The present invention ensures the comprehensiveness of the analysis of the power consumption information of each self-check process by calculating the average self-check power consumption and the average self-check duration.

[0120] Further, based on the average power consumption information corresponding to each inspection process, the current chip power consumption information and the current running process, in each inspection process, screening the current self-inspection process includes:

[0121] Get the process content of the currently running process;

[0122] Extract the running process features corresponding to the process content;

[0123] Based on each inspection process, the self-inspection process content of each inspection process is obtained to obtain the content of each inspection process;

[0124] Extracting the self-inspection process features corresponding to the contents of each inspection process to obtain the respective inspection process features corresponding to the respective inspection processes;

[0125] Calculate the similarity between each running process feature and each self-check process feature respectively;

[0126] Among the self-inspection process features, the self-inspection process features with similarity greater than the similarity threshold are taken as candidate features;

[0127] In each self-inspection process, the self-inspection process corresponding to the candidate feature is used as a candidate self-inspection process;

[0128] Based on the current power consumption information and the average power consumption information corresponding to each candidate self-check process, calculating the power consumption deviation value between each candidate self-check process and the currently running process;

[0129] A candidate self-check process with the largest power consumption deviation value is selected as the current self-check process.

[0130] In this embodiment, one implementation method of extracting the running process features corresponding to the process content and extracting the self-check process features corresponding to each inspection process content is: each process content or self-check process content is converted into text to obtain the text content of each process content or self-check process content, and then, based on a neural network of natural language processing technology, the text features of each text content are extracted respectively to obtain the running process features or self-check process features of each process content or self-check process content.

[0131] In this embodiment, the similarity between each running process feature and each self-check process feature can be calculated respectively, but is not limited to, by using a cosine similarity algorithm.

[0132] In this embodiment, the similarity threshold is a preset value and can be set according to actual conditions.

[0133] In this embodiment, based on the current power consumption information and the average power consumption information corresponding to each candidate self-check process, the power consumption deviation value between each candidate self-check process and the current running process is calculated, specifically: the deviation value between the average unit power consumption value of each candidate self-check process and the power consumption value of the current running process is calculated to obtain a first power consumption deviation value; the duration deviation value between the average duration of each candidate self-check process and the average running duration of the current running process is calculated to obtain a second deviation value; wherein the deviation value includes positive and negative deviation values, and the positive deviation value indicates that the running duration of the current running process is shorter than the running duration of the current self-check process, or the power consumption value of the current running process is lower than the power consumption value of the current self-check process; the first deviation value and the second deviation value are used as power consumption deviation values.

[0134] In this embodiment, the candidate self-check process with the largest power consumption deviation value is screened, that is, the candidate self-check process with a running time much longer than the current running process and a power consumption value much greater than the current running process is screened. The screening of the candidate self-check process can replace the candidate self-check process with the current running process, and can remove the high-power consumption and long-time self-check process, thereby greatly reducing the power consumption value of the self-check process.

[0135] After the present invention screens the candidate self-check processes by the similarity of the process contents, the screened running time is much longer than the currently running process, and the power consumption value is much greater than the candidate self-check processes of the currently running process, thereby greatly reducing the power consumption value of the self-check process and improving the degree of power saving of the self-check task.

[0136] Furthermore, after completing the current chip self-check process and before obtaining the new running state and the remaining chip self-check tasks, it also includes:

[0137] Record the operation log information of the current running process;

[0138] Get the current self-check process content of the current self-check process;

[0139] Based on the operation log information and the current self-check process content, obtaining the remaining self-check process content of the current self-check process;

[0140] Using the current self-inspection process including the remaining self-inspection process content as a new self-inspection process;

[0141] Generate new sub-self-check tasks based on the new self-check process;

[0142] Each sub-self-check task is updated based on the new sub-self-check task.

[0143] In this embodiment, after generating a new sub-self-check task based on the new self-check process, the method further includes: replacing the self-check task corresponding to the current self-check process with the new sub-self-check task.

[0144] In this embodiment, a small amount of power consumption is consumed in recording the operation log information corresponding to the current operation process and evaluating the log.

[0145] In this embodiment, the remaining self-check process content is the process content not included in the current running process. For example, when the current running process is (A, B, C, D) and the self-check process content is (A, B, C, D, E, F), the remaining self-check process is (E, F). However, when the self-check process content is equal to or less than the current running process, the self-check process will not have any remaining self-check process content. The present invention determines whether there is any remaining self-check process content based on the above rules.

[0146] In this embodiment, the new sub-self-check task has the same task objective as the self-check task corresponding to the new sub-self-check task, but the self-check process of the new sub-self-check task is the remaining self-check process.

[0147] In this embodiment, the remaining chip self-test tasks include the self-test tasks corresponding to the current self-test process that has been screened. Since the current self-test process and the current running process may not completely correspond, that is, there are some self-test processes that have not been executed, the present invention regenerates new self-test tasks for the unexecuted self-test processes and replaces the self-test tasks of the current self-test process. During the screening process, the new self-test task needs to match the current task process corresponding to the completed self-test process corresponding to the unexecuted self-test process before it can be matched. For example, the self-check process corresponding to the new self-check task includes (D, E, F), and the original self-check process corresponding to the self-check process is (A, B, C, D, E, F). After the first screening is the current self-check process, when the current running process is executed, the self-check process only completes (A, B, C, D). Then, when the second screening is performed, the current running process that can match the self-check process at least includes the process corresponding to (A, B, C, D, E, F), that is, the current running process can be (A, B, C, D, E, F, ...), but it cannot be the process type corresponding to (A, C, D, E, F, ...), (B, C, D, E, F, ...), (C, D, E, F, ...), (D, E, F, ...). The ellipsis can correspond to a specific process or no specific process, that is, the current running process completely corresponds to the original process. However, in the actual execution process, only the operation information of the current operation process when running the (D, E, F) part needs to be recorded, so as to execute the detection process of the self-check task for the operation information of this part.

[0148] The present invention regenerates sub-self-check tasks by identifying the completion degree of the self-check process, thereby ensuring that each self-check process can be completed and the power consumption of each self-check process is reduced to a minimum value.

[0149] In this embodiment, another implementation of the chip self-test method under low power consumption conditions is:

[0150] Obtain the current operating status of the chip and the chip self-test task, and obtain the current chip power consumption information based on the current operating status;

[0151] Based on the chip self-check task, obtain the self-check process of each sub-self-check task to obtain the respective self-check process;

[0152] Based on each self-check process, average power consumption information corresponding to each self-check process is obtained to obtain average power consumption information corresponding to each self-check process;

[0153] Based on the average power consumption information corresponding to each self-check process, the current chip power consumption information and the current running process, in each self-check process, the current self-check process is selected to perform chip self-check processing, and after the chip self-check processing of the current self-check process is completed, a new running state of the chip is re-acquired;

[0154] Get all unfinished sub-self-check tasks;

[0155] The new running state replaces the current running state, and all unfinished sub-self-test tasks replace the chip self-test task of the chip, and the step of obtaining the current chip power consumption information based on the current running state is returned to be executed until all sub-self-test tasks are completed.

[0156] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0157] Accordingly, in order to solve the above technical problems, the present invention also provides a chip self-test system under low power consumption conditions. Figure 3 , which is a structural diagram of an embodiment of a chip self-test system under low power consumption conditions provided by the present invention.

[0158] The chip self-checking system 20 under low power consumption conditions includes: a power consumption acquisition module 201, a data acquisition module 202 and a chip self-checking module 203;

[0159] The power consumption acquisition module 201 is used to acquire the operating power consumption of the chip in real time;

[0160] The data acquisition module 202 is used to acquire the current operating state of the chip and the chip self-check task when the operating power consumption is lower than a preset threshold; and obtain each sub-self-check task based on the chip self-check task;

[0161] The chip self-check module 203 is used to perform current chip self-check processing based on the current running state and chip self-check tasks;

[0162] The chip self-test module 203 is also used to obtain a new operating state and remaining chip self-test tasks after completing the current chip self-test process, and continue the chip self-test process based on the new operating state and the remaining chip self-test tasks until all sub-self-test tasks are completed.

[0163] Each module in the chip self-test system under the above low power consumption condition can be implemented in whole or in part by software, hardware and their combination. Each module can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory in the computer device in the form of software, so that the processor can call and execute the corresponding operations of each module.

[0164] The present invention also provides a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, the steps of the chip self-test method under low power consumption conditions as described in any one of the above items are implemented.

[0165] In one embodiment, the internal structure diagram of the terminal device can be as follows: Figure 3 As shown. The terminal device includes a processor, a memory, a communication interface, a display unit and an input device connected through a system bus. Among them, the processor of the terminal device is used to provide computing and control capabilities. The memory of the terminal device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The communication interface of the terminal device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be achieved through WIFI, a mobile cellular network, NFC (near field communication) or other technologies. When the computer program is executed by the processor, a chip self-test method under low power consumption conditions is implemented. The display unit of the terminal device can be a liquid crystal display or an electronic ink display, and the input system of the terminal device can be a touch layer covered on the display, or a button, trackball or touchpad set on the terminal device housing, or an external keyboard, touchpad or mouse, etc.

[0166] Those skilled in the art will understand that Figure 3 The structure shown in the figure is only a block diagram of a partial structure related to the scheme of the present application, and does not constitute a limitation on the terminal device to which the scheme of the present application is applied. The specific terminal device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0167] The present invention also provides a storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the chip self-test method under low power consumption conditions as described in any one of the above items are implemented.

[0168] The present invention also provides a computer program product, comprising a computer program, which, when executed by a processor, implements the steps of any one of the above-mentioned chip self-test methods under low power consumption conditions.

[0169] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0170] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetoresistive random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, etc., but are not limited to this.

[0171] Compared with the prior art, the embodiments of the present invention have the following beneficial effects:

[0172] Compared with the prior art, the self-check running program can only ensure that the chip completes the self-check task, but cannot ensure that the chip runs at low power consumption, resulting in poor self-check power saving effect of the chip. The present invention obtains the current chip power consumption information of the current running state, thereby screening the current self-test process in each test process, so that the self-test process is integrated with the current running process corresponding to the current running state; because the current self-test process may not be exactly the same as the current running process, each currently remaining running process replaces the original self-test process to perform chip self-test, thereby realizing the technical solution of self-testing while running; because the chip self-test is only performed when the running power consumption is lower than the preset threshold in the present invention, the chip runs under low power consumption conditions, and the power consumption of the chip running process is in a low power consumption environment, thereby avoiding the high power consumption self-test of the prior art; the present invention divides the running data of the low power running process into tasks and processes, and completes each sub-self-test task respectively, thereby realizing the low power self-test effect of the chip, which not only reduces the extra workload of the chip and avoids increasing the chip power consumption, but also greatly reduces the power consumption value of the self-test task while ensuring that all self-test tasks can be completed, thereby comprehensively improving the power saving effect of the chip self-test.

[0173] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0174] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present invention. It should be understood that the above description is only a specific embodiment of the present invention and is not intended to limit the scope of protection of the present invention. It is particularly pointed out that for those skilled in the art, any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of protection of the present invention.

Claims

1. A chip self-test method under low power consumption conditions, characterized in that: include: Obtain the operating power consumption of the chip in real time; When the operating power consumption is lower than a preset threshold, the current operating status of the chip and the chip self-check task are obtained; Obtain each sub-self-check task based on the chip self-check task; Perform current chip self-check processing based on current running status and chip self-check tasks; After completing the current chip self-test processing, obtain the new running state and the remaining chip self-test tasks, and continue the chip self-test processing based on the new running state and the remaining chip self-test tasks until all sub-self-test tasks are completed.

2. A chip self-test method under low power consumption conditions as claimed in claim 1, characterized in that: The current chip self-check process is performed based on the current running state and the chip self-check task, including: Based on the current running state, obtaining current chip power consumption information and current running process; Based on the chip self-check task, obtain the self-check process of each sub-self-check task to obtain the respective self-check processes; Based on each inspection process, query the average power consumption information corresponding to each inspection process in the historical self-inspection database; Based on the average power consumption information corresponding to each inspection process, the current chip power consumption information and the current running process, in each inspection process, the current self-inspection process is selected; Perform current chip self-test based on the current self-test process.

3. A chip self-test method under low power consumption conditions as claimed in claim 2, characterized in that: The obtaining of current chip power consumption information and current operation process based on the current operation state includes: Based on the current running state, obtaining the current power consumption value and the current running task of the chip; Based on the current running task, obtain the current running process; Based on the current running process, query the average unit power consumption value and the average running time of the current running process in the historical database; Adjust the average unit power consumption value based on the current power consumption value to obtain the current average unit power consumption value; Based on the current average unit power consumption value and the average operating time, current chip power consumption information is obtained.

4. A chip self-test method under low power consumption conditions as claimed in claim 2, characterized in that: The step of obtaining the self-test process of each sub-self-test task based on the chip self-test task includes: Obtaining respective inspection targets based on the chip self-inspection task; wherein the respective inspection targets correspond to the respective sub-self-inspection tasks one by one; Based on the respective inspection targets, query the task flow of each sub-self-inspection task in the self-inspection database respectively; Get the average task power consumption of each task process; For each sub-self-check task, a task flow with the lowest average task power consumption is selected from among the task flows corresponding to the sub-self-check task as the self-check flow of the sub-self-check task.

5. A chip self-test method under low power consumption conditions as claimed in claim 4, characterized in that: The querying of average power consumption information corresponding to each inspection process in a historical self-inspection database based on each inspection process includes: For each self-check process, in the historical self-check database, obtain each historical self-check log of the self-check process, the historical self-check power consumption of each historical self-check log, and the historical self-check duration of each historical self-check log; Based on the historical self-check duration of each historical self-check log, calculate the average self-check duration of the self-check process; Based on the historical self-test power consumption of each historical self-test log, calculate the average self-test power consumption of the self-test process; The average self-checking time and the average self-checking power consumption are used as the average power consumption information corresponding to the self-checking process.

6. A chip self-test method under low power consumption conditions as claimed in claim 2, characterized in that: The method of screening the current self-check process in each inspection process based on the average power consumption information corresponding to each inspection process, the current chip power consumption information and the current running process includes: Get the process content of the currently running process; Extract the running process features corresponding to the process content; Based on each inspection process, the self-inspection process content of each inspection process is obtained to obtain the content of each inspection process; Extracting the self-inspection process features corresponding to the contents of each inspection process to obtain the respective inspection process features corresponding to the respective inspection processes; Calculate the similarity between each running process feature and each self-check process feature respectively; Among the self-inspection process features, the self-inspection process features with similarity greater than the similarity threshold are taken as candidate features; In each self-inspection process, the self-inspection process corresponding to the candidate feature is used as a candidate self-inspection process; Based on the current power consumption information and the average power consumption information corresponding to each candidate self-check process, calculating the power consumption deviation value between each candidate self-check process and the currently running process; A candidate self-check process with the largest power consumption deviation value is selected as the current self-check process.

7. A chip self-test method under low power consumption conditions as claimed in claim 6, characterized in that: After completing the current chip self-check process and before obtaining the new running state and the remaining chip self-check tasks, it also includes: Record the operation log information of the current running process; Get the current self-check process content of the current self-check process; Based on the operation log information and the current self-check process content, obtaining the remaining self-check process content of the current self-check process; Using the current self-inspection process including the remaining self-inspection process content as a new self-inspection process; Generate new sub-self-check tasks based on the new self-check process; Each sub-self-check task is updated based on the new sub-self-check task.

8. A chip self-test system under low power consumption conditions, characterized in that: include: Power consumption acquisition module, data acquisition module and chip self-test module; Wherein, the power consumption acquisition module is used to acquire the operating power consumption of the chip in real time; The data acquisition module is used to acquire the current operating state of the chip and the chip self-check task when the operating power consumption is lower than a preset threshold; and obtain each sub-self-check task based on the chip self-check task; The chip self-check module is used to perform current chip self-check processing based on the current running state and chip self-check tasks; The chip self-test module is also used to obtain a new operating state and remaining chip self-test tasks after completing the current chip self-test processing, and continue the chip self-test processing based on the new operating state and the remaining chip self-test tasks until all sub-self-test tasks are completed.

9. A terminal device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the steps of the chip self-test method under low power consumption conditions as described in any one of claims 1 to 7 are implemented.

10. A storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the chip self-test method under low power consumption conditions as claimed in any one of claims 1 to 7 are implemented.

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