Self-starting bias circuit and circuit board
By designing a self-start bias circuit including a bias module and a self-start module, the problem that the bias circuit cannot start in extreme environments is solved, the self-start and normal operation of the circuit are realized, and power consumption is reduced under normal conditions.
Patent Information
- Application Number
- CN202411531576.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-30
- Publication Date
- 2025-02-11
AI Technical Summary
In extreme working environments such as low temperature and low voltage, the bias circuit cannot start normally, resulting in abnormal operation of the electronic circuit system.
Design a self-start bias circuit, including a bias module and a self-start module. The bias module includes a first current mirror and a second current mirror, and the self-starting module starts the bias module and operates normally by driving current. When the bias module is working properly, the self-start module is turned off to reduce quiescent current consumption.
The self-start function of the bias circuit in extreme environments is realized to ensure the normal operation of the electronic circuit system and reduce power consumption in normal state.
Smart Images
Figure CN119414912A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of electronic circuits, and in particular to a self-starting bias circuit and a circuit board. Background Art
[0002] In some electronic circuits containing active components, bias circuits are usually set up to provide a stable current or voltage to the active components to ensure that the active components work in a suitable working range. However, in some extreme working environments, such as low temperature and low voltage, the bias circuit cannot be started normally, which will cause the electronic circuit system to work abnormally. Summary of the invention
[0003] In order to solve the self-starting problem of the bias circuit, the present application provides the following technical solutions:
[0004] In a first aspect, a self-starting bias circuit is provided, comprising a bias module and a self-starting module;
[0005] The bias module includes: a first voltage input terminal, a first current input terminal and a second current input terminal;
[0006] The self-starting module includes: a second voltage input terminal, a first current output terminal and a second current output terminal;
[0007] The first voltage input terminal is electrically connected to the second voltage input terminal, the first current output terminal is electrically connected to the first current input terminal, and the second current output terminal is electrically connected to the second current input terminal;
[0008] The self-starting bias circuit is configured such that, in response to the bias module working normally, the self-starting module does not work; in response to the bias module working abnormally, the self-starting module provides a driving current to the bias module so that the bias module works normally after starting.
[0009] Further, the bias module includes: a first current mirror and a second current mirror;
[0010] The first current mirror comprises: a first current mirror first port, a first current mirror second port, a first current mirror third port and a first current mirror fourth port;
[0011] The second current mirror comprises: a second current mirror first port, a second current mirror second port, a second current mirror third port and a second current mirror fourth port;
[0012] The first port of the first current mirror and the second port of the first current mirror are connected to the input voltage, the third port of the first current mirror is electrically connected to the first port of the second current mirror, the fourth port of the first current mirror is electrically connected to the second port of the second current mirror, and the third port of the second current mirror and the fourth port of the second current mirror are grounded.
[0013] Furthermore, the bias module further includes: a first resistor, a second resistor and a third resistor;
[0014] The first port of the first current mirror is connected in series with the first resistor and then connected to the input voltage;
[0015] The second port of the first current mirror is connected in series with a second resistor and then connected to the input voltage;
[0016] The third port of the second current mirror is connected in series with the third resistor and then grounded.
[0017] Further, the first current mirror includes: a first transistor and a second transistor;
[0018] The first transistor includes: a first transistor first electrode, a first transistor second electrode and a first transistor third electrode;
[0019] The second transistor includes: a second transistor first electrode, a second transistor second electrode and a second transistor third electrode;
[0020] The second electrode of the first transistor serves as the first port of the first current mirror;
[0021] The third electrode of the first transistor serves as the third port of the first current mirror;
[0022] The second electrode of the second transistor serves as the second port of the first current mirror;
[0023] The third stage of the second transistor serves as the fourth port of the first current mirror;
[0024] The first electrode of the first transistor is electrically connected to the first electrode of the second transistor, and the first electrode of the first transistor is electrically connected to the third electrode of the first transistor.
[0025] Further, the first transistor and the second transistor are both P-channel metal-oxide-semiconductor field effect transistors;
[0026] The first electrode of the first transistor is the gate of the first transistor, the second electrode of the first transistor is the source of the first transistor, and the third electrode of the first transistor is the drain of the first transistor;
[0027] The first electrode of the second transistor is the gate of the second transistor, the second electrode of the second transistor is the source of the second transistor, and the third electrode of the second transistor is the drain of the second transistor.
[0028] Further, the second current mirror includes: a third transistor and a fourth transistor;
[0029] The third transistor includes: a third transistor first electrode, a third transistor second electrode and a third transistor third electrode;
[0030] The fourth transistor includes: a fourth transistor first electrode, a fourth transistor second electrode and a fourth transistor third electrode;
[0031] The second electrode of the third transistor serves as the second port of the second current mirror;
[0032] The third electrode of the third transistor serves as the fourth port of the second current mirror;
[0033] The second electrode of the fourth transistor serves as the first port of the second current mirror;
[0034] The third stage of the fourth transistor serves as the third port of the second current mirror;
[0035] The first electrode of the third transistor is electrically connected to the first electrode of the fourth transistor, and the first electrode of the third transistor is electrically connected to the second electrode of the third transistor.
[0036] Further, the third transistor and the fourth transistor are both N-channel metal-oxide-semiconductor field effect transistors;
[0037] The first electrode of the third transistor is a gate electrode of the third transistor, the second electrode of the third transistor is a drain electrode of the third transistor, and the third electrode of the third transistor is a source electrode of the third transistor;
[0038] The first electrode of the fourth transistor is the gate of the fourth transistor, the second electrode of the fourth transistor is the drain of the fourth transistor, and the third electrode of the fourth transistor is the source of the fourth transistor.
[0039] Further, the self-starting module includes: a fifth transistor, a sixth transistor and a seventh transistor;
[0040] The fifth transistor includes: a fifth transistor first electrode, a fifth transistor second electrode and a fifth transistor third electrode;
[0041] The sixth transistor includes: a first electrode of a sixth transistor, a second electrode of a sixth transistor, and a third electrode of a sixth transistor;
[0042] The seventh transistor includes: a first electrode of the seventh transistor, a second electrode of the seventh transistor and a third electrode of the seventh transistor;
[0043] The first electrode of the fifth transistor is used as the second current output terminal, the second electrode of the sixth transistor is used as the first current output terminal, and the second electrode of the seventh transistor is used as the second voltage input terminal;
[0044] The first electrode of the fifth transistor is electrically connected to the third electrode of the sixth transistor, the third electrode of the fifth transistor is grounded, the second electrode of the fifth transistor is electrically connected to the third electrode of the seventh transistor, and the first electrode of the sixth transistor is electrically connected to the first electrode of the seventh transistor and the third electrode of the seventh transistor.
[0045] Further, the fifth transistor and the sixth transistor are both N-channel metal-oxide-semiconductor field effect transistors, and the seventh transistor is a P-channel metal-oxide-semiconductor field effect transistor;
[0046] The first electrode of the fifth transistor is the gate electrode of the fifth transistor, the second electrode of the fifth transistor is the drain electrode of the fifth transistor, and the third electrode of the fifth transistor is the source electrode of the fifth transistor;
[0047] The first electrode of the sixth transistor is the gate electrode of the sixth transistor, the second electrode of the sixth transistor is the drain electrode of the sixth transistor, and the third electrode of the sixth transistor is the source electrode of the sixth transistor;
[0048] The first electrode of the seventh transistor is the gate of the seventh transistor, the second electrode of the seventh transistor is the source of the seventh transistor, and the third electrode of the seventh transistor is the source of the seventh transistor.
[0049] In a second aspect, a circuit board is disclosed, comprising the self-starting bias circuit described in the first aspect.
[0050] The beneficial effects of the technical solution provided by the embodiment of the present application are:
[0051] By implementing the self-starting bias circuit and circuit board disclosed in the embodiments of the present application, when the circuit is abnormally started, the sixth transistor is turned on, while the fifth transistor and the seventh transistor are turned off, the first transistor and the second transistor are turned on, and the current flows through the first transistor and the second transistor to the fourth transistor and the third transistor respectively, the potential of the first electrode of the third transistor increases, and the third transistor and the fourth transistor are turned on, so that the bias circuit works to generate a bias current; after the bias circuit is normally started, the fifth transistor is turned on, so that the sixth transistor is turned off, and then the self-starting module is turned off, thereby reducing static current consumption. BRIEF DESCRIPTION OF THE DRAWINGS
[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.
[0053] Figure 1 is a schematic diagram of a self-starting bias circuit module provided in an embodiment of the present application;
[0054] Figure 2 is a schematic diagram of a bias module circuit provided in an embodiment of the present application;
[0055] Figure 3 is another bias module circuit schematic diagram provided in an embodiment of the present application;
[0056] Figure 4 This is a schematic diagram of a self-starting module circuit provided in an embodiment of the present application;
[0057] Figure 5 is a circuit diagram of a startup bias circuit provided in an embodiment of the present application;
[0058] Figure 6 It is a schematic diagram of a startup bias circuit provided by an embodiment of the present application to provide bias for an active element;
[0059] Figure 7 It is a schematic diagram of another startup bias circuit provided in an embodiment of the present application for providing bias for an active element. DETAILED DESCRIPTION
[0060] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in the implementation mode of this application will be clearly and completely described below in conjunction with the drawings in the implementation mode of this application. Obviously, the described implementation mode is only a part of the embodiments of this application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.
[0061] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure shall have the usual meanings understood by persons with ordinary skills in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "one" or "the" do not indicate a quantity limitation, but indicate that there is at least one. The numbers in the drawings of the specification only indicate the distinction between various functional components or modules, and do not indicate the logical relationship between components or modules. Words such as "include" or "comprise" and similar words mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.
[0062] Hereinafter, various embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that in the accompanying drawings, the same reference numerals are given to components having substantially the same or similar structures and functions, and repeated descriptions thereof will be omitted.
[0063] In order to solve the self-starting problem of the bias circuit, the present application provides the following embodiments.
[0064] In some embodiments, Figure 1 As shown, a self-starting bias circuit includes a bias module 1 and a self-starting module 2;
[0065] The bias module 1 includes: a first voltage input terminal 1 i , the first current input terminal 1 i1 And the second current input terminal 1 i2 ;
[0066] The self-starting module 2 includes: a second voltage input terminal 2 i , the first current output terminal 2 o1 And the second current output terminal 2 o2 ;
[0067] First voltage input terminal 1 i The second voltage input terminal 2 i Electrical connection, first current output terminal 1 o1 With the first current input terminal 2 i1 Electrical connection, second current output terminal 1 o2 Electrically connected to the second current input terminal 2 i2 .
[0068] The self-starting bias circuit is configured such that, in response to the bias module 1 working normally, the self-starting module 2 does not work; in response to the bias module 1 working abnormally, the self-starting module 2 provides a driving current to the bias module 1 so that the bias module 1 works normally after starting.
[0069] Specifically, Figure 2 As shown, the bias module 1 includes: a first current mirror 11 and a second current mirror 12;
[0070] The first current mirror 11 includes: a first current mirror first port 111, a first current mirror second port 112, a first current mirror third port 113 and a first current mirror fourth port 114;
[0071] The second current mirror 12 includes: a second current mirror first port 121, a second current mirror second port 122, a second current mirror third port 123 and a second current mirror fourth port 124;
[0072] The first current mirror first port 111 and the first current mirror second port 112 are connected to the input voltage V DD The first current mirror third port 113 is electrically connected to the second current mirror first port 121 , the first current mirror fourth port 114 is electrically connected to the second current mirror second port 122 , and the second current mirror third port 123 and the second current mirror fourth port 124 are grounded.
[0073] Preferably, if Figure 3 As shown, the bias module 1 further includes: a first resistor R1, a second resistor R2 and a third resistor R3;
[0074] The first port 111 of the first current mirror is connected in series with the first resistor R1 and connected to the input voltage V DD ;
[0075] The second port 112 of the first current mirror is connected in series with the second resistor R2 and connected to the input voltage V DD ;
[0076] The third port 123 of the second current mirror is connected in series with the third resistor R3 and then grounded.
[0077] The first current mirror 11 includes: a first transistor T1 and a second transistor T2;
[0078] The first transistor T1 includes: a first transistor first electrode T 11 , the second electrode T of the first transistor 12 and the third electrode T of the first transistor 13 ;
[0079] The second transistor T2 includes: a first electrode T 21 , the second transistor second electrode T 22 and the third electrode T of the second transistor 23 ;
[0080] The first transistor second electrode T 12 A first port 111 as a first current mirror;
[0081] The third electrode T of the first transistor 13 A third port 113 as a first current mirror;
[0082] The second transistor second electrode T 22 A second port 112 as a first current mirror;
[0083] The second transistor third stage T 23 A fourth port 114 as a first current mirror;
[0084] The first transistor first electrode T 11 The first electrode T of the second transistor 21 Electrically connected, the first transistor first electrode T 11 The third electrode T of the first transistor 13 Electrical connection.
[0085] Further, the first transistor T1 and the second transistor T2 are both P-channel metal-oxide-semiconductor field effect transistors;
[0086] The first transistor first electrode T 11 is the gate of the first transistor T1, and the second electrode T 12 is the source of the first transistor T1, and the third electrode of the first transistor T 13 is the drain of the first transistor T1;
[0087] The first electrode T of the second transistor 21 is the gate of the second transistor T2, and the second electrode T 22 is the source of the second transistor T2, and the third electrode T 23 is the drain of the second transistor T2.
[0088] The second current mirror 12 includes: a third transistor T3 and a fourth transistor T4;
[0089] The third transistor T3 includes: a first electrode T 31 , the second electrode T of the third transistor 32 and the third electrode T of the third transistor 33 ;
[0090] The fourth transistor T4 includes: a first electrode T 41 , the second electrode T of the fourth transistor 42 and the third electrode T of the fourth transistor 43 ;
[0091] The second electrode T of the third transistor 32 A second port 122 as a second current mirror;
[0092] The third transistor third electrode T 33 A fourth port 124 as a second current mirror;
[0093] The second electrode T of the fourth transistor 42 A first port 121 as a second current mirror;
[0094] The fourth transistor third stage T 43 A third port 123 as a second current mirror;
[0095] The first electrode T of the third transistor 31 and the first electrode T of the fourth transistor 41 Electrically connected, the first electrode T of the third transistor 31 The second electrode T of the third transistor 32 Electrical connection.
[0096] Further, the third transistor T3 and the fourth transistor T4 are both N-channel metal-oxide-semiconductor field effect transistors;
[0097] The first electrode T of the third transistor 31is the gate of the third transistor T3, and the second electrode T 32 is the drain of the third transistor T3, and the third electrode T 33 is the source of the third transistor T3;
[0098] The first electrode T of the fourth transistor 41 is the gate of the fourth transistor T4, and the second electrode T 42 is the drain of the fourth transistor T4, and the third electrode T 43 is the source of the fourth transistor T4.
[0099] The first current mirror 11 is a linear current mirror, and the second current mirror 12 is a nonlinear current mirror. Due to the existence of the third resistor R3, the currents of the third transistor T3 and the fourth transistor T4 in the second current mirror 12 are not in linear proportion.
[0100] Preferably, the first transistor T1 and the second transistor T2 are P-channel metal-oxide-semiconductor field effect transistors of the same model, which, on the one hand, ensures that the function of the linear current mirror is realized; on the other hand, makes the current flowing through the third transistor T3 and the current flowing through the fourth transistor T4 the same. The third transistor T3 and the fourth transistor T4 are N-channel metal-oxide-semiconductor field effect transistors to realize the function of the nonlinear current mirror.
[0101] Adoption I B represents the current flowing through the third transistor T3 or the current flowing through the fourth transistor T4. It can be known that the gate-source voltage of the fourth transistor T4 is:
[0102] I GS3 =V GS4 +I B R3
[0103] Among them, V GS3 represents the gate-source voltage of the third transistor, V GS4 represents the gate-source voltage of the fourth transistor, I B represents the current flowing through the third transistor or the fourth transistor, and R3 represents the resistance value of the third resistor.
[0104] It can be seen from the above formula that when the circuit is not started normally and the circuit does not generate bias current, the circuit will have zero voltage. At this time, the self-starting module works and provides driving current to the bias module, so that the bias module can start normally and output bias current. When the bias module works normally, the self-starting module stops working, thereby stopping the input of driving current to the bias module. When the bias module works normally, the self-starting module can stop working. Therefore, no additional current flows through the components in the self-starting module, and the self-starting module no longer consumes electrical energy, reducing the overall power consumption of the self-starting bias circuit.
[0105] Preferably, the value of the bias voltage is adjusted by setting the resistance of the third resistor R3.
[0106] Specifically, the self-starting module 2 is as follows Figure 4 As shown, it includes: a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7;
[0107] The fifth transistor T5 includes: a first electrode T 51 , the second electrode T of the fifth transistor 52 and the third electrode T of the fifth transistor 53 ;
[0108] The sixth transistor T6 includes: a first electrode T 61 , the second electrode T of the sixth transistor 62 and the third electrode T of the sixth transistor 63 ;
[0109] The seventh transistor T7 includes: a first electrode T 71 , the second electrode T of the seventh transistor 72 and the third electrode T of the seventh transistor 73 ;
[0110] The first electrode T of the fifth transistor 51 As the second current output terminal 2 o2 , the second electrode T of the sixth transistor 62 As the first current output terminal 2 o1 , the second electrode T of the seventh transistor 72 As the second voltage input terminal 2 i ;
[0111] The first electrode T of the fifth transistor 51 and the third electrode T of the sixth transistor 63 Electrically connected, the third electrode T of the fifth transistor 53 The second electrode T of the fifth transistor is grounded. 52 and the third electrode T of the seventh transistor 73 Electrically connected, the first electrode T of the sixth transistor 61 and the first electrode T of the seventh transistor 71 and the third electrode T of the seventh transistor 73 Electrical connection.
[0112] The self-starting module 2 is configured to: stop working in response to the bias module 1 working normally; and provide a driving current to the bias module 1 in response to the bias module 1 working abnormally, so that the bias module 1 works normally after starting.
[0113] Preferably, the fifth transistor T5 and the sixth transistor T6 are both N-channel metal-oxide-semiconductor field effect transistors, and the seventh transistor T7 is a P-channel metal-oxide-semiconductor field effect transistor;
[0114] The first electrode T of the fifth transistor 51 is the gate electrode of the fifth transistor T5, and the second electrode T 52 is the drain of the fifth transistor T5, and the third electrode T 53 is the source of the fifth transistor T5;
[0115] The first electrode T of the sixth transistor 61 is the gate electrode of the sixth transistor T6, and the second electrode T 62 is the drain of the sixth transistor T6, and the third electrode T 63 is the source of the sixth transistor T6;
[0116] The first electrode T of the seventh transistor 71 is the gate electrode of the seventh transistor T7, and the second electrode T 72 is the source of the seventh transistor T7, and the third electrode T 73 It is the source of the seventh transistor T7.
[0117] Figure 5 The circuit diagram of the self-starting bias circuit is shown. When the bias circuit starts normally, the first transistor T1 and the second transistor T2 are turned on, and the current flows to the third transistor T3 and the fourth transistor T4 through the first transistor T1 and the second transistor T2 respectively, and the third transistor T3 and the fourth transistor T4 are turned on, and the fifth transistor T5 is turned on. After the fifth transistor T5 is turned on, the gate voltage of the sixth transistor T6 is pulled down, so that the gate-source voltage of the sixth transistor T6 is less than its turn-on voltage. Therefore, the sixth transistor T6 is turned off, the startup circuit does not work, does not consume static current, and the bias module 1 of the self-starting bias circuit works normally to generate a bias current.
[0118] When the circuit is abnormally started, the gate potential of the fifth transistor T5 is 0, the fifth transistor T5 is turned off, and the gate potential of the seventh transistor T7 is the input voltage V DD The seventh transistor T7 is turned off; the gate potential of the sixth transistor T6 is high, and the sixth transistor T6 is turned on; the gate potentials of the first transistor T1 and the second transistor T2 are both low, the first transistor T1 and the second transistor T2 are turned on, and the current passes through the first transistor T1 and the second transistor T2 to the third transistor T3 and the fourth transistor T4 respectively. As the gate potential of the third transistor T3 increases, the third transistor T3 and the fourth transistor T4 are turned on, the bias module starts working, and generates a bias current.
[0119] After the bias module works normally, the fifth transistor T5 is turned on, so that the gate-source voltage of the sixth transistor T6 is less than its start-up voltage, the sixth transistor T6 is turned off, the self-starting module stops working, no longer affects the working state of the bias module, and does not consume static current.
[0120] The self-starting bias circuit provided in the embodiment of the present application uses three transistors to realize the function of the self-starting module, and the circuit structure is simple; since the number of components used is small, it is conducive to miniaturization of products using the self-starting bias circuit.
[0121] In other embodiments, a circuit board includes a self-starting bias circuit.
[0122] Specifically, the self-starting bias circuit includes a bias module 1 and a self-starting module 2;
[0123] The bias module 1 includes: a first voltage input terminal 1 i , the first current input terminal 1 i1 And the second current input terminal 1 i2 ;
[0124] The self-starting module 2 includes: a second voltage input terminal 2 i , the first current output terminal 2 o1 And the second current output terminal 2 o2 ;
[0125] First voltage input terminal 1 i The second voltage input terminal 2 i Electrical connection, first current output terminal 1 o1 With the first current input terminal 2 i1 Electrical connection, second current output terminal 1 o2 Electrically connected to the second current input terminal 2 i2 ;
[0126] The self-starting bias circuit is configured such that, in response to the bias module 1 working normally, the self-starting module 2 does not work; in response to the bias module 1 working abnormally, the self-starting module 2 provides a driving current to the bias module 1 so that the bias module 1 works normally after starting.
[0127] Furthermore, the bias module 1 includes: a first current mirror 11 and a second current mirror 12;
[0128] The first current mirror 11 includes: a first current mirror first port 111, a first current mirror second port 112, a first current mirror third port 113 and a first current mirror fourth port 114;
[0129] The second current mirror 12 includes: a second current mirror first port 121, a second current mirror second port 122, a second current mirror third port 123 and a second current mirror fourth port 124;
[0130] The first current mirror first port 111 and the first current mirror second port 112 are connected to the input voltage V DD The first current mirror third port 113 is electrically connected to the second current mirror first port 121 , the first current mirror fourth port 114 is electrically connected to the second current mirror second port 122 , and the second current mirror third port 123 and the second current mirror fourth port 124 are grounded.
[0131] Furthermore, the bias module 1 further includes: a first resistor R1, a second resistor R2 and a third resistor R3;
[0132] The first port 111 of the first current mirror is connected in series with the first resistor R1 and connected to the input voltage V DD ;
[0133] The second port 112 of the first current mirror is connected in series with the second resistor R2 and connected to the input voltage V DD ;
[0134] The third port 123 of the second current mirror is connected in series with the third resistor R3 and then grounded.
[0135] Further, the first current mirror 11 includes: a first transistor T1 and a second transistor T2;
[0136] The first transistor T1 includes: a first transistor first electrode T 11 , the second electrode T of the first transistor 12 and the third electrode T of the first transistor 13 ;
[0137] The second transistor T2 includes: a first electrode T 21 , the second transistor second electrode T 22 and the third electrode T of the second transistor 23 ;
[0138] The first transistor second electrode T 12 A first port 111 as a first current mirror;
[0139] The third electrode T of the first transistor 13 A third port 113 as a first current mirror;
[0140] The second transistor second electrode T 22 A second port 112 as a first current mirror;
[0141] The second transistor third stage T 23 A fourth port 114 as a first current mirror;
[0142] The first transistor first electrode T 11 The first electrode T of the second transistor 21 Electrically connected, the first transistor first electrode T 11 The third electrode T of the first transistor 13 Electrical connection.
[0143] Further, the first transistor T1 and the second transistor T2 are both P-channel metal-oxide-semiconductor field effect transistors;
[0144] The first transistor first electrode T 11 is the gate of the first transistor T1, and the second electrode T 12 is the source of the first transistor T1, and the third electrode of the first transistor T 13 is the drain of the first transistor T1;
[0145] The first electrode T of the second transistor 21 is the gate of the second transistor T2, and the second electrode T 22 is the source of the second transistor T2, and the third electrode T 23 is the drain of the second transistor T2.
[0146] Further, the second current mirror 12 includes: a third transistor T3 and a fourth transistor T4;
[0147] The third transistor T3 includes: a first electrode T 31 , the second electrode T of the third transistor 32 and the third electrode T of the third transistor 33 ;
[0148] The fourth transistor T4 includes: a first electrode T 41 , the second electrode T of the fourth transistor 42 and the third electrode T of the fourth transistor 43 ;
[0149] The second electrode T of the third transistor 32 A second port 122 as a second current mirror;
[0150] The third transistor third electrode T 33 A fourth port 124 as a second current mirror;
[0151] The second electrode T of the fourth transistor 42 A first port 121 as a second current mirror;
[0152] The fourth transistor third stage T 43 A third port 123 as a second current mirror;
[0153] The first electrode T of the third transistor 31 and the first electrode T of the fourth transistor 41 Electrically connected, the first electrode T of the third transistor 31 The second electrode T of the third transistor 32 Electrical connection.
[0154] Further, the third transistor T3 and the fourth transistor T4 are both N-channel metal-oxide-semiconductor field effect transistors;
[0155] The first electrode T of the third transistor 31 is the gate of the third transistor T3, and the second electrode T 32 is the drain of the third transistor T3, and the third electrode T 33 is the source of the third transistor T3;
[0156] The first electrode T of the fourth transistor 41 is the gate of the fourth transistor T4, and the second electrode T 42 is the drain of the fourth transistor T4, and the third electrode T 43 is the source of the fourth transistor T4.
[0157] Further, the self-starting module 2 includes: a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7;
[0158] The fifth transistor T5 includes: a first electrode T 51 , the second electrode T of the fifth transistor 52 and the third electrode T of the fifth transistor 53 ;
[0159] The sixth transistor T6 includes: a first electrode T 61 , the second electrode T of the sixth transistor 62 and the third electrode T of the sixth transistor 63 ;
[0160] The seventh transistor T7 includes: a first electrode T 71 , the second electrode T of the seventh transistor 72 and the third electrode T of the seventh transistor 73 ;
[0161] The first electrode T of the fifth transistor 51 As the second current output terminal 2 o2 , the second electrode T of the sixth transistor 62 As the first current output terminal 2 o1 , the second electrode T of the seventh transistor 72 As the second voltage input terminal 2 i ;
[0162] The first electrode T of the fifth transistor 51 and the third electrode T of the sixth transistor 63 Electrically connected, the third electrode T of the fifth transistor 53 The second electrode T of the fifth transistor is grounded. 52 and the third electrode T of the seventh transistor 73 Electrically connected, the first electrode T of the sixth transistor 61 and the first electrode T of the seventh transistor 71 and the third electrode T of the seventh transistor 73 Electrical connection.
[0163] Further, the fifth transistor T5 and the sixth transistor T6 are both N-channel metal-oxide-semiconductor field effect transistors, and the seventh transistor T7 is a P-channel metal-oxide-semiconductor field effect transistor;
[0164] The first electrode T of the fifth transistor 51 is the gate electrode of the fifth transistor T5, and the second electrode T 52 is the drain of the fifth transistor T5, and the third electrode T 53 is the source of the fifth transistor T5;
[0165] The first electrode T of the sixth transistor 61 is the gate electrode of the sixth transistor T6, and the second electrode T 62 is the drain of the sixth transistor T6, and the third electrode T 63 is the source of the sixth transistor T6;
[0166] The first electrode T of the seventh transistor 71 is the gate electrode of the seventh transistor T7, and the second electrode T 72 is the source of the seventh transistor T7, and the third electrode T 73 It is the source of the seventh transistor T7.
[0167] like Figure 6 As shown, the circuit board also includes an active component, and the self-starting bias circuit also includes a bias output port OUT. Usually, the second electrode of the third transistor is used as the bias output port OUT. The bias output port OUT is electrically connected to the active device 3 to provide a stable bias for the active component so that the active component works in a suitable working area.
[0168] Indicatively, Figure 7 FIG. 1 shows a case where the self-starting bias circuit provides bias for an active element. The active element 3 is a comparator in a low voltage dropout linear regulator. The bias input port 3 of the comparator B The bias output port OUT is electrically connected to the bias output port OUT.
[0169] By implementing the self-starting bias circuit and circuit board disclosed in the embodiment of the present application, when the circuit is abnormally started, the sixth transistor is turned on, while the fifth transistor and the seventh transistor are turned off, the first transistor and the second transistor are turned on, and the current flows through the first transistor and the second transistor to the fourth transistor and the third transistor respectively, the potential of the first electrode of the third transistor increases, and the third transistor and the fourth transistor are turned on, so that the bias circuit works to generate a bias current; after the bias circuit is normally started, the fifth transistor is turned on, so that the sixth transistor is turned off, and then the self-starting module is turned off, thereby reducing the power consumption of the circuit; the circuit structure is simple, which reduces the design difficulty; the circuit uses fewer components, saves the area occupied by the circuit, and thus reduces the space provided for reducing the volume of the product.
[0170] All the above optional technical solutions can be arbitrarily combined to form optional embodiments of the present application, which will not be described one by one here.
[0171] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made to those skilled in the art without departing from the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may also include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.
Claims
1. A self-starting bias circuit, characterized in that: Including bias module and self-starting module; The bias module includes: a first voltage input terminal, a first current input terminal and a second current input terminal; The self-starting module comprises: a second voltage input terminal, a first current output terminal and a second current output terminal; The first voltage input terminal is electrically connected to the second voltage input terminal, the first current output terminal is electrically connected to the first current input terminal, and the second current output terminal is electrically connected to the second current input terminal; The self-starting bias circuit is configured such that, in response to the bias module working normally, the self-starting module does not work; in response to the bias module working abnormally, the self-starting module provides a driving current to the bias module so that the bias module works normally after starting.
2. The self-starting bias circuit according to claim 1, characterized in that: The bias module includes: a first current mirror and a second current mirror; The first current mirror comprises: a first current mirror first port, a first current mirror second port, a first current mirror third port and a first current mirror fourth port; The second current mirror comprises: a second current mirror first port, a second current mirror second port, a second current mirror third port and a second current mirror fourth port; The first port of the first current mirror and the second port of the first current mirror are connected to an input voltage, the third port of the first current mirror and the first port of the second current mirror are electrically connected, the fourth port of the first current mirror and the second port of the second current mirror are electrically connected, and the third port of the second current mirror and the fourth port of the second current mirror are grounded.
3. The self-starting bias circuit according to claim 2, characterized in that: The bias module also includes a third resistor; The third port of the second current mirror is connected in series with the third resistor and then grounded.
4. The self-starting bias circuit according to claim 3, characterized in that: The bias module further includes: a first resistor and a second resistor; The first port of the first current mirror is connected in series with the first resistor and then connected to the input voltage; The second port of the first current mirror is connected in series with the second resistor and then connected to the input voltage.
5. The self-starting bias circuit according to any one of claims 2 to 4, characterized in that: The first current mirror comprises: a first transistor and a second transistor; The first transistor includes: a first transistor first electrode, a first transistor second electrode and a first transistor third electrode; The second transistor includes: a second transistor first electrode, a second transistor second electrode and a second transistor third electrode; The second electrode of the first transistor serves as the first port of the first current mirror; The third electrode of the first transistor serves as the third port of the first current mirror; The second electrode of the second transistor serves as the second port of the first current mirror; The third stage of the second transistor serves as the fourth port of the first current mirror; The first electrode of the first transistor is electrically connected to the first electrode of the second transistor, and the first electrode of the first transistor is electrically connected to the third electrode of the first transistor.
6. The self-starting bias circuit according to claim 5, characterized in that: The first transistor and the second transistor are both P-channel metal-oxide-semiconductor field effect transistors; The first electrode of the first transistor is the gate of the first transistor, the second electrode of the first transistor is the source of the first transistor, and the third electrode of the first transistor is the drain of the first transistor; The first electrode of the second transistor is the gate of the second transistor, the second electrode of the second transistor is the source of the second transistor, and the third electrode of the second transistor is the drain of the second transistor.
7. The self-starting bias circuit according to any one of claims 2 to 4, characterized in that: The second current mirror comprises: a third transistor and a fourth transistor; The third transistor includes: a third transistor first electrode, a third transistor second electrode and a third transistor third electrode; The fourth transistor includes: a fourth transistor first electrode, a fourth transistor second electrode and a fourth transistor third electrode; The second electrode of the third transistor serves as the second port of the second current mirror; The third electrode of the third transistor serves as the fourth port of the second current mirror; The second electrode of the fourth transistor serves as the first port of the second current mirror; The third stage of the fourth transistor serves as the third port of the second current mirror; The first electrode of the third transistor is electrically connected to the first electrode of the fourth transistor, and the first electrode of the third transistor is electrically connected to the second electrode of the third transistor.
8. The self-starting bias circuit according to claim 7, characterized in that: The third transistor and the fourth transistor are both N-channel metal-oxide-semiconductor field effect transistors; The first electrode of the third transistor is the gate of the third transistor, the second electrode of the third transistor is the drain of the third transistor, and the third electrode of the third transistor is the source of the third transistor; The first electrode of the fourth transistor is the gate of the fourth transistor, the second electrode of the fourth transistor is the drain of the fourth transistor, and the third electrode of the fourth transistor is the source of the fourth transistor.
9. The self-starting bias circuit according to claim 1, characterized in that: The self-starting module comprises: a fifth transistor, a sixth transistor and a seventh transistor; The fifth transistor comprises: a first electrode of a fifth transistor, a second electrode of a fifth transistor and a third electrode of a fifth transistor; The sixth transistor includes: a first electrode of a sixth transistor, a second electrode of a sixth transistor and a third electrode of a sixth transistor; The seventh transistor comprises: a first electrode of a seventh transistor, a second electrode of a seventh transistor and a third electrode of a seventh transistor; The first electrode of the fifth transistor serves as the second current output terminal, the second electrode of the sixth transistor serves as the first current output terminal, and the second electrode of the seventh transistor serves as the second voltage input terminal; The first electrode of the fifth transistor is electrically connected to the third electrode of the sixth transistor, the third electrode of the fifth transistor is grounded, the second electrode of the fifth transistor is electrically connected to the third electrode of the seventh transistor, and the first electrode of the sixth transistor is electrically connected to the first electrode of the seventh transistor and the third electrode of the seventh transistor; The self-starting module is configured as follows: in response to the bias module working normally, the self-starting module does not work; in response to the bias module working abnormally, the self-starting module provides a driving current to the bias module so that the bias module works normally after starting.
10. The self-starting bias circuit according to claim 9, characterized in that: The fifth transistor and the sixth transistor are both N-channel metal-oxide-semiconductor field effect transistors, and the seventh transistor is a P-channel metal-oxide-semiconductor field effect transistor; The first electrode of the fifth transistor is the gate electrode of the fifth transistor, the second electrode of the fifth transistor is the drain electrode of the fifth transistor, and the third electrode of the fifth transistor is the source electrode of the fifth transistor; The first electrode of the sixth transistor is the gate electrode of the sixth transistor, the second electrode of the sixth transistor is the drain electrode of the sixth transistor, and the third electrode of the sixth transistor is the source electrode of the sixth transistor; The first electrode of the seventh transistor is the gate of the seventh transistor, the second electrode of the seventh transistor is the source of the seventh transistor, and the third electrode of the seventh transistor is the source of the seventh transistor.