Overcurrent protection circuit applied to low-voltage input LDO (Low Dropout Regulator)

Abstract

The invention belongs to the technical field of integrated circuits, and particularly relates to an overcurrent protection circuit applied to a low-voltage input LDO (Low Dropout Regulator), which comprises a current sampling circuit, an operational amplifier circuit and a current comparison circuit, the current sampling circuit is used for sampling LDO load current and converting the LDO load current into a voltage signal; the operational amplifier circuit is used for ensuring the sampling accuracy and outputting a comparison signal; and the current comparison circuit is used for converting the comparison signal output by the operational amplifier circuit into a current signal, comparing the current signal with a reference current source, and limiting the current of the output power tube when the output of the LDO is over-current. The ports of the circuit output tube and the sampling tube are at the same potential during sampling, so that the circuit has the characteristics of accurate sampling and easiness in design, and has certain universality in circuit design.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits, and in particular relates to an overcurrent protection circuit applied to a low-voltage input LDO. Background Art

[0002] The overcurrent protection circuit is a common submodule of the low-dropout linear regulator (LDO) chip. When a high-power NMOS tube is used as the power output tube of the LDO, the output power tube is very easy to be broken down and burned when there is a current overload or output short circuit during operation. Therefore, the LDO needs an overcurrent protection function to limit the current of the output power tube, thereby protecting the LDO chip and the back-end load at the same time.

[0003] There are usually two problems in the existing common overcurrent protection circuit design applied to LDO: first, the current sampling is not accurate enough, and the sampling circuit has a certain degree of offset, resulting in large differences in the current limit value of the LDO under different application conditions; second, the sampling and processing of the output current signal usually requires additional comparator, reference and other modules, and in order to meet the low voltage difference requirements, an additional internal power supply is usually required, and the large circuit scale leads to high chip cost. Summary of the invention

[0004] In order to solve the above technical problems, the present invention provides an overcurrent protection circuit applied to a low voltage input LDO, characterized in that it comprises: a current sampling circuit, an operational amplifier circuit and a current comparison circuit;

[0005] The current sampling circuit is used to sample the LDO load current and convert it into a voltage signal;

[0006] The operational amplifier circuit is used to ensure the accuracy of sampling and output a comparison signal;

[0007] The current comparison circuit is used to convert the comparison signal output by the operational amplifier circuit into a current signal and compare it with a reference current source, so as to limit the current of the output power tube when the output of the LDO is overcurrent.

[0008] Beneficial effects of the present invention:

[0009] (1) When the output tube and the sampling tube of the circuit of the present invention are sampling, each port is at the same potential, and the current sampling accuracy is high;

[0010] (2) The circuit of the present invention has a dual power supply structure, and the power supply voltage required for operation is low;

[0011] (3) The circuit of the present invention requires less external bias, has a simple structure and is low in cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a circuit schematic diagram of the present invention;

[0013] Figure 2 It is a simulation schematic diagram of the change of waveform of key nodes of the circuit with load current under 0.35um BCD process of the present invention. DETAILED DESCRIPTION

[0014] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0015] like Figure 1 As shown, an embodiment of the present invention provides an overcurrent protection circuit applied to a low voltage input LDO, characterized in that it includes: a current sampling circuit, an operational amplifier circuit and a current comparison circuit;

[0016] The current sampling circuit is used to sample the LDO load current and convert it into a voltage signal;

[0017] The operational amplifier circuit is used to ensure the accuracy of sampling and output a comparison signal;

[0018] The current comparison circuit is used to convert the comparison signal output by the operational amplifier circuit into a current signal and compare it with the reference current source, so as to limit the current of the output power tube when the output of the LDO is overcurrent.

[0019] The current sampling circuit includes an operational amplifier A0, resistors R1-R2, and NMOS tubes N1-N3. The operational amplifier A0, resistors R1-R2, and NMOS tube N1 constitute the basic structure of LDO. The positive input end of the operational amplifier A0 is connected to the reference level VREF, and the output end is connected to the gate of the output power tube N1 and the sampling tube N2, which is named VG; the drain of N1 is connected to the first power supply VIN, and the source is connected to one end of the resistor R1, which serves as the output port LDOOUT of the LDO, which is named VP; the other end of R1 is connected to one end of R2 and connected to the negative input end of A0; the other end of R2 is grounded GND; the drain of the sampling tube N2 is connected to the first power supply VIN, and the source is connected to the drain of N3, which is named VM; the source of N3 is grounded GND.

[0020] The operational amplifier circuit includes PMOS tubes P1-P10, NMOS tubes N4-N8, bias current sources IBIAS1-IBIAS2, and bias voltage source VBIAS1. The sources of P1, P2, P3, and P4 are connected to a first power source VIN, the drain of P1 is connected to IBIAS1 and connected to the gates of P1, P2, P3, and P4 to form a current mirror structure;

[0021] The sources of P5 and P6 are connected to the second power supply VCP, the drain of P5 is connected to IBIAS2 and connected to the gates of P5 and P6 to form a current mirror structure; the drain of P6 is connected to the source of P7 and P8; the drain of P2 is connected to the source of P9 and P10; the gates of P7 and P10 are connected to VM and connected to the drain of N4; the gates of P8 and P9 are connected to VP; the drain of P3 is connected to the drain of N5 and is connected to the gates of N7 and N8; the drain of P4 is connected to the drain of N6 The drain is connected to the gate of N3 in the current sampling circuit, which is named VO; the gates of N4, N5, and N6 are connected to the bias voltage source VBIAS1; the source of N4 is grounded to GND; the drains of P7 and P10 are connected to the source of N5 and to the drain of N7; the drains of P8 and P9 are connected to the source of N6 and to the drain of N8; the sources of N7 and N8 are grounded to GND; P7-P10 and N4-N8 together constitute a folded common source and common gate structure.

[0022] The current comparison circuit includes PMOS tubes P11-P12, NMOS tubes N9-N13, a reference current source IREF, and a bias voltage source VBIAS2. The drain of N9 is connected to a first power source VIN; the gates of N9 and N10 are connected to the bias voltage source VBIAS2; the source of N9 is connected to the gate of N11 and connected to VO; the sources of P11 and P12 are connected to the first power source VIN, and the gates of P11 and P12 are connected to the drain of P11 and the drain of N10; the source of N10 is connected to the drain of N11 and connected to the reference current source VREF; the source of N11 is grounded GND; the drain of P12 is connected to the drain of N12, the gate of N12, and the gate of N13; the sources of N12 and N13 are grounded GND; the drain of N13 is connected to VG in the current sampling circuit.

[0023] The principle of the present invention is as follows:

[0024] In the current sampling circuit of the present invention, the operational amplifier A0, resistors R1-R2, and NMOS tube N1 represent the basic structure of LDO, where N1 is the output power tube of LDO. Ignoring the offset in the circuit, the operational amplifier circuit of the subsequent stage clamps the VP and VM points to the same voltage, that is, it can be considered that VP = VM in the normal working state of LDO without overcurrent. Assuming that the width-to-length ratio of N1 and N2 is N1:N2 = m:1 (m is the first positive integer), the load current of LDO is I load , we can get the current of sampling tube N2 at this time:

[0025]

[0026] Among them, I N2 is the current flowing through the sampling tube N2.

[0027] Since the gate, source and drain voltages of the sampling tube N2 and the power tube N1 in this structure are the same, N2 can perform accurate current sampling.

[0028] In the operational amplifier circuit of the present invention, P7, P8, P9, and P10 form a dual-path input structure, wherein the gates of P7 and P10 serve as the positive input terminal VM of the operational amplifier, and the gates of P8 and P9 serve as the negative input terminal VP of the operational amplifier. The operational amplifier is powered by two power supplies, a first power supply VIN and a second power supply VCP, wherein the first power supply VIN is usually the power supply of the chip, and the second power supply VCP is usually the internal power supply generated by the charge pump inside the chip. The LDO with NMOS as the output power tube usually has a charge pump module inside, so the circuit has certain versatility. IBIAS1 and IBIAS2 provide bias current for the dual-path input respectively. When the circuit works under a higher power supply, the dual-path input structure composed of P7, P8, P9, and P10 starts working at the same time; when the circuit works under a lower power supply, VCP>VIN, VIN is not enough to provide sufficient voltage difference for P9 and P10, VCP supplies power to the input terminal composed of P7 and P8, and the operational amplifier circuit switches to a single-path input mode to continue working. P7, P8, P9, P10, N5, N6, N7, and N8 form a folded common source and common gate structure of the op amp, which provides a higher gain while increasing the swing of the op amp, so that it can work normally under a lower power supply VIN. The gates of N4, N5, and N6 are driven by a suitable bias voltage VBIAS1, where the function of N4 is to generate a suitable voltage at the drain, i.e., the positive input terminal VP of the operational amplifier, before the output of the LDO is established or when the LDO is unloaded, so as to improve the establishment speed and detection accuracy of the overcurrent detection after the LDO load is established.

[0029] The working principle of the operational amplifier circuit is as follows: When the load current I load When it increases, the gate voltage VG of N1 and N2 increases, and the current I N2 The source voltage VM of N2 tends to increase. VP, as the output terminal of LDO, is considered to remain unchanged when the LDO load changes. Therefore, the increase of VM will cause the drain voltage of P7 and P10 to decrease, and the drain voltage of P8 and P9 to increase, thereby causing the output VO of the operational amplifier to increase. The increase of VO will be fed back to the N3 tube in the current sampling circuit to increase its conduction degree, so that VM tends to decrease, thereby realizing the clamping effect of the operational amplifier on VP and VM.

[0030] In the current comparison circuit of the present invention, the bias voltage VBIAS2 provides a bias for the gates of N9 and N10, and turns on N9 before the output VO of the operational amplifier is established, so that VO has an initial voltage, thereby improving the establishment speed and detection accuracy of overcurrent detection. N10 works as a switch tube. IREF is the maximum I REF When the LDO is in a non-overcurrent state, the output VO of the operational amplifier is low, N11 is turned on and works in the saturation region, and the current flowing through N11 can be obtained:

[0031]

[0032] Among them, I N11 is the current flowing through N11, μ n is the electron mobility, C ox is the oxide layer capacitance, W N11 is the channel width of N11, L N11 is the channel length of N11, V GSN11 is the gate-source voltage of N11, V TH is the threshold voltage of the MOS tube, and VO is the voltage at the VO point.

[0033] From formula (2), we can know that as the voltage of the operational amplifier output VO increases, the current flowing through N11 will increase accordingly. When VO continues to rise until it exceeds the maximum current I that IREF can provide REF When the reference current source IREF is insufficient to continue to provide sufficient current for N11, N10 is turned on and P11 continues to provide additional current for N11. At this time, the current of P11 is copied to N13 by the current mirror structure composed of P11, P12, N12, and N13, so that it has a tendency to flow through the current, thereby pulling the VG point to a low level, thereby limiting the output current of the LDO output power tube N1 and realizing the overcurrent protection function.

[0034] In the current sampling circuit, the N3 tube works in the saturation region, and its current can be obtained as:

[0035]

[0036] Among them, I N3 is the current flowing through N3, I N2 is the current flowing through N2, W N3 is the channel width of N3, L N3 is the channel length of N3, V GSN3 is the gate-source voltage of N3;

[0037] Assume that the width-to-length ratio of N3 and N11 is N3:N11=n:1 (n is the second positive integer), that is:

[0038]

[0039] Combining formulas (2), (3) and (4), we can get the current I of N11: N11 for:

[0040]

[0041] And it is assumed that when the current of N11 is equal to I REF When is the detection flip threshold of the overcurrent protection circuit, that is:

[0042] I N11 =I REF (6)

[0043] Combining formulas (1), (3), (5), and (6), we can get the output current limit of the LDO: LIM for:

[0044] I LIM =m·n·I REF (7)

[0045] It can be obtained from formula (7) that the output current limit value of the overcurrent protection circuit of the present invention for the LDO is only related to the width-to-length ratio of N1, N2 and N3, N11, and has the characteristics of accurate sampling and easy design, and has certain versatility in circuit design.

[0046] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. An overcurrent protection circuit applied to a low voltage input LDO, characterized in that: include: Current sampling circuit, operational amplifier circuit and current comparison circuit; The current sampling circuit is used to sample the LDO load current and convert it into a voltage signal; The operational amplifier circuit is used to ensure the accuracy of sampling and output a comparison signal; The current comparison circuit is used to convert the comparison signal output by the operational amplifier circuit into a current signal and compare it with a reference current source, so as to limit the current of the output power tube when the output of the LDO is overcurrent.

2. The overcurrent protection circuit for low voltage input LDO according to claim 1, characterized in that: The current sampling circuit includes: an operational amplifier A0, resistors R1-R2, and NMOS tubes N1-N3; The positive input terminal of operational amplifier A0 is connected to the reference level VREF, and the output terminal is connected to the gate of NMOS tubes N1 and N2, which is named VG; The drain of the NMOS tube N1 is connected to the first power source VIN, and the source is connected to one end of the resistor R1, serving as the output port LDOOUT of the LDO, which is named VP; The other end of the resistor R1 is connected to one end of the resistor R2 and to the negative input end of the operational amplifier A0; the other end of the resistor R2 is grounded GND; The drain of the NMOS tube N2 is connected to the first power source VIN, and the source is connected to the drain of the NMOS tube N3, which is named VM; The source of the NMOS tube N3 is grounded GND and connected to the operational amplifier circuit and the current comparison circuit; The gate of the NMOS tube N3 is connected to a current comparison circuit; The drains of the NMOS tubes N1 and N2 are also connected to the operational amplifier circuit and the current comparison circuit; VP, VM, and GND are connected to the operational amplifier circuit.

3. The overcurrent protection circuit for low voltage input LDO according to claim 2, characterized in that: The operational amplifier A0, resistors R1-R2, and NMOS tube N1 constitute the basic circuit structure of LDO.

4. The overcurrent protection circuit for low voltage input LDO according to claim 1, characterized in that: The operational amplifier circuit includes: PMOS tubes P1-P10, NMOS tubes N4-N8, bias current sources IBIAS1-IBIAS2, and bias voltage source VBIAS1; The sources of the PMOS tubes P1, P2, P3, and P4 are connected to the first power supply VIN, the current sampling circuit, and the current comparison circuit; The drain of the PMOS tube P1 is connected to the bias current source IBIAS1 and is connected to the gates of the PMOS tubes P1, P2, P3, and P4 to form a current mirror structure; The sources of the PMOS transistors P5 and P6 are connected to the second power supply VCP, the drain of the PMOS transistor P5 is connected to the bias current source IBIAS2 and connected to the gates of the PMOS transistors P5 and P6 to form a current mirror structure; The drain of the PMOS tube P6 is connected to the sources of the PMOS tubes P7 and P8; The drain of the PMOS tube P2 is connected to the sources of the PMOS tubes P9 and P10; The gates of the PMOS tubes P7, P8, P9, and P10 are connected to a current sampling circuit; The gates of the PMOS tubes P7 and P10 are connected to the drain of the NMOS tube N4; The drain of the PMOS tube P3 is connected to the drain of the NMOS tube N5, and is also connected to the gates of the NMOS tubes N7 and N8; The drain of the PMOS tube P4 is connected to the drain of the NMOS tube N6, and is connected to the current sampling circuit and the current comparison circuit, which are named VO; The gates of NMOS tubes N4, N5, and N6 are connected to a bias voltage source VBIAS1; The source of the NMOS tube N4 is grounded to GND, a current sampling circuit and a current comparison circuit; The drains of the PMOS tubes P7 and P10 are connected to the source of the NMOS tube N5 and to the drain of the NMOS tube N7; The drains of the PMOS tubes P8 and P9 are connected to the source of the NMOS tube N6 and to the drain of the NMOS tube N8; The source electrodes of the NMOS tubes N7 and N8 are grounded to GND, a current sampling circuit and a current comparison circuit; The PMOS transistors P7-P10 and the NMOS transistors N4-N8 together form a folded cascode structure.

5. The overcurrent protection circuit for low voltage input LDO according to claim 1, characterized in that: The current comparison circuit includes PMOS tubes P11-P12, NMOS tubes N9-N13, a reference current source IREF, and a bias voltage source VBIAS2; The drain of the NMOS tube N9 is connected to the first power supply VIN, the current sampling circuit and the operational amplifier circuit; The gates of NMOS tubes N9 and N10 are connected and connected to a bias voltage source VBIAS2; The source of the NMOS tube N9 is connected to the gate of the NMOS tube N11, and is connected to the current sampling circuit and the operational amplifier circuit; The sources of the PMOS tubes P11 and P12 are connected to the first power source VIN, the current sampling circuit and the operational amplifier circuit, and the gates of the PMOS tubes P11 and P12 are connected to the drain of the PMOS tube P11 and the drain of the NMOS tube N10; The source of the NMOS tube N10 is connected to the drain of N11 and is also connected to the reference current source VREF; The source of the NMOS tube N11 is grounded to GND, a current sampling circuit and an operational amplifier circuit; The drain of the PMOS tube P12 is connected to the drain of the NMOS tube N12, the gate of N12 and the gate of N13; The source electrodes of the NMOS tubes N12 and N13 are grounded to GND, a current sampling circuit and an operational amplifier circuit; The drain of the NMOS tube N13 is connected to the current sampling circuit.

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