Method and device for realizing display switching of front VGA and rear VGA of server based on CPLD and BMC

Abstract

The invention discloses a device for realizing display switching of a front VGA (Video Graphics Array) and a rear VGA of a server based on a CPLD (Complex Programmable Logic Device) and a BMC (Baseboard Management Controller), the BMC communicates with the CPLD through the IIC to realize remote switching control; the front VGA interface and the rear VGA interface are respectively connected with the VGA R / G / B one-to-two Switch chip and are used for accessing a display; the VGA R / G / B one-to-two Switch chip is used for receiving a level signal of the CPLD and realizing display switching of a front VGA and a rear VGA; the MOS switch is used for converting the two groups of IIC data signals SDA after level conversion through a pull-up resistor and then respectively connecting the two groups of IIC data signals SDA to a GPIO0 interface and a GPIO1 interface of the CPLD; and the switch button is connected with a GPIO4 port of the CPLD and is used for controlling switching enabling of R1 / G1 / B1 and R2 / G2 / B2 signals. Free switching of front and rear VGA display is achieved through simple hardware circuit design, and when the two displays are connected at the same time, one display can be supported through software detection or hardware switch selection; and meanwhile, the switching stability of the front VGA and the rear VGA is ensured through the dual redundancy design of a hardware circuit

Description

Technical Field

[0001] The present invention relates to the technical field of server management, and in particular to a method and device for switching front and rear VGA displays of a server. Background Art

[0002] As society continues to develop and progress, servers play a vital role in all walks of life. At present, some servers only have one VGA interface display, which is inconvenient for technicians to maintain on site; although some servers have front and rear VGA interface display functions, connecting two VGA monitors at the same time may cause no display.

[0003] Therefore, there is an urgent need for a method and device for switching the front and rear VGA displays of a server, which can realize free switching of VGA displays through simple hardware circuit design. Summary of the invention

[0004] In order to solve the problems in the prior art, the present invention proposes a method and device for realizing front and rear VGA display switching of a server based on CPLD and BMC.

[0005] The present invention is specifically implemented through the following technical solutions:

[0006] A device for realizing front and rear VGA display switching of a server based on CPLD and BMC, the device comprising a complex programmable logic device CPLD, a baseboard control management chip BMC, a VGA R / G / B one-to-two switch chip, a switch button, a MOS switch, a front VGA interface and a rear VGA interface;

[0007] Among them, CPLD is used to determine whether the front VGA is in place, and output the corresponding level signal according to the judgment result; BMC communicates with CPLD through IIC to realize remote switching control of front and rear VGA display; the front VGA interface and the rear VGA interface are respectively connected to the VGA R / G / B one-to-two Switch chip for accessing the display; the VGAR / G / B one-to-two Switch chip is used to receive the level signal of CPLD to realize the signal switching of the front VGA and rear VGA; the MOS switch is used to connect the two groups of IIC data signals SDA after level conversion to the GPIO0 and GPIO1 interfaces of the CPLD respectively after conversion by pull-up resistors; the switch button is connected to the GPIO4 port of the CPLD to control the switching enable of the R1 / G1 / B1 and R2 / G2 / B2 signals.

[0008] As a further improvement of the present invention, the IIC signal led out by the BMC chip is connected to the front and rear VGA interfaces respectively through the VGA R / G / B one-to-two Switch chip, and the two groups of IIC data signal SDA pull-up resistors after level conversion are connected to the GPIO0 and GPIO1 interfaces of the CPLD respectively through MOS tube conversion, as display access in-place signals; the digital grounds of the front VGA and the rear VGA are also connected to the GPIO2 and GPIO3 interfaces of the CPLD respectively, also as display access in-place signals; at the same time, the R / G / B Select signal is led out from the GPIO4 port of the CPLD through two switch buttons to the VGAR / G / B one-to-two Switch chip, as R1 / G1 / B1 and R2 / G2 / B2 signal switching enable.

[0009] As a further improvement of the present invention, the two switch buttons can be front-mounted ear-hanging button switches; the hardware design of the front-mounted ear-hanging button switch is also designed as a redundant fault-tolerant design, and the R1 / G1 / B1 and R2 / G2 / B2 signal switching is enabled by opening and closing the front-mounted ear-hanging button switches 1 and 2.

[0010] As a further improvement of the present invention, the CPLD is connected to the VGAR / G / B one-to-two Switch chip through the front ear button switch 2 and the front ear button switch 1 in sequence; when the front ear button switch 2 is disconnected and the front ear button switch 1 is closed, the front VGA display is realized; when the front ear button switch 2 is disconnected and the front ear button switch 1 is disconnected, the rear VGA display is realized.

[0011] As a further improvement of the present invention, when the VGA control flag VGA_FLAG is 0, the CPLD takes over the VGA front and rear switching control:

[0012] If GPIO0 or GPIO2 is low level, the GPIO4 interface outputs low level and the front VGA is displayed;

[0013] If GPIO0 or GPIO2 is low level, GPIO1 or GPIO3 is low level, then GPIO4 interface outputs low level, and the front VGA is displayed;

[0014] If GPIO0 and GPIO2 are high level, and GPIO1 or GPIO3 is low level, the GPIO4 interface outputs high level and the rear VGA is displayed.

[0015] As a further improvement of the present invention, when the VGA control flag VGA_FLAG is 1, the BMC takes over the VGA front and back switching control:

[0016] When the front VGA is in place and VGA_Select is 0, the GPIO4 interface outputs a low level and the front VGA is displayed;

[0017] When the rear VGA is in place and VGA_Select is 1, the GPIO4 interface outputs a high level and the rear VGA is displayed.

[0018] As a further improvement of the present invention, when the CPLD analysis is abnormal and the front and rear VGA interfaces cannot be switched normally, the front ear button switch 2 is disconnected, and the front and rear VGA interfaces are switched by opening or closing the front ear button switch 1.

[0019] The beneficial effects of the present invention are as follows: compared with the existing technology, the present invention can realize free switching of VGA displays through simple hardware circuit design, and when two displays are connected at the same time, software detection or hardware switch can be used to select and support one of the displays for display; at the same time, the dual redundant design of the hardware circuit greatly improves the fault tolerance rate and ensures the stability of the front and rear VGA switching; the circuit is simple and the cost is low. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The circuit design diagram of the device for realizing the front and rear VGA display switching of the server based on CPLD and BMC of the present invention;

[0021] Figure 2 The present invention is a working principle diagram of a device for realizing front and rear VGA display switching of a server based on CPLD and BMC. DETAILED DESCRIPTION

[0022] The present invention is further described below in conjunction with the accompanying drawings and specific implementation methods.

[0023] The device for realizing front and rear VGA display switching of a server based on CPLD and BMC comprises a complex programmable logic device CPLD, a baseboard control management chip BMC, a VGA R / G / B one-to-two switch chip, a switch button, a MOS switch, a front VGA interface and a rear VGA interface.

[0024] Among them, CPLD is used to determine whether the front VGA is in place and output the corresponding level signal according to the judgment result; BMC communicates with CPLD through IIC to realize remote switching control of front and rear VGA display; the front VGA interface and the rear VGA interface are respectively connected to the VGA R / G / B one-to-two Switch chip for accessing the display; the VGAR / G / B one-to-two Switch chip is used to receive the level signal of CPLD to realize the signal switching of the front VGA and rear VGA; the switch button is connected to the GPIO4 port of CPLD to control the switching enable of R1 / G1 / B1 and R2 / G2 / B2 signals.

[0025] like Figure 1 As shown, the hardware circuit design of the present invention includes:

[0026] The IIC signals (including serial data line (SDA) signals and serial clock line (SCL) signals) derived from the baseboard management control BMC chip (taking the AST2600 chip as an example) are respectively connected to the front and rear VGA interfaces through the VGA R / G / B one-to-two Switch chip (taking the PI3V713-A chip as an example), and the two groups of IIC data signal SDA pull-up resistors after level conversion are respectively connected to the GPIO0 and GPIO1 interfaces of the CPLD through MOS tube conversion as display access in-place signals.

[0027] The front VGA and rear VGA pins PIN10 (digital ground) are also connected to the GPIO2 and GPIO3 interfaces of the CPLD respectively, which also serve as display access in-place signals.

[0028] At the same time, the R / G / B Select signal is led out from the GPIO4 port of the CPLD through two switch buttons (closed by default) to the VGA R / G / B one-to-two Switch chip as the R1 / G1 / B1 and R2 / G2 / B2 signal switching enable. The two switch buttons can be front-mounted ear button switches.

[0029] The hardware design of the front hanging ear button switch is also a redundant fault-tolerant design. The front hanging ear button switches 1 and 2 can be opened and closed to control the switching of R1 / G1 / B1 and R2 / G2 / B2 signals. The dual redundant design of the hardware circuit greatly improves the fault tolerance rate and ensures the stability of the front and rear VGA switching. Specifically, the CPLD is connected to the VGA R / G / B one-to-two Switch chip through the front hanging ear button switch 2 and the front hanging ear button switch 1 in turn. When the front hanging ear button switch 2 is disconnected and the front hanging ear button switch 1 is closed, the display connected to the front VGA interface works (referred to as the front VGA display); when the front hanging ear button switch 2 is disconnected and the front hanging ear button switch 1 is disconnected, the display connected to the rear VGA interface works (referred to as the rear VGA display).

[0030] Similarly, in remote management, the BMC communicates with the motherboard CPLD through IIC (Inter-Integrated Circuit) to achieve remote switching of the front and rear VGA.

[0031] Combination Figure 2 The front and rear VGA switching principle of the present invention is introduced as follows:

[0032] (1) BMC remotely manages and issues commands through the web, and communicates with CPLD through IIC. When the VGA control flag VGA_FLAG transmitted by BMC to CPLD is 1, BMC takes over the control of VGA front and rear switching, and switches the front and rear VGA through the VGA_select level in the IIC register; when VGA_FLAG is 0, CPLD takes over the control of VGA front and rear switching.

[0033] (2) When the VGA control flag VGA_FLAG is 0, the CPLD takes over the VGA front and back switching control, including:

[0034] 1. If GPIO0 or GPIO2 is low level, the GPIO4 interface outputs low level and the front VGA is displayed;

[0035] If GPIO0 or GPIO2 is low level, GPIO1 or GPIO3 is low level, the GPIO4 interface outputs low level and the front VGA is displayed.

[0036] 2. If GPIO0 and GPIO2 are high level and GPIO1 or GPIO3 is low level, the GPIO4 interface will output high level and the rear VGA will be displayed.

[0037] (3) When the VGA control flag VGA_FLAG is 1, the BMC takes over the control of VGA front and rear switching:

[0038] BMC obtains the information of the front and rear VGA in place through IIC. When the front VGA is in place and VGA_select is 0, the CPLDGPIO4 interface outputs a low level and the front VGA is displayed; when the rear VGA is in place and VGA_select is 1, the CPLD GPIO4 interface outputs a high level and the rear VGA is displayed.

[0039] CPLD switches front and rear VGA principle:

[0040] (1) When the VGA control flag VGA_FLAG is 0, the CPLD takes over the VGA front and rear switching control:

[0041] By default, the rear VGA is connected to the monitor, that is, the VGA R / G / B one-to-two Switch chip enable pin Select is set to high level by default to make it work normally. The CPLD will refresh every 200us to detect whether the front and rear VGA are connected to the monitor. When CPLD detects that the level of the front VGA clock signal SDA after conversion by the MOS switch is low, that is, GPIO0 is low, or the front VGA PIN10 is low, that is, GPIO2 is low, the front VGA R2 / G2 / B2 channel is turned on, that is, the VGA R / G / B one-to-two Switch chip enable pin Select is low, that is, the CPLD GPIO4 interface outputs a low level; when the rear VGA display is connected, CPLD detects that the level of the rear VGA clock signal SDA after conversion by the MOS switch is low, that is, GPIO1 is low, or the rear VGA PIN10 is low, that is, GPIO4 is low, CPLD will first detect whether the front VGA display is in place. If the front VGA display is in place, the front VGA display is maintained. Otherwise, the front VGA R1 / G1 / B1 channel is turned on, that is, the VGA R / G / B one-to-two Switch chip enable pin Select is high, that is, the CPLD The GPIO4 interface outputs a high level, and the rear VGA display can display normally. As long as one of the two in-position signals meets the conditions, the front and rear VGA displays can be switched freely, and the redundant design improves the fault tolerance rate.

[0042] (2) When the VGA control flag VGA_FLAG is 1, the BMC takes over the control of VGA front and rear switching:

[0043] By default, the rear VGA is connected to the display, that is, the default VGA R / G / B one-to-two Switch chip enable pin Select is high to make it work normally. The CPLD will refresh every 200us to detect whether the front and rear VGA are connected to the display. The CPLD detects that the level of the front VGA clock signal SDA after the MOS switch conversion is low, that is, GPIO0 is low, or the front VGAPIN10 is low, that is, GPIO2 is low; when the rear VGA display is connected, the CPLD detects that the level of the rear VGA clock signal SDA after the MOS switch conversion is low, that is, GPIO1 is low, or the rear VGA PIN10 is low, that is, GPIO3 is low. The BMC communicates with the CPLD through IIC to obtain the information of the front and rear displays in place. When the front VGA is in place and VGA_select is 0, the CPLD GPIO4 interface outputs a low level, and the front VGA is displayed; when the rear VGA is in place and VGA_select is 1, the CPLD GPIO4 interface outputs a high level, and the rear VGA is displayed. When the front and rear monitors are connected at the same time, the BMC can also flexibly switch the front and rear VGA displays through VGA_select.

[0044] (3) When the CPLD logic chip analysis is abnormal and the front and rear VGA interfaces cannot be switched normally, the front mounting ear button switch 2 can be disconnected, and the front and rear VGA interfaces can be switched by disconnecting or closing the front mounting ear button switch 1. The redundant design improves the fault tolerance rate.

[0045] The dual redundant design of the hardware circuit of the present invention greatly improves the fault tolerance rate and ensures the switching stability of the front and rear VGAs.

[0046] The above description is only a preferred embodiment of the present invention, and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention. For ordinary technicians in this field, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as belonging to the protection scope of the present invention.

Claims

1. A device for switching between front and rear VGA displays of a server based on CPLD and BMC, characterized in that: The device includes: a complex programmable logic device (CPLD), a baseboard control and management chip (BMC), a VGA R / G / B one-to-two switch chip, a switch button, a MOS switch, a front VGA interface, and a rear VGA interface; Among them, the CPLD is used to determine whether the front VGA is in place and output the corresponding level signal based on the judgment result; the BMC communicates with the CPLD through the IIC to realize remote switching control of the front and rear VGA displays; the front VGA interface and the rear VGA interface are respectively connected to the VGA R / G / B one-to-two switch chip for accessing the display; the VGA R / G / B one-to-two switch chip is used to receive the level signal from the CPLD to realize signal switching between the front VGA and rear VGA; the MOS switch is used to convert the two sets of IIC data signals SDA after level conversion through pull-up resistors and connect them to the GPIO0 and GPIO1 interfaces of the CPLD respectively; the switch button is connected to the GPIO4 port of the CPLD to control the switching enable of the R1 / G1 / B1 and R2 / G2 / B2 signals.

2. The device according to claim 1, wherein The IIC signal derived from the BMC chip is connected to the front and rear VGA interfaces respectively through the VGA R / G / B one-to-two Switch chip, and the two sets of IIC data signal SDA pull-up resistors after level conversion are connected to the GPIO0 and GPIO1 interfaces of the CPLD respectively through MOS tube conversion, as display access in place signals; the digital grounds of the front VGA and rear VGA are also connected to the GPIO2 and GPIO3 interfaces of the CPLD respectively, also as display access in place signals; at the same time, the R / G / B Select signal is derived from the GPIO4 port of the CPLD and passed through two switch buttons to the VGA R / G / B one-to-two Switch chip, as the R1 / G1 / B1 and R2 / G2 / B2 signal switching enable.

3. The device according to claim 2, wherein The two switch buttons are front-mounted ear button switches; the hardware design of the front-mounted ear button switch is also a redundant fault-tolerant design, and the R1 / G1 / B1 and R2 / G2 / B2 signal switching is controlled by opening and closing the front-mounted ear button switches 1 and 2.

4. The device according to claim 3, wherein The CPLD is connected to the VGA R / G / B one-to-two switch chip through front mounting ear button switch 2 and front mounting ear button switch 1 in sequence.

5. The device according to claim 2, wherein When the VGA control flag VGA_FLAG is 0, the CPLD takes over the control of VGA front and rear switching: If GPIO0 or GPIO2 is low, the GPIO4 interface outputs a low level and the front VGA is displayed; If GPIO0 or GPIO2 is low level, GPIO1 or GPIO3 is low level, then GPIO4 interface outputs low level and front VGA is displayed; If GPIO0 and GPIO2 are high and GPIO1 or GPIO3 is low, the GPIO4 interface outputs a high level and the rear VGA display is used.

6. The device according to claim 2, wherein When the VGA control flag VGA_FLAG is 1, the BMC takes over the control of VGA front and rear switching: When the front VGA is in place and VGA_select is 0, the GPIO4 interface outputs a low level and the front VGA is displayed; When the rear VGA is in place and VGA_select is 1, the GPIO4 interface outputs a high level and the rear VGA is displayed.

7. The device according to claim 3 or 4, wherein: When the CPLD parsing is abnormal and the front and rear VGA interfaces cannot be switched normally, disconnect the front mounting ear button switch 2 and switch the front and rear VGA interfaces by disconnecting or closing the front mounting ear button switch 1.

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