Static time sequence analysis method and device based on layout characteristics and electronic equipment

Abstract

The embodiment of the invention discloses a static time sequence analysis method and device based on layout features and electronic equipment. According to the scheme, the gate-level netlist of the circuit can be obtained, the time sequence diagram is established according to the gate-level netlist, the nodes and the directed edges in the time sequence diagram are filled with the first statistical characteristics respectively, the first layout characteristics of each connection network in the time sequence diagram are calculated, and the time sequence diagram is expanded according to the first layout characteristics; and constructing a static time sequence analysis prediction model based on the graph neural network and the convolutional neural network, and predicting the delay of a connecting line time sequence arc, the delay of a logic gate time sequence arc and the delay of a pin node in the expanded time sequence diagram, thereby determining a static time sequence analysis result. According to the method, the layout characteristics of the circuit are obtained by extracting and coding the nodes of the connection network, and the static time sequence analysis prediction model is modeled according to the layout characteristics, so that the prediction accuracy of the prediction model in the layout areas with different aspect ratios is improved.

Description

Technical Field

[0001] The present application relates to the technical field of timing analysis, and in particular to a static timing analysis method, device and electronic device based on layout features. Background Art

[0002] The design of digital integrated circuits must meet certain timing relationships, otherwise the circuit design will not achieve the expected results. The main function of timing analysis is to verify whether the designer's constraints are met based on the delay of the circuit's internal logic and wiring. Timing analysis includes dynamic timing analysis and static timing analysis. Dynamic timing analysis, also known as simulation, has a huge scale of test vectors for dynamic timing analysis and may have incomplete test vectors, which ultimately consumes a lot of development resources and cannot expose all timing problems. The advantage of static timing analysis is that it can exhaust all paths without inputting test vectors, can perform comprehensive timing function checks on circuit designs, and can use the results of timing analysis to optimize processes such as synthesis and placement and routing in the EDA process. Static timing analysis has been increasingly used in the design of digital integrated circuits.

[0003] The existing static timing analysis prediction method is to model the input circuit as a directed acyclic graph, annotate the statistical characteristics of logic gates on the nodes and edges of the graph, use a statistical machine learning model to predict the delay of the connecting wires and logic gates, and accumulate the delays to obtain a static timing analysis prediction for the entire circuit. However, in actual applications, the applicant found that the existing static timing analysis prediction method did not consider the impact of the aspect ratio of the layout area, but simply made predictions based on the statistical characteristics of the logic gates and connecting wires. The prediction accuracy in the layout area scenario with a special aspect ratio is poor. Summary of the invention

[0004] The present application provides a static timing analysis method, device and electronic device based on layout features. The layout features of the circuit are obtained by extracting and encoding the connection network nodes, and a static timing analysis prediction model is modeled according to the layout features, thereby improving the prediction accuracy of the prediction model in layout areas with different aspect ratios.

[0005] The present application provides a static timing analysis method based on layout features, including:

[0006] Obtaining a gate-level netlist of the circuit, and establishing a timing diagram according to the gate-level netlist;

[0007] Filling first statistical features into nodes and directed edges in the timing graph respectively, calculating first layout features of each connection network in the timing graph, and expanding the timing graph according to the first layout features;

[0008] A static timing analysis prediction model is built based on graph neural networks and convolutional neural networks, and the delay of the connection line timing arc, the delay of the logic gate timing arc, and the delay of the pin node in the expanded timing diagram are predicted;

[0009] The static timing analysis result is determined by the delay of the connection line timing arc, the delay of the logic gate timing arc and the delay of the pin node.

[0010] Optionally, the timing graph is a directed acyclic graph, the nodes are circuit ports or logic gate pins, the directed edges are connection line timing arcs or logic unit timing arcs, and the nodes and directed edges in the timing graph are respectively filled with the first statistical feature, including:

[0011] Filling the nodes in the timing graph with two-dimensional coordinate information, fan-out number information of the corresponding connection network, and timing path endpoint information;

[0012] The directed edges in the timing diagram are filled with the distance information between the driver and the load in the connection line timing arc and the lookup table corresponding to the nonlinear delay model timing library in the logic unit timing arc.

[0013] Optionally, calculating the first layout feature of each connection net in the timing diagram includes:

[0014] Dividing the layout area into a plurality of densely packed connection nets in the timing diagram;

[0015] The RUDY of the circuit is calculated according to the plurality of connection nets by the following formula:

[0016]

[0017] Where RUDY(x,y) represents the rectangular uniform line density feature on the grid with coordinates (x,y), n is the connection network number, and HPWL n is the half-circumference length of the connecting network, w n and h n are the width and height of the bounding box of the connection network, and are the coordinates of the lower left corner of the bounding box of the connection network.

[0018] Optionally, expanding the timing diagram according to the first layout feature includes:

[0019] For each connection net, a connection net node is added according to the corresponding first layout feature, and an undirected edge is established between the connection net node and a circuit port or logic gate pin associated with the current connection net.

[0020] Optionally, after expanding the timing diagram according to the first layout feature, the method further includes:

[0021] For the expanded timing diagram, extract a partial area from the RUDY diagram according to the position information of the plurality of connection nets in the layout area, and convert the partial area into a fixed value by linear interpolation to fill it again as a second layout feature;

[0022] The number information of the load logic gate pins or circuit ports corresponding to the connection network nodes, the half-circle length information of the connection network and the boundary information of the connection network are obtained to be filled again as the second statistical feature.

[0023] Optionally, predict the delay of the connection line timing arc in the expanded timing diagram, including:

[0024] Encoding the second layout feature of the connection network node through a convolutional neural network, and concatenating the output embedding value with the second statistical feature of the connection network node to obtain the embedding value of the connection network node;

[0025] Calculate the embedding value of the pin node through the graph neural network and the embedding value of the connection network node;

[0026] The delay of the connection line timing arc is calculated according to the embedded value of the pin node.

[0027] Optionally, predict the delay of logic gate timing arcs in the expanded timing diagram, including:

[0028] Mapping the slew time of the logic gate timing arc input or the load capacitance value of the logic gate timing arc output to a probability vector;

[0029] The probability vector is converted into a one-dimensional vector, and the delay of the logic gate timing arc is calculated based on the one-dimensional vector.

[0030] Optionally, predict the delay of the pin nodes in the expanded timing diagram, including:

[0031] Determine the topological structure of the timing diagram and perform topological sorting;

[0032] The delays of the pin nodes belonging to the same topological order are calculated, and the calculation results are used as the calculation input of the next topological order until the calculation of the last topological order is completed to obtain the target delay of the pin nodes.

[0033] The present application also provides a static timing analysis device based on layout features, comprising:

[0034] Establishing a module for obtaining a gate-level netlist of a circuit and establishing a timing diagram according to the gate-level netlist;

[0035] An expansion module, configured to fill the nodes and directed edges in the timing graph with first statistical features, calculate the first layout feature of each connection network in the timing graph, and expand the timing graph according to the first layout feature;

[0036] The prediction module is used to build a static timing analysis prediction model based on graph neural networks and convolutional neural networks, and predict the delay of the connection line timing arc, the delay of the logic gate timing arc, and the delay of the pin node in the expanded timing diagram;

[0037] The determination module is used to determine the static timing analysis result through the delay of the connection line timing arc, the delay of the logic gate timing arc and the delay of the pin node.

[0038] The present application also provides an electronic device, characterized in that the electronic device includes a memory and a processor, the memory stores a computer program, and the processor executes the steps of any one of the static timing analysis methods based on layout features provided in the present application by calling the computer program stored in the memory.

[0039] The static timing analysis method based on layout features provided by the present application can obtain the gate-level netlist of the circuit, and establish a timing diagram based on the gate-level netlist, fill the first statistical features into the nodes and directed edges in the timing diagram respectively, calculate the first layout feature of each connection network in the timing diagram, and expand the timing diagram based on the first layout feature, build a static timing analysis prediction model based on the graph neural network and the convolutional neural network, and predict the delay of the connection line timing arc, the delay of the logic gate timing arc and the delay of the pin node in the expanded timing diagram, and determine the static timing analysis result by the delay of the connection line timing arc, the delay of the logic gate timing arc and the delay of the pin node. The present application obtains the layout features of the circuit by extracting and encoding the connection network nodes, and models the static timing analysis prediction model based on the layout features, thereby improving the prediction accuracy of the static timing analysis prediction model in layout areas with different aspect ratios. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solution in the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative work.

[0041] Figure 1 It is a flow chart of a static timing analysis method based on layout features provided in an embodiment of the present application;

[0042] Figure 2It is another flow chart of a static timing analysis method based on layout features provided in an embodiment of the present application;

[0043] Figure 3 is a schematic diagram of the prediction accuracy of the layout area under different aspect ratios provided by the embodiment of the present application;

[0044] Figure 4 It is a structural schematic diagram of a static timing analysis device based on layout features provided in an embodiment of the present application;

[0045] Figure 5 It is a structural schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0046] Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

[0047] It should be noted that, in this article, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element. In addition, components, features, and elements with the same name in different embodiments of the present application may have the same meaning or different meanings, and their specific meanings need to be determined by their explanation in the specific embodiment or further combined with the context of the specific embodiment.

[0048] It should be understood that, although the various steps in the flowchart in the embodiment of the present application are displayed in sequence according to the indication of the arrows, these steps are not necessarily performed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and it can be performed in other orders. Moreover, at least a portion of the steps in the figure may include a plurality of sub-steps or a plurality of stages, and these sub-steps or stages are not necessarily performed at the same time, but can be performed at different times, and their execution order is not necessarily performed in sequence, but can be performed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

[0049] It should be noted that, in this article, step codes such as 101, 102, etc. are used for the purpose of expressing the corresponding content more clearly and concisely, and do not constitute a substantial limitation on the sequence. When implementing the step, those skilled in the art may execute 102 first and then 101, etc., but these should all be within the scope of protection of this application.

[0050] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0051] An embodiment of the present application provides a static timing analysis method based on layout features. The executor of the static timing analysis method based on layout features may be a static timing analysis device based on layout features provided in an embodiment of the present application, or a server integrating the static timing analysis device based on layout features, wherein the static timing analysis device based on layout features may be implemented in hardware or software.

[0052] like Figure 1 As shown, Figure 1 : is a flow chart of a static timing analysis method based on layout features provided in an embodiment of the present application. The specific flow of the static timing analysis method based on layout features may be as follows:

[0053] 101. Obtain the gate-level netlist of the circuit and create a timing diagram based on the gate-level netlist.

[0054] Among them, the gate-level netlist is a file that describes the interconnection relationship between circuit elements (mainly gate circuits or elements of the same level). In the EDA process, the gate-level netlist can be generated by synthesis and layout and routing tools. Specifically, the design input of the circuit is first obtained, such as hardware description language (HDL) code (such as Verilog or VHDL) or circuit schematics, and then the HDL code or circuit schematics are converted into a gate-level netlist using a synthesis tool (such as Design Compiler). The synthesis tool can convert the design into an equivalent gate-level circuit based on the gate circuit model in the target process library. After obtaining the gate-level netlist, the layout and routing tool (such as IC Compiler) will further process the gate-level netlist, optimize it according to design rules, power consumption, performance and other factors, and generate the final layout and routing results, while providing an updated gate-level netlist.

[0055] In one embodiment, after obtaining the above-mentioned gate-level netlist, a corresponding timing diagram can be further established, wherein the timing diagram is used to describe the signal transmission and delay relationship between circuit elements. Specifically, the gate-level netlist file can be parsed to obtain the connection relationship and delay information of each element in the circuit, and a data structure is established according to the parsing result to encapsulate the various elements and connection relationships in the circuit. The above-mentioned data structure can reflect the input, output, delay and other attributes of the element. Then, through the timing diagram drawing function in the drawing tool or EDA tool, a timing diagram is drawn according to the established data structure. It should be noted that the timing diagram is a directed acyclic graph, and the nodes in the timing diagram are circuit ports or logic gate pins, and the directed edges in the timing diagram are connecting line timing arcs or logic unit timing arcs.

[0056] 102. Fill the nodes and directed edges in the timing graph with first statistical features respectively, calculate the first layout feature of each connection network in the timing graph, and expand the timing graph according to the first layout feature.

[0057] In one embodiment, the first statistical feature corresponding to the node may include: two-dimensional coordinate information of the node in the layout area, fan-out number information corresponding to the connection network to which the node belongs, information on whether the node is an output, and information on whether the node is a timing path endpoint. The first statistical feature corresponding to the directed edge may include statistical features of the connection line timing arc and statistical features of the logic unit timing arc. Further, the statistical features of the connection line timing arc may include the distance between the driver and the load, and the statistical features of the logic unit timing arc may include a lookup table in the nonlinear delay model timing library. It should be noted that in the nonlinear delay model (NLDM) timing library, a lookup table (LUT) is a data structure for storing and quickly retrieving delay information under specific conditions. In the NLDM timing library, the lookup table is usually used to store delay information related to input transition time and output capacitance. These delay information include rising edge delay, falling edge delay, and output transition time.

[0058] In one embodiment, when calculating the first layout feature of each connection net in the timing diagram, the layout area in the timing diagram may be divided into a plurality of densely laid connection nets, and then a first layout feature represented in a matrix form may be constructed. The first layout feature may be RUDY (Rectangular Uniform Wire Density). The specific calculation process is as follows:

[0059]

[0060] Where RUDY(x,y) represents the rectangular uniform line density feature on the grid with coordinates (x,y), n is the connection network number, and HPWL n is the half-circumference length of the connecting network, w n and h n are the width and height of the bounding box of the connection network, and is the coordinate of the lower left corner of the bounding box of the connection network, and The coordinates of the upper right corner of the bounding box of the connection network.

[0061] In one embodiment, after the first layout feature is calculated, the timing diagram can be further expanded according to the first layout feature. Specifically, for each connection net, a connection net node can be added according to the corresponding first layout feature, and an undirected edge can be established between the connection net node and the circuit port or logic gate pin associated with the current connection net.

[0062] 103. A static timing analysis prediction model is constructed based on graph neural network and convolutional neural network, and the delay of the connection line timing arc, the delay of the logic gate timing arc and the delay of the pin node in the expanded timing diagram are predicted.

[0063] In one embodiment, a static timing analysis prediction model based on GNN and CNN is constructed, and the prediction model can specifically include a connection network prediction module, a logic gate prediction module, and a data transfer module. Among them, the connection network prediction module can use CNN connection network nodes for encoding to obtain layout features, splice the embedded values ​​output by CNN with the statistical features of the connection network nodes, and obtain the encoded connection network node embedding values ​​after multi-layer perceptron encoding. Then, the GNN module is used to perform feature aggregation on the connection network nodes and pin nodes, and the embedded values ​​of the pin nodes are updated. Finally, the multi-layer perceptron can be used to predict the delay of the timing arc of the connection line.

[0064] The logic gate prediction module maps the slew time of the logic gate timing arc input and the load capacitance value of the logic gate timing arc output into probability vectors one by one, and after transforming the probability vectors, obtains the prediction of the delay of the logic gate timing arc through the multi-layer perceptron module.

[0065] The data transmission module calculates the prediction result of the delay of the pin node according to the topological structure of the timing diagram, wherein the constructed directed acyclic graph can be topologically sorted in advance to determine the topological level of each node.

[0066] 104. The static timing analysis result is determined by the delay of the connection line timing arc, the delay of the logic gate timing arc and the delay of the pin node.

[0067] The embodiment of the present application uses CNN to extract and encode layout features, which can effectively capture key information in the layout, provide rich and effective feature representation for model training, and combine with GNN modeling circuit structure to effectively combine layout features and structural features, capture the complex relationship between layout, topology and static timing, and effectively solve the problem that the static timing analysis prediction model cannot effectively utilize layout features, thereby improving the prediction accuracy of the static timing analysis prediction model in layout areas with different width-to-height ratios (aspect ratios).

[0068] As described above, the static timing analysis method based on layout features proposed in the embodiment of the present application can obtain the gate-level netlist of the circuit, and establish a timing diagram based on the gate-level netlist, fill the first statistical features into the nodes and directed edges in the timing diagram respectively, calculate the first layout feature of each connection network in the timing diagram, and expand the timing diagram based on the first layout feature, build a static timing analysis prediction model based on the graph neural network and the convolutional neural network, and predict the delay of the connection line timing arc, the delay of the logic gate timing arc and the delay of the pin node in the expanded timing diagram, and determine the static timing analysis result by the delay of the connection line timing arc, the delay of the logic gate timing arc and the delay of the pin node. The embodiment of the present application obtains the layout features of the circuit by extracting and encoding the connection network nodes, and models the static timing analysis prediction model based on the layout features, thereby improving the prediction accuracy of the prediction model in layout areas with different aspect ratios.

[0069] The method described in the above embodiment will be further described below.

[0070] See also Figure 2 , Figure 2 1 is another flow chart of a static timing analysis method based on layout features provided in an embodiment of the present application. The method comprises:

[0071] 201. Obtain a gate-level netlist of the circuit, and establish a timing diagram based on the gate-level netlist.

[0072] 202 . Fill the nodes and directed edges in the timing graph with first statistical features respectively, calculate the first layout feature of each connection network in the timing graph, and expand the timing graph according to the first layout feature.

[0073] The specific contents of step 201 and step 202 can refer to the description of the corresponding contents in the previous embodiment, and will not be further elaborated here.

[0074] 203. Fill the expanded timing diagram with second layout features and second statistical features.

[0075] In one embodiment, for the expanded timing diagram, a partial area can be extracted from the RUDY diagram according to the position information of multiple connection nets in the layout area, and this partial area is converted into a fixed value through linear interpolation to be filled again as the second layout feature. Then, the number information of the load logic gate pins or circuit ports corresponding to the connection net nodes, the half-circle length information of the connection net, and the boundary information of the connection net are obtained to be filled again as the second statistical feature.

[0076] 204. Based on graph neural network and convolutional neural network, connection network prediction module, logic gate prediction module and data transmission module are constructed respectively.

[0077] Specifically, the connection network prediction module can use CNN to encode the connection network nodes to obtain layout features, concatenate the embedding values ​​output by CNN with the statistical features of the connection network nodes, and obtain the encoded connection network node embedding values ​​after encoding by a multi-layer perceptron. The calculation formula of this process is as follows:

[0078]

[0079] Among them, h′ n is the encoded connection network node embedding value, W n is the weight matrix of the multilayer perceptron, σ is the Sigmoid activation function, is the layout feature of the connected network nodes, is the statistical characteristic of the nodes in the connected network, This is a vector concatenation operation.

[0080] Then, the GNN module is used to aggregate the features of the connection network nodes and the pin nodes, and the embedding value of the pin nodes is updated. The process is divided into two parts. The first part is to obtain the updated embedding value h″ after the connection network node aggregates the features of its neighbor pin nodes. n , the formula of this process is as follows:

[0081]

[0082] Among them, W pn is the weight of the multilayer perceptron, N(n) is the neighbor pin node of the network node n, and h p is the statistical characteristic of the pin node p.

[0083] The second part is that the connected network node broadcasts the updated embedding value to its neighbor pin node, and the pin node updates its own embedding value h′ according to the received embedding value p , the formula of this process is as follows:

[0084]

[0085] Among them, h′p is the updated embedding value of the pin node p, W np are the weights of the multi-layer perceptron.

[0086] Furthermore, a multi-layer perceptron is used to predict the delay of the timing arc of the connection line, the slew time of the load port or pin, and the load capacitance at the driving port or pin. The formula of this process is expressed as follows:

[0087]

[0088] Where x represents the delay of the connection line timing arc, the slew time of the load port or pin, and the predicted result of the load capacitance at the driving port or pin, W t is the weight of the multilayer perceptron, p and q are the starting point pin node and the end point pin node of the connecting line timing arc, respectively, h q is the statistical characteristic of the pin node q, h′ q is the updated embedding value of the pin node q, Slew p is the slew time of the origin pin node.

[0089] In one embodiment, the logic gate prediction module maps the slew time of the logic gate timing arc input and the load capacitance value of the logic gate timing arc output into a probability vector one by one, and each element in the probability vector is the probability that the input value is within the value interval. The formula of the process is expressed as follows:

[0090]

[0091] Among them, v is the slew time of the logic gate timing arc input or the load capacitance value of the logic gate timing arc output, V is the lookup table header corresponding to the logic gate timing arc in the timing library, W is a multi-layer perceptron, and d is a probability vector of the same scale as V.

[0092] The probability vector calculated above is cross-multiplied to obtain a probability distribution matrix with the same shape as the lookup table corresponding to the timing arc of the logic gate in the timing library. The probability distribution matrix is ​​Hadamard-producted with the lookup table corresponding to the timing arc of the logic gate in the timing library. The obtained matrix is ​​converted into a one-dimensional vector. The delay of the timing arc of the logic gate and the prediction of the output pin slew time are obtained through the multi-layer perceptron module. The formula of this process is expressed as follows:

[0093]

[0094] Among them, x c is the delay of the logic gate timing arc and the slew time of the logic gate timing arc endpoint pin node, W c is the weight of the multi-layer perceptron. Flat means flattening the matrix into a one-dimensional vector. and dc They respectively represent the probability vectors corresponding to the slew time of the logic gate timing arc input and the load capacitance value of the logic gate timing arc output, ⊙ represents the Hadamard product, Slew represents the slew time of the logic gate timing arc input, and Cap represents the load capacitance value of the logic gate timing arc output.

[0095] In one embodiment, the data transmission module transmits and calculates the prediction results according to the topological structure of the timing diagram. The model iteratively calculates the overall static timing analysis results according to the topological order of the circuit structure, and each time calculates the delay and slew time of the pin nodes belonging to the same topological order, and uses the results as the input of the calculation of the next topological order until the last topological order is completed. For the terminal pin node of the logic gate timing arc, if two or more logic gate timing arcs converge on the same pin node, the maximum delay and the maximum slew time are taken as the delay and slew time of the pin node.

[0096] 205. The static timing analysis prediction model composed of a connection network prediction module, a logic gate prediction module and a data transfer module is trained.

[0097] First, you need to prepare the circuits to be trained. After setting layout areas with different aspect ratios for each circuit, run the layout algorithm for the layout area settings of each aspect ratio of each circuit. Collect the data after the layout is completed to construct the timing diagram and extract the layout features. Run clock tree synthesis, routing, parasitic parameter extraction and static timing analysis to obtain the static timing analysis results as the label of the training data.

[0098] The model parameters are optimized based on the gradient descent method, so that the model can gradually learn and give more accurate prediction results. The objective function of the gradient descent optimization is obtained by linearly adding the pin node loss, logic gate timing arc loss and connection line timing arc loss. The calculation formula is as follows:

[0099]

[0100] Loss=Loss p +Loss c +Loss n

[0101] Among them, Loss is the loss function of model training. p is the pin node loss, P is the pin node set, including all pin nodes, t p and p are the model’s predicted values ​​of the delay value and slew time of the pin node, and are the delay value of the pin node and the actual value of the slew time, loss c is the logic gate timing arc loss, Lossn is the timing arc loss of the connecting line, E cell is the set of logic gate timing arcs, including all logic gate timing arcs, E net is the set of connection line timing arcs, including all connection line timing arcs, d e is the model's prediction of the delay of the timing arc, is the true value of the delay of the timing arc.

[0102] 206. The trained static timing analysis prediction model is used to predict the delay of the connection line timing arc, the delay of the logic gate timing arc and the delay of the pin node.

[0103] 207. The static timing analysis result is determined by the delay of the connection line timing arc, the delay of the logic gate timing arc and the delay of the pin node.

[0104] The embodiment of the present application extracts and encodes the connection network nodes to obtain the circuit layout features, and when modeling the static timing prediction model, the circuit layout features are combined with the impact of the static timing analysis prediction, thereby improving the prediction accuracy of the static timing analysis prediction model in layout areas with different aspect ratios. Compared with the prior art, the present application has achieved better prediction accuracy in layout areas with different aspect ratios. The prediction accuracy results are as follows: Figure 3 As shown, Figure 3 The prediction accuracy in the example is based on R^2, and the comparison index is the delay value of the pin. It can be seen that the prediction accuracy of the method of the embodiment of the present application under different layout area aspect ratios is significantly improved compared with the prior art.

[0105] As described above, the static timing analysis method based on layout features proposed in the embodiment of the present application can obtain the gate-level netlist of the circuit, and establish a timing diagram according to the gate-level netlist, fill the first statistical features into the nodes and directed edges in the timing diagram respectively, calculate the first layout feature of each connection network in the timing diagram, and expand the timing diagram according to the first layout feature, fill the second layout feature and the second statistical feature into the expanded timing diagram, and construct the connection network prediction module, the logic gate prediction module and the data transfer module based on the graph neural network and the convolutional neural network respectively, and train the static timing analysis prediction model composed of the connection network prediction module, the logic gate prediction module and the data transfer module, and predict the delay of the connection line timing arc, the delay of the logic gate timing arc and the delay of the pin node through the trained static timing analysis prediction model, and determine the static timing analysis result through the delay of the connection line timing arc, the delay of the logic gate timing arc and the delay of the pin node. The present application obtains the layout features of the circuit by extracting and encoding the connection network nodes, and models the static timing analysis prediction model according to the layout features, thereby improving the prediction accuracy of the prediction model in layout areas with different aspect ratios.

[0106] In order to implement the above method, an embodiment of the present application also provides a static timing analysis device based on layout features, which can be specifically integrated in terminal devices such as mobile phones, tablet computers, personal computers, cloud computers and other devices.

[0107] For example, Figure 4 As shown, Figure 4 1 is a schematic diagram of a structure of a static timing analysis device based on layout features provided in an embodiment of the present application. The static timing analysis device based on layout features may include:

[0108] Establishing module 301, used to obtain a gate-level netlist of a circuit and establish a timing diagram according to the gate-level netlist;

[0109] An expansion module 302 is used to fill the first statistical features into the nodes and directed edges in the timing graph, calculate the first layout feature of each connection network in the timing graph, and expand the timing graph according to the first layout feature;

[0110] Prediction module 303, used to build a static timing analysis prediction model based on graph neural network and convolutional neural network, and predict the delay of connection line timing arc, logic gate timing arc and pin node in the expanded timing diagram;

[0111] The determination module 304 is used to determine the static timing analysis result through the delay of the connection line timing arc, the delay of the logic gate timing arc and the delay of the pin node.

[0112] As can be seen from the above, the static timing analysis device based on layout features proposed in the embodiment of the present application can obtain the gate-level netlist of the circuit, and establish a timing diagram based on the gate-level netlist, fill the first statistical features into the nodes and directed edges in the timing diagram respectively, calculate the first layout feature of each connection network in the timing diagram, and expand the timing diagram based on the first layout feature, build a static timing analysis prediction model based on the graph neural network and the convolutional neural network, and predict the delay of the connection line timing arc, the delay of the logic gate timing arc and the delay of the pin node in the expanded timing diagram, and determine the static timing analysis result through the delay of the connection line timing arc, the delay of the logic gate timing arc and the delay of the pin node. The embodiment of the present application obtains the layout features of the circuit by extracting and encoding the connection network nodes, and models the static timing analysis prediction model based on the layout features, thereby improving the prediction accuracy of the prediction model in layout areas with different aspect ratios.

[0113] All of the above technical solutions can be arbitrarily combined to form optional embodiments of the present application, which will not be described in detail here.

[0114] A person of ordinary skill in the art will appreciate that all or part of the steps in the various methods of the above embodiments may be completed by instructions, or by controlling related hardware through instructions. The instructions may be stored in a computer-readable storage medium and loaded and executed by a processor.

[0115] To this end, an embodiment of the present application provides a computer-readable storage medium, in which a plurality of computer programs are stored, and the computer program can be loaded by a processor to execute the steps in any static timing analysis method based on layout features provided in the embodiment of the present application. For example, the computer program can execute the following steps:

[0116] Obtaining a gate-level netlist of the circuit, and establishing a timing diagram based on the gate-level netlist;

[0117] Filling first statistical features into nodes and directed edges in the timing graph respectively, calculating first layout features of each connection network in the timing graph, and expanding the timing graph according to the first layout features;

[0118] A static timing analysis prediction model is built based on graph neural networks and convolutional neural networks, and the delay of the connection line timing arc, the delay of the logic gate timing arc, and the delay of the pin node in the expanded timing diagram are predicted;

[0119] The static timing analysis result is determined by the delay of the connection line timing arc, the delay of the logic gate timing arc and the delay of the pin node.

[0120] The specific implementation of the above operations can be found in the previous embodiments, which will not be described in detail here.

[0121] The storage medium may include: a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0122] Since the computer program stored in the storage medium can execute the steps in any one of the static timing analysis methods based on layout features provided in the embodiments of the present application, the beneficial effects that can be achieved by any one of the static timing analysis methods based on layout features provided in the embodiments of the present application can be achieved. Please refer to the previous embodiments for details and will not be repeated here.

[0123] An embodiment of the present application also provides an electronic device, including a memory and a processor, wherein the memory is used to store a computer program, and the processor is used to call and run the computer program from the memory, so that the device equipped with the chip executes the methods in various possible implementation modes as described above.

[0124] For example, the computer device mentioned above may be a terminal device with corresponding functions such as a mobile phone, a tablet computer, a personal computer, a cloud computer, etc. Figure 5 , Figure 5 A schematic diagram of the structure of a computer provided in an embodiment of the present application.

[0125] The computer device 400 may include components such as a memory 401 and a processor 402. Those skilled in the art will appreciate that Figure 5 The computer device structure shown in the figure does not constitute a limitation on the computer device, and may include more or less components than shown in the figure, or combine certain components, or arrange the components differently.

[0126] The memory 401 may be used to store applications and data. The applications stored in the memory 401 include executable codes. The applications may be composed of various functional modules. The processor 402 executes various functional applications and data processing by running the applications stored in the memory 401.

[0127] Processor 402 is the control center of the computer device. It uses various interfaces and lines to connect the various parts of the entire computer device. By running or executing applications stored in memory 401 and calling data stored in memory 401, it executes various functions of the computer device and processes data, thereby monitoring the computer device as a whole.

[0128] In this embodiment, the processor 402 in the computer device will load the executable code corresponding to the process of one or more application programs into the memory 401 according to the following instructions, and the processor 402 will run the application program stored in the memory 401 to execute:

[0129] Obtaining a gate-level netlist of the circuit, and establishing a timing diagram based on the gate-level netlist;

[0130] Filling first statistical features into nodes and directed edges in the timing graph respectively, calculating first layout features of each connection network in the timing graph, and expanding the timing graph according to the first layout features;

[0131] A static timing analysis prediction model is built based on graph neural networks and convolutional neural networks, and the delay of the connection line timing arc, the delay of the logic gate timing arc, and the delay of the pin node in the expanded timing diagram are predicted;

[0132] The static timing analysis result is determined by the delay of the connection line timing arc, the delay of the logic gate timing arc and the delay of the pin node.

[0133] It is understood that the above scenarios are only examples and do not constitute a limitation on the application scenarios of the technical solutions provided in the embodiments of the present application. The technical solutions of the present application can also be applied to other scenarios. For example, it is known to those skilled in the art that with the evolution of the system architecture and the emergence of new business scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0134] The steps in the method of the embodiment of the present application can be adjusted in order, combined and deleted according to actual needs. The modules in the device of the embodiment of the present application can be combined, divided and deleted according to actual needs.

[0135] In the present application, the same or similar terminology concepts, technical solutions and / or application scenario descriptions are generally described in detail only the first time they appear. When they appear again later, they are generally not repeated for the sake of brevity. When understanding the technical solutions and other contents of the present application, for the same or similar terminology concepts, technical solutions and / or application scenario descriptions that are not described in detail later, reference can be made to the previous related detailed descriptions.

[0136] In the present application, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0137] The various technical features of the technical solution of the present application can be arbitrarily combined. In order to make the description concise, not all possible combinations of the various technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of the present application.

[0138] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loading and executing computer program instructions on a computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server, a data center, etc. that contains one or more available media integrated. The available medium can be a magnetic medium, (e.g., a floppy disk, a storage disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state storage disk Solid State Disk), etc.

[0139] The above is a detailed introduction to a static timing analysis method, device and electronic device based on layout features provided in an embodiment of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A static timing analysis method based on layout features, characterized in that: include: Obtaining a gate-level netlist of the circuit, and establishing a timing diagram based on the gate-level netlist; Filling first statistical features into nodes and directed edges in the timing graph respectively, calculating first layout features of each connection network in the timing graph, and expanding the timing graph according to the first layout features; A static timing analysis prediction model is built based on graph neural networks and convolutional neural networks, and the delay of the connection line timing arc, the delay of the logic gate timing arc, and the delay of the pin node in the expanded timing diagram are predicted; The static timing analysis result is determined by the delay of the connection line timing arc, the delay of the logic gate timing arc and the delay of the pin node.

2. The static timing analysis method based on layout features according to claim 1, characterized in that: The timing diagram is a directed acyclic graph, the nodes are circuit ports or logic gate pins, the directed edges are connection line timing arcs or logic unit timing arcs, and the nodes and directed edges in the timing diagram are respectively filled with the first statistical features, including: Filling the nodes in the timing graph with two-dimensional coordinate information, fan-out number information of the corresponding connection network, and timing path endpoint information; The directed edges in the timing diagram are filled with the distance information between the driver and the load in the connection line timing arc and the lookup table corresponding to the nonlinear delay model timing library in the logic unit timing arc.

3. The static timing analysis method based on layout features according to claim 1, characterized in that: The calculating the first layout feature of each connection net in the timing diagram comprises: Dividing the layout area into a plurality of densely packed connection nets in the timing diagram; The RUDY diagram of the circuit is calculated according to the multiple connection nets by the following formula: Where RUDY(x,y) represents the rectangular uniform line density feature on the grid with coordinates (x,y), n is the connection network number, and HPWL n is the half-circumference length of the connecting network, w n and h n are the width and height of the bounding box of the connection network, and are the coordinates of the lower left corner of the bounding box of the connection network.

4. The static timing analysis method based on layout features as claimed in claim 3, characterized in that: The step of expanding the timing diagram according to the first layout feature comprises: For each connection net, a connection net node is added according to the corresponding first layout feature, and an undirected edge is established between the connection net node and a circuit port or logic gate pin associated with the current connection net.

5. The static timing analysis method based on layout features as claimed in claim 4, characterized in that: After expanding the timing diagram according to the first layout feature, the method further includes: For the expanded timing diagram, extract a partial area from the RUDY diagram according to the position information of the plurality of connection nets in the layout area, and convert the partial area into a fixed value by linear interpolation to fill it again as a second layout feature; The number information of the load logic gate pins or circuit ports corresponding to the connection network nodes, the half-circle length information of the connection network and the boundary information of the connection network are obtained to be filled again as the second statistical feature.

6. The static timing analysis method based on layout features as claimed in claim 5, characterized in that: The delay of the connection line timing arc in the predicted expanded timing diagram includes: Encoding the second layout feature of the connection network node through a convolutional neural network, and concatenating the output embedding value with the second statistical feature of the connection network node to obtain the embedding value of the connection network node; Calculating the embedding value of the pin node through the graph neural network and the embedding value of the connection network node; The delay of the connection line timing arc is calculated according to the embedded value of the pin node.

7. The static timing analysis method based on layout features according to claim 6, characterized in that: The delay of the logic gate timing arc in the predicted expanded timing diagram includes: Mapping the slew time of the logic gate timing arc input or the load capacitance value of the logic gate timing arc output to a probability vector; The probability vector is converted into a one-dimensional vector, and the delay of the logic gate timing arc is calculated based on the one-dimensional vector.

8. The static timing analysis method based on layout features according to claim 7, characterized in that: The delay of the pin node in the predicted expanded timing diagram includes: Determine the topological structure of the timing diagram and perform topological sorting; The delays of the pin nodes belonging to the same topological order are calculated, and the calculation results are used as the calculation input of the next topological order until the calculation of the last topological order is completed to obtain the target delay of the pin nodes.

9. A static timing analysis device based on layout features, characterized in that: include: Establishing a module for obtaining a gate-level netlist of a circuit and establishing a timing diagram according to the gate-level netlist; An expansion module, configured to fill the nodes and directed edges in the timing graph with first statistical features, calculate the first layout feature of each connection network in the timing graph, and expand the timing graph according to the first layout feature; The prediction module is used to build a static timing analysis prediction model based on graph neural networks and convolutional neural networks, and predict the delay of the connection line timing arc, the delay of the logic gate timing arc, and the delay of the pin node in the expanded timing diagram; The determination module is used to determine the static timing analysis result through the delay of the connection line timing arc, the delay of the logic gate timing arc and the delay of the pin node.

10. An electronic device, characterized in that: The electronic device includes a memory and a processor, wherein a computer program is stored in the memory, and the processor executes the steps in the static timing analysis method based on layout features as described in any one of claims 1 to 8 by calling the computer program stored in the memory.

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