Power consumption measurement method for circuit design, model acquisition method and related device

Abstract

The embodiment of the invention provides a power consumption measurement method for a circuit design, a model acquisition method and a related device, and the method comprises the steps: constructing a measurement input matrix according to the operation data of the circuit design; calling a pre-trained power consumption determination model, wherein the power consumption determination model is obtained by training by minimizing an error between the prediction tag and the real tag; the real label indication circuit is designed in a real power consumption interval corresponding to the training input data, and predicts probability distribution of each power consumption interval corresponding to the training input data predicted by the label indication power consumption determination model; and taking the measurement input matrix as input of the power consumption determination model, and processing the measurement input matrix by using the power consumption determination model to obtain probability distribution of the circuit design output by the power consumption determination model in a plurality of power consumption intervals, and taking the probability distribution as a power consumption measurement result. The calculation amount of the power consumption determination model can be reduced and the measurement efficiency can be improved on the premise of ensuring the measurement accuracy.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of computer technology, and specifically to a power consumption measurement method, a model acquisition method, and related devices for circuit design. Background Art

[0002] As the complexity of the circuits in integrated circuit products increases, the power consumption of the chip is also increasing. The increase in chip power consumption will lead to an increase in chip heat generation and a decrease in reliability. The existing low-power solution to reduce chip power consumption requires the chip to have the function of real-time and accurate monitoring of the current power consumption of the chip. Therefore, how to improve the accuracy of power consumption calculation has become a problem that needs to be solved urgently by those skilled in the art. Summary of the invention

[0003] In view of this, an embodiment of the present application provides a power consumption measurement method, a model acquisition method and related devices for circuit design to improve the accuracy of power consumption calculation.

[0004] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0005] The present application provides a method for measuring power consumption of a circuit design, including:

[0006] Constructing a measurement input matrix according to the operation data of the circuit design, wherein the measurement input matrix at least includes the flip rate of each flip signal of multiple functional modules of the circuit design;

[0007] And, calling a pre-trained power consumption determination model, wherein the power consumption determination model is trained to minimize the error between the predicted label and the real label; wherein the real label indicates the real power consumption interval corresponding to the training input data of the circuit design, and the predicted label indicates the probability distribution of each power consumption interval corresponding to the training input data predicted by the power consumption determination model;

[0008] The measurement input matrix is ​​used as the input of the power consumption determination model, and the power consumption determination model is used to process the measurement input matrix to obtain the probability distribution of the circuit design output by the power consumption determination model in multiple power consumption intervals as the power consumption measurement result.

[0009] Optionally, constructing a measurement input matrix according to the operation data of the circuit design includes:

[0010] Obtaining the flip rate of each flip signal of multiple functional modules of the circuit design from the operation data of the circuit design;

[0011] A measurement input matrix is ​​constructed according to the toggle rates of each toggle signal of multiple functional modules of the circuit design; wherein the measurement input matrix includes a functional module dimension indicating multiple functional modules, and a toggle signal dimension indicating multiple toggle signals, and a data of the functional module dimension and the toggle signal dimension in the measurement input matrix represents the toggle rate of a toggle signal of a functional module.

[0012] Optionally, the power consumption determination model includes: an output layer; the output layer includes a plurality of nodes, one node corresponds to a power consumption interval, and is used to predict the score of the measurement input matrix in the corresponding power consumption interval;

[0013] The step of using the measurement input matrix as an input of the power consumption determination model and processing the measurement input matrix using the power consumption determination model to obtain a probability distribution of the circuit design output by the power consumption determination model in multiple power consumption intervals as a power consumption measurement result includes:

[0014] Inputting the measurement input matrix into the power consumption determination model, and using each node of the output layer to predict the score of the measurement input matrix in each power consumption interval;

[0015] The scores of the measurement input matrix in each power consumption interval are converted into probability distributions of the measurement input matrix in each power consumption interval, so as to obtain probability distributions of the circuit design in multiple power consumption intervals as power consumption measurement results.

[0016] Optionally, the output layer further includes a softmax function, and the softmax function is used to convert the scores of the measurement input matrix predicted by each node in each power consumption interval into a probability distribution of the measurement input matrix in each power consumption interval.

[0017] Optionally, the power consumption determination model further includes: an input layer and a hidden layer;

[0018] The input layer is used to input the measurement input matrix;

[0019] The hidden layer is used to extract the flip rate features in the measurement input matrix to obtain a flip rate feature matrix; normalize the flip rate feature matrix, and reduce the feature dimension and feature quantity of the flip rate feature matrix after normalization to obtain a flip rate key feature matrix; map the flip rate key feature matrix to the output layer.

[0020] Optionally, the hidden layer includes: a first convolutional layer, a normalization layer, an activation layer, a pooling layer, and a first fully connected layer;

[0021] The first convolution layer is used to perform convolution calculation on the measurement input matrix to extract the flip rate feature in the measurement input matrix to obtain the flip rate feature matrix;

[0022] The normalization layer is used to perform normalization processing on the flip rate feature matrix;

[0023] The activation layer is used to perform activation function processing after the flip rate feature matrix is ​​normalized, so as to transform the power consumption determination model from a linear model to a nonlinear model;

[0024] The pooling layer is used to extract the key features of the flip rate from the flip rate feature matrix after normalization, so as to reduce the feature dimension and the number of features and obtain the flip rate key feature matrix;

[0025] The first fully connected layer is used to perform a convolution operation on the flip rate key feature matrix and provide the convolution operation result to the output layer.

[0026] Optionally, the first convolution layer includes 4 convolution kernels, the convolution kernel includes a convolution matrix with 3 rows and 3 columns, and the convolution kernel is used to perform convolution calculation on the data in the convolution matrix to extract the flipping rate features in the measurement input matrix and store them in the flipping rate feature matrix.

[0027] Optionally, the normalization layer includes calculating the mean and standard deviation of the flip rate features of the flip rate feature matrix; standardizing the flip rate features of the flip rate feature matrix based on the mean and standard deviation, and restoring the feature expression capability of the flip rate features.

[0028] Optionally, the activation layer includes a ReLU activation function for mapping negative values ​​of the power consumption determination model to a zeroth value.

[0029] Optionally, the pooling layer includes multiple pooling convolution kernels, and the pooling convolution kernel is a convolution matrix with 2 rows and 2 columns, which is used to pool the data in the pooling convolution matrix;

[0030] The pooling convolution kernel includes a maximization function for selecting the largest data in the pooling convolution matrix as output.

[0031] Optionally, the first fully connected layer includes 1024 neurons, the neurons include multiple convolution kernels, the convolution kernel includes a convolution matrix, the convolution kernel is used to perform convolution calculation on the data in the convolution matrix, and provide the convolution operation result to the output layer.

[0032] Optionally, the power consumption measurement result is used for power consumption optimization decision of the circuit design, and the power consumption optimization decision includes adjusting the operating frequency and / or voltage of the circuit design.

[0033] The present application also provides a method for obtaining a power consumption calculation model.

[0034] include:

[0035] Get pre-silicon simulation data for circuit design;

[0036] Determining the simulated dynamic power consumption of the circuit design and the flip rate of each flip signal of multiple functional modules of the circuit design according to the simulation data;

[0037] Constructing training input data according to the flipping rates of the flipping signals of the plurality of functional modules, and determining the real label of the training input data according to the simulated dynamic power consumption; the real label indicates that the circuit design is in the real power consumption interval corresponding to the training input data;

[0038] According to the training input data, the neural network model is trained with the goal of minimizing the error between the predicted label and the true label output by the neural network model; wherein the predicted label indicates the probability distribution of each power consumption interval corresponding to the training input data predicted by the neural network model;

[0039] The trained neural network model is used as the power consumption determination model.

[0040] Optionally, constructing training input data according to the flip rates of each flip signal of multiple functional modules includes: constructing a training input matrix as the training input data according to the flip rates of each flip signal of multiple functional modules of the circuit design; wherein the training input matrix includes a functional module dimension indicating multiple functional modules, and a flip signal dimension indicating multiple flip signals, and one data of the functional module dimension and the flip signal dimension in the training input matrix represents the flip rate of a flip signal of a functional module.

[0041] Optionally, the neural network model includes:

[0042] An input layer, used for inputting the measurement input matrix;

[0043] The hidden layer is used to extract the flip rate features in the training input matrix to obtain a flip rate feature matrix; normalize the flip rate feature matrix, and reduce the feature dimension and feature quantity of the flip rate feature matrix after the normalization process to obtain a flip rate key feature matrix; and map the flip rate key feature matrix to the output layer;

[0044] Output layer; the output layer includes a plurality of nodes, one node corresponds to a power consumption interval, and is used to predict the score of the measurement input matrix in the corresponding power consumption interval.

[0045] Optionally, the hidden layer includes: a first convolutional layer, a normalization layer, an activation layer, a pooling layer, and a first fully connected layer;

[0046] The first convolution layer is used to perform convolution calculation on the training input matrix to extract the flip rate feature in the training input matrix to obtain a flip rate feature matrix;

[0047] The normalization layer is used to perform normalization processing on the flip rate feature matrix;

[0048] The activation layer is used to perform activation function processing after the flip rate feature matrix is ​​normalized, so as to transform the power consumption determination model from a linear model to a nonlinear model;

[0049] The pooling layer is used to extract the key features of the flip rate from the flip rate feature matrix after normalization, so as to reduce the feature dimension and the number of features and obtain the flip rate key feature matrix;

[0050] The first fully connected layer is used to perform a convolution operation on the flip rate key feature matrix and provide the convolution operation result to the output layer.

[0051] Optionally, the training of the neural network model according to the training input data takes minimizing the error between the predicted label and the true label output by the neural network model as a training goal, and the training of the neural network model includes:

[0052] According to the training input data, the model parameters of the neural network model are iteratively adjusted by the gradient descent method to minimize the total loss of the training set, thereby obtaining a trained neural network model; wherein the total loss of the training set is represented by a loss function, and the loss function is used to calculate the error between the predicted label and the true label; the training set includes multiple training input data, and one training input data corresponds to simulation data corresponding to a verification case of a circuit design in a pre-silicon test scenario.

[0053] The present application also provides a power consumption measurement device for a circuit design, including:

[0054] A measurement data acquisition module, used to construct a measurement input matrix according to the operation data of the circuit design, wherein the measurement input matrix at least includes the flip rate of each flip signal of multiple functional modules of the circuit design;

[0055] A power consumption determination model calling module, used to call a pre-trained power consumption determination model, wherein the power consumption determination model is trained to minimize the error between the predicted label and the real label; wherein the real label indicates the real power consumption interval corresponding to the training input data of the circuit design, and the predicted label indicates the probability distribution of each power consumption interval corresponding to the training input data predicted by the power consumption determination model;

[0056] A training data input module is used to use the measurement input matrix as the input of the power consumption determination model, and use the power consumption determination model to process the measurement input matrix to obtain the probability distribution of the circuit design output by the power consumption determination model in multiple power consumption intervals as the power consumption measurement result.

[0057] The embodiment of the present application also provides a device for obtaining a power consumption calculation model, including:

[0058] A simulation data acquisition module, used to acquire simulation data before circuit design silicon;

[0059] A simulation data processing module, used to determine the simulated dynamic power consumption of the circuit design and the flip rate of each flip signal of multiple functional modules of the circuit design according to the simulation data;

[0060] A training data acquisition module, used to construct training input data according to the flipping rates of the flipping signals of the plurality of functional modules, and to determine the real label of the training input data according to the simulated dynamic power consumption; the real label indicates that the circuit design is in the real power consumption interval corresponding to the training input data;

[0061] A model training module is used to train a neural network model based on the training input data, with the goal of minimizing the error between the predicted label and the true label output by the neural network model; wherein the predicted label indicates the probability distribution of each power consumption interval corresponding to the training input data predicted by the neural network model; and the trained neural network model is used as a power consumption determination model.

[0062] An embodiment of the present application also provides a computing device, including a memory and a processor, wherein the memory stores computer instructions, and the processor calls the computer instructions stored in the memory to execute the power consumption measurement method of the circuit design as described above, and / or the method for obtaining the power consumption calculation model as described above.

[0063] An embodiment of the present application also provides a storage medium, which stores a design program for a chip. When the design program is executed, it implements the power consumption measurement method of the circuit design as described above, and / or the method for obtaining the power consumption calculation model as described above.

[0064] An embodiment of the present application also provides a computer program product, which, when executed, implements the power consumption measurement method of the circuit design as described above, and / or the method for obtaining the power consumption calculation model as described above.

[0065] The power consumption measurement method of the circuit design provided in the embodiment of the present application constructs a measurement input matrix according to the operation data of the circuit design, wherein the measurement input matrix includes at least the flipping rates of each flipping signal of multiple functional modules of the circuit design; and calls a pre-trained power consumption determination model, wherein the power consumption determination model is trained to minimize the error between the predicted label and the real label; wherein the real label indicates the real power consumption interval of the circuit design corresponding to the training input data, and the predicted label indicates the probability distribution of each power consumption interval corresponding to the training input data predicted by the power consumption determination model; the measurement input matrix is ​​used as the input of the power consumption determination model, and the measurement input matrix is ​​processed using the power consumption determination model to obtain the probability distribution of the circuit design in multiple power consumption intervals output by the power consumption determination model as the power consumption measurement result.

[0066] It can be seen that by using the flip rate of each flip signal of multiple functional modules of the circuit design as the input for measuring power consumption, and using the power consumption determination model, obtaining the probability distribution of the circuit design output by the power consumption determination model in multiple power consumption intervals based on the flip rate, the power consumption measurement result can be obtained more accurately. Furthermore, using the probability distribution of multiple power consumption intervals as the power consumption measurement result instead of directly calculating the specific value of the power consumption can reduce the calculation amount of the power consumption determination model and improve the measurement efficiency while ensuring the measurement accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0068] Figure 1 A schematic diagram of a flow chart of a method for measuring power consumption of a circuit design provided in an embodiment of the present application;

[0069] Figure 2 Another schematic diagram of a flow chart of a method for measuring power consumption of a circuit design provided in an embodiment of the present application;

[0070] Figure 3 A partial structural schematic diagram of a circuit design is provided for an embodiment of the present application;

[0071] Figure 4 A schematic diagram of the structure of a power consumption determination model provided in an embodiment of the present application;

[0072] Figure 5 A schematic flow chart of a method for measuring power consumption of a hidden layer running a power consumption determination model provided in an embodiment of the present application;

[0073] Figure 6 A schematic diagram of a process of obtaining a power consumption calculation model provided in an embodiment of the present application;

[0074] Figure 7 Another schematic diagram of a flow chart of a method for obtaining a power consumption calculation model provided in an embodiment of the present application;

[0075] Figure 8 A schematic diagram of the structure of a power consumption measurement device for a circuit design provided in an embodiment of the present application;

[0076] Fig. 9 A schematic diagram of the structure of a device for acquiring an electric power consumption calculation model provided in an embodiment of the present application. DETAILED DESCRIPTION

[0077] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0078] As the chip scale expands, the power consumption of the chip is also increasing. Excessive power consumption of the chip will lead to increased heat generation and decreased reliability. Therefore, whether the power consumption of the chip is reasonable is an important consideration in integrated circuit design. Chip design not only pursues high performance and small area, but also has comprehensive requirements for performance, area, and power consumption. Low-power design that reduces chip power consumption has become an important technology in chip design.

[0079] One low-power solution is to monitor the current power consumption of the chip in real time and adjust the frequency and voltage of the chip according to the current power consumption of the chip. Specifically, TDP (Thermal Design Power) is the thermal design power consumption index of the chip, which is usually used to identify how much heat the chip is designed to dissipate to ensure that it can work stably at the nominal frequency. Without exceeding TDP, the maximum operating frequency and maximum operating voltage need to be set to achieve optimal performance. Otherwise, the clock frequency and voltage can only be set by retaining a large margin, which will cause performance loss. When adjusting the frequency and voltage of the chip, it is usually combined with AVFS (Adaptive Voltage Frequency Scaling) or DVFS (Dynamic Voltage Frequency Scaling) technology. This low-power solution requires that the chip has the function of accurately monitoring the current power consumption of the chip in real time.

[0080] The power consumption of a chip usually consists of dynamic power consumption and background power consumption. Dynamic power consumption consists of switch power consumption and short-circuit power consumption. Background power consumption is exponentially related to voltage and temperature.

[0081] Dynamic power consumption accounts for a large proportion of chip power consumption, but as the process changes, background power consumption also accounts for a large proportion. Since the overall background power consumption is exponentially related to voltage and temperature, and the technology for measuring voltage and temperature is simple and highly accurate, the background power consumption can be accurately calculated by real-time monitoring of temperature and voltage.

[0082] There are many factors that affect the dynamic power consumption of a chip, including chip voltage, chip manufacturing process, chip circuit scale, clock frequency, signal flip rate, circuit working status, etc., which will affect the dynamic power consumption of the chip. Therefore, estimating dynamic power consumption is relatively difficult and requires the establishment of a reasonable mathematical model.

[0083] Furthermore, the dynamic power consumption of the chip is mainly composed of the flip power consumption and short circuit power consumption in the chip. The calculation formula of flip power consumption is: switch =C eff ×V 2 ×F. The formula for calculating short-circuit power consumption is: The calculation formula of dynamic power consumption is the sum of flip power consumption and short-circuit power consumption, that is, P dyn =P switch +P short Among them, C eff is the effective capacitance, V is the power supply voltage, F is the frequency, t sc is the short circuit time, V t is the transistor threshold voltage, and τ is the transistor gain factor.

[0084] After further simplifying the calculation formula of dynamic power consumption, we can get the formula: P dyn =(C m ×V+C b )×V 2 ×F, where C b =C eff ,

[0085] In the above formula, information such as effective capacitance and short-circuit time cannot be measured in the chip, so they can be combined into C m and C b These two parameters can be obtained through post-silicon testing. The voltage value V of the chip can be directly obtained by directly measuring the voltage of the circuit. The frequency F is proportional to the dynamic power consumption, so as long as the frequency F can be accurately obtained, the dynamic power consumption can be estimated more accurately.

[0086] In a method for power consumption estimation, the simulated dynamic power consumption of the design to be tested that can be accurately obtained during the simulation process, and the flip rates of multiple flip signals, are linearly fitted based on the linear relationship between the dynamic power consumption of the design to be tested and the signal flip, and a flip weight related to the flip rate of the flip signal is calculated. Since the simulated dynamic power consumption used when obtaining the flip weight is accurate, when the design to be tested is actually used, the actual dynamic power consumption of the design to be tested calculated by the flip weight and the accurately measured flip rate of the flip signal, and the actual dynamic power consumption of the design to be tested are also determined to be accurate values. This avoids using an estimated value with a large error to calculate the actual dynamic power consumption when calculating the actual dynamic power consumption, thereby improving the calculation accuracy of the actual dynamic power consumption.

[0087] The above method of calculating weights by linear fitting based on the linear relationship between dynamic power consumption and signal flipping of the design to be tested is usually applicable to the case where the functional modules are not large and the number of flipping signals of each functional module is small, for example, less than 30. When the number of flipping signals of each functional module is large, NNLS fitting will become more difficult and even overfitting will occur. In addition, when estimating power consumption at the large SOC level, it is often necessary to perform weight fitting for multiple modules separately, which increases the workload.

[0088] To solve the above problems, the present application provides a method for measuring power consumption of a circuit design, which obtains the power consumption of the circuit design by calling a pre-trained power consumption determination model to more accurately calculate the power consumption of the chip. As an optional implementation, Figure 1 FIG. 1 is a flow chart showing a method for measuring power consumption of a circuit design provided in an embodiment of the present application. Figure 1 As shown, the power consumption measurement method of the circuit design provided in the embodiment of the present application includes the following steps.

[0089] Step S10: constructing a measurement input matrix according to the operation data of the circuit design. The measurement input matrix at least includes the flip rate of each flip signal of multiple functional modules of the circuit design.

[0090] It should be noted that, from the above content, it can be seen that the dynamic power consumption can be estimated more accurately by only obtaining the flip rate of the circuit design. Therefore, it can be considered that the flip rate of the circuit design is data that has a greater correlation with the power consumption of the circuit design. Therefore, using the training data constructed by the flip rate to train and construct a neural network model can make the power consumption of the circuit design obtained by the trained neural network model more accurate.

[0091] Specifically, in an optional implementation, such as Figure 2 As shown, the step S10 includes step S11: acquiring the flip rate of each flip signal of multiple functional modules of the circuit design from the operation data of the circuit design.

[0092] In an optional implementation, the functional modules are modules divided according to the logic functions in the design to be tested. In a complete design to be tested, a flip signal that flips can only act on a single logic function, so the design to be tested needs to be divided into multiple functional modules according to the logic functions, and the flip rate of the flip signal in each functional module needs to be obtained.

[0093] The flip signal includes the bus control signal and / or read / write enable signal of the functional module. When selecting multiple flip signals of the functional module, it is necessary to select flip signals that can fully reflect the flip activity of the functional module. Such flip signals are usually some signals related to data transmission, and can continuously jump and flip with the transmission of the flip signal, such as the control signals used to manage and coordinate data transmission between the master device and the slave device in the AXI (Advanced eXtensible Interface, an on-chip bus) protocol, such as AWVALID (Address Write VALID) signal, ARVALID (Address Read VALID) signal, RVALID (Read Data VALID) signal, and WVALID (WriteData VALID) signal, or some read enable signals and write enable signals, such as WEN (Write Enable), REN (Read Enable), etc.

[0094] It should be noted that, since the flip rates of multiple flip signals of multiple functional modules are obtained for the power consumption determination model, and the power consumption determination model usually includes a pooling layer, the pooling layer can effectively avoid overfitting. Therefore, when selecting the flip signal, the number of flip signals does not need to consider the problem of overfitting, and a larger number of flip signals can be selected to obtain better results. In an optional implementation, the number of flip signals can be 64, 128, etc.

[0095] Specifically, the method for obtaining the flip rate is as follows: Figure 3 As shown, the design to be tested 1 includes multiple functional modules 2 to 6. Each functional module needs to be connected to at least one counter, and the four functional modules are connected to a total of 7 counters, namely counters 11 to 17. Each counter corresponds to a flip signal of the functional module, namely flip signal 0 to flip signal 6. Each time a flip signal flips, the counter corresponding to the flip signal accumulates 1, and the counting result of the counter is stored in the register as the flip number of the flip signal for software to read. In the pre-silicon simulation process, the flip number of the flip signal can be read as simulation data.

[0096] It should be noted that in order to ensure that the flip rate of the flip signal obtained during the simulation process is consistent with that obtained during actual use, in an optional implementation, the design to be tested also includes the counter as described above, and the flip rates of the multiple flip signals in each test scenario are also obtained through the counter as described above.

[0097] Please continue to refer to Figure 2 ,like Figure 2 As shown, the step S10 also includes a step S12: constructing a measurement input matrix according to the flip rate of each flip signal of multiple functional modules of the circuit design. Wherein, the measurement input matrix includes a functional module dimension indicating multiple functional modules and a flip signal dimension indicating multiple flip signals, and the functional module dimension and the flip signal dimension represent the flip rate of a flip signal of a functional module in one data of the measurement input matrix. In this way, the flip rate of each flip signal of multiple functional modules can be transformed from a sequence into a matrix to facilitate input into a trained neural network model.

[0098] Specifically, in an optional implementation, an example of the input matrix is ​​shown in Table 1 below:

[0099] Flip rate matrix Signal 0 Signal 1 Signal 2 … Signal N-1 Module 0 ACT_rate(0,0) ACT_rate(0,1) ACT_rate(0,2) ACT_rate(0,N-1) Module 1 ACT_rate(1,0) ACT_rate(1,1) ACT_rate(1,2) ACT_rate(1,N-1) Module 2 ACT_rate(2,0) ACT_rate(2,1) ACT_rate(2,2) ACT_rate(1,N-1) … … … … … Module B-1 ACT_rate(B-1,0) ACT_rate(B-1,1) ACT_rate(B-1,N-1)

[0100] Table 1

[0101] As shown in Table 1, it is assumed that the number of functional modules in the circuit design is B, and the number of flip signals selected by each module is at most N. At this time, the input matrix is ​​a B*N matrix, and each row of the input matrix is ​​a functional module dimension, corresponding to the flip rate of the flip signal of a functional module; each column is a flip signal dimension, indicating that the flip rate is the flip rate of the nth flip signal in the functional module. As shown in Table 1, ACT_rate(j,i) represents the flip rate of the i-th signal of the j-th module, j=0,1,…B-1; i=0,1,…N-1. It should be noted that when selecting the flip signal, the number of flip signals selected by each module may be different, so there is no relationship between the flip rates of different rows in the same column.

[0102] Furthermore, if the number of flip signals of a certain functional module is less than N, a blank table will appear at the end of a row of the table corresponding to the functional module. In order to accurately extract each feature in the input matrix, that is, the flip rate of the flip signal, the zeroth value can be used to fill in the blank table to make the table complete.

[0103] Please continue to refer to Figure 1 ,like Figure 1As shown, the power consumption measurement method of the circuit design also includes step S20: calling a pre-trained power consumption determination model, wherein the power consumption determination model is trained to minimize the error between the predicted label and the true label. The true label indicates the true power consumption interval of the circuit design corresponding to the training input data, and the predicted label indicates the probability distribution of each power consumption interval corresponding to the training input data predicted by the power consumption determination model.

[0104] It should be noted that, in an optional implementation, the power consumption measurement result is used for power consumption optimization decision of circuit design, and the power consumption optimization decision includes adjusting the operating frequency and / or voltage of the circuit design. That is, the purpose of measuring the power consumption of the circuit in actual production work is mainly to adjust the frequency and voltage of the circuit within a certain power consumption range to achieve an optimal configuration of performance and power consumption.

[0105] Therefore, when measuring the power consumption of a circuit, it is not necessary to obtain an absolutely accurate power consumption measurement result, and the power consumption of the circuit can be locked within a power consumption value range that meets the requirements. Correspondingly, when training the power consumption determination model or using the power consumption determination model, the pre-input power consumption measurement result or the obtained power consumption measurement result is also a power consumption value range.

[0106] Furthermore, when dividing the power consumption value interval, in order to more accurately determine the power consumption of the circuit, the power consumption value interval is divided into unequal intervals rather than equal intervals. For example, in order to ensure the normal operation of the circuit and the chip, the normal power consumption of the circuit is maintained near TDP (Thermal Design Power), and TDP is a value used to identify how much heat the CPU or GPU is designed to dissipate to ensure stable operation at the nominal frequency. Therefore, in practical applications, it is only necessary to pay attention to whether the power consumption measurement result is near TDP, and then the power consumption value near TDP can be divided into smaller intervals when dividing the power consumption interval, while the power consumption value with a large difference from TDP can be divided into larger intervals.

[0107] Step S30: using the measurement input matrix as input of the power consumption determination model, and using the power consumption determination model to process the measurement input matrix to obtain the probability distribution of the circuit design in multiple power consumption intervals output by the power consumption determination model as the power consumption measurement result.

[0108] Further, as mentioned above, the structure output by the power consumption determination model is a power consumption interval, so the power consumption determination model requires a structure for predicting the power consumption interval. Specifically, in an optional implementation, Figure 4As shown, the power consumption determination model includes: an output layer 10; the output layer includes a plurality of nodes, one node corresponds to a power consumption interval, and is used to predict the score of the measured input matrix in the corresponding power consumption interval. In this way, the power consumption determination model can predict the input data in the corresponding power consumption interval based on the score of the measured input matrix in the corresponding power consumption interval, without obtaining a specific power consumption value. Thus, the amount of calculation is reduced while ensuring the prediction accuracy.

[0109] Specifically, the power consumption range can be divided into one-hot encoding (One-Hot Encoding) for each power consumption range as a power consumption label. For example, the actual power consumption range of the chip is 10W to 100W, and the TDP is 80W. The power consumption range can be divided into 10 intervals, corresponding to 10 power consumption labels, as follows

[0110] As shown in Table 2:

[0111] Power Consumption Label Division range, unit W Remark P0 10～50 Low values ​​are usually of little concern P1 50～70 P2 70～75 P3 75～78 P4 78～80 P5 80～82 Near TDP, high attention P6 82～85 Near TDP, high attention P7 85～90 High values ​​are more concerned P8 90～95 High values ​​are more concerned

[0112] Table 2

[0113] It should be noted that there is no limit to the number of the power consumption tags. In an optional implementation, the minimum range of the power consumption tags may be 1W.

[0114] Furthermore, in order to measure the score of the input matrix in the corresponding power consumption interval and determine the power consumption interval, in an optional implementation, as Figure 2 As shown, the step S30 includes:

[0115] Step S31: input the measurement input matrix into the power consumption determination model, and use each node of the output layer to predict the score of the measurement input matrix in each power consumption interval.

[0116] It should be noted that when the power consumption determination model processes the measurement input matrix, it will obtain multiple eigenvalues ​​related to the power consumption measurement results. These eigenvalues ​​can usually be regarded as power consumption values, and then the score of a certain power consumption interval is the number of eigenvalues ​​included in the power consumption interval.

[0117] Step S32: converting the scores of the measurement input matrix in each power consumption interval into the probability distribution of the measurement input matrix in each power consumption interval, so as to obtain the probability distribution of the circuit design in multiple power consumption intervals as the power consumption measurement result.

[0118] It should be noted that when the power consumption determination model is used for processing, the number of eigenvalues ​​related to the power consumption measurement results may be large, for example, there are thousands of results. At this time, the gradient vanishing or exploding problem is prone to occur when training the power consumption determination model. And when using the power consumption determination model, the range size of each power consumption interval is inconsistent, and the scores of the measurement input matrix in each power consumption interval are not comparable, which makes it difficult to use it to determine the power consumption measurement results. Converting the scores of the measurement input matrix in each power consumption interval into the probability distribution of the measurement input matrix in each power consumption interval can enhance the comparability and credibility of the power consumption measurement results, and can also alleviate the problem of gradient vanishing or exploding, which is convenient for optimization in training the power consumption determination model.

[0119] Specifically, in order to convert the scores of the measurement input matrix in each power consumption interval into the probability distribution of the measurement input matrix in each power consumption interval, in an optional implementation, the output layer further includes a softmax function. The softmax function is used to convert the scores of the measurement input matrix predicted by each node in each power consumption interval into the probability distribution of the measurement input matrix in each power consumption interval.

[0120] The softmax function is a function for converting a quantity output into a probability distribution and making the sum of probabilities 1. The softmax function can be used to quickly obtain an accurate probability distribution when solving classification problems, and has strong stability when training the power consumption determination model.

[0121] Specifically, the formula of the softmax function is: Among them, C is the number of nodes in the output layer, z i is the probability value of the i-th node in the output layer, and e is a natural constant.

[0122] Furthermore, in order to facilitate the power consumption determination model to obtain the model input and facilitate the user to interact with the power consumption determination model, the power consumption determination model includes a structure for obtaining the model input. Specifically, in an optional implementation, Figure 4 As shown, the power consumption determination model further includes: an input layer 20, and the input layer is used to input the measurement input matrix.

[0123] Further, after obtaining the measurement input matrix as the measurement input matrix through the input layer, the power consumption determination model needs to process the data in the measurement input matrix to obtain the eigenvalues ​​related to the power consumption measurement result for determining the power consumption measurement result. Specifically, in an optional implementation, Figure 4 As shown, the power consumption determination model further includes: a hidden layer 30. Figure 5As shown, the hidden layer is used to sequentially execute step S41: extract the flip rate features in the measurement input matrix to obtain the flip rate feature matrix. Step S42: normalize the flip rate feature matrix. Step S43: reduce the feature dimension and feature quantity of the flip rate feature matrix after normalization to obtain the flip rate key feature matrix. Step S44: map the flip rate key feature matrix to the output layer. Thereby obtaining the eigenvalues ​​related to the power consumption measurement results.

[0124] It should be noted that the hidden layer also includes multiple parts to implement the above steps S41 to S44. Specifically, in an optional implementation, the hidden layer includes: a first convolutional layer 31, a normalization layer 32, an activation layer 33, a pooling layer 34, and a first fully connected layer 35.

[0125] Specifically, in an optional implementation, the first convolution layer 31 is used to execute step S41: perform convolution calculation on the measurement input matrix to extract the flip rate features in the measurement input matrix to obtain the flip rate feature matrix.

[0126] The first convolution layer 31 includes 4 convolution kernels, and the convolution kernel is a matrix with equal number of rows and columns. The convolution kernel is used to perform a convolution operation on the measured input matrix to obtain a flip rate feature. In an optional implementation, the convolution kernel is a convolution matrix with 3 rows and 3 columns. Since the first convolution layer 31 includes 4 convolution kernels, after the first convolution layer 31 completes the step S41, 4 flip rate feature matrices can be obtained.

[0127] It should be noted that when extracting the flip rate feature, the convolution kernel can choose any position of the measured input matrix as the starting point. For example, the part of the upper left corner of 3 rows and 3 columns in Table 1 is used as the starting point. At this time, the data in the convolution kernel includes ACT_rate(0,0), ACT_rate(0,1), ACT_rate(0,2), ACT_rate(1,0), ACT_rate(1,1), ACT_rate(1,2), ACT_rate(2,0), ACT_rate(2,1), ACT_rate(2,2). Then, the above 9 values ​​are convolved to obtain a first flip rate feature. The first flip rate feature is the value of the first row and first column of the flip rate feature matrix obtained by the convolution kernel.

[0128] Afterwards, the convolution kernel slides on the measurement input matrix, one row or one column at a time, until all the data of the measurement input matrix is ​​read. After each sliding of the convolution kernel, a convolution operation is performed again and the result is output to the flip rate feature matrix. The position of the flip rate feature output after the convolution kernel slides on the measurement input matrix moves the same distance in the flip rate feature matrix. For example, if the convolution kernel moves one column to the right, the flip rate feature output by the convolution kernel after the movement is located in the first row and second column of the flip rate feature matrix.

[0129] The formula for the convolution operation performed by the convolution kernel is: Among them, W is the weight value of the convolution kernel, m is the size of the convolution kernel, which is 3 here, x is the value of the original input, that is, the measured input matrix, u is the row number of the original input in the convolution matrix, v is the column number of the original input in the convolution matrix, i is the row number of the original input in the measured input matrix, and j is the column number of the original input in the measured input matrix.

[0130] Furthermore, in an optional implementation, the normalization layer 32 is also included after the convolution layer to execute step S42: normalizing the flip rate feature matrix. The normalization process can normalize the values ​​of the flip rate feature matrix to data with a mean of 0 and a variance of 1. This can speed up the training of the power consumption determination model, reduce the dependence of the power consumption determination model on the preset parameters input during initialization during training, and enhance the generalization ability of the power consumption determination model.

[0131] It should be noted that, in an optional implementation, the normalization method of the normalization layer 32 is batch normalization. The batch normalization needs to first calculate the mean and standard deviation of the flip rate feature in the flip rate feature matrix, then standardize the flip rate feature in the flip rate feature matrix based on the mean and standard deviation, and finally restore the feature expression ability of the flip rate feature through the learning parameters obtained during training.

[0132] Furthermore, in an optional implementation, if Figure 5 As shown, after step S42, step S421 is also included: performing activation function processing to transform the power consumption determination model from a linear model to a nonlinear model. In this way, the linear model can be transformed into a nonlinear model, thereby avoiding the gradient disappearance and resulting in failure to converge during the back propagation training process.

[0133] Correspondingly, the activation layer 33 is also included after the normalization layer 32, which is used to execute the step S421 after the flipping rate feature matrix is ​​normalized. Specifically, the method for performing activation function processing includes Sigmoid function, ELU function, tanh function, PReLU function, Maxout function, Softmax function, ReLU activation function or leaky ReLU activation function. Specifically, the activation function of the activation layer 33 is the ReLU activation function. The ReLU activation function maps the negative value of the power consumption determination model to the zeroth value, thereby converting the linear model of the determination model into a nonlinear model. The formula of the ReLU activation function is: f(x)=max(0,x), where X is the input of the activation layer 33.

[0134] Furthermore, in an optional implementation, the power consumption determination model further includes the pooling layer 34, which is used to perform step S43: extracting the key features of the flip rate from the flip rate feature matrix after normalization to reduce the feature dimension and feature quantity, and obtain the flip rate key feature matrix. In this way, the amount of data in the power consumption determination model can be reduced, thereby reducing the number of weight parameters of the subsequent fully connected layer, and filtering out some noise to avoid overfitting.

[0135] The pooling method of the pooling layer 34 includes maximum pooling or average pooling. Specifically, in an optional implementation, the method for extracting the flip rate key feature includes the maximum pooling method. That is, through the pooling convolution kernel of the pooling layer 34, multiple data in the flip rate feature matrix are selected, and the maximum value thereof is used as a flip rate key feature, thereby constructing a new flip rate key feature matrix. The number of pooling convolution kernels of the pooling layer 34 is consistent with the number of convolution kernels of the previous convolution layer of the pooling layer 34. The size of the pooling convolution kernel of the pooling layer 34 is determined according to the performance of the hardware. In an optional implementation, the size of the pooling convolution kernel of the pooling layer 34 is a convolution matrix of 2 rows and 2 columns. The calculation formula of the maximum pooling function of the pooling layer 34 is: Among them, X is the input of the pooling layer 34, X(p,q) is the value of the flip rate feature matrix at position (p,q), i is the row number of the output result in the flip rate key feature matrix, and j is the column number of the output result in the flip rate key feature matrix.

[0136] Furthermore, in order to obtain more accurate power consumption measurement results, in an optional implementation, the power consumption determination model also includes a second convolution layer for performing convolution calculations on the flip rate key feature matrix. This is to extract higher-level and more abstract features within the flip rate key feature matrix to obtain a power consumption feature matrix. It should be noted that the second convolution layer has 6 convolution kernels, so 6 power consumption feature matrices can be obtained.

[0137] Furthermore, after obtaining the power consumption characteristic matrix, it is also necessary to perform normalization, activation function, and pooling processing on the power consumption characteristic matrix. Therefore, in an optional implementation, the power consumption determination model also includes a set of normalization layers 32, activation layers 33, and pooling layers 34 corresponding to the second convolution layer. After passing through the second convolution layer, and the normalization layer 32, activation layer 33, and pooling layer 34 corresponding to the second convolution layer, 6 power consumption key characteristic matrices can be obtained.

[0138] Furthermore, after obtaining the power consumption key feature matrix, in an optional implementation, the power consumption determination model further includes the first fully connected layer 35, which is used to perform step S44: performing a convolution operation on the flip rate key feature matrix, and providing the convolution operation result to the output layer. In this way, the power consumption key feature matrix can be converted into eigenvalues ​​related to the power consumption measurement result, so as to predict the score of the measurement input matrix in each power consumption interval, and then obtain the power consumption measurement result.

[0139] Specifically, in an optional implementation, the number of neurons in the first fully connected layer 35 is 1024. In the first fully connected layer 35, each neuron is a group of convolution kernels, and there are 1024 groups of convolution kernels in total. The number of convolution kernels in each group of convolution kernels is the same as the number of convolution kernels in the pooling layer 34 of the previous layer of the first fully connected layer 35. For example, when there is a second convolution layer, the pooling layer 34 corresponding to the second convolution layer has 6 convolution kernels, so there are 6 convolution kernels in each group of convolution kernels in the first fully connected layer 35, and there are 1024*6 convolution kernels in total in the fully connected layer. And the size of each convolution kernel is equal to the size of the pooling layer 34 of the previous layer of the first fully connected layer 35. For example, if the size of the pooling layer 34 of the previous layer of the first fully connected layer 35 is 32 rows and 32 columns, then the size of each convolution kernel of the first fully connected layer 35 is 32 rows and 32 columns.

[0140] The output formula of the jth neuron in the first fully connected layer 35 is: Wherein, w is the weight, x is the input, n is the nth neuron of the pooling layer 34, u is the row number, v is the column number, and j=0, 1, 2, ..., 1023. In this way, the first fully connected layer 35 can output a total of 1024 convolution operation results. A total of 1024*6*32*32=6291456 weight values ​​are required in the first fully connected layer 35.

[0141] Furthermore, in order to select and amplify the features with the strongest correlation with the power consumption measurement and suppress irrelevant features or noise features. In an optional implementation, the power consumption determination model also includes a second fully connected layer, which is used to perform a convolution operation on the result of the first convolution layer 31 and provide the convolution operation result to the output layer. The number of convolution kernels in the second fully connected layer is the same as the number of neurons in the first convolution layer 31, which is 1024.

[0142] It should be noted that each convolution kernel of the second fully connected layer needs to process all 1024 convolution operation results output by the first fully connected layer 35, and the output formula of the jth convolution kernel of the second fully connected layer is: Wherein, w is the weight, x is the input, u is the row number, v is the column number, and j = 0, 1, 2, ..., 1023. In this way, the second fully connected layer can also output a total of 1024 convolution operation results. A total of 1024*1024 = 1048576 weight values ​​are required in the second fully connected layer.

[0143] It should be noted that if it is necessary to further select and amplify the features that are most relevant to power consumption measurement and suppress irrelevant features or noise features, more fully connected layers can be designed. The structure of the more fully connected layers is the same as that of the second fully connected layer, and will not be repeated here.

[0144] In this way, by using the flip rate of each flip signal of multiple functional modules of the circuit design as the input for measuring power consumption, and using the power consumption determination model, the probability distribution of the circuit design output by the power consumption determination model in multiple power consumption intervals can be obtained based on the flip rate, and the power consumption measurement result can be obtained more accurately. Furthermore, using the probability distribution of multiple power consumption intervals as the power consumption measurement result instead of directly calculating the specific value of the power consumption can reduce the calculation amount of the power consumption determination model and improve the measurement efficiency while ensuring the measurement accuracy.

[0145] The embodiment of the present application also provides a method for obtaining a power consumption calculation model, by training the power consumption determination model, so that the result of using the power consumption determination model to calculate the power consumption of the chip is more accurate. As an optional implementation, Figure 6 FIG. 1 is a flow chart showing a method for obtaining a power consumption calculation model provided in an embodiment of the present application. Figure 6 As shown, the method for obtaining the power consumption calculation model provided in the embodiment of the present application includes the following steps.

[0146] Step S51: Acquire circuit design pre-silicon simulation data.

[0147] It should be noted that in order to obtain better training results, multiple groups of test scenarios can be designed when obtaining pre-silicon simulation data of the circuit design to obtain simulation data of the circuit design under each pre-silicon test scenario. In an optional implementation, the simulation data includes a waveform fsdb file of the circuit design and the number of flips of each flip signal of multiple functional modules. The number of flips is used to subsequently calculate the flip rate of each flip signal of multiple functional modules.

[0148] In order to obtain the number of flips, in an optional implementation, the circuit design includes multiple counters. Figure 3 For example, the circuit design includes functional modules 0 to 4. Each functional module needs to be connected to at least one counter, and the four functional modules are connected to a total of 7 counters, namely counters 11 to 17. Each counter corresponds to a flip signal of the functional module, namely flip signal 0 to flip signal 6. Each time a flip signal flips, the counter corresponding to the flip signal accumulates 1, and the counting result of the counter is stored in the register as the flip number of the flip signal for the software to read.

[0149] The waveform fsdb file is a file that represents the complete spectrum width of a waveform in digital signal processing. It is used in electronic design automation tools to store and analyze the simulation results of digital circuits. The waveform fsdb file can effectively process a large amount of waveform data, which is convenient for designing and verifying complex digital systems. The waveform fsdb file can accurately obtain the simulated dynamic power consumption of the design to be tested during the simulation process, as well as the simulated dynamic power consumption of each functional module in the design to be tested.

[0150] Step S52: Determine the simulated dynamic power consumption of the circuit design and the flip rate of each flip signal of multiple functional modules of the circuit design according to the simulation data.

[0151] Specifically, in an optional implementation, the flip rate of each flip signal of the multiple functional modules can be obtained according to the flip number of each flip signal of the multiple functional modules. For example, when calculating the flip rate, a preset time window can be set, and the flip number of the flip signal in the time window can be counted, and then the number of signal flips of the flip signal in a time period can be calculated, which is converted into a flip rate. Further, the time of the time window for counting the flip number of the flip signal can be set as a unit time. For example, the time of the time window is uniformly set to 1us, so as to detect the flip number of each flip signal within 1us during the operation of the circuit to calculate the flip rate. For example, a flip signal flips once within 1us, and the flip rate of the flip signal is 1 time / 1us=1MHz, and the unit of the count value is MHz. For example, if a signal flips 200 times within 1us, the flip rate of the signal is 200MHz.

[0152] Step S53: constructing training input data according to the flipping rates of the flipping signals of the plurality of functional modules, and determining the real label of the training input data according to the simulated dynamic power consumption. The real label indicates that the circuit design is in the real power consumption interval corresponding to the training input data.

[0153] It should be noted that determining the true label of the training input data according to the simulated dynamic power consumption includes determining the power consumption interval described in the simulated dynamic power consumption as the true power consumption interval.

[0154] Furthermore, in an optional implementation, if Figure 7 As shown, the step S53 includes step S531: constructing a training input matrix as the measurement input matrix according to the flip rates of the flip signals of the multiple functional modules of the circuit design. The training input matrix includes a functional module dimension indicating the multiple functional modules and a flip signal dimension indicating the multiple flip signals, and one data of the functional module dimension and the flip signal dimension in the training input matrix represents the flip rate of one flip signal of one functional module.

[0155] Furthermore, the neural network model is the power consumption determination model before training, so the structure of the neural network model is the same as that of the power consumption determination model. In an optional implementation, the neural network model includes: an input layer for inputting the measurement input matrix.

[0156] The hidden layer is used to extract the flip rate features in the training input matrix to obtain a flip rate feature matrix; normalize the flip rate feature matrix, and reduce the feature dimension and feature quantity of the flip rate feature matrix after normalization to obtain a flip rate key feature matrix; map the flip rate key feature matrix to the output layer.

[0157] Furthermore, in an optional implementation, if Figure 4 As shown, the hidden layer includes: a first convolutional layer 31, a normalization layer 32, an activation layer 33, a pooling layer 34, and a first fully connected layer 35;

[0158] The first convolution layer 31 is used to perform convolution calculation on the training input matrix to extract the flip rate feature in the training input matrix to obtain a flip rate feature matrix;

[0159] The normalization layer 32 is used to normalize the flip rate feature matrix.

[0160] The activation layer 33 is used to perform activation function processing after the flip rate feature matrix is ​​normalized, so as to transform the power consumption determination model from a linear model to a nonlinear model.

[0161] The pooling layer 34 is used to extract the flip rate key features from the flip rate feature matrix after normalization, so as to reduce the feature dimension and the number of features and obtain the flip rate key feature matrix.

[0162] It should be noted that the first convolution layer 31, and the normalization layer 32, activation layer 33 and pooling layer 34 corresponding to the first convolution layer 31, are a set of structures for extracting the features of the flip rate feature matrix. The neural network model may also include a second convolution layer and a normalization layer 32, activation layer 33 and pooling layer 34 corresponding to the second convolution layer to further refine the features.

[0163] The first fully connected layer 35 is used to perform a convolution operation on the flip rate key feature matrix and provide the convolution operation result to the output layer.

[0164] Furthermore, in order to select and amplify the features with the strongest correlation with the power consumption measurement and suppress irrelevant features or noise features. In an optional implementation, the power consumption determination model also includes a second fully connected layer, which is used to perform a convolution operation on the result of the first convolution layer 31 and provide the convolution operation result to the output layer. The number of convolution kernels in the second fully connected layer is the same as the number of neurons in the first convolution layer 31.

[0165] The neural network model also includes an output layer; the output layer includes a plurality of nodes, one node corresponds to a power consumption interval, and is used to predict the score of the measured input matrix in the corresponding power consumption interval. In this way, the power consumption determination model can predict the input data in the corresponding power consumption interval based on the score of the measured input matrix in the corresponding power consumption interval, without obtaining a specific power consumption value. Thus, the amount of calculation is reduced while ensuring the prediction accuracy.

[0166] Please continue to refer to Figure 6 The method for obtaining the power consumption calculation model further includes step S54: training the neural network model according to the training input data with the training goal of minimizing the error between the predicted label output by the neural network model and the true label. The predicted label indicates the probability distribution of each power consumption interval corresponding to the training input data predicted by the neural network model.

[0167] Furthermore, in an optional implementation, if Figure 7 As shown, the step S54 includes step S541: according to the training input data, the model parameters of the neural network model are iteratively adjusted by the gradient descent method to minimize the total loss of the training set to obtain the trained neural network model. The total loss of the training set is represented by a loss function, and the loss function is used to calculate the error between the predicted label and the true label; the training set includes multiple training input data, and one training input data corresponds to the simulation data corresponding to the verification case of the circuit design in a test scenario.

[0168] It should be noted that the training input data of each of the test scenarios includes the training input matrix of the circuit design under the test scenario and the actual power consumption label. In an optional implementation, the step S541 includes iteratively adjusting the model parameters of the neural network model by the gradient descent method according to the training input data until the loss function of the neural network model reaches a certain value and no longer converges. The loss function (Loss Function) is a function that measures the gap between the predicted label and the true label of the neural network model. Models of different task types use different loss functions, including regression loss functions and classification loss functions. Specifically, the loss function of the neural network model is a classification loss function.

[0169] In the iterative adjustment of the model parameters of the neural network model by the gradient descent method, the model parameters include the parameters in the convolution layer and the parameters in the fully connected layer. Further, in an optional implementation, as Figure 7 As shown, before step S541, step S542 is also included: initializing the parameters of the convolutional layer and the fully connected layer. Specifically, the initialization method is to assign values ​​to the parameters of the convolutional layer and the fully connected layer. The values ​​assigned to the parameters of the convolutional layer and the fully connected layer are preset values ​​determined based on experience, or random values.

[0170] Please continue to refer to Figure 6 The method for acquiring the power consumption calculation model further includes step S55: using the trained neural network model as a power consumption determination model.

[0171] In this way, the required power consumption determination model can be obtained through the above-mentioned method for obtaining the power consumption calculation model. Then, the flip rate of each flip signal of multiple functional modules of the circuit design is used as the input for measuring power consumption, and the power consumption determination model is used to obtain the probability distribution of the circuit design output by the power consumption determination model in multiple power consumption intervals based on the flip rate, so that the power consumption measurement result can be obtained more accurately. Then, the probability distribution of multiple power consumption intervals is used as the power consumption measurement result, instead of directly calculating the specific value of the power consumption, which can reduce the calculation amount of the power consumption determination model and improve the measurement efficiency while ensuring the measurement accuracy.

[0172] The embodiment of the present application also provides a power consumption measurement device for a circuit design, which obtains the power consumption of the circuit design by calling a pre-trained power consumption determination model to more accurately calculate the power consumption of the chip. As an optional implementation, Figure 8 The schematic diagram of the structure of the power consumption measurement device of the circuit design provided in the embodiment of the present application is shown. Figure 8 As shown, the power consumption measurement device of the circuit design provided in the embodiment of the present application includes the following structure.

[0173] A measurement data acquisition module 100, configured to construct a measurement input matrix according to operation data of the circuit design, wherein the measurement input matrix at least includes the flip rate of each flip signal of a plurality of functional modules of the circuit design;

[0174] The power consumption determination model calling module 200 is used to call a pre-trained power consumption determination model, wherein the power consumption determination model is trained to minimize the error between the predicted label and the real label; wherein the real label indicates the real power consumption interval corresponding to the training input data of the circuit design, and the predicted label indicates the probability distribution of each power consumption interval corresponding to the training input data predicted by the power consumption determination model;

[0175] The training data input module 300 is used to use the measurement input matrix as the input of the power consumption determination model, and use the power consumption determination model to process the measurement input matrix to obtain the probability distribution of the circuit design output by the power consumption determination model in multiple power consumption intervals as the power consumption measurement result.

[0176] Further, in an optional implementation, the measurement data acquisition module 100 includes: acquiring the flip rate of each flip signal of multiple functional modules of the circuit design from the operation data of the circuit design; constructing a measurement input matrix according to the flip rate of each flip signal of the multiple functional modules of the circuit design, wherein the measurement input matrix includes a functional module dimension indicating multiple functional modules, and a flip signal dimension indicating multiple flip signals, and a data of the functional module dimension and the flip signal dimension in the measurement input matrix represents the flip rate of a flip signal of a functional module.

[0177] Furthermore, in an optional implementation, the power consumption determination model includes: an output layer; the output layer includes multiple nodes, one node corresponds to a power consumption interval, and is used to predict the score of the measurement input matrix in the corresponding power consumption interval. The training data input module 300 includes: inputting the measurement input matrix into the power consumption determination model, using each node of the output layer to predict the score of the measurement input matrix in each power consumption interval; converting the score of the measurement input matrix in each power consumption interval into the probability distribution of the measurement input matrix in each power consumption interval, so as to obtain the probability distribution of the circuit design in multiple power consumption intervals as the power consumption measurement result.

[0178] Furthermore, in an optional implementation, the power consumption determination model also includes: an input layer and a hidden layer; the input layer is used to input the measured input matrix; the hidden layer is used to extract the flip rate features in the measured input matrix to obtain a flip rate feature matrix; normalizing the flip rate feature matrix, and reducing the feature dimension and feature quantity of the flip rate feature matrix after normalization to obtain a flip rate key feature matrix; mapping the flip rate key feature matrix to the output layer.

[0179] Furthermore, in an optional implementation, the power consumption measurement result is used for power consumption optimization decision of the circuit design, and the power consumption optimization decision includes adjusting the operating frequency and / or voltage of the circuit design.

[0180] The embodiment of the present application also provides a device for obtaining a power consumption calculation model, which trains the power consumption determination model to make the result of using the power consumption determination model to calculate the power consumption of the chip more accurate. As an optional implementation, Figure 8 FIG. 1 is a schematic diagram showing a structure of a device for obtaining a power consumption calculation model provided in an embodiment of the present application. Figure 8 As shown, the device for acquiring the power consumption calculation model provided in the embodiment of the present application includes the following structure.

[0181] The simulation data acquisition module 400 is used to acquire simulation data before circuit design silicon.

[0182] A simulation data processing module 500, for determining the simulated dynamic power consumption of the circuit design and the flip rate of each flip signal of multiple functional modules of the circuit design according to the simulation data;

[0183] The training data acquisition module 600 is used to construct training input data according to the flipping rates of the flipping signals of the plurality of functional modules, and to determine the real label of the training input data according to the simulated dynamic power consumption; the real label indicates that the circuit design is in the real power consumption interval corresponding to the training input data;

[0184] The model training module 700 is used to train the neural network model according to the training input data, with the goal of minimizing the error between the predicted label and the true label output by the neural network model; wherein the predicted label indicates the probability distribution of each power consumption interval corresponding to the training input data predicted by the neural network model; and the trained neural network model is used as a power consumption determination model.

[0185] Further, in an optional implementation, the training data acquisition module 600 includes: constructing a training input matrix as the training input data according to the flip rates of each flip signal of multiple functional modules of the circuit design; wherein the training input matrix includes a functional module dimension indicating multiple functional modules, and a flip signal dimension indicating multiple flip signals, and a data of the functional module dimension and the flip signal dimension in the training input matrix represents the flip rate of a flip signal of a functional module.

[0186] Furthermore, in an optional implementation, the neural network model includes: an input layer for inputting the training input data; a hidden layer for extracting the flip rate features in the training input matrix to obtain a flip rate feature matrix; normalizing the flip rate feature matrix, and reducing the feature dimension and feature quantity of the flip rate feature matrix after normalization to obtain a flip rate key feature matrix; mapping the flip rate key feature matrix to the output layer; the output layer; the output layer includes multiple nodes, one node corresponds to a power consumption interval, and is used to predict the score of the training input data in the corresponding power consumption interval.

[0187] An embodiment of the present application also provides a computer device, including a memory and a processor, wherein the memory stores computer instructions, and the processor calls the computer instructions stored in the memory to execute a power consumption measurement method for a circuit design as provided in an embodiment of the present application, and / or a method for obtaining a power consumption calculation model as provided in an embodiment of the present application.

[0188] An embodiment of the present application also provides a storage medium, which stores a design program for a chip. When the design program is executed, it implements a power consumption measurement method for a circuit design such as steps S10 to S44, and / or a method for obtaining a power consumption calculation model such as steps S51 to S55.

[0189] An embodiment of the present application also provides a computer program product, which, when executed, implements a method for measuring power consumption of a circuit design such as steps S10 to S44, and / or a method for acquiring a power consumption calculation model such as steps S51 to S55.

[0190] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A method for measuring power consumption of a circuit design, characterized in that: include: Constructing a measurement input matrix according to the operation data of the circuit design, wherein the measurement input matrix at least includes the flip rate of each flip signal of multiple functional modules of the circuit design; And, calling a pre-trained power consumption determination model, wherein the power consumption determination model is trained to minimize the error between the predicted label and the real label; wherein the real label indicates the real power consumption interval corresponding to the training input data of the circuit design, and the predicted label indicates the probability distribution of each power consumption interval corresponding to the training input data predicted by the power consumption determination model; The measurement input matrix is ​​used as the input of the power consumption determination model, and the power consumption determination model is used to process the measurement input matrix to obtain the probability distribution of the circuit design output by the power consumption determination model in multiple power consumption intervals as the power consumption measurement result.

2. The method for measuring power consumption of a circuit design according to claim 1, wherein: The constructing of the measurement input matrix according to the operation data of the circuit design comprises: Obtaining the flip rate of each flip signal of multiple functional modules of the circuit design from the operation data of the circuit design; A measurement input matrix is ​​constructed according to the toggle rates of each toggle signal of multiple functional modules of the circuit design; wherein the measurement input matrix includes a functional module dimension indicating multiple functional modules, and a toggle signal dimension indicating multiple toggle signals, and a data of the functional module dimension and the toggle signal dimension in the measurement input matrix represents the toggle rate of a toggle signal of a functional module.

3. The method for measuring power consumption of a circuit design according to claim 2, wherein: The power consumption determination model comprises: an output layer; the output layer comprises a plurality of nodes, one node corresponds to one power consumption interval, and is used to predict the score of the measurement input matrix in the corresponding power consumption interval; The step of using the measurement input matrix as an input of the power consumption determination model and processing the measurement input matrix using the power consumption determination model to obtain a probability distribution of the circuit design output by the power consumption determination model in multiple power consumption intervals as a power consumption measurement result includes: Inputting the measurement input matrix into the power consumption determination model, and using each node of the output layer to predict the score of the measurement input matrix in each power consumption interval; The scores of the measurement input matrix in each power consumption interval are converted into probability distributions of the measurement input matrix in each power consumption interval, so as to obtain probability distributions of the circuit design in multiple power consumption intervals as power consumption measurement results.

4. The method for measuring power consumption of a circuit design as claimed in claim 3, characterized in that: The output layer also includes a softmax function, which is used to convert the scores of the measurement input matrix predicted by each node in each power consumption interval into the probability distribution of the measurement input matrix in each power consumption interval.

5. The method for measuring power consumption of a circuit design as claimed in claim 3, characterized in that: The power consumption determination model also includes: an input layer and a hidden layer; The input layer is used to input the measurement input matrix; The hidden layer is used to extract the flip rate features in the measurement input matrix to obtain a flip rate feature matrix; normalize the flip rate feature matrix, and reduce the feature dimension and feature quantity of the flip rate feature matrix after normalization to obtain a flip rate key feature matrix; map the flip rate key feature matrix to the output layer.

6. The method for measuring power consumption of a circuit design as claimed in claim 5, characterized in that: The hidden layer includes: a first convolutional layer, a normalization layer, an activation layer, a pooling layer, and a first fully connected layer; The first convolution layer is used to perform convolution calculation on the measurement input matrix to extract the flip rate feature in the measurement input matrix to obtain the flip rate feature matrix; The normalization layer is used to perform normalization processing on the flip rate feature matrix; The activation layer is used to perform activation function processing after the flip rate feature matrix is ​​normalized, so as to transform the power consumption determination model from a linear model to a nonlinear model; The pooling layer is used to extract the key features of the flip rate from the flip rate feature matrix after normalization, so as to reduce the feature dimension and the number of features and obtain the flip rate key feature matrix; The first fully connected layer is used to perform a convolution operation on the flip rate key feature matrix and provide the convolution operation result to the output layer.

7. The method for measuring power consumption of a circuit design according to claim 6, wherein: The first convolution layer includes 4 convolution kernels, and the convolution kernel includes a convolution matrix with 3 rows and 3 columns. The convolution kernel is used to perform convolution calculation on the data in the convolution matrix to extract the flipping rate features in the measurement input matrix and store them in the flipping rate feature matrix.

8. The method for measuring power consumption of a circuit design as claimed in claim 6, characterized in that: The normalization layer includes calculating the mean and standard deviation of the flip rate features of the flip rate feature matrix; standardizing the flip rate features of the flip rate feature matrix based on the mean and standard deviation, and restoring the feature expression capability of the flip rate features.

9. The method for measuring power consumption of a circuit design according to claim 6, wherein: The activation layer includes a ReLU activation function for mapping negative values ​​of the power consumption determination model to a zeroth value.

10. The method for measuring power consumption of a circuit design according to claim 6, wherein: The pooling layer includes a plurality of pooling convolution kernels, and the pooling convolution kernel is a convolution matrix with 2 rows and 2 columns, which is used to pool the data in the pooling convolution matrix; The pooling convolution kernel includes a maximization function for selecting the largest data in the pooling convolution matrix as output.

11. The method for measuring power consumption of a circuit design according to claim 6, wherein: The first fully connected layer includes 1024 neurons, each of which includes a plurality of convolution kernels, each of which includes a convolution matrix, and the convolution kernel is used to perform convolution calculation on the data in the convolution matrix, and provide the convolution operation result to the output layer.

12. The method for measuring power consumption of a circuit design according to claim 1, wherein: The power consumption measurement result is used for power consumption optimization decision of the circuit design, and the power consumption optimization decision includes adjusting the operating frequency and / or voltage of the circuit design.

13. A method for obtaining a power consumption calculation model, characterized in that: include: Get pre-silicon simulation data for circuit design; Determining the simulated dynamic power consumption of the circuit design and the flip rate of each flip signal of multiple functional modules of the circuit design according to the simulation data; constructing training input data according to the flipping rates of the flipping signals of the plurality of functional modules, and determining the true labels of the training input data according to the simulated dynamic power consumption; The real label indicates that the circuit design is in the real power consumption interval corresponding to the training input data; According to the training input data, the neural network model is trained with the goal of minimizing the error between the predicted label and the true label output by the neural network model; wherein the predicted label indicates the probability distribution of each power consumption interval corresponding to the training input data predicted by the neural network model; The trained neural network model is used as the power consumption determination model.

14. The method for obtaining the power consumption calculation model according to claim 13, characterized in that: The method of constructing training input data according to the flipping rates of each flipping signal of multiple functional modules includes: constructing a training input matrix as the training input data according to the flipping rates of each flipping signal of multiple functional modules of the circuit design; wherein the training input matrix includes a functional module dimension indicating multiple functional modules, and a flipping signal dimension indicating multiple flipping signals, and one data of the functional module dimension and the flipping signal dimension in the training input matrix represents the flipping rate of one flipping signal of one functional module.

15. The method for obtaining the power consumption calculation model according to claim 13, characterized in that: The neural network model includes: An input layer, used for inputting the training input data; The hidden layer is used to extract the flip rate features in the training input matrix to obtain a flip rate feature matrix; normalize the flip rate feature matrix, and reduce the feature dimension and feature quantity of the flip rate feature matrix after the normalization process to obtain a flip rate key feature matrix; and map the flip rate key feature matrix to the output layer; Output layer; the output layer includes multiple nodes, one node corresponds to a power consumption interval, and is used to predict the score of the training input data in the corresponding power consumption interval.

16. The method for obtaining the power consumption calculation model according to claim 15, characterized in that: The hidden layer includes: a first convolutional layer, a normalization layer, an activation layer, a pooling layer, and a first fully connected layer; The first convolution layer is used to perform convolution calculation on the training input matrix to extract the flip rate feature in the training input matrix to obtain a flip rate feature matrix; The normalization layer is used to perform normalization processing on the flip rate feature matrix; The activation layer is used to perform activation function processing after the flip rate feature matrix is ​​normalized, so as to transform the power consumption determination model from a linear model to a nonlinear model; The pooling layer is used to extract the key features of the flip rate from the flip rate feature matrix after normalization, so as to reduce the feature dimension and the number of features and obtain the flip rate key feature matrix; The first fully connected layer is used to perform a convolution operation on the flip rate key feature matrix and provide the convolution operation result to the output layer.

17. The method for acquiring the power consumption calculation model according to claim 13, characterized in that: According to the training input data, minimizing the error between the predicted label and the true label output by the neural network model is taken as the training goal, and training the neural network model includes: According to the training input data, the model parameters of the neural network model are iteratively adjusted by the gradient descent method to minimize the total loss of the training set, thereby obtaining a trained neural network model; wherein the total loss of the training set is represented by a loss function, and the loss function is used to calculate the error between the predicted label and the true label; the training set includes multiple training input data, and one training input data corresponds to simulation data corresponding to a verification case of a circuit design in a pre-silicon test scenario.

18. A power consumption measurement device for a circuit design, characterized in that: include: A measurement data acquisition module, used to construct a measurement input matrix according to the operation data of the circuit design, wherein the measurement input matrix at least includes the flip rate of each flip signal of multiple functional modules of the circuit design; A power consumption determination model calling module, used to call a pre-trained power consumption determination model, wherein the power consumption determination model is trained to minimize the error between the predicted label and the real label; wherein the real label indicates the real power consumption interval corresponding to the training input data of the circuit design, and the predicted label indicates the probability distribution of each power consumption interval corresponding to the training input data predicted by the power consumption determination model; A training data input module is used to use the measurement input matrix as the input of the power consumption determination model, and use the power consumption determination model to process the measurement input matrix to obtain the probability distribution of the circuit design output by the power consumption determination model in multiple power consumption intervals as the power consumption measurement result.

19. A device for acquiring a power consumption calculation model, characterized in that: include: A simulation data acquisition module, used to acquire simulation data before circuit design silicon; A simulation data processing module, used to determine the simulated dynamic power consumption of the circuit design and the flip rate of each flip signal of multiple functional modules of the circuit design according to the simulation data; A training data acquisition module, used to construct training input data according to the flip rate of each flip signal of multiple functional modules, and determine the real label of the training input data according to the simulated dynamic power consumption; The real label indicates that the circuit design is in the real power consumption interval corresponding to the training input data; A model training module is used to train a neural network model based on the training input data, with the goal of minimizing the error between the predicted label and the true label output by the neural network model; wherein the predicted label indicates the probability distribution of each power consumption interval corresponding to the training input data predicted by the neural network model; and the trained neural network model is used as a power consumption determination model.

20. A computing device, characterized in that It includes a memory and a processor, the memory stores computer instructions, and the processor calls the computer instructions stored in the memory to execute the power consumption measurement method of the circuit design as described in any one of claims 1 to 12, and / or the method for obtaining the power consumption calculation model as described in any one of claims 13 to 17.

21. A storage medium, characterized in that: The storage medium stores a design program of the chip, and when the design program is executed, it implements the power consumption measurement method of the circuit design as described in any one of claims 1-12, and / or the method for obtaining the power consumption calculation model as described in any one of claims 13-17.

22. A computer program product, characterized in that When the computer program product is executed, it implements the power consumption measurement method of the circuit design as described in any one of claims 1-12, and / or the method for obtaining the power consumption calculation model as described in any one of claims 13-17.

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