ECO basic unit structure, layout method and system

Abstract

The invention relates to an ECO basic unit structure, a layout method and a layout system. The IC structure includes first to third n-wells aligned in a first direction in a semiconductor substrate, wherein the first n-well is separated from each of the second and third n-wells by a corresponding space; a first plurality of active regions, a gate structure, and a metalloid definition (MD) segment covering and electrically connected to the active region in the first n-well; a first tap structure covering and electrically connected to the second n-well; a second tap structure covering and electrically connected to the third n-well; and a first metal segment extending in the first direction, covering the first plurality of transistors, and electrically connected to each of the first and second tap structures.

Description

Technical Field

[0001] The present disclosure relates to an ECO basic unit structure, a layout method and a system. Background Art

[0002] The continuing trend of integrated circuit (IC) miniaturization has resulted in increasingly smaller devices that consume less power but provide more functionality at higher speeds than previous technologies. Miniaturization has been achieved through innovations in design and manufacturing that are closely tied to increasingly stringent specifications. Various electronic design automation (EDA) tools are used to generate, modify, and verify the design of semiconductor devices while ensuring that design and manufacturing specifications are met. Summary of the invention

[0003] According to one aspect of the present disclosure, an integrated circuit (IC) structure is provided, comprising: first to third n-wells aligned along a first direction in a semiconductor substrate, wherein the first n-well is separated from each of the second and third n-wells by a corresponding space; a first plurality of active regions, gate structures, and metal-like definition (MD) segments covering and electrically connected to the active regions located in the first n-well; a first tap structure covering and electrically connected to the second n-well; a second tap structure covering and electrically connected to the third n-well; and a first metal segment extending in the first direction, covering a first plurality of transistors, and electrically connected to each of the first and second tap structures.

[0004] According to one aspect of the present disclosure, a method for generating an integrated circuit (IC) layout diagram is provided, the method comprising: aligning first to third n-well regions along a first direction in the IC layout diagram, wherein the first n-well region is separated from each of the second and third n-well regions by a distance at least corresponding to a minimum n-well spacing rule; positioning a first tap via region in the second n-well region; positioning a second tap via region in the third n-well region; placing a first engineering change order (ECO) basic unit in the first n-well region; establishing a first electrical connection between the second and third n-well regions by overlapping each of the first and second tap via regions with a first metal region extending across the first n-well region in the first direction; and storing the IC layout diagram in a storage device.

[0005] According to one aspect of the present disclosure, an electronic design automation (EDA) system is provided, comprising: a processor; and a non-transitory computer-readable storage medium comprising computer program codes for one or more programs, wherein the non-transitory computer-readable storage medium and the computer program codes are configured to utilize the processor so that the processor performs the following operations: positioning a first tap via region in a second n-well region of a first to third n-well region of an integrated circuit (IC) layout diagram, the first n-well region being separated from each of the second and third n-well regions along a first direction by a distance at least corresponding to a minimum n-well spacing rule; positioning a second tap via region in the third n-well region; placing a first engineering change order (ECO) basic cell in the first n-well region; overlapping each of the first and second tap via regions with a first metal region extending across the first n-well region in the first direction, thereby establishing a first electrical connection between the second and third n-well regions; routing a first voltage distribution path to the first electrical connection, the first voltage distribution path being configured to distribute a first voltage level; and storing the IC layout diagram in a storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the size of various features can be arbitrarily increased or reduced.

[0007] Figure 1 is a diagram of an IC layout and a corresponding IC structure according to some embodiments.

[0008] Figure 2 is a diagram of an IC layout and a corresponding IC structure according to some embodiments.

[0009] Figure 3 is a diagram of an IC layout and a corresponding IC structure according to some embodiments.

[0010] Figure 4 is a diagram of an IC layout and a corresponding IC structure according to some embodiments.

[0011] Figure 5 is a diagram of an IC layout and a corresponding IC structure according to some embodiments.

[0012] Figure 6 is a diagram of an IC layout and a corresponding IC structure according to some embodiments.

[0013] Figure 7 is a diagram of an IC layout and a corresponding IC structure according to some embodiments.

[0014] Figure 8 is a diagram of an IC layout and a corresponding IC structure according to some embodiments.

[0015] Fig. 9 is a flow chart of a method of generating an IC layout diagram according to some embodiments.

[0016] Fig.10 is a block diagram of an IC design system according to some embodiments.

[0017] Fig.11 is a block diagram of an integrated circuit (IC) manufacturing system and an IC manufacturing flow associated therewith, according to some embodiments. DETAILED DESCRIPTION

[0018] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. In order to simplify the present disclosure, specific examples of components, values, operations, materials, arrangements, etc. are described below. Of course, these are examples only and are intended to be limited. Other components, values, operations, materials, arrangements, etc. may also be taken into account. For example, in the following description, forming a first feature on or on a second feature may include an embodiment in which the first feature and the second feature are formed in a direct contact manner, and may also include an embodiment in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of brevity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0019] Additionally, spatially relative terms (e.g., "below," "lower," "above," "higher," etc.) may be used herein to facilitate describing the relationship of one element or feature shown in a figure relative to another element(s) or feature(s). These spatially relative terms are also intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be similarly interpreted accordingly.

[0020] In various embodiments, an integrated circuit (IC) structure, a layout diagram, and an IC design system involve two types of standard cells: standard functional cells and standard spare cells, the latter of which are referred to as engineering change order (ECO) cells. Standard functional cells are defined using a specific internal arrangement of components to provide (in operation) corresponding common lower-level functions, for example, logic functions including inverters, NAND, NOR, XOR, D latches, decoupling capacitors (DeCap), AND-OR-NON (AOI), OR-AND-NON (OAI), multiplexers, flip-flops, etc.

[0021] ECO cells include ECO basic cells and ECO programming cells. ECO programming cells refer to ECO basic cells that have been programmed. Similar to functional cells, ECO basic cells are defined by a specific internal arrangement of components. Unlike functional cells, ECO basic cells are not configured to provide specific functions. In contrast to standard cells that operate (are operational), ECO basic cells (not yet programmed) do not operate (are non-operating).

[0022] Recall that the ECO cells are spare cells, and if necessary, the arrangement of the ECO cells is sufficient to enable the ECO cells to be "programmed" (converted) to operate and provide one of the same common lower-level functions provided by the corresponding standard functional cells. In some embodiments, the arrangement of each ECO cell is sufficient to enable a given ECO cell to be "programmed" (converted) to operate and provide one of the logic functions including inverters, NAND, NOR, XOR, D latches, decoupling capacitors (DeCap), AND-OR-NON (AOI), OR-AND-NON (OAI), multiplexers, flip-flops, etc. In some embodiments, the ECO cells are programmed (converted) to ECO programming cells by changing one or more connections (connections within the ECO cells) within at least one ECO cell (e.g., metal-to-silicon contacts and / or metal-to-polysilicon contacts), or other metal layer changes using corresponding vias or contacts.

[0023] In some applications, electronic design automation (EDA) tools are used to select standard functional cells from a standard cell library and place the standard functional cells together with non-standard cells (if any) in an initial layout. EDA tools are also used to perform routing, through which standard functional cells and non-standard cells are connected using one or more metal layers and corresponding through holes and contacts. EDA tools are also used to test routing. According to the test results, the selection, placement and routing of standard and non-standard cells are modified. In at least some embodiments, the overall selection, placement, routing and testing (SPRT) process is iterative. Finally, the SPRT process iteration converges on the final layout.

[0024] A near-final layout (or a layout that is otherwise considered final) may need to be modified for a variety of reasons (e.g., design changes, unacceptable timing issues, unacceptable electromigration issues, etc.) In anticipation of relatively minor modifications, and as a safeguard (or precaution) against having to restart (start over again) the iterative SPRT process, the EDA tool is also used to place one or more ECO primitives in the initial layout.

[0025] Because the ECO basic cells are not operational, the ECO basic cells are not connected to the functional cells. When the final layout is to be modified, one or more ECO basic cells undergo "programming", which converts one or more ECO basic cells into one or more ECO "programmed" cells. The ECO programmed cells are then wired to be operationally connected to one or more standard functional cells.

[0026] In various embodiments discussed below, the ECO basic cell can be placed in one of a plurality of n-wells, so that the transistor body region or bulk region can be driven to a voltage level different from the voltage level of the body region of transistors in adjacent n-wells (e.g., transistors included in standard functional cells or other ECO cells) during operation. Compared to an approach in which the ECO basic cell shares an n-well with standard functional cells and other ECO cells, routing flexibility and design efficiency are thereby improved, so that additional design activities (e.g., SPRT process iterations or ECO cell customization) can be avoided.

[0027] As discussed below, Figures 1 to 8 is a diagram of an IC layout and a corresponding IC structure according to some embodiments. Figures 1 to 8 The figures in FIG. 1 represent IC layout diagrams 100 to 800 and (for example, according to the following reference Fig.11 The discussed IC manufacturing system and associated IC manufacturing flow 1100) are based at least in part on the corresponding IC structures 100 to 800 manufactured by the IC layout diagrams 100 to 800. According to some embodiments, Fig. 9 is a flow chart of a method 900 of generating an IC layout diagram (eg, IC layout diagrams 100 to 800), and Fig.10 is a block diagram of an IC design system 1000 (eg, EDA system 1000 ) configured to perform some or all of the operations of method 900 .

[0028] like Figure 1As depicted, IC layout / structure 100 includes n-well regions / n-wells NW1 to NW3 located in a substrate SUB, an instance of a metalloid-defined (MD) region / segment MD (labeled singly for clarity) extending along a Y direction, an instance of a via region / structure V0 (labeled singly for clarity), and an instance of a first metal region / segment M1 (labeled singly for clarity) extending along an X direction perpendicular to the Y direction.

[0029] The n-well regions / n-wells NW1 to NW3 are regions of an IC layout (eg, IC layout 100 ) that at least partially define n-doped volumes within a substrate SUB in a manufacturing process corresponding to the IC layout / structure.

[0030] The n-well regions NW1 to NW3 are aligned in the X direction, the n-well regions NW1 and NW2 are separated by a space S1 in the X direction, and the n-well regions NW2 and NW3 are separated by a space S2 in the X direction.

[0031] Each of the spaces S1 and S2 is a distance greater than or equal to a minimum spacing rule of a manufacturing process. In various embodiments, the spaces S1 and S2 are equal to or different from each other.

[0032] In various embodiments, the space S1 or S2 corresponds to a portion of the substrate SUB or an isolation region / structure, such as a volume of a dielectric material, located between corresponding n-well regions / n-well pairs NW1 / NW2 and / or NW2 / NW3 .

[0033] Each of the n-well regions / n-wells NW1 to MW3 includes at least one instance of an MD region MD, which is a region in the IC layout diagram that overlaps with the corresponding n-well region NW1 to NW3 and at least partially defines a conductive MD segment MD that covers and is electrically connected to the underlying n-wells NW1 to NW3. The MD segment MD is also referred to in some embodiments as a metal zero over oxide (MOOD) segment MD, which is included in the lowest conductive (e.g., metal and / or highly doped semiconductor material) layer in the manufacturing process.

[0034] Each of the n-well regions / n-wells NW1 to MW3 also includes at least one instance of a via region V0, which is a region in the IC layout diagram that overlaps with a corresponding instance of the MD region MD and at least partially defines a via structure V0, which covers and is electrically connected to the corresponding underlying MD segment MD. The via structure V0 is a conductive volume configured to provide electrical connection between underlying features (e.g., MD segment MD) and overlying features (e.g., instances of metal segment M1 discussed below).

[0035] like Figure 1As depicted, the combination of the MD region / segment MD and the instance of the via region / structure V0 in each of the n-well regions / n-wells NW1 to MW3 thus corresponds to a tap feature / structure 'Tap' configured to at least partially define an electrical connection between the underlying n-well regions / n-wells NW1 to NW3 and the overlying metal region / segment M1.

[0036] The metal region M1 is a region of the IC layout that overlaps one or more features including an instance of the via region V0 and at least partially defines a metal (e.g., copper) segment M1 that covers and is electrically connected to the corresponding underlying instance of the via structure V0. In some embodiments, the metal segment M1, also referred to as a metal segment M1 in some embodiments, is included in the lowest metal layer of a routing process (e.g., an automatic place and route (APR) process) corresponding to the IC layout.

[0037] exist Figure 1 In the depicted embodiment, the n-well region NW2 includes a region Function located between two instances of the tap feature Tap. The region Function is a region where one or more instances of an ECO base cell 'ECObase' are located in an IC layout diagram (eg, IC layout diagram 100), for example, as described below with respect to Figures 2 to 8 As discussed, one or more instances of the cell ECO base can be programmed as one or more functional (eg, logic) devices.

[0038] The region Function includes instances of via regions / structures V0 corresponding to electrical connections between one or more functional devices and overlapping / overlaying instances of metal regions / segments M1, each instance of metal regions / segments M1 being electrically connected to instances of tap features / structures Tap located in n-well regions / n-well NW2. Thus, the instances of metal regions / segments M1 are configured to be able to drive one or more instances of n-well regions / n-well NW2 and cell ECO base (whether programmed or not) to a first voltage level (e.g., based on routing through an overlaying metal interconnect structure).

[0039] A single instance of metal region / segment M1 overlaps / overlays an instance of a tap feature / structure Tap located in each of n-well regions / n-wells NW1 and NW3, and overlaps / overlays region Function, and is therefore configured to electrically connect n-well regions / n-wells NW1 and NW3 to each other, while electrically isolating n-well region / n-well NW2 from n-well regions / n-wells NW1 and NW3. Thus, the instance of metal region / segment M1 is configured to be able to drive n-well regions / n-wells NW1 and NW3 and any corresponding functional circuits to a second voltage level that is different from the first voltage level (e.g., based on routing through an overlying metal interconnect structure).

[0040] exist Figure 1 In the depicted embodiment, IC layout / structure 100 includes three additional instances of metal region / segment M1 that are wider in the Y direction than other instances of metal region / segment M1. In various embodiments, the additional instances of metal region / segment M1 are included in a power distribution structure (e.g., a power grid) configured to distribute a reference voltage level (e.g., ground) and one or more power supply voltage levels (e.g., VDD) within IC layout / structure 100.

[0041] exist Figure 1 In the depicted embodiment, the region Function extends a distance (height) in the Y direction equal to twice the pitch of the additional instances of metal region / segment M1. In various embodiments, the region Function extends a distance equal to the pitch or equal to a multiple of the pitch greater than two.

[0042] exist Figure 1 In the depicted embodiment, each of the n-well regions NW1-MW3 extends across the entire region Function in the Y direction. In some embodiments, one or more of the n-well regions NW1-MW3 extends across a portion of the region Function, such as a distance equal to the pitch.

[0043] Through the configuration discussed above, the IC layout / structure 100 can include an ECO base cell placed in the n-well region / n-well NW2, such as the cell ECO base discussed below, so that the transistor body region or main body region can be driven to a voltage level different from the voltage level of the body region of the transistor in the adjacent n-well region / n-well NW1 and NW3 (e.g., the transistor included in the standard functional cell or other ECO cell) in operation. Compared with the method in which the ECO base cell shares the n-well with the standard functional cell and other ECO cells, the wiring flexibility and design efficiency are thereby improved, so that additional design activities (such as SPRT process iteration or ECO cell customization) can be avoided.

[0044] Figure 2 Depicted is an IC layout diagram / structure 200 including n-well regions / n-wells NW1 to NW3 in a substrate SUB, an instance of an MD region / segment MD, a via region / structure V0, a ​​first metal region / segment M1, and X and Y directions, as described above with respect to Figure 1 Each is discussed.

[0045] like Figure 2As shown, a non-limiting example of the region Function (not labeled for clarity) includes instances of the unit ECO base arranged in two rows and two columns. In some embodiments, some or all of the rows (indicated by bold borders) correspond to a single instance of the unit ECO base, which is twice as wide in the X direction as other instances of the unit ECO base.

[0046] Figure 2 The depicted arrangement of the unit ECO base is a non-limiting example provided for illustration purposes. In various embodiments, the IC layout diagram / structure (e.g., IC layout diagram / structure 200) includes instances of the unit ECO base having other configurations, for example, some or all of the columns correspond to a single instance of the unit ECO base that is twice as tall in the Y direction as other instances of the unit ECO base.

[0047] exist Figure 2 In the depicted embodiment, the IC layout / structure 200 includes an instance of a metal region / segment M1 extending in the X direction and overlapping / overlying a tap feature / structure Tap located in each of the n-well regions / n-wells NW1, NW2, and NW3, and is thus configured to electrically connect the n-well regions / n-wells NW1, NW2, and NW3 to each other. Therefore, the instance of the metal region / segment M1 is configured to be able to drive the n-well regions / n-wells NW1, NW2, and NW3 and any corresponding ECO cells and / or functional circuits to the same voltage level (e.g., based on routing through an overlying metal interconnect structure).

[0048] therefore, Figure 1 and Figure 2 The depicted embodiment shows alternative routing options so that one or more instances of cell ECO base placed in n-well region / n-well NW2 can be driven to the same or different voltage levels than those applied to n-well regions / n-wells NW1 and NW3. In accordance with having this routing flexibility, the following discussed Figures 3 to 8 Each of the Figures does not depict an example of a metal region / segment M1 having a specific configuration.

[0049] Figure 3 A simplified diagram of an IC layout / structure 300 is depicted, including n-well regions / n-wells NW1 to NW3 in a substrate SUB, examples of tap features / structures Tap and cell ECO base, and X and Y directions, each discussed above.

[0050] Figure 3Depicted is a non-limiting example of an IC layout diagram / structure 300 including four instances of a unit ECO base arranged in two rows and two columns. In some embodiments, each instance of a unit ECO base has the same orientation with respect to the X and Y directions. In some embodiments, one or more instances of a unit ECO base are symmetric with (mirrored with) one or more other instances of a unit ECO base with respect to the X or Y axis (e.g., a boundary between one or more instances of a unit ECO base), as discussed further below.

[0051] Figure 4 A simplified diagram of an IC layout diagram / structure 400 is depicted, which includes n-well regions / n-wells NW1 to NW3 located in a substrate SUB, four instances of a cell ECO base (individual instances are labeled for clarity) (each instance includes an instance of an MD region / segment MD and a via region / structure V0), and X and Y directions, each of which is discussed above.

[0052] Each instance of cell ECO base also includes an instance of active area / region AA, gate region / structure G, metal zero over polysilicon (M0PO) region / segment M0, and cutting MD region CMD (a single instance of each is labeled for clarity).

[0053] An active area (e.g., active area AA) is an area in an IC layout diagram that at least partially defines a volume in a corresponding substrate or n-well, such as a substrate area or an n-well area (e.g., n-well areas NW1 to NW3), in which various features, such as transistor channels and / or source / drain features, are formed in a corresponding IC structure through a manufacturing process.

[0054] The gate region (e.g., gate region R) is an area in the IC layout diagram that at least partially defines a volume in a corresponding IC structure, in which a gate electrode (also referred to as a polysilicon gate or polysilicon in some embodiments) and a gate dielectric layer are formed by a manufacturing process.

[0055] The MOPO region (e.g., MOPO region M0) is a region in the IC layout diagram that at least partially defines a conductive segment (e.g., MOPO segment M0) that covers and is electrically connected to the underlying gate structure. The MOPO segment M0 is included in the lowest conductive (e.g., metal and / or highly doped semiconductor material) layer in the manufacturing process.

[0056] The cut MD area is an area in the IC layout diagram that defines the following block in the corresponding IC structure: within the block, parts of the MD segments MD are removed after the MD segments MD are formed in the manufacturing process, so that the resulting MD segments MD are electrically isolated from each other.

[0057] In a given instance of a cell ECO base, instances of active area / region AA, gate region / structure G, M0PO region / segment M0, MD region / segment MD, via region / structure V0, and cutting MD region CMD are arranged in a pattern in which the instance of the cell ECO base can be programmed as a selectable cell function.

[0058] In various embodiments, each instance of the unit ECO base corresponds to the same pattern or multiple patterns. In some embodiments, two patterns are symmetrical to each other about an axis (eg, a boundary between the two patterns).

[0059] In some embodiments, Figure 4 The depicted examples of unit ECO base correspond to a first row in which the second pattern is symmetrical to the first pattern about a boundary extending in the Y direction and a second row in which the third and fourth patterns are symmetrical to the first and second patterns about a boundary extending in the X direction.

[0060] Figure 5 and Figure 6 Each of them depicts a simplified diagram of the corresponding IC layout diagram / structure 500 or 600, which includes n-well regions / n-wells NW1 to NW3 located in the substrate SUB, six instances of the cell ECO base (a single instance is labeled for clarity) (each instance includes multiple instances of the active area / region AA, the gate region / structure G, the M0PO region / segment M0, the MD region / segment MD, the through-hole region / structure V0, and the cutting MD region CMD (not labeled for clarity)), and the X and Y directions, each of which is discussed above.

[0061] In various embodiments, instances of the unit ECO base included in the IC layout diagrams / structures 500 and 600 include corresponding instances of active areas / regions AA, gate regions / structures G, M0PO regions / segments M0, MD regions / segments MD, through-hole regions / structures V0, and cutting MD regions CMD arranged in one or more patterns, which in some embodiments have symmetry corresponding to one or more axes.

[0062] Figure 7 and Figure 8 Each depicts a simplified diagram of a corresponding IC layout / structure 700 or 800 including n-well regions / n-wells NW1 to NW3 in a substrate SUB and an instance of a cell ECO base including various features (not labeled for clarity).

[0063] Figure 7The depicted non-limiting example includes four instances of cell ECO base located in n-well region / n-well NW2, and Figure 8 The depicted non-limiting example includes a single instance of cell ECO base located in n-well region / n-well NW2 , the single instance being configured as a decoupling capacitive device DCAP2 .

[0064] Each of IC layouts / structures 300 to 800 is configured according to IC layouts / structures 100 and 200 by including various instances of cell ECO base in n-well region / n-well NW2 , thereby enabling the benefits discussed above with respect to IC layouts / structures 100 and 200 .

[0065] Fig. 9 is a flowchart of a method 900 for generating an IC layout diagram according to some embodiments. In some embodiments, generating an IC layout diagram includes: generating Figures 1 to 8 Some or all of one or more of the IC layout diagrams 100 to 800 discussed.

[0066] In some embodiments, some or all of method 900 is performed by a processor of a computer. In some embodiments, some or all of method 900 is performed by the following description of Fig.10 The discussed IC layout diagram generation system 1000 is executed by the processor 1002 .

[0067] In some embodiments, one or more operations of method 900 are a subset of operations of a method of forming an IC device. In some embodiments, one or more operations of method 900 are an IC manufacturing flow (e.g., as described below with respect to manufacturing system 1100 and Fig.11 A subset of the operations of the IC manufacturing flow discussed.

[0068] In some embodiments, the operations of method 900 are as follows: Fig. 9 In some embodiments, the operations of method 900 are performed simultaneously and / or in a sequence similar to that of Fig. 9 In some embodiments, one or more operations of method 900 are performed before, between, during, and / or after one or more operations of method 900 are performed.

[0069] At operation 902, first through third n-well regions are aligned along a first direction in an IC layout diagram. Aligning the first through third n-well regions includes separating the first n-well region from each of the second and third n-well regions by a distance at least corresponding to a minimum n-well spacing rule.

[0070] In some embodiments, according to the above Figures 1 to 8As discussed in one or more of the IC layout diagrams 100 to 800 , aligning the first to third n-well regions includes aligning n-well regions NW2 , NW1 , and NW3 , n-well region NW2 being separated from n-well region NW1 by space S1 , and n-well region NW2 being separated from n-well region NW3 by space S2 .

[0071] In some embodiments, aligning the first to third n-well regions includes positioning the first tap via region in the second n-well region and positioning the second tap via region in the third n-well region. In some embodiments, aligning the first to third n-well regions includes positioning the third and fourth tap via regions in the first n-well region.

[0072] In some embodiments, locating the tap via region includes: locating an instance of a tap feature Tap, the tap feature Tap including the above-mentioned Figure 1 and Figure 2 An example of a through-hole region V0 is discussed which overlaps with a corresponding example of an MD region MD.

[0073] At operation 904, a first ECO basic unit is placed in the first n-well region. In some embodiments, placing the first ECO basic unit in the first n-well region includes: Figures 1 to 8 The discussed cell ECO base is placed in the n-well region NW2.

[0074] In some embodiments, placing the first ECO basic unit in the first n-well region includes placing a plurality of ECO basic units including the first ECO basic unit in the first n-well region, for example, according to Figures 2 to 8 An example of a cell ECO base in the n-well region NW2 of one or more of .

[0075] At operation 906, the second and third n-well regions are electrically connected. Electrically connecting the second and third n-well regions includes establishing a first electrical connection between the second and third n-well regions by overlapping each of the first and second tap via regions with a first metal region extending across the first n-well region in a first direction.

[0076] In some embodiments, overlapping each of the first and second tap via regions with a first metal region extending across the first n-well region in the first direction includes overlapping instances of the tap feature Tap corresponding to the n-well regions NW1 and NW3 with instances of the metal region M1 extending across the n-well region NW2 in the X direction, as described above with respect to Figure 1 and Figure 2 discussed.

[0077] In some embodiments, electrically connecting the second and third n-well regions includes: establishing a second electrical connection between the third and fourth tap via regions by overlapping each of the third and fourth tap via regions with a second metal region extending across the first ECO unit cell in the first direction, for example, as described above with respect to Figure 1 discussed.

[0078] In some embodiments, electrically connecting the second and third n-well regions includes overlapping each of the third and fourth tapping via regions with the first metal region, thereby establishing a first electrical connection between each of the second and third n-well regions and the first n-well region, for example, as described above with respect to Figure 2 discussed.

[0079] At operation 908, in some embodiments, the ECO base cell is configured as a functional unit. In some embodiments, configuring the ECO base cell as a functional unit includes adding and / or modifying one or more electrical connections within the functional unit to configure the ECO base cell to perform one or more logical or other functions.

[0080] In various embodiments, configuring the ECO basic unit as a functional unit includes: configuring a subset or all of the plurality of ECO basic units as corresponding functional units. In some embodiments, configuring the ECO basic unit as a functional unit includes: configuring the above-mentioned Figures 1 to 8 One or more instances of the unit ECO base in question.

[0081] In some embodiments, configuring the ECO primitives as functional units includes performing one or more routing operations, such as one or more APR operations. In some embodiments, configuring the ECO primitives as functional units includes routing a plurality of electrical signal paths to the functional units.

[0082] In some embodiments, configuring the ECO base unit as a functional unit includes routing a first voltage distribution path (eg, configured to distribute a first voltage level) to the first electrical connection.

[0083] In some embodiments, configuring the ECO base unit as a functional unit includes routing a second voltage distribution path (eg, configured to distribute a second voltage level different from the first voltage level) to the second electrical connection.

[0084] At operation 910, in some embodiments, the IC layout diagram is stored in a storage device. In some embodiments, storing the IC layout diagram in the storage device includes: storing the IC layout diagram in an IC layout library (e.g., the layout library 1009 of the IC layout diagram generation system 1000), as described below. Fig.10 Have a discussion.

[0085] In various embodiments, storing the IC layout diagram in a storage device includes storing the IC layout diagram in a non-volatile, computer-readable memory or a cell library (e.g., a database), and / or includes storing the IC layout diagram over a network. In some embodiments, storing the IC layout diagram in a storage device includes: storing the IC layout diagram in a non-volatile, computer-readable memory or a cell library (e.g., a database), and / or storing the IC layout diagram over a network. Fig.10 The network 1014 of the IC layout generation system 1000 discussed stores IC layouts.

[0086] At operation 912, in some embodiments, one or more manufacturing operations are performed based on the IC layout diagram. In some embodiments, performing the one or more manufacturing operations includes: performing one or more photolithography exposures based on the IC layout diagram. Fig.11 Discussion One or more manufacturing operations, such as one or more photolithography exposures, are performed based on the IC layout.

[0087] By performing some or all of the operations of method 900, an IC layout is generated in which one or more instances of the ECO basic unit are placed in a dedicated n-well area configured according to IC layout diagrams 100 and 200, so that the IC layout can achieve the benefits discussed above with respect to IC layout diagrams / structures 100 and 200.

[0088] Fig.10 is a block diagram of an electronic design automation (EDA) system 1000 according to some embodiments.

[0089] In some embodiments, EDA system 1000 includes an APR system. The methods of designing a layout diagram described herein represent that wire routing arrangements according to one or more embodiments may be implemented, for example, using EDA system 1000 according to some embodiments.

[0090] In some embodiments, EDA system 1000 is a general purpose computing device including a hardware processor 1002 and a non-transitory computer readable storage medium 1004. Storage medium 1004 is encoded with (i.e., stores) computer program code 1006 (i.e., a set of executable instructions), among other things. Execution of instructions 1006 by hardware processor 1002 (at least in part) represents an EDA tool that implements part or all of the methods described herein (hereinafter referred to as described processes and / or methods) according to one or more embodiments.

[0091] The processor 1002 is electrically coupled to the computer readable storage medium 1004 via a bus 1008. The processor 1002 is also electrically coupled to an I / O interface 1010 via the bus 1008. A network interface 1012 is also electrically connected to the processor 1002 via the bus 1008. The network interface 1012 is connected to a network 1014, so that the processor 1002 and the computer readable storage medium 1004 can be connected to external elements via the network 1014. The processor 1002 is configured to execute computer program code 1006 encoded in the computer readable storage medium 1004 so that the system 1000 can be used to perform part or all of the described processes and / or methods. In one or more embodiments, the processor 1002 is a central processing unit (CPU), a multiprocessor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0092] In one or more embodiments, the computer-readable storage medium 1004 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, the computer-readable storage medium 1004 includes semiconductor or solid-state memory, magnetic tape, removable computer disk, random access memory (RAM), read-only memory (ROM), rigid disk, and / or optical disk. In one or more embodiments using optical disks, the computer-readable storage medium 1004 includes a compact disk read-only memory (CD-ROM), a compact disk read / write (CD-R / W), and / or a digital video disk (DVD).

[0093] In one or more embodiments, the storage medium 1004 stores computer program code 1006 configured to cause the system 1000 (where such execution (at least in part) represents an EDA tool) to be used to perform some or all of the described processes and / or methods. In one or more embodiments, the storage medium 1004 also stores information that facilitates the execution of some or all of the described processes and / or methods. In one or more embodiments, the storage medium 1004 stores a cell library 1007 of IC layout cells including such cells as disclosed herein. In one or more embodiments, the storage medium 1004 stores one or more layout drawings 1009 corresponding to one or more layouts disclosed herein.

[0094] The EDA system 1000 includes an I / O interface 1010. The I / O interface 1010 is coupled to an external circuit. In one or more embodiments, the I / O interface 1010 includes a keyboard, a keypad, a mouse, a trackball, a trackpad, a touch screen, and / or cursor direction keys for transmitting information and commands to the processor 1002.

[0095] The EDA system 1000 also includes a network interface 1012 coupled to the processor 1002. The network interface 1012 allows the system 1000 to communicate with a network 1014 to which one or more other computer systems are connected. The network interface 1012 includes: a wireless network interface, such as Bluetooth, WIFI, WIMAX, GPRS, or WCDMA; or a wired network interface, such as Ethernet, USB, or IEEE-1364. In one or more embodiments, part or all of the described processes and / or methods are implemented in two or more systems 1000.

[0096] The system 1000 is configured to receive information through the I / O interface 1010. The information received through the I / O interface 1010 includes one or more of instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 1002. The information is transmitted to the processor 1002 via the bus 1008. The EDA system 1000 is configured to receive information related to a user interface (UI) through the I / O interface 1010. The information is stored in the computer readable medium 1004 as the UI 1042.

[0097] In some embodiments, some or all of the described processes and / or methods are implemented as a standalone software application for execution by a processor. In some embodiments, some or all of the described processes and / or methods are implemented as a software application that is part of an additional software application. In some embodiments, some or all of the described processes and / or methods are implemented as a plug-in for a software application. In some embodiments, at least one of the described processes and / or methods is implemented as a software application that is part of an EDA tool. In some embodiments, some or all of the described processes and / or methods are implemented as a software application used by the EDA system 1000. In some embodiments, the system 1000 is implemented using a software application such as a CADENCE DESIGN SYSTEMS, Inc. A tool such as or another suitable layout generation tool is used to generate a layout diagram including standard cells.

[0098] In some embodiments, these processes are implemented as functions of a program stored in a non-transitory computer-readable recording medium. Examples of non-transitory computer-readable recording media include, but are not limited to, external / removable and / or internal / built-in storage devices or memory units, such as one or more of the following: optical disks (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROMs), RAMs, memory cards, etc.

[0099] Fig.111 is a block diagram of an integrated circuit (IC) manufacturing system 1100 and its associated IC manufacturing process according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 1100 is used to manufacture at least one of the following items: (A) one or more semiconductor masks, or (B) at least one component in a layer of a semiconductor integrated circuit.

[0100] exist Fig.11 In the embodiment, the IC manufacturing system 1100 includes entities that interact with each other in the design, development, and manufacturing cycle and / or services related to manufacturing IC devices 1160, such as design room 1120, mask room 1130, and IC manufacturer / fab 1150. The entities in the system 1100 are connected by a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more other entities and provides services to one or more other entities and / or receives services from one or more other entities. In some embodiments, two or more of the design room 1120, mask room 1130, and IC fab 1150 are owned by a single larger company. In some embodiments, two or more of the design room 1120, mask room 1130, and IC fab 1150 coexist in a public facility and use public resources.

[0101] The design office (or design team) 1120 generates an IC design layout 1122. The IC design layout 1122 includes various geometric patterns designed for the IC device 1160. The geometric pattern corresponds to the pattern of the metal, oxide or semiconductor layer of each component constituting the IC device 1160 to be manufactured. Various layers are combined to form various IC features. For example, a part of the IC design layout 1122 includes various IC features, such as active areas, gate electrodes, source and drain, metal wires or through holes for interlayer interconnection, and openings for bonding pads, which are formed in semiconductor substrates (e.g., silicon wafers) and various material layers arranged on the semiconductor substrate. The design office 1120 implements appropriate design programs to form the IC design layout 1122. The design program includes one or more logical designs, physical designs, or layout and routing. The IC design layout 1122 is presented in one or more data files with information of geometric patterns. For example, the IC design layout 1122 can be represented in a GDSII file format or a DFII file format.

[0102] The mask chamber 1130 includes data preparation 1132 and mask manufacturing 1144. The mask chamber 1130 uses the IC design layout drawing 1122 to manufacture one or more masks 1145 for manufacturing various layers of the IC device 1160 according to the IC design layout drawing 1122. The mask chamber 1130 performs mask data preparation 1132, wherein the IC design layout drawing 1122 is converted into a representative data file (RDF). The mask data preparation 1132 provides the RDF to the mask manufacturing 1144. The mask manufacturing 1144 includes a mask writer. The mask writer converts the RDF into an image on a substrate, for example, a mask (reticle) 1145 or a semiconductor wafer 1153. The design layout drawing 1122 is manipulated by the mask data preparation 1132 to conform to the specific characteristics of the mask writer and / or the requirements of the IC fab 1150. In Fig.11 , mask data preparation 1132 and mask manufacturing 1144 are shown as separate elements. In some embodiments, mask data preparation 1132 and mask manufacturing 1144 may be collectively referred to as mask data preparation.

[0103] In some embodiments, mask data preparation 1132 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout 1122. In some embodiments, mask data preparation 1132 also includes resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shift masks, other suitable techniques, etc., or a combination of the foregoing. In some embodiments, inverse lithography techniques (ILT), which treat OPC as an inverse imaging problem, are also used.

[0104] In some embodiments, mask data preparation 1132 includes a mask rule checker (MRC) that checks an IC design layout 1122 that has been processed in OPC using a set of mask creation standard rules that contain certain geometric and / or connectivity restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1122 to compensate for lithography implementation effects during mask fabrication 1144, which may undo some of the modifications performed by the OPC in order to satisfy the mask creation standard rules.

[0105] In some embodiments, mask data preparation 1132 includes a lithography process check (LPC) that simulates a process to be implemented by IC fab 1150 to manufacture IC device 1160. LPC simulates this process based on IC design layout diagram 1122 to create a simulated manufactured device, such as IC device 1160. Process parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with tools used to manufacture ICs, and / or other aspects of the manufacturing process. LPC takes into account various factors, such as aerial image contrast, depth of focus (DOF), mask error enhancement factor (MEEF), other suitable factors, etc., or a combination of the foregoing. In some embodiments, after the simulated manufactured device is created by LPC, if the shape of the simulated device is not sufficient to meet the design rules, OPC and / or MRC are repeated to further improve the IC design layout diagram 1122.

[0106] It should be understood that the above description of mask data preparation 1132 is simplified for the purpose of clarity. In some embodiments, data preparation 1132 includes additional features such as logic operations (LOPs) to modify IC design layout 1122 according to manufacturing rules. In addition, the processes applied to IC design layout 1122 during data preparation 1132 can be performed in a variety of different orders.

[0107] After mask data preparation 1132 and during mask manufacturing 1144, a mask 1145 or a set of masks 1145 are manufactured based on the modified IC design layout 1122. In some embodiments, mask manufacturing 1144 includes performing one or more photolithography exposures based on the IC design layout 1122. In some embodiments, based on the modified IC design layout 1122, an electron beam (e-beam) or a plurality of electron beam mechanisms are used to form a pattern on a mask (photomask or reticle) 1145. The mask 1145 can be formed using various techniques. In some embodiments, the mask 1145 is formed using binary techniques. In some embodiments, the mask pattern includes opaque areas and transparent areas. A radiation beam (e.g., an ultraviolet (UV) beam) used to expose an image sensitive material layer (e.g., a photoresist) coated on a wafer is blocked by the opaque area and passes through the transparent area. In one example, a binary mask version of mask 1145 includes a transparent substrate (e.g., fused quartz) and an opaque material (e.g., chromium) coated in the opaque areas of the binary mask. In another example, mask 1145 is formed using a phase shift technique. In a phase shift mask (PSM) version of mask 1145, various features in a pattern formed on the phase shift mask are configured to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase shift mask can be an attenuated PSM or an alternating PSM. The mask(s) generated by mask manufacturing 1144 are used for various processes. For example, such mask(s) are used in an ion implantation process to form various doped regions in semiconductor wafer 1153, such mask(s) are used in an etching process to form various etching regions in semiconductor wafer 1153, and / or such mask(s) are used in other suitable processes.

[0108] IC fab 1150 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, IC fab 1150 is a semiconductor foundry. For example, there may be a manufacturing facility for front-end manufacturing of multiple IC products (front-end of line (FEOL) manufacturing), while a second manufacturing facility may provide back-end manufacturing for interconnection and packaging of IC products (back-end of line (BEOL) manufacturing), and a third manufacturing facility may provide other services for the foundry.

[0109] IC fab 1150 includes fabrication tools 1152 configured to perform various fabrication operations on semiconductor wafer 1153 to fabricate IC devices 1160 according to mask(s) (e.g., mask 1145). In various embodiments, fabrication tools 1152 include one or more of the following: a wafer stepper, an ion implanter, a photoresist coater, a processing chamber (e.g., a CVD chamber or LPCVD furnace), a CMP system, a plasma etching system, a wafer cleaning system, or other fabrication equipment capable of performing one or more suitable fabrication processes as discussed herein.

[0110] IC fab 1150 uses (one or more) masks 1145 manufactured by mask chamber 1130 to manufacture IC devices 1160. Therefore, IC fab 1150 at least indirectly uses IC design layout 1122 to manufacture IC devices 1160. In some embodiments, semiconductor wafer 1153 is manufactured by IC fab 1150 using (one or more) masks 1145 to form IC devices 1160. In some embodiments, IC manufacturing includes performing one or more photolithography exposures based on IC design layout 1122 at least indirectly. Semiconductor wafer 1153 includes a silicon substrate or other suitable substrate having a material layer formed thereon. Semiconductor wafer 1153 also includes one or more of various doped regions, dielectric features, multi-level interconnects, etc. (formed in subsequent manufacturing steps).

[0111] In some embodiments, the IC structure includes: first to third n-wells aligned along a first direction in a semiconductor substrate, wherein the first n-well is separated from each of the second and third n-wells by a corresponding space; a first plurality of active regions, gate structures, and MD segments, covering and electrically connected to the active regions located in the first n-well; a first tap structure, covering and electrically connected to the second n-well; a second tap structure, covering and electrically connected to the third n-well; and a first metal segment, extending in the first direction, covering the first plurality of transistors, and electrically connected to each of the first and second tap structures. In some embodiments, the IC structure includes: third and fourth tap structures, covering and electrically connected to the first n-well; and a second metal segment extending in the first direction, wherein the second metal segment covers and electrically connected to each of the third and fourth tap structures, and is electrically isolated from the first metal segment. In some embodiments, the first metal segment is configured to have a first voltage level, and the second metal segment is configured to have a second voltage level different from the first voltage level. In some embodiments, the IC structure includes: third and fourth tap structures covering and electrically connected to the first n-well, wherein the first metal segment is electrically connected to each of the third and fourth tap structures. In some embodiments, the first plurality of active regions, gate structures, and MD segments include a first pattern, and the IC structure includes a second plurality of active regions, gate structures, and MD segments, covering and electrically connected to active regions located in the first n-well and including the first pattern. In some embodiments, the first plurality of active regions, gate structures, and MD segments include a first pattern, the IC structure includes a second plurality of active regions, gate structures, and MD segments, covering and electrically connected to active regions located in the first n-well and including a second pattern, and the second pattern is symmetrical to the first pattern about a first axis perpendicular to the first direction. In some embodiments, the IC structure includes a third and fourth plurality of active regions, gate structures, and MD segments, covering and electrically connected to active regions located in the first n-well and including respective third and fourth patterns, wherein the third and fourth patterns are symmetrical to the first and second patterns about a second axis along the first direction.

[0112] In some embodiments, a method for generating an IC layout diagram includes: aligning first to third n-well regions in the IC layout diagram along a first direction, wherein the first n-well region is separated from each of the second and third n-well regions by a distance at least corresponding to a minimum n-well spacing rule; positioning a first tap via region in the second n-well region; positioning a second tap via region in the third n-well region; placing a first ECO cell in the first n-well region; establishing a first electrical connection between the second and third n-well regions by overlapping each of the first and second tap via regions with a first metal region extending across the first n-well region in the first direction; and storing the IC layout diagram in a storage device. In some embodiments, the method includes: positioning the third and fourth tap via regions in the first n-well region, and establishing a second electrical connection between the third and fourth tap via regions by overlapping each of the third and fourth tap via regions with a second metal region extending across the first ECO cell in the first direction. In some embodiments, the method includes: routing a first voltage distribution path to the first electrical connection, and routing a second voltage distribution path to the second electrical connection, wherein the first and second voltage distribution paths are configured to distribute separate voltage levels. In some embodiments, the method includes: positioning the third and fourth tap via regions in the first n-well region, wherein establishing the first electrical connection includes: overlapping each of the third and fourth tap via regions with the first metal region, thereby establishing a first electrical connection between each of the second and third n-well regions and the first n-well region. In some embodiments, placing the first ECO basic cell in the first n-well region includes: placing the second ECO basic cell in the first n-well region, adjacent to the first ECO basic cell in a first direction. In some embodiments, placing the first ECO basic cell in the first n-well region includes: placing the second ECO basic cell in the first n-well region, adjacent to the first ECO basic cell in a first direction, the first and second ECO basic cells are symmetrical about a boundary between the first and second ECO basic cells; and placing the third and fourth ECO basic cells in the first n-well region, adjacent to the first and second ECO basic cells in a second direction perpendicular to the first direction, the first and third ECO basic cells are symmetrical about a boundary between the first and third ECO basic cells, and the second and fourth ECO basic cells are symmetrical about a boundary between the second and fourth ECO basic cells. In some embodiments, placing the first ECO basic unit in the first n-well region includes: placing the second and third ECO basic units in the first n-well region, adjacent to the first ECO basic unit in one direction of a first direction or a second direction perpendicular to the first direction; and placing the third to fifth ECO basic units in the first n-well region, adjacent to the first to third ECO basic units in the other direction of the first or second directions.In some embodiments, the method includes configuring the first ECO base cell as a functional ECO cell and routing a plurality of electrical signal paths to the functional ECO cell.

[0113] In some embodiments, an EDA system includes a processor and a non-transitory computer-readable storage medium, the non-transitory computer-readable storage medium including computer program code for one or more programs, the non-transitory computer-readable storage medium and the computer program code being configured to: utilize a processor so that the processor positions a first tap via region in a second n-well region of a first to third n-well region of an IC layout diagram, the first n-well region being separated from each of the second and third n-well regions along a first direction by a distance at least corresponding to a minimum n-well spacing rule; positions a second tap via region in the third n-well region; places a first ECO basic unit in the first n-well region; overlaps each of the first and second tap via regions with a first metal region extending across the first n-well region along a first direction, thereby establishing a first electrical connection between the second and third n-well regions; routes a first voltage distribution path to the first electrical connection, the first voltage distribution path being configured to distribute a first voltage level; and stores the IC layout diagram in a storage device. In some embodiments, the non-transitory computer readable storage medium and the computer program code are configured to: further cause the processor to perform the following operations with a processor: position the third and fourth tap via regions in the first n-well region; overlap each of the third and fourth tap via regions with a second metal region extending across the first ECO basic unit in the first direction, thereby establishing a second electrical connection between the third and fourth tap via regions; and route a second voltage distribution path to the second electrical connection, the second voltage distribution path being configured to distribute a second voltage level different from the first voltage level. In some embodiments, the non-transitory computer readable storage medium and the computer program code are configured to: further cause the processor to perform the following operations with a processor: position the third and fourth tap via regions in the first n-well region, and overlap each of the third and fourth tap via regions with the first metal region, thereby establishing a first electrical connection between each of the second and third n-well regions and the first n-well region. In some embodiments, the non-transitory computer readable storage medium and the computer program code are configured to further cause the processor to configure the first ECO basic unit as a functional ECO unit with a processor, and route multiple electrical signal paths to the functional ECO unit. In some embodiments, the first ECO basic unit is a first ECO basic unit among multiple ECO basic units, and the non-transitory computer readable storage medium and the computer program code are configured to: use the processor to further cause the processor to place multiple ECO basic units including the first ECO basic unit in a first n-well area of ​​the IC layout diagram.

[0114] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. It should be appreciated by those skilled in the art that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purpose and / or achieving the same advantages of the embodiments described herein. It should also be appreciated by those skilled in the art that these equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions and modifications without departing from the spirit and scope of the present disclosure.

[0115] Example 1. An integrated circuit (IC) structure comprising:

[0116] first to third n-wells aligned along a first direction in a semiconductor substrate, wherein the first n-well is separated from each of the second and third n-wells by a corresponding space;

[0117] a first plurality of active regions, gate structures, and metalloid definition (MD) segments overlying and electrically connected to active regions located in the first n-well;

[0118] a first tap structure covering and electrically connected to the second n-well;

[0119] a second tap structure covering and electrically connected to the third n-well; and

[0120] A first metal segment extends in the first direction, covers the first plurality of transistors, and is electrically connected to each of the first and second tap structures.

[0121] Example 2. The IC structure of Example 1, further comprising:

[0122] third and fourth tap structures covering and electrically connected to the first n-well; and

[0123] a second metal segment extending in said first direction,

[0124] The second metal segment covers and is electrically connected to each of the third and fourth tap structures, and is electrically isolated from the first metal segment.

[0125] Example 3. The IC structure of Example 2, wherein:

[0126] The first metal segment is configured to have a first voltage level, and

[0127] The second metal segment is configured to have a second voltage level different from the first voltage level.

[0128] Example 4. The IC structure of Example 1, further comprising:

[0129] third and fourth tap structures covering and electrically connected to the first n-well,

[0130] Wherein, the first metal segment is electrically connected to each of the third and fourth tap structures.

[0131] Example 5. The IC structure of Example 1, wherein:

[0132] The first plurality of active regions, gate structures, and MD segments include a first pattern, and

[0133] The IC structure further includes a second plurality of active regions, a gate structure, and an MD segment covering and electrically connected to the active regions in the first n-well and including the first pattern.

[0134] Example 6. The IC structure of Example 1, wherein:

[0135] The first plurality of active regions, gate structures and MD segments include a first pattern,

[0136] The IC structure further includes: a second plurality of active regions, gate structures, and MD segments covering and electrically connected to the active regions located in the first n-well and including a second pattern, and

[0137] The second pattern is symmetrical to the first pattern about a first axis perpendicular to the first direction.

[0138] Example 7. The IC structure of Example 6, further comprising:

[0139] a third and fourth plurality of active regions, gate structures and MD segments covering and electrically connected to the active regions located in the first n-well and comprising respective third and fourth patterns,

[0140] The third and fourth patterns are symmetrical to the first and second patterns about a second axis along the first direction.

[0141] Example 8. A method of generating an integrated circuit (IC) layout diagram, the method comprising:

[0142] aligning first through third n-well regions along a first direction in the IC layout diagram, wherein the first n-well region is separated from each of the second and third n-well regions by a distance that corresponds at least to a minimum n-well spacing rule;

[0143] positioning a first tap via region in the second n-well region;

[0144] positioning a second tap via region in the third n-well region;

[0145] placing a first engineering change order (ECO) cell in the first n-well region;

[0146] establishing a first electrical connection between the second and third n-well regions by overlapping each of the first and second tap via regions with a first metal region extending across the first n-well region in the first direction; and

[0147] The IC layout diagram is stored in a storage device.

[0148] Example 9. The method according to Example 8, further comprising:

[0149] positioning third and fourth tap via regions in the first n-well region; and

[0150] A second electrical connection between the third and fourth tapping via regions is established by overlapping each of the third and fourth tapping via regions with a second metal region extending across the first ECO cell in the first direction.

[0151] Example 10. The method according to Example 9, further comprising:

[0152] routing a first voltage distribution path to the first electrical connection; and

[0153] routing a second voltage distribution path to the second electrical connection,

[0154] Wherein, the first and second voltage distribution paths are configured to distribute separate voltage levels.

[0155] Example 11. The method according to Example 8, further comprising:

[0156] positioning third and fourth tapping via regions in the first n-well region,

[0157] The establishing of the first electrical connection includes: overlapping each of the third and fourth branch via regions with the first metal region, thereby establishing a first electrical connection between each of the second and third n-well regions and the first n-well region.

[0158] Example 12. The method according to Example 8, wherein

[0159] Placing the first ECO basic unit in the first n-well region further includes: placing a second ECO basic unit in the first n-well region, adjacent to the first ECO basic unit in the first direction.

[0160] Example 13. The method of Example 8, wherein placing the first ECO basic unit in the first n-well region further comprises:

[0161] placing a second ECO basic unit in the first n-well region, adjacent to the first ECO basic unit in the first direction, the first and second ECO basic units being symmetrical about a boundary between the first and second ECO basic units; and

[0162] The third and fourth ECO basic cells are placed in the first n-well region, adjacent to the first and second ECO basic cells in a second direction perpendicular to the first direction, the first and third ECO basic cells are symmetrical about a boundary between the first and third ECO basic cells, and the second and fourth ECO basic cells are symmetrical about a boundary between the second and fourth ECO basic cells.

[0163] Example 14. The method of Example 8, wherein placing the first ECO basic unit in the first n-well region further comprises:

[0164] placing second and third ECO basic units in the first n-well region adjacent to the first ECO basic unit in one of the first direction or a second direction perpendicular to the first direction; and

[0165] Third to fifth ECO basic cells are placed in the first n-well region adjacent to the first to third ECO basic cells in the other of the first or second directions.

[0166] Example 15. The method according to Example 8, further comprising:

[0167] configuring the first ECO basic unit as a functional ECO unit; and

[0168] A plurality of electrical signal paths are routed to the functional ECO cells.

[0169] Example 16. An electronic design automation (EDA) system comprising:

[0170] Processor; and

[0171] A non-transitory computer readable storage medium including computer program code for one or more programs, the non-transitory computer readable storage medium and the computer program code configured to, with the processor, cause the processor to perform the following operations:

[0172] positioning a first tap via region in a second n-well region of first through third n-well regions of an integrated circuit (IC) layout, the first n-well region being separated from each of the second and third n-well regions along a first direction by a distance at least corresponding to a minimum n-well spacing rule;

[0173] positioning a second tap via region in the third n-well region;

[0174] placing a first engineering change order (ECO) cell in the first n-well region;

[0175] overlapping each of the first and second tap via regions with a first metal region extending across the first n-well region in the first direction, thereby establishing a first electrical connection between the second and third n-well regions;

[0176] routing a first voltage distribution path to the first electrical connection, the first voltage distribution path being configured to distribute a first voltage level; and

[0177] The IC layout diagram is stored in a storage device.

[0178] Example 17. The EDA system of Example 16, wherein the non-transitory computer readable storage medium and the computer program code are configured to, with the processor, further cause the processor to perform the following operations:

[0179] positioning third and fourth tap via regions in the first n-well region;

[0180] overlapping each of the third and fourth tapping via regions with a second metal region extending across the first ECO cell in the first direction, thereby establishing a second electrical connection between the third and fourth tapping via regions; and

[0181] A second voltage distribution path is routed to the second electrical connection, the second voltage distribution path being configured to distribute a second voltage level different from the first voltage level.

[0182] Example 18. The EDA system of Example 16, wherein the non-transitory computer readable storage medium and the computer program code are configured to, with the processor, further cause the processor to perform the following operations:

[0183] positioning third and fourth tap via regions in the first n-well region; and

[0184] Each of the third and fourth tapping via regions overlaps the first metal region, thereby establishing a first electrical connection between each of the second and third n-well regions and the first n-well region.

[0185] Example 19. The EDA system of Example 16, wherein the non-transitory computer readable storage medium and the computer program code are configured to, with the processor, further cause the processor to perform the following operations:

[0186] configuring the first ECO basic unit as a functional ECO unit; and

[0187] A plurality of electrical signal paths are routed to the functional ECO cells.

[0188] Example 20. The EDA system of Example 16, wherein:

[0189] The first ECO basic unit is a first ECO basic unit among a plurality of ECO basic units, and

[0190] The non-transitory computer readable storage medium and the computer program code are configured to, with the processor, further cause the processor to perform the following operation: placing the plurality of ECO basic cells including the first ECO basic cell in the first n-well region of the IC layout diagram.

Claims

1. An integrated circuit (IC) structure, comprising: first to third n-wells aligned along a first direction in a semiconductor substrate, wherein the first n-well is separated from each of the second and third n-wells by a corresponding space; a first plurality of active regions, gate structures, and metalloid definition (MD) segments overlying and electrically connected to active regions located in the first n-well; a first tap structure covering and electrically connected to the second n-well; a second tap structure covering and electrically connected to the third n-well; and A first metal segment extends in the first direction, covers the first plurality of transistors, and is electrically connected to each of the first and second tap structures.

2. The IC structure according to claim 1, further comprising: third and fourth tap structures covering and electrically connected to the first n-well; as well as a second metal segment extending in said first direction, The second metal segment covers and is electrically connected to each of the third and fourth tap structures, and is electrically isolated from the first metal segment.

3. The IC structure according to claim 2, wherein: The first metal segment is configured to have a first voltage level, and The second metal segment is configured to have a second voltage level different from the first voltage level.

4. The IC structure according to claim 1, further comprising: third and fourth tap structures covering and electrically connected to the first n-well, Wherein, the first metal segment is electrically connected to each of the third and fourth tap structures.

5. The IC structure according to claim 1, wherein: The first plurality of active regions, gate structures, and MD segments include a first pattern, and The IC structure further includes a second plurality of active regions, a gate structure, and an MD segment covering and electrically connected to the active regions in the first n-well and including the first pattern.

6. The IC structure according to claim 1, wherein: The first plurality of active regions, gate structures and MD segments include a first pattern, The IC structure further includes: a second plurality of active regions, gate structures, and MD segments covering and electrically connected to the active regions located in the first n-well and including a second pattern, and The second pattern is symmetrical to the first pattern about a first axis perpendicular to the first direction.

7. The IC structure of claim 6, further comprising: a third and fourth plurality of active regions, gate structures and MD segments covering and electrically connected to the active regions located in the first n-well and comprising respective third and fourth patterns, The third and fourth patterns are symmetrical to the first and second patterns about a second axis along the first direction.

8. A method for generating an integrated circuit (IC) layout diagram, the method comprising: aligning first through third n-well regions along a first direction in the IC layout diagram, wherein the first n-well region is separated from each of the second and third n-well regions by a distance that corresponds at least to a minimum n-well spacing rule; positioning a first tap via region in the second n-well region; positioning a second tap via region in the third n-well region; placing a first engineering change order (ECO) cell in the first n-well region; establishing a first electrical connection between the second and third n-well regions by overlapping each of the first and second tap via regions with a first metal region extending across the first n-well region in the first direction; and The IC layout diagram is stored in a storage device.

9. The method according to claim 8, further comprising: positioning third and fourth tap via regions in the first n-well region; as well as A second electrical connection between the third and fourth tapping via regions is established by overlapping each of the third and fourth tapping via regions with a second metal region extending across the first ECO cell in the first direction.

10. An electronic design automation (EDA) system comprising: processor; as well as A non-transitory computer readable storage medium including computer program code for one or more programs, the non-transitory computer readable storage medium and the computer program code configured to, with the processor, cause the processor to perform the following operations: positioning a first tap via region in a second n-well region of first through third n-well regions of an integrated circuit (IC) layout, the first n-well region being separated from each of the second and third n-well regions along a first direction by a distance at least corresponding to a minimum n-well spacing rule; positioning a second tap via region in the third n-well region; placing a first engineering change order (ECO) cell in the first n-well region; overlapping each of the first and second tap via regions with a first metal region extending across the first n-well region in the first direction, thereby establishing a first electrical connection between the second and third n-well regions; routing a first voltage distribution path to the first electrical connection, the first voltage distribution path being configured to distribute a first voltage level; as well as The IC layout diagram is stored in a storage device.

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