Display device

Abstract

A display device is disclosed. According to one aspect of the present disclosure, the display device includes: a first substrate; a plurality of wires disposed on the first substrate and connected to the plurality of data pads and the plurality of gate pads; and a pair of electrostatic discharge circuits connected to the plurality of wirings, respectively, one of the pair of electrostatic discharge circuits being electrically connected to the plurality of high potential power lines and the other being electrically connected to the plurality of low potential power lines. Accordingly, a pair of electrostatic discharge circuits is connected to each of the plurality of wirings to easily protect the plurality of wirings from static electricity.

Description

[0001] This application is a divisional application of the original invention patent application with application number 202410092880.3 (application date: January 23, 2024, invention name: display device). Technical Field

[0002] The present disclosure relates to a display device, and more particularly, for example but not limited to, to a display device using a light emitting diode (LED). Background Art

[0003] As display devices used for monitors of computers, televisions, cellular phones, and the like, there are organic light emitting display (OLED) devices that are self-luminous devices, liquid crystal display (LCD) devices that require a separate light source, and the like.

[0004] The application range of the display device is diversified to personal digital assistants as well as monitors of computers and televisions, and display devices having a large display area and reduced volume and weight are being studied.

[0005] In addition, recently, a display device including a light emitting diode (LED) is attracting attention as a next-generation display device. Since LED is formed of an inorganic material rather than an organic material, it has excellent reliability, making its life longer than that of a liquid crystal display device or an organic light emitting display device. In addition, LED has a faster light emission speed, excellent light emission efficiency, and strong impact resistance, making it excellent in stability and able to display images with high brightness.

[0006] The description provided in the description of the background technology section should not be assumed to be prior art simply because it is mentioned in the description of the background technology section or is associated with the description of the background technology section. The description of the background technology section may include information describing one or more aspects of the subject technology, and the description in this part does not limit the present invention. Summary of the invention

[0007] The inventors have recognized the above requirements for the light emission speed, light emission efficiency, impact resistance, etc. of the display device and the limitations on static electricity. Therefore, one object to be achieved by the present disclosure is to provide a display device that protects the display panel from static electricity.

[0008] Another object to be achieved by the present disclosure is to provide a display device that easily discharges static electricity entering the upper and lower regions of a display panel.

[0009] Still another object to be achieved by the present disclosure is to provide a display device that protects a plurality of wirings from static electricity.

[0010] Still another object to be achieved by the present disclosure is to provide a display device that minimizes the occurrence of a short-circuit problem between wirings or a disconnection problem of wirings due to static electricity.

[0011] The objects of the present disclosure are not limited to the above objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0012] According to one aspect of the present disclosure, a display device includes: a first substrate, in which a plurality of pixel areas and a plurality of gate drive areas are defined; a plurality of first pad electrodes, which are disposed on the first substrate and include a plurality of data pads and a plurality of gate pads; a plurality of wirings, which are disposed on the first substrate and connected to the plurality of data pads and the plurality of gate pads; and a pair of electrostatic discharge circuits, which are respectively connected to the plurality of wirings, one of the pair of electrostatic discharge circuits being electrically connected to a plurality of high potential power lines, and the other being electrically connected to a plurality of low potential power lines. Therefore, a pair of electrostatic discharge circuits is connected to each of the plurality of wirings to easily protect the plurality of wirings from static electricity.

[0013] Additional details of example implementations are included in the detailed description and the accompanying drawings.

[0014] According to the present disclosure, an electrostatic discharge circuit is formed to protect a display panel from static electricity.

[0015] According to the present disclosure, static electricity entering the display panel through the side surface of the display panel can be easily discharged.

[0016] According to the present disclosure, disconnection of a plurality of wirings or a short circuit problem between the plurality of wirings caused by static electricity can be minimized.

[0017] The effects according to the present disclosure are not limited to the contents of the above examples, and more various effects are included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0020] Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0021] Figure 2B is a perspective view of a spliced ​​display device according to an exemplary embodiment of the present disclosure;

[0022] Figure 3is a plan view of a display panel of a display device according to an exemplary embodiment of the present disclosure;

[0023] Figure 4A and Figure 4B is a plan view illustrating a pixel region of a display device according to an exemplary embodiment of the present disclosure;

[0024] Figure 5 is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure;

[0025] Figure 6 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure;

[0026] Figure 7 is an enlarged plan view of a display device according to an exemplary embodiment of the present disclosure;

[0027] Fig. 8A and Figure 8B is a circuit diagram of an electrostatic discharge circuit of a display device according to an exemplary embodiment of the present disclosure;

[0028] Fig. 9 is a plan view of an electrostatic discharge circuit of a display device according to an exemplary embodiment of the present disclosure;

[0029] Fig. 10A and Fig. 10B is a circuit diagram of an electrostatic discharge circuit of a display device according to another exemplary embodiment of the present disclosure; and

[0030] Fig.11 is a plan view of an electrostatic discharge circuit of a display device according to another exemplary embodiment of the present disclosure.

[0031] Throughout the drawings and detailed description, unless otherwise described, the same drawing reference numerals should be understood to refer to the same elements, features, and structures. The relative sizes and depictions of these elements may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0032] By referring to the exemplary embodiments described in detail below in conjunction with the accompanying drawings, the advantages and features of the present disclosure and the methods for achieving these advantages and features will become clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. Exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the content of the present disclosure and the scope of the present disclosure. In addition, the present disclosure is limited only by the scope of the claims and their equivalents.

[0033] The shapes, sizes, areas, ratios, angles, quantities, etc. shown in the drawings for describing the exemplary embodiments of the present disclosure are only examples, and the present disclosure is not limited thereto. Throughout the specification, similar reference numerals generally represent similar elements. In addition, in the following description of the present disclosure, a detailed explanation of known related art may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "comprising", "having", "including", "containing", "constituting", "made of", "formed of", "composed of", and the like used herein are generally intended to allow the addition of other components, unless these terms are used together with terms such as "only". Unless otherwise expressly stated, the singular also includes the plural.

[0034] Even if not explicitly stated, the components are interpreted as including an ordinary error range or an ordinary tolerance range.

[0035] When terms such as "on," "over," "above," "below," "below," "beside," "under," "near," "near," "adjacent," "on the side of," "close to," etc. are used to describe the positional relationship between two components, one or more components may be located between the two components, unless these terms are used together with terms such as "immediately" or "directly."

[0036] Spatially relative terms, such as "below," "below," "under," "lower," "above," "upper," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that, in addition to the orientation shown in the figures, spatially relative terms may also include different orientations of elements in use or operation. For example, if the elements in the figures are inverted, elements described as being "below" or "below" other elements or features will be oriented as being "above" other elements or features. Therefore, the exemplary term "below" may include orientations below and above. Similarly, the exemplary terms "above" or "above" may include orientations "above" and "below."

[0037] When describing a temporal relationship, terms such as "after", "subsequently", "next", "following", "before", etc. may include any situation where two events are not consecutive, unless terms such as "immediately", "directly" or "directly" are explicitly used.

[0038] When an element or layer is “on” another element or layer, another element or layer may be interposed therebetween or directly on the other element or layer.

[0039] Although terms such as "first", "second", "A", "B", "a", and "b" are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component to be mentioned below may be the second component in the technical concept of the present disclosure.

[0040] In addition, when describing the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. may be used herein. Each of these terms is not used to limit the nature, order or sequence of the corresponding component, but is only used to distinguish the corresponding component from other components. In the case of describing that a certain structural element or layer is "connected", "coupled", "bonded" or "joined" to another structural element or layer, it is generally interpreted that the other structural element or layer can be directly or indirectly "connected", "coupled", "bonded" or "joined" to the structural element or layer.

[0041] The term "at least one" should be understood to include any and all combinations of one or more associated listed items. For example, the meaning of "at least one of the first, second, and third items" means the combination of all items proposed from two or more of the first, second, and third items as well as the first, second, or third item.

[0042] The term "device" as used herein may refer to a display device including a display panel and a driver for driving the display panel. Examples of display devices may include light emitting diodes (LEDs), etc. In addition, examples of devices may include laptop computers, televisions, computer monitors, automotive devices, wearable devices, and automotive equipment devices, as well as complete electronic devices (or devices) or complete sets of devices (or devices) including LEDs, etc. as complete products or final products, for example, mobile electronic devices such as smart phones or electronic tablets, but embodiments of the present disclosure are not limited thereto.

[0043] Like reference numerals generally refer to like elements throughout the specification.

[0044] The size and thickness of each component shown in the drawings are illustrated for convenience of description, and the present disclosure is not limited to the size and thickness of the illustrated components.

[0045] The features of the various embodiments of the present disclosure may be partially or completely attached or combined with each other and may be technically interlocked and operated in various ways, and the embodiments may be implemented independently or in association with each other.

[0046] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the example embodiments belong. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0047] In aspects of the present disclosure, for ease of description, source electrodes and drain electrodes are distinguished from each other. However, source electrodes and drain electrodes may be used interchangeably. A source electrode may be a drain electrode, and a drain electrode may be a source electrode. In addition, a source electrode in any aspect of the present disclosure may be a drain electrode in another aspect of the present disclosure, and a drain electrode in any aspect of the present disclosure may be a source electrode in another aspect of the present disclosure.

[0048] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0049] Figure 1 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Figure 2A is a partial cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figure 2B is a perspective view of a spliced ​​display device according to an exemplary embodiment of the present disclosure. All components of each display device according to all embodiments of the present disclosure are operably connected and configured. Figure 1 In the present invention, for convenience of description, among various components of the display device 100, only the display panel PN, the gate driver GD, the data driver DD, and the timing controller TC are illustrated.

[0050] Reference Figure 1 , the display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD supplying various signals to the display panel PN, and a timing controller TC controlling the gate driver GD and the data driver DD.

[0051] The gate driver GD supplies a plurality of scan signals to the plurality of scan lines SL according to a plurality of gate control signals supplied from the timing controller TC. Figure 1 The example in which a gate driver GD is set to be separated from one side of the display panel PN is shown, but the number of gate drivers GD and their arrangement are not limited to this. For example, the number of gate drivers GD can be two, and the two gate drivers GD are respectively set on both sides of the display panel PN and separated from the display panel PN.

[0052] The data driver DD converts image data input from the timing controller TC into data voltages using reference gamma voltages according to a plurality of data control signals supplied from the timing controller TC. The data driver DD may supply the converted data voltages to a plurality of data lines DL.

[0053] The timing controller TC aligns the image data input from the outside to provide the image data to the data driver DD. The timing controller TC can use the synchronization signals (e.g., dot clock signals, data enable signals, and horizontal / vertical synchronization signals) input from the outside to generate a gate control signal and a data control signal. Here, the horizontal synchronization signal is a signal indicating the time taken for one horizontal line of the display screen, and the vertical synchronization signal is a signal indicating the time taken for one frame of the display screen. The data enable signal may correspond to a signal indicating a period of supplying a data voltage to the pixel PX. The timing controller TC supplies the generated gate control signal and data control signal to the gate driver GD and the data driver DD, respectively, to control the gate driver GD and the data driver DD.

[0054] The display panel PN is a configuration for displaying an image to a user, and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL intersect each other, and a plurality of sub-pixels SP are connected to the scan lines SL and the data lines DL, respectively. In addition, although not shown in the drawings, each of the plurality of sub-pixels SP may be connected to a high potential power line VL1, a low potential power line VL2, a reference line, etc.

[0055] In the display panel PN, a display area AA and a non-display area NA disposed near or around the display area AA may be defined.

[0056] The display area AA is an area where an image is displayed in the display device 100. In the display area AA, a plurality of sub-pixels SP constituting a plurality of pixels PX and a circuit for driving the plurality of sub-pixels SP may be provided. The plurality of sub-pixels SP are the minimum units constituting the display area AA, and n sub-pixels SP may form one pixel PX, where n is a positive integer. In each of the plurality of sub-pixels SP, a light emitting diode 130, a thin film transistor TFT for driving the light emitting diode 130, and the like may be provided. The plurality of light emitting diodes 130 may be defined in different ways according to the type of the display panel PN. For example, when the display panel PN is an inorganic light emitting display panel PN, the light emitting diode 130 may be an inorganic light emitting diode (LED) or an inorganic micro light emitting diode (LED), and when the display panel PN is an organic light emitting display panel PN, the light emitting diode 130 may be an organic light emitting diode (OLED), but the embodiments of the present disclosure are not limited thereto.

[0057] In the display area AA, a plurality of wirings for transmitting various signals to the plurality of sub-pixels SP are provided. For example, the plurality of wirings may include a plurality of data lines DL for supplying a data voltage to each of the plurality of sub-pixels SP, a plurality of scan lines SL for supplying a scan signal to each of the plurality of sub-pixels SP, and the like. The plurality of scan lines SL extend in one direction in the display area AA to be connected to the plurality of sub-pixels SP, and the plurality of data lines DL extend in a direction different from the one direction in the display area AA to be connected to the plurality of sub-pixels SP. In addition, in the display area AA, a low potential power line VL2, a high potential power line VL1, and the like may also be provided, but are not limited thereto.

[0058] The non-display area NA is an area where no image is displayed, so that the non-display area NA can be defined as an area extending from the display area AA. In the non-display area NA, a connection line, a pad electrode, or a driver IC such as a gate driver IC or a data driver IC that transmits a signal to the sub-pixel SP of the display area AA can be disposed.

[0059] In addition, the non-display area NA may be located on the rear surface of the display panel PN (ie, a surface on which the sub-pixels SP are not disposed) or may be omitted, and is not limited to that shown in the drawings.

[0060] In addition, drivers such as a gate driver GD, a data driver DD, and a timing controller TC may be connected to the display panel PN in various ways. For example, the gate driver GD may be installed in the non-display area NA in a gate-in-panel (GIP) manner, or may be installed between a plurality of sub-pixels SP in the display area AA in a gate-in-display area (GIA) manner. For example, the data driver DD and the timing controller TC are formed in separate flexible films and printed circuit boards. The data driver DD and the timing controller TC may be electrically connected to the display panel PN by bonding the flexible film and the printed circuit board to pad electrodes formed in the non-display area NA of the display panel PN.

[0061] If the gate driver GD is installed in a GIP manner, and the data driver DD and the timing controller TC transmit signals to the display panel PN through the pad electrode of the non-display area NA, the area of ​​the non-display area NA for setting the gate driver GD and the pad electrode needs to be larger than a predetermined level. Therefore, the frame may increase.

[0062] On the contrary, when the gate driver GD is installed in the display area AA in a GIA manner, and the side lines SRL connecting the signal lines on the front surface of the display panel PN to the pad electrodes on the rear surface of the display panel PN are formed to bond the flexible film and the printed circuit board to the rear surface of the display panel PN, the non-display area NA can be minimized on the front surface of the display panel PN. That is, when the gate driver GD, the data driver DD, and the timing controller TC are connected to the display panel PN as described above, a zero bezel having substantially no bezel can be realized.

[0063] Specifically, refer to Figure 2A and Figure 2B In the non-display area NA of the display panel PN, a plurality of pad electrodes for transmitting various signals to a plurality of sub-pixels SP are provided. For example, in the non-display area NA on the front surface of the display panel PN, a first pad electrode PAD1 for transmitting signals to a plurality of sub-pixels SP is provided. In the non-display area NA on the rear surface of the display panel PN, a second pad electrode PAD2 electrically connected to a driving component (e.g., a flexible film and a printed circuit board) is provided. That is, on the front surface of the display panel PN where an image is displayed, a pad area of ​​the non-display area NA where the first pad electrode PAD1 is provided can be formed to a minimum.

[0064] In this case, although not shown in the drawings, various signal lines (eg, scan lines SL, data lines DL, etc.) connected to the plurality of sub-pixels SP extend from the display area AA to the non-display area NA to be electrically connected to the first pad electrode PAD1.

[0065] The side line SRL is disposed along the side surface of the display panel PN. The side line SRL may electrically connect the first pad electrode PAD1 on the front surface of the display panel PN and the second pad electrode PAD2 on the rear surface of the display panel PN. Therefore, a signal from a driving component on the rear surface of the display panel PN may be transmitted to a plurality of sub-pixels SP through the second pad electrode PAD2, the side line SRL, and the first pad electrode PAD1. Therefore, a signal transmission path is formed from the front surface of the display panel PN to the side surface and the rear surface to minimize the area of ​​the non-display region NA on the front surface of the display panel PN.

[0066] Reference Figure 2B , a spliced ​​display device TD with a large screen size can be realized by connecting a plurality of display devices 100. Figure 2B As shown, when the spliced ​​display device TD is implemented using the display device 100 with a minimized frame, the seam area (the area of ​​the seam region) between the display devices 100 where no image is displayed is minimized, so that the display quality can be improved.

[0067] For example, a plurality of sub-pixels SP may form one pixel PX, and a distance D1 between an outermost pixel PX of one display device 100 and an outermost pixel PX of another display device 100 adjacent to the one display device may be implemented to be equal to a distance D1 between pixels PX in one display device 100. Therefore, a distance D1 between pixels PX between display devices 100 is constantly configured to minimize a seam area (the area of ​​a seam region).

[0068] However, Figure 2A and Figure 2B It is illustrative so that the display device 100 according to the exemplary embodiment of the present disclosure may be a general display device 100 having a bezel, but is not limited thereto.

[0069] Figure 3 is a plan view of a display panel of a display device according to an exemplary embodiment of the present disclosure. Figure 4A and Figure 4B is a plan view illustrating a pixel region of a display device according to an exemplary embodiment of the present disclosure. Figure 5 is a cross-sectional view of a display device according to an exemplary embodiment of the present disclosure. Figure 4A In the figure, only a plurality of light emitting diodes 130, a driving transistor DT of a pixel circuit and a plurality of wirings are illustrated. Figure 4B , only a plurality of reflection plates RF and a plurality of light emitting diodes 130 are illustrated, but the embodiments of the present disclosure are not limited thereto.

[0070] First, refer to Figures 3 to 5 , the display panel PN includes a first substrate 110. The first substrate 110 is a substrate that supports components disposed above the display device 100, and may be an insulating substrate. A plurality of pixels PX are formed on the first substrate 110 to display an image. For example, the first substrate 110 may be formed of glass or resin. In addition, the first substrate 110 may be formed of a polymer or plastic. In some exemplary embodiments, the first substrate 110 may be formed of a plastic material having flexibility or a flexible polymer film. For example, the flexible polymer film may be made of any one of polyimide (PI), polyethylene terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyether sulfone (PES), polyarylate (PAR), polysulfone (PSF), cyclic olefin copolymer (COC), triacetyl cellulose (TAC), polyvinyl alcohol (PVA) and polystyrene (PS), and the present disclosure is not limited thereto.

[0071] Reference Figure 3In the first substrate 110, a plurality of pixel areas UPA, a plurality of gate drive areas GA, and a plurality of pad areas PA1 and PA2 are provided. The plurality of pixel areas UPA and the plurality of gate drive areas GA may be included in the display area AA of the display panel PN.

[0072] First, a plurality of pixel areas UPA are areas where a plurality of pixels PX are disposed. The plurality of pixel areas UPA may be disposed by forming a plurality of rows and a plurality of columns. Each of the plurality of pixels PX disposed in the plurality of pixel areas UPA includes a plurality of sub-pixels SP. Each of the plurality of sub-pixels SP includes a light emitting diode 130 and a pixel circuit to emit light independently.

[0073] The plurality of gate drive areas GA are areas where gate drivers GD are provided. The gate drivers GD may be installed in the display area AA in a gate-in-display area (GIA) manner. For example, the gate drive area GA may be formed between the plurality of pixel areas UPA along a row direction and / or a column direction. The gate driver GD formed in the gate drive area GA may supply a scan signal to the plurality of scan lines SL.

[0074] The gate driver GD disposed in the gate drive area GA may include a circuit for outputting a scan signal. For example, like a pixel circuit, the gate driver may include a plurality of gate drive transistors and / or capacitors. Here, the active layers of the plurality of gate drive transistors may be formed of a semiconductor material such as an oxide semiconductor material, an amorphous semiconductor material, a polycrystalline semiconductor material, or an organic semiconductor material, but are not limited thereto.

[0075] Oxide semiconductor materials can have excellent effects of preventing leakage current and relatively cheap manufacturing costs. Oxide semiconductors can be made of metal oxides such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) and titanium (Ti) or metals such as zinc (Zn), indium (In), gallium (Ga), tin (Sn) or titanium (Ti) and combinations of their oxides. Specifically, oxide semiconductors can include zinc oxide (ZnO), zinc tin oxide (ZTO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium gallium zinc oxide (IGZO), indium zinc tin oxide (IZTO), indium zinc oxide (IZO), indium gallium tin oxide (IGTO) and indium gallium oxide (IGO), but are not limited thereto.

[0076] The polycrystalline semiconductor material has a fast moving speed of carriers such as electrons and holes, and thus has high mobility, and has low power consumption and excellent reliability. The polycrystalline semiconductor may be made of polycrystalline silicon (poly-Si), but is not limited thereto.

[0077] The amorphous semiconductor material may be made of amorphous silicon (a-Si), but is not limited thereto.

[0078] The organic semiconductor material may include metal organic compounds, but is not limited thereto.

[0079] The active layers of the plurality of gate drive transistors may be formed of the same material or different materials from each other. In addition, the active layers of the plurality of gate drive transistors of the gate driver may be formed of the same material as the active layers of the various transistors of the pixel circuit, or different materials from each other.

[0080] The plurality of pad areas PA1 and PA2 are areas where a plurality of first pad electrodes PAD1 are provided. The plurality of first pad electrodes PAD1 may transmit various signals to various wirings extending along the column direction in the display area AA. For example, the plurality of first pad electrodes PAD1 include a data pad DP, a gate pad GP, a high potential power pad VP1, and a low potential power pad VP2. The data pad DP transmits a data voltage to the data line DL, and the gate pad GP transmits a clock signal, a start signal, a gate low voltage, and a gate high voltage for driving the gate driver GD to the gate driver GD. The high potential power pad VP1 transmits a high potential power voltage to the high potential power line VL1, and the low potential power pad VP2 transmits a low potential power voltage to the low potential power line VL2.

[0081] The plurality of pad regions PA1 and PA2 include a first pad region PA1 located at the upper edge of the display panel PN and a second pad region PA2 located at the lower edge of the display panel PN. At this time, in the first pad region PA1 and the second pad region PA2, different types of first pad electrodes PAD1 may be provided. For example, in the first pad region PA1, a data pad DP, a gate pad GP, and a high potential power pad VP1 may be provided among the plurality of first pad electrodes PAD1. In the second pad region PA2, a low potential power pad VP2 may be provided.

[0082] At this time, the plurality of first pad electrodes PAD1 may be formed to have different sizes. For example, the plurality of data pads DP connected one-to-one to the plurality of data lines DL may have a narrower width, while the high potential power pad VP1, the low potential power pad VP2, and the gate pad GP may have a larger width. For example, the width of each of the high potential power pad VP1, the low potential power pad VP2, and the gate pad GP may be greater than the width of each of the plurality of data pads DP. However, Figure 3 The widths of the data pad DP, the gate pad GP, the high potential power pad VP1, and the low potential power pad VP2 shown in FIG. 1 are exemplary, so that the first pad electrode PAD1 may be configured in various sizes, but are not limited thereto.

[0083] In addition, in order to reduce the border of the display panel PN, the edge of the display panel PN may be cut to remove it. A plurality of pixels PX, a plurality of wirings, and a plurality of first pad electrodes PAD1 are formed on an initial first substrate 110i, and an edge portion of the initial first substrate 110i is ground to reduce the border area. During the grinding process, a portion of the initial first substrate 110i is removed to form a first substrate 110 having a smaller size. At this time, a plurality of first pad electrodes PAD1 and wirings disposed at the edge of the first substrate 110 may be partially removed. Therefore, only a portion of the plurality of first pad electrodes PAD1 may remain on the first substrate 110.

[0084] Next, a plurality of data lines DL extending from the plurality of first pad electrodes PAD1 along the column direction are disposed on the first substrate 110 of the display panel PN. The plurality of data lines DL may extend from the plurality of data pads DP of the first pad area PA1 toward the plurality of pixel areas UPA. The plurality of data lines DL may extend along the column direction and overlap the plurality of pixel areas UPA. Therefore, the plurality of data lines DL may transmit a data voltage to a pixel circuit of each of the plurality of sub-pixels SP.

[0085] A plurality of high potential power lines VL1 extending along the column direction are provided on the first substrate 110 of the display panel PN. Some of the plurality of high potential power lines VL1 extend from the high potential power pads VP1 of the first pad area PA1 to the plurality of pixel areas UPA to transmit high potential power voltages to the light emitting diodes 130 of the plurality of sub-pixels SP, respectively. Other high potential power lines VL1 of the plurality of high potential power lines VL1 may be electrically connected to another high potential power line VL1 through an auxiliary high potential power line AVL1 described below. Figure 3 In the description, although it is exemplified that one high potential power line VL1 and one high potential power pad VP1 are provided for convenience of description, a plurality of high potential power lines VL1 and a plurality of high potential power pads VP1 may be provided.

[0086] A plurality of low potential power lines VL2 extending along the column direction are provided on the first substrate 110 of the display panel PN. At least some of the plurality of low potential power lines VL2 extend from the low potential power pad VP2 of the second pad area PA2 to the plurality of pixel areas UPA to transmit the low potential power voltage to the pixel circuit of each of the plurality of sub-pixels SP. Other low potential power lines VL2 of the plurality of low potential power lines VL2 may be electrically connected to another low potential power line VL2 through an auxiliary low potential power line AVL2 to be described below.

[0087] A plurality of scan lines SL extending along the row direction are disposed on the first substrate 110 of the display panel PN. The plurality of scan lines SL extend along the row direction and may be disposed across a plurality of pixel areas UPA and a plurality of gate drive areas GA. The plurality of scan lines SL may transmit scan signals from the gate driver GD to pixel circuits of a plurality of sub-pixels SP.

[0088] A plurality of auxiliary high potential power lines AVL1 extending along the row direction are arranged on the first substrate 110 of the display panel PN. The plurality of auxiliary high potential power lines AVL1 may be arranged in the region between the plurality of pixel areas UPA. The plurality of auxiliary high potential power lines AVL1 extending along the row direction are electrically connected to the plurality of high potential power lines VL1 extending along the column direction through contact holes. The plurality of auxiliary high potential power lines AVL1 and the plurality of high potential power lines VL1 may form a mesh structure. Therefore, the plurality of auxiliary high potential power lines AVL1 and the plurality of high potential power lines VL1 are configured to form a mesh structure to minimize voltage drop and voltage deviation.

[0089] A plurality of auxiliary low potential power lines AVL2 extending in the row direction are arranged on the first substrate 110 of the display panel PN. A plurality of auxiliary low potential power lines AVL2 may be arranged in the region between the plurality of pixel regions UPA. A plurality of auxiliary low potential power lines AVL2 extending in the row direction are electrically connected to a plurality of low potential power lines VL2 extending in the column direction through contact holes. A plurality of auxiliary low potential power lines AVL2 and a plurality of low potential power lines VL2 may form a mesh structure. Therefore, a plurality of auxiliary low potential power lines AVL2 and a plurality of low potential power lines VL2 are configured to form a mesh structure to reduce the resistance of the wiring and minimize the voltage deviation.

[0090] Reference Figure 3 and Figure 4A , a plurality of gate drive lines GVL extending in the row direction and the column direction are disposed on the first substrate 110 of the display panel PN. Some of the plurality of gate drive lines GVL extend from the gate pad GP of the first pad area PA1 to the gate drive area GA to transmit signals to the gate driver GD. Other gate drive lines GVL of the plurality of gate drive lines GVL may extend in the row direction and transmit signals to the gate drivers GD of the plurality of gate drive areas GA. Therefore, various signals are transmitted from the gate drive lines GVL to the gate driver GD to drive the gate driver GD.

[0091] The plurality of gate driving lines GVL may include wirings for transmitting a clock signal, a start signal, a gate high voltage, and a gate low voltage to the gate driver GD. Therefore, various signals are transmitted from the gate driving lines GVL to the gate driver GD to drive the gate driver GD.

[0092] For example, refer to Figure 4A The plurality of gate driving lines GVL may include a gate power line that transmits a power voltage to the gate driver GD of the gate driving area GA. The plurality of gate power lines include a first gate power line VGHL that transmits a gate high voltage to the gate driver GD and a second gate power line VGLL that transmits a gate low voltage to the gate driver GD.

[0093] A plurality of alignment keys are disposed in an area between a plurality of pixel areas UPA in the display panel PN. The plurality of alignment keys are used for alignment during a manufacturing process of the display panel PN. The plurality of alignment keys include a first alignment key AK1 and a second alignment key AK2.

[0094] The first alignment key AK1 may be disposed in the gate driving area GA between the plurality of pixel areas UPA. The first alignment key AK1 may be used to check the alignment position of the plurality of light emitting diodes 130. For example, the first alignment key AK1 may have a cross shape, but is not limited thereto.

[0095] The second alignment key AK2 may be disposed to overlap with the high potential power line VL1 between the plurality of pixel areas UPA. In the high potential power line VL1, a hole overlapping with the second alignment key AK2 is formed to divide the second alignment key AK2 and the high potential power line VL1. The second alignment key AK2 may be used to align the display panel PN and the donor. The display panel PN and the donor are aligned using the second alignment key AK2, and a plurality of light emitting diodes 130 of the donor may be transferred to the display panel PN. For example, the second alignment key AK2 may have a circular ring shape, but is not limited thereto.

[0096] In the following, reference will be made to Figure 4A , Figure 4B and Figure 5 The plurality of sub-pixels SP of the pixel area UPA are described in more detail.

[0097] Reference Figure 4A and Figure 4B In one pixel area UPA, a plurality of sub-pixels SP forming one pixel PX are provided. The sub-pixel SP is the smallest unit constituting a screen, and each of the plurality of sub-pixels SP may emit light having a different wavelength from each other. For example, the plurality of sub-pixels SP may include a first sub-pixel SP1, a second sub-pixel SP2, a third sub-pixel SP3, and a fourth sub-pixel SP4 emitting light of different colors. For example, the first sub-pixel SP1 and the second sub-pixel SP2 may be red sub-pixels, the third sub-pixel SP3 may be a green sub-pixel, and the fourth sub-pixel SP4 may be a blue sub-pixel, but is not limited thereto.

[0098] Alternatively, the plurality of sub-pixels SP may include a red sub-pixel SPR as a first sub-pixel, a green sub-pixel SPG as a second sub-pixel, and a blue sub-pixel SPB as a third sub-pixel. Alternatively, the plurality of sub-pixels SP may further include a white sub-pixel. For example, the plurality of sub-pixels SP may include a red sub-pixel, a green sub-pixel, and a blue sub-pixel, wherein the red sub-pixel, the green sub-pixel, and the blue sub-pixel may be arranged in a repeated manner. Alternatively, the plurality of sub-pixels SP may include a red sub-pixel, a green sub-pixel, a blue sub-pixel, and a white sub-pixel, wherein the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be arranged in a repeated manner, or the red sub-pixel, the green sub-pixel, the blue sub-pixel, and the white sub-pixel may be arranged in a quadrilateral type. For example, the red sub-pixel, the blue sub-pixel, and the green sub-pixel may be arranged sequentially along the row direction, or the red sub-pixel, the blue sub-pixel, the green sub-pixel, and the white sub-pixel may be arranged sequentially along the row direction.

[0099] However, in the exemplary embodiment of the present disclosure, the color type, arrangement type, and arrangement order of the sub-pixels are not limited and may be configured in various forms according to light emitting characteristics, device life, and device specifications.

[0100] In addition, the sub-pixels may have different light-emitting areas according to the light-emitting characteristics. For example, a sub-pixel emitting light of a color different from the color of the blue sub-pixel may have a light-emitting area different from the light-emitting area of ​​the blue sub-pixel. For example, a red sub-pixel, a blue sub-pixel, and a green sub-pixel, or a red sub-pixel, a blue sub-pixel, a white sub-pixel, and a green sub-pixel may each have a different light-emitting area.

[0101] Hereinafter, description will be made by assuming that one pixel PX includes one first subpixel SP1, one second subpixel SP2, one third subpixel SP3, and one fourth subpixel SP4 (ie, two red subpixels, one green subpixel, and one blue subpixel). However, the configuration of the pixel PX is not limited thereto.

[0102] Reference Figure 4AAs described above, a plurality of wirings for supplying various signals to a plurality of sub-pixels SP are provided in a plurality of pixel areas UPA of the first substrate 110. For example, a plurality of data lines DL extending along the column direction, a plurality of high potential power lines VL1, and a plurality of low potential power lines VL2 may be provided on the first substrate 110. For example, a plurality of light emitting control signal lines EL extending along the row direction, a plurality of auxiliary high potential power lines AVL1, a plurality of auxiliary low potential power lines AVL2, a plurality of first scan lines SL1, and a plurality of second scan lines SL2 may be provided on the first substrate 110. The high potential power line VL1 extending along the column direction may be electrically connected to the auxiliary high potential power line AVL1 extending along the row direction through a contact hole. At this time, the light emitting control signal line EL transmits the light emitting control signal to the pixel circuits of the plurality of sub-pixels SP to respectively control the light emitting timing of the plurality of sub-pixels SP.

[0103] Some of the gate drive lines GVL that transmit signals to a plurality of gate drivers GD that are arranged to be spaced apart from each other and between which the pixel area UPA is located may be arranged across the pixel area UPA while extending in the row direction. For example, a first gate power line VGHL that supplies a gate high voltage to the gate driver GD and a second gate power line VGLL that supplies a gate low voltage may be arranged across the pixel area UPA.

[0104] In addition, although the plurality of scan lines SL are illustrated as including the first scan line SL1 and the second scan line SL2, the configuration of the plurality of scan lines SL may vary according to the pixel circuit configuration of the subpixel SP and is not limited thereto. For example, the plurality of scan lines SL include n scan lines, where n is a positive integer.

[0105] A pixel circuit for driving the light emitting diode 130 is provided in each of the plurality of sub-pixels SP on the first substrate 110. The pixel circuit may include a plurality of transistors and a plurality of capacitors. Figure 4A and Figure 5 In the figure, for the convenience of description, only the driving transistor DT, the first capacitor C1 and the second capacitor C2 in the configuration of the pixel circuit are illustrated. However, the pixel circuit may also include a switching transistor, a sensing transistor, a light emitting control transistor, etc., but is not limited thereto. In the pixel circuit of the present disclosure, various configurations of the internal compensation circuit are possible. For example, the number of transistors TFT in the pixel circuit of the present disclosure may be three or more, and the number of capacitors may be 1 or more. For example, the pixel circuit of the present disclosure may be a 3T1C pixel circuit including three TFTs and one capacitor, a 3T2C pixel circuit including three TFTs and two capacitors, a 5T1C pixel circuit including five TFTs and one capacitor, a 5T2C pixel circuit including five TFTs and two capacitors, or a 7T2C pixel circuit including seven TFTs and two capacitors, etc.

[0106] First, a light shielding layer BSM is disposed on the first substrate 110. The light shielding layer BSM blocks light incident on the active layer ACT of a plurality of transistors to minimize leakage current. For example, the light shielding layer BSM is disposed under the active layer ACT of the driving transistor DT to block light incident on the active layer ACT. If light is irradiated onto the active layer ACT, leakage current is generated, which may reduce the reliability of the transistor. Therefore, a light shielding layer BSM that blocks light is disposed on the first substrate 110 to improve the reliability of the driving transistor DT. The light shielding layer BSM may be composed of an opaque conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof), but is not limited thereto.

[0107] The buffer layer 111 is disposed on the light shielding layer BSM. The buffer layer 111 can reduce the penetration of moisture or impurities through the first substrate 110. The buffer layer 111 can be composed of a single layer, a double layer or more layers of silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto. For example, the buffer layer 111 can be formed by a single layer or a multilayer inorganic film, for example, the single layer inorganic film can be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multilayer inorganic film can be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto. However, depending on the type of the first substrate 110 or the type of the thin film transistor, the buffer layer 111 can be omitted, but is not limited thereto.

[0108] The driving transistor DT includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE. The driving transistor DT is disposed on the buffer layer 111.

[0109] First, the active layer ACT of the driving transistor DT is arranged on the buffer layer 111. The active layer ACT can be formed of a semiconductor material such as an oxide semiconductor, amorphous silicon, polycrystalline silicon or a metal organic compound, but is not limited to this. In addition, although not shown in the drawings, in addition to the driving transistor DT, other transistors such as a switching transistor, a sensing transistor and a light emitting control transistor can also be arranged on the buffer layer 111. The active layers of other transistors can also be formed of semiconductor materials such as oxide semiconductors, amorphous silicon, polycrystalline silicon or metal organic compounds, but are not limited to this. The active layers of the transistors included in the pixel circuit (for example, the driving transistor DT, the switching transistor, the sensing transistor and the light emitting control transistor) can be formed of the same material, or of different materials.

[0110] The gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 is an insulating layer that electrically insulates the active layer ACT from the gate electrode GE. The gate insulating layer 112 may be composed of a single layer, a double layer, or more layers of silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto. For example, the gate insulating layer 112 may be formed by a single layer or a multilayer inorganic film, for example, the single layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multilayer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0111] The gate electrode GE is disposed on the gate insulating layer 112. The gate electrode GE may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0112] The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed on the gate electrode GE. Contact holes through which the source electrode SE and the drain electrode DE are each connected to the active layer ACT are formed in the first interlayer insulating layer 113 and the second interlayer insulating layer 114. The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are insulating layers that protect the components thereunder, and may be composed of a single layer, a double layer, or more layers of silicon oxide SiOx or silicon nitride SiNx, but are not limited thereto. For example, each of the first interlayer insulating layer 113 and the second interlayer insulating layer 114 may be formed by a single layer or a multilayer inorganic film, for example, a single layer of inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and a multilayer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0113] A source electrode SE and a drain electrode DE electrically connected to the active layer ACT are disposed on the second interlayer insulating layer 114. The source electrode SE is electrically connected to the first electrode 134 of the light emitting diode 130 and the second capacitor C2, and the drain electrode DE is electrically connected to another configuration of the pixel circuit. The source electrode SE and the drain electrode DE may be formed of a conductive material (e.g., copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof), but are not limited thereto.

[0114] Next, the first capacitor C1 is disposed on the gate insulating layer 112. The first capacitor C1 includes a 1-1th capacitor electrode C1a and a 1-2th capacitor electrode C1b.

[0115] First, the 1-1th capacitor electrode C1a is disposed on the gate insulating layer 112. The 1-1th capacitor electrode C1a may be integrally formed with the gate electrode GE of the driving transistor DT.

[0116] The 1-2nd capacitor electrode C1b is disposed on the first interlayer insulating layer 113. The 1-2nd capacitor electrode C1b is disposed to overlap with the 1-1st capacitor electrode C1a with the first interlayer insulating layer 113 therebetween.

[0117] Therefore, the first capacitor C1 is connected to the gate electrode GE of the driving transistor DT to maintain the voltage of the gate electrode GE of the driving transistor DT for a predetermined period of time.

[0118] Next, the second capacitor C2 is disposed on the first substrate 110. The second capacitor C2 includes a 2-1st capacitor electrode C2a, a 2-2nd capacitor electrode C2b, and a 2-3rd capacitor electrode C2c. The second capacitor C2 includes a 2-1st capacitor electrode C2a as a lower capacitor electrode, a 2-2nd capacitor electrode C2b as a middle capacitor electrode, and a 2-3rd capacitor electrode C2c as an upper capacitor electrode.

[0119] The 2-1st capacitor electrode C2a is disposed on the first substrate 110. The 2-1st capacitor electrode C2a is disposed on the same layer as the light shielding layer BSM, and may be formed of the same material as the light shielding layer BSM.

[0120] The 2-2nd capacitor electrode C2b is disposed on the buffer layer 111 and the gate insulating layer 112. The 2-2nd capacitor electrode C2b is disposed on the same layer as the gate electrode GE, and may be formed of the same material as the gate electrode GE.

[0121] The 2-3rd capacitor electrode C2c is disposed on the first interlayer insulating layer 113. The 2-3rd capacitor electrode C2c may be composed of a first layer C2c1 and a second layer C2c2. The first layer C2c1 of the 2-3rd capacitor electrode C2c may be formed on the same layer as the 1-2nd capacitor electrode C1b using the same material. The first layer C2c1 may be disposed to overlap the 2-1st capacitor electrode C2a and the 2-2nd capacitor electrode C2b with the first interlayer insulating layer 113 therebetween, for example, the first interlayer insulating layer 113 is disposed between the first layer C2c1 of the 2-3rd capacitor electrode C2c and the 2-2nd capacitor electrode C2b.

[0122] The second layer C2c2 of the 2-3rd capacitor electrode C2c is disposed on the second interlayer insulating layer 114. The second layer C2c2 is a portion extending from the source electrode SE of the driving transistor DT and may be connected to the first layer C2c1 through a contact hole of the second interlayer insulating layer 114.

[0123] Therefore, the second capacitor C2 is electrically connected between the source electrode SE of the driving transistor DT and the light emitting diode 130 to increase the inherent capacitance of the light emitting diode 130 and allow the light emitting diode 130 to emit light with higher brightness.

[0124] The first passivation layer 115a is disposed on the driving transistor DT, the first capacitor C1, and the second capacitor C2. The first passivation layer 115a is an insulating layer that protects the components below the first passivation layer 115a, and may be composed of an inorganic material such as silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto. For example, the first passivation layer 115a may be formed by a single-layer or multi-layer inorganic film, for example, the single-layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multi-layer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0125] The first planarization layer 116a is disposed on the first passivation layer 115a. The first planarization layer 116a may planarize the upper portion of the pixel circuit including the driving transistor DT. The first planarization layer 116a may be composed of a single layer, a double layer or more layers, and for example, composed of benzocyclobutene or acrylic organic material, but is not limited thereto.

[0126] Common Reference Figure 4B and Figure 5 , a plurality of reflective plates RF are disposed on the first planarization layer 116a. The reflective plate RF is a configuration that reflects light emitted from a plurality of light emitting diodes 130 above the first substrate 110, and may be formed with a shape corresponding to each of a plurality of sub-pixels SP. One reflective plate RF may be arranged to cover most of the area of ​​one sub-pixel SP. The reflective plate RF reflects the light emitted from the light emitting diode 130, and may also be used as an electrode that electrically connects the light emitting diode 130 and the pixel circuit. Therefore, considering the light reflection efficiency and resistance, the reflective plate RF may include various conductive layers. For example, the reflective plate RF may use an opaque conductive layer such as silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti) or an alloy thereof and a transparent conductive layer such as indium tin oxide (ITO), but the structure of the reflective plate RF is not limited thereto.

[0127] The reflection plate RF includes a first reflection plate RF1 corresponding to the first sub-pixel SP1, a second reflection plate RF2 corresponding to the second sub-pixel SP2, a third reflection plate RF3 corresponding to the third sub-pixel SP3, and a fourth reflection plate RF4 corresponding to the fourth sub-pixel SP4.

[0128] The first reflector RF1 includes a 1-1 reflector RF1a overlapping most of the first sub-pixel SP1 and a 1-2 reflector RF1b overlapping the red light emitting diode 130R of the first sub-pixel SP1. The 1-1 reflector RF1a may reflect light emitted from the red light emitting diode 130R above the red light emitting diode 130R. The 1-1 reflector RF1a may be electrically connected to the source electrode SE of the driving transistor DT and the second capacitor C2 through the first contact hole CH1 of the first planarization layer 116a and the first passivation layer 115a. Therefore, the 1-1 reflector RF1a may electrically connect the first electrode 134 of the red light emitting diode 130R and the driving transistor DT. The 1-2 reflector RF1b may reflect light emitted from the red light emitting diode 130R above the red light emitting diode 130R. The 1-2 reflector RF1b may serve as an electrode electrically connecting the second electrode 135 of the red light emitting diode 130R and the high potential power line VL1.

[0129] The second reflection plate RF2 includes a 2-1 reflection plate RF2a overlapping with most of the second sub-pixel SP2 and a 2-2 reflection plate RF2b overlapping with the red light emitting diode 130R of the second sub-pixel SP2. The 2-1 reflection plate RF2a may reflect light emitted from the red light emitting diode 130R to above the red light emitting diode 130R. The 2-1 reflection plate RF2a is electrically connected to the source electrode SE of the driving transistor DT and the second capacitor C2 through the first contact hole CH1 to transmit the driving current from the driving transistor DT to the first electrode 134 of the red light emitting diode 130R. The 2-2 reflection plate RF2b may serve as an electrode that reflects light emitted from the red light emitting diode 130R above the red light emitting diode 130R and electrically connects the second electrode 135 of the red light emitting diode 130R to the high potential power line VL1.

[0130] The third reflective plate RF3 may be formed as one third reflective plate RF3 overlapping the entire third sub-pixel SP3. The third reflective plate RF3 may reflect light emitted from the green light emitting diode 130G of the third sub-pixel SP3 to above the green light emitting diode 130G. The third reflective plate RF3 is electrically connected to the source electrode SE of the driving transistor DT and the second capacitor C2 through the first contact hole CH1 to transfer the driving current from the driving transistor DT to the first electrode 134 of the green light emitting diode 130G.

[0131] The fourth reflective plate RF4 may be formed as one fourth reflective plate RF4 overlapping the entire fourth sub-pixel SP4. The fourth reflective plate RF4 may reflect light emitted from the blue light emitting diode 130B of the fourth sub-pixel SP4 to above the blue light emitting diode 130B. The fourth reflective plate RF4 is electrically connected to the source electrode SE of the driving transistor DT and the second capacitor C2 through the first contact hole CH1 to transfer the driving current from the driving transistor DT to the first electrode 134 of the blue light emitting diode 130B.

[0132] In addition, although it has been described that the first sub-pixel SP1 and the second sub-pixel SP2 are formed with two reflective plates RF, and the third sub-pixel SP3 and the fourth sub-pixel SP4 are formed with one reflective plate RF, the reflective plate RF may be designed in various ways. For example, only one reflective plate RF may be provided in all the multiple sub-pixels SP such as the third sub-pixel SP3 and the fourth sub-pixel SP4, or multiple reflective plates RF may be provided in all the sub-pixels such as the first sub-pixel SP1 and the second sub-pixel SP2, but the reflective plate is not limited thereto.

[0133] In addition, it has been described that the red light emitting diode 130R of each of the first sub-pixel SP1 and the second sub-pixel SP2 is electrically connected to the high potential power line VL1 through the 1-2 reflector RF1b and the 2-2 reflector RF2b. However, all the red light emitting diodes 130R, the green light emitting diodes 130G, and the blue light emitting diodes 130B may be individually connected to the high potential power line VL1 without the reflector RF, but are not limited thereto.

[0134] Reference Figure 5 , the second passivation layer 115b is disposed on the plurality of reflective plates RF. The second passivation layer 115b is an insulating layer that protects the components below the second passivation layer 115b, and may be composed of a single layer, a double layer, or more layers of silicon oxide SiOx or silicon nitride SiNx, but is not limited thereto. For example, the second passivation layer 115b may be formed by a single layer or a multilayer inorganic film, for example, the single layer inorganic film may be a silicon oxide (SiOx) film or a silicon nitride (SiNx) film, and the multilayer inorganic film may be formed by alternately stacking one or more layers of silicon oxide (SiOx) film, one or more layers of silicon nitride (SiNx) film, and one or more layers of amorphous silicon (a-Si), but the present disclosure is not limited thereto.

[0135] The adhesive layer AD is disposed on the second passivation layer 115b. The adhesive layer AD is formed on the entire surface of the first substrate 110 to fix the light emitting diode 130 disposed on the adhesive layer AD. The adhesive layer AD may be formed of a light-curing adhesive material cured by light. For example, the adhesive layer AD may be formed of an acrylic material including a photoresist, but is not limited thereto. The adhesive layer AD may be formed on the entire surface of the first substrate 110 except for the pad region where the first pad electrode PAD1 is disposed.

[0136] A plurality of light emitting diodes 130 are disposed in each of the plurality of sub-pixels SP on the adhesive layer AD. The light emitting diode 130 is an element that emits light by current, and may include a red light emitting diode 130R that emits red light, a green light emitting diode 130G that emits green light, and a blue light emitting diode 130B that emits blue light, and realizes light of various colors including white through a combination thereof. For example, the light emitting diode 130 may be a light emitting diode (LED) or a micro LED, but is not limited thereto.

[0137] A red light emitting diode 130R is respectively arranged in each of the first sub-pixel SP1 and the second sub-pixel SP2. A pair of green light emitting diodes 130G is arranged in the third sub-pixel SP3, and a pair of blue light emitting diodes 130B is arranged in the fourth sub-pixel SP4. That is, two red light emitting diodes 130R, two green light emitting diodes 130G and two blue light emitting diodes 130B can be arranged in one pixel PX. At this time, each of the red light emitting diodes 130R is connected to the driving transistor DT of each of the first sub-pixel SP1 and the second sub-pixel SP2 to be driven individually. On the contrary, a pair of green light emitting diodes 130G of the third sub-pixel SP3 and a pair of blue light emitting diodes 130B of the fourth sub-pixel SP4 are respectively connected in parallel to a driving transistor DT to be driven, for example, a pair of green light emitting diodes 130G of the third sub-pixel SP3 is connected in parallel to a driving transistor DT to be driven, and a pair of blue light emitting diodes 130B of the fourth sub-pixel SP4 is connected in parallel to a driving transistor DT to be driven.

[0138] The plurality of light emitting diodes 130 include a first semiconductor layer 131 , a light emitting layer 132 , a second semiconductor layer 133 , a first electrode 134 , and a second electrode 135 .

[0139] The first semiconductor layer 131 is disposed on the adhesive layer AD, and the second semiconductor layer 133 is disposed on the first semiconductor layer 131. The first semiconductor layer 131 and the second semiconductor layer 133 may be layers formed by doping n-type or p-type impurities into a specific material. For example, the first semiconductor layer 131 and the second semiconductor layer 133 may be layers doped with n-type or p-type impurities in a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP), or gallium arsenide (GaAs). The p-type impurity may be magnesium (Mg), zinc (Zn), beryllium (Be), etc., and the n-type impurity may be silicon (Si), germanium (Ge), tin (Sn), etc., but is not limited thereto.

[0140] The light emitting layer 132 is disposed between the first semiconductor layer 131 and the second semiconductor layer 133. Holes and electrons are supplied from the first semiconductor layer 131 and the second semiconductor layer 133 to the light emitting layer 132 to emit light. The light emitting layer 132 may be formed of a single layer or a multi-quantum well (MQW) structure, and may be formed of, for example, indium gallium nitride (InGaN), gallium nitride (GaN), etc., but is not limited thereto.

[0141] The first electrode 134 is disposed on the first semiconductor layer 131. The first electrode 134 is an electrode that electrically connects the driving transistor DT and the first semiconductor layer 131. In this case, the first semiconductor layer 131 is a semiconductor layer doped with n-type impurities, and the first electrode 134 may be a cathode. The first electrode 134 may be disposed on the top surface of the first semiconductor layer 131 exposed from the light emitting layer 132 and the second semiconductor layer 133. The first electrode 134 may be composed of a conductive material (for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof), but is not limited thereto.

[0142] The second electrode 135 is disposed on the second semiconductor layer 133. The second electrode 135 may be disposed on the top surface of the second semiconductor layer 133. The second electrode 135 is an electrode electrically connecting the high potential power line VL1 and the second semiconductor layer 133. In this case, the second semiconductor layer 133 is a semiconductor layer doped with p-type impurities, and the second electrode 135 may be an anode. The second electrode 135 may be composed of a conductive material (for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof), but is not limited thereto.

[0143] Next, an encapsulation layer 136 is provided to surround the first semiconductor layer 131, the light emitting layer 132, the second semiconductor layer 133, the first electrode 134, and the second electrode 135. The encapsulation layer 136 is formed of an insulating material to protect the first semiconductor layer 131, the light emitting layer 132, and the second semiconductor layer 133. In the encapsulation layer 136, contact holes exposing the first electrode 134 and the second electrode 135 are formed to electrically connect the first connection electrode CE1 and the second connection electrode CE2 to the first electrode 134 and the second electrode 135.

[0144] In addition, a portion of the side surface of the first semiconductor layer 131 may be exposed from the encapsulation layer 136. The light emitting diode 130 manufactured on the wafer is separated from the wafer to be transferred to the display panel PN. However, during the process of separating the light emitting diode 130 from the wafer, a portion of the encapsulation layer 136 may be torn. For example, during the process of separating the light emitting diode 130 from the wafer, a portion of the encapsulation layer 136 adjacent to the lower edge of the first semiconductor layer 131 of the light emitting diode 130 is torn. Therefore, a portion of the lower side surface of the first semiconductor layer 131 may be exposed to the outside. However, although the lower portion of the light emitting diode 130 is exposed from the encapsulation layer 136, the first connection electrode CE1 and the second connection electrode CE2 are also formed after forming the second planarization layer 116b and the third planarization layer 116c covering the side surface of the first semiconductor layer 131. Therefore. The short circuit problem can be reduced.

[0145] The second planarization layer 116 b and the third planarization layer 116 c are disposed on the adhesive layer AD and the light emitting diode 130 .

[0146] The second planarization layer 116b overlaps a portion of the side surface of the plurality of light emitting diodes 130 to fix and protect the plurality of light emitting diodes 130. The second planarization layer 116b may be formed using a half-tone mask. Therefore, the second planarization layer 116b may be formed to have a step.

[0147] Specifically, a portion of the second planarization layer 116b that is relatively adjacent to the light emitting diode 130 is formed to have a smaller thickness, and a portion of the second planarization layer 116b that is relatively far from the light emitting diode 130 may be formed to have a larger thickness. The portion of the second planarization layer 116b that is adjacent to the light emitting diode 130 is arranged to surround the light emitting diode 130, and may also be in contact with the side surface of the light emitting diode 130. Therefore, the torn portion of the encapsulation layer 136 that protects the side surface of the first semiconductor layer 131 of the light emitting diode 130 during the process of separating the light emitting diode 130 from the wafer to transfer to the display panel PN may be covered by the second planarization layer 116b. Thus, the contact and short circuit problems of the subsequent connection electrodes CE1 and CE2 with the first semiconductor layer 131 may be suppressed.

[0148] The third planarization layer 116c is formed to cover the second planarization layer 116b and the upper portion of the light emitting diode 130. The third planarization layer 116c may include a contact hole exposing the first electrode 134 and the second electrode 135 of the light emitting diode 130. The first electrode 134 and the second electrode 135 of the light emitting diode 130 are exposed from the third planarization layer 116c, and the third planarization layer 116c is partially disposed in a region between the first electrode 134 and the second electrode 135 to reduce a short circuit problem. The second planarization layer 116b and the third planarization layer 116c may be composed of a single layer, a double layer or more layers, and may be formed of, for example, a photoresist or an acrylic organic material, but are not limited thereto.

[0149] In addition, the third planarization layer 116c may cover the light emitting diode 130 and the region adjacent to the light emitting diode 130. The third planarization layer 116c is disposed in the region of the sub-pixel SP surrounded by the bank BB and may be disposed in an island shape, but its shape is not limited thereto. The bank BB may be disposed in a portion of the top surface of the second planarization layer 116b, and the third planarization layer 116c may be disposed in another portion of the top surface of the second planarization layer 116b.

[0150] The first connection electrode CE1 and the second connection electrode CE2 are disposed on the third planarization layer 116c. The first connection electrode CE1 is an electrode electrically connecting the second electrode 135 of the light emitting diode 130 and the high potential power line VL1. The first connection electrode CE1 may be electrically connected to the second electrode 135 of the light emitting diode 130 through a contact hole formed in the third planarization layer 116c.

[0151] The second connection electrode CE2 is an electrode electrically connecting the first electrode 134 of the light emitting diode 130 and the driving transistor DT. The second connection electrode CE2 may be connected to the 1-1st reflection plate RF1a, the 2-1st reflection plate RF2a, the third reflection plate RF3, and the fourth reflection plate RF4 of each of the plurality of sub-pixels SP through a contact hole formed in the third planarization layer 116c, the second planarization layer 116b, the adhesive layer AD, and the second passivation layer 115b. Therefore, the 1-1st reflection plate RF1a, the 2-1st reflection plate RF2a, the third reflection plate RF3, and the fourth reflection plate RF4 are also connected to the source electrode SE of the driving transistor DT, so that the source electrode SE of the driving transistor DT and the first electrode 134 of the light emitting diode 130 may be electrically connected to each other.

[0152] In addition, the first electrode 134, the second connection electrode CE2 and the reflective plate RF are illustrated as being electrically connected to the source electrode SE of the driving transistor DT. However, the first electrode 134, the second connection electrode CE2 and the reflective plate RF may be connected to the drain electrode DE of the driving transistor DT, but are not limited thereto.

[0153] The bank BB is disposed on the first connection electrode CE1, the second connection electrode CE2, and the second planarization layer 116b exposed from the third planarization layer 116c. The bank BB may be disposed to be spaced apart from the light emitting diode 130 by a predetermined interval and at least partially overlap the reflective plate RF. For example, the bank BB may cover a portion of the second connection electrode CE2 formed in the contact hole of the third planarization layer 116c and the second planarization layer 116b. In addition, the bank BB may be disposed on the second planarization layer 116b at a predetermined interval from the light emitting diode 130. In this case, the bank BB and the third planarization layer 116c may be spaced apart from each other on a portion of the second planarization layer 116b having a smaller thickness. That is, the end of the bank BB and the end of the third planarization layer 116c may be disposed on a portion of the second planarization layer 116b having a smaller thickness formed by a half-tone mask process to be spaced apart from each other. The bank BB may be formed of an opaque material to reduce color mixing between a plurality of sub-pixels SP, and may be formed of a black resin, for example, but is not limited thereto.

[0154] In addition, the thickness of a portion of the bank BB formed in the contact hole of the third planarization layer 116c and the second planarization layer 116b to cover a portion of the second connection electrode CE2 and the thickness of a portion of the bank BB disposed on the second planarization layer 116b may be different from each other. Specifically, when a portion of the bank BB covers a portion of the second connection electrode CE2 formed in the contact hole of the third planarization layer 116c and the second planarization layer 116b, since the contact hole is formed from the second passivation layer 115b to the third planarization layer 116c, the bank BB may be disposed below the light emitting diode 130 (i.e., disposed lower than the light emitting diode 130). Therefore, the thickness of the portion of the bank BB covering a portion of the second connection electrode CE2 formed in the contact hole of the third planarization layer 116c and the second planarization layer 116b may be greater than the thickness of a portion of the bank BB disposed on the second planarization layer 116b.

[0155] The first protective layer 117 is disposed on the first connection electrode CE1, the second connection electrode CE2, and the bank BB. The first protective layer 117 is a layer that protects components below the first protective layer 117. The first protective layer 117 may be composed of a single layer, a double layer or more layers, and for example, composed of benzocyclobutene, a light-transmitting epoxy resin, a photoresist, or an acrylic organic material, but is not limited thereto.

[0156] A plurality of first pad electrodes PAD1 are disposed in the first pad area PA1 and the second pad area PA2 of the first substrate 110. Each of the plurality of first pad electrodes PAD1 may be composed of a plurality of conductive layers. For example, each of the plurality of first pad electrodes PAD1 includes a first conductive layer PE1a, a second conductive layer PE1b, and a third conductive layer PE1c.

[0157] First, a first conductive layer PE1a is disposed on the second interlayer insulating layer 114. The first conductive layer PE1a may be formed of the same conductive material as the source electrode SE and the drain electrode DE, and may be composed of, for example, copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0158] The first passivation layer 115a is disposed on the first conductive layer PE1a, and the second conductive layer PE1b is disposed on the first passivation layer 115a. The second conductive layer PE1b may be formed of the same conductive material as the reflective plate RF, and may be composed of, for example, silver (Ag), aluminum (Al), molybdenum (Mo) or an alloy thereof, but is not limited thereto.

[0159] The third conductive layer PE1c is disposed on the second conductive layer PE1b. The third conductive layer PE1c may be formed of the same conductive material as the first and second connection electrodes CE1 and CE2 (eg, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), but is not limited thereto.

[0160] At this time, although not shown in the drawings, a portion of the plurality of conductive layers of the first pad electrode PAD1 is electrically connected to the plurality of wirings on the first substrate 110 to supply various signals to the plurality of wirings and the plurality of sub-pixels SP. For example, the first conductive layer PE1a and / or the second conductive layer PE1b of the first pad electrode PAD1 are connected to the data line DL, the high potential power line VL1, the low potential power line VL2, etc. provided in the display area AA to transmit signals thereto.

[0161] The first metal layer ML1, the second metal layer ML2, and a plurality of insulating layers may be disposed under the first pad electrode PAD1. The first metal layer ML1, the second metal layer ML2, and a plurality of insulating layers are disposed under the first pad electrode PAD1 to adjust the step of the first pad electrode PAD1. For example, the buffer layer 111, the gate insulating layer 112, the first metal layer ML1, the first interlayer insulating layer 113, and the second metal layer ML2 may be sequentially disposed between the first pad electrode PAD1 and the first substrate 110. The first metal layer ML1 may be formed of the same conductive material as the gate electrode GE, and the second metal layer ML2 may be formed of the same conductive material as the 1-2 capacitor electrode C1b. However, the plurality of insulating layers, the first metal layer ML1, and the second metal layer ML2 under the first pad electrode PAD1 may be omitted according to design, and are not limited thereto.

[0162] The second substrate 120 is disposed below the first substrate 110. The second substrate 120 is a substrate that supports components disposed below the display device 100, and may be an insulating substrate. For example, the second substrate 120 may be formed of glass or resin. In addition, the second substrate 120 may include a polymer or plastic. The second substrate 120 may be formed of the same material as the first substrate 110. In some exemplary embodiments, the second substrate 120 may be formed of a plastic material having flexibility or a flexible polymer film. For example, the flexible polymer film may be made of any one of polyimide (PI), polyethylene terephthalate (PET), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polycarbonate (PC), polyether sulfone (PES), polyarylate (PAR), polysulfone (PSF), cyclic olefin copolymer (COC), triacetyl cellulose (TAC), polyvinyl alcohol (PVA) and polystyrene (PS), and the present disclosure is not limited thereto.

[0163] The bonding layer BDL is disposed between the first substrate 110 and the second substrate 120. The bonding layer BDL may be formed of a material cured by various curing methods to bond the first substrate 110 and the second substrate 120. The bonding layer BDL may be disposed in a partial region between the first substrate 110 and the second substrate 120, or may be disposed in the entire region.

[0164] A plurality of second pad electrodes PAD2 are disposed on the rear surface of the second substrate 120. The plurality of second pad electrodes PAD2 are electrodes that transmit signals from a driving component disposed on the rear surface of the second substrate 120 to a plurality of side lines SRL, a plurality of first pad electrodes PAD1, and a plurality of wirings on the first substrate 110. The plurality of second pad electrodes PAD2 are disposed in an end portion of the second substrate 120 in the non-display area NA to be electrically connected to the side lines SRL covering the end portion of the second substrate 120.

[0165] At this time, a plurality of second pad electrodes PAD2 may also be provided to correspond to the plurality of pad areas PA1 and PA2. A plurality of first pad electrodes PAD1 may be provided to correspond to the plurality of second pad electrodes PAD2, respectively, and then the first and second pad electrodes PAD1 and PAD2 overlapping each other may be electrically connected through the side line SRL.

[0166] Each of the plurality of second pad electrodes PAD2 includes a plurality of conductive layers. For example, each of the plurality of second pad electrodes PAD2 includes a fourth conductive layer PE2a, a fifth conductive layer PE2b, and a sixth conductive layer PE2c.

[0167] First, the fourth conductive layer PE2a is disposed under the second substrate 120. The fourth conductive layer PE2a may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0168] The fifth conductive layer PE2b is disposed under the fourth conductive layer PE2a. The fifth conductive layer PE2b may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof, but is not limited thereto.

[0169] The sixth conductive layer PE2c is disposed under the fifth conductive layer PE2b. The sixth conductive layer PE2c may be formed of a conductive material (eg, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO)), but is not limited thereto.

[0170] The second protective layer 121 is disposed in the remaining area of ​​the second substrate 120. The second protective layer 121 may protect various wirings and driving components formed on the second substrate 120. The second protective layer 121 may be composed of a single layer, a double layer or more layers, and may be composed of, for example, benzocyclobutene, a light-transmitting epoxy resin, a photoresist, or an acrylic organic insulating material, but is not limited thereto.

[0171] Although not shown in the drawings, a driving component including a plurality of flexible films and a printed circuit board may be disposed on the rear surface of the second substrate 120. The plurality of flexible films are components in which various components such as a data driver IC are disposed on a base film having ductility to supply signals to a plurality of sub-pixels SP. The printed circuit board is a component electrically connected to the plurality of flexible films to supply signals to the driving IC. On the printed circuit board, various components for supplying various signals to the driving IC may be disposed.

[0172] For example, the fourth conductive layer PE2a and / or the fifth conductive layer PE2b of the second pad electrode PAD2 extend to a plurality of flexible films disposed on the rear surface of the second substrate 120 to be electrically connected to the plurality of flexible films. The plurality of flexible films may supply various signals to the plurality of side lines SRL, the plurality of first pad electrodes PAD1, the plurality of wirings, and the plurality of sub-pixels SP through the second pad electrode PAD2. Therefore, the signal from the driving component may be transmitted to the signal line and the plurality of sub-pixels SP on the front surface of the first substrate 110 through the plurality of second pad electrodes PAD2 of the second substrate 120, the side lines SRL, and the plurality of first pad electrodes PAD1 of the first substrate 110.

[0173] Next, a plurality of side lines SRL are disposed on the side surfaces of the first substrate 110 and the second substrate 120. The plurality of side lines SRL may electrically connect a plurality of first pad electrodes PAD1 formed on the top surface of the first substrate 110 and a plurality of second pad electrodes PAD2 formed on the rear surface of the second substrate 120. The plurality of side lines SRL may be disposed to surround the side surface of the display device 100. Each of the plurality of side lines SRL may cover the first pad electrode PAD1 at the end of the first substrate 110, the side surface of the first substrate 110, the side surface of the second substrate 120, and the second pad electrode PAD2 at the end of the second substrate 120. For example, the plurality of side lines SRL may be formed by a pad printing method using, for example, a conductive ink including silver (Ag), copper (Cu), molybdenum (Mo), chromium (Cr), or the like.

[0174] A side insulating layer 140 covering the plurality of side lines SRL is provided. The side insulating layer 140 may be formed on the top surface of the first substrate 110, the side surface of the first substrate 110, the side surface of the second substrate 120, and the rear surface of the second substrate 120 to cover the side lines SRL. The side insulating layer 140 may protect the plurality of side lines SRL.

[0175] In addition, when the plurality of side lines SRL are formed of a metal material, there may be a problem that external light is reflected from the plurality of side lines SRL or light emitted from the light emitting diode 130 is reflected from the plurality of side lines SRL and thus visually recognized by the user. Therefore, the side insulating layer 140 is configured to include a black material to suppress reflection of external light. For example, the side insulating layer 140 may be formed by a pad printing method using an insulating material including a black material (e.g., black ink).

[0176] A sealing member 150 is provided to cover the side insulating layer 140. The sealing member 150 is provided to surround the side surface of the display device 100 to protect the display device 100 from external impact, moisture and oxygen. For example, the sealing member 150 may be formed of polyimide (PI), polyurethane, epoxy resin, acrylic-based insulating material, etc., but is not limited thereto.

[0177] The optical film MF is disposed on the sealing member 150, the side insulating layer 140, and the first protective layer 117. The optical film MF may be a functional film that realizes a higher quality image while protecting the display device 100. For example, the optical film MF may be an anti-scattering film, an anti-glare film, an anti-reflection film, a low-reflection film, an Oled transmittance controllable film, or a polarizer, but is not limited thereto.

[0178] In addition, the edge of the sealing member 150 and the edge of the optical film MF may be arranged on the same line. During the manufacturing process of the display device 100, the optical film ML having a larger size is attached above the first substrate 110, and the sealing member 150 covering the side insulating layer 140 may be formed. Thereafter, a laser is irradiated on the sealing member 150 and the optical film MF to correspond to the edge of the display device 100 to cut a portion of the sealing member 150 and the optical film MF. Therefore, the size of the display device 100 is adjusted by the peripheral cutting process of the sealing member 150 and the optical film MF, and the edge of the display device 100 may be formed to be flat.

[0179] In addition, the display device 100 according to the exemplary embodiment of the present disclosure may be formed into a zero-border structure having substantially no border using the side lines SRL. At this time, in the zero-border structure, a separate mechanism that surrounds the display panel PN and serves as a ground may not be formed. Therefore, compared with a general display device 100 having a mechanism, in the display device 100 having a zero-border structure, static electricity may more easily enter the display panel PN through the side lines SRL located on the side surface of the display panel PN and the first pad electrode PAD1 connected to the side lines SRL. Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, an electrostatic discharge circuit ESD is formed in the display panel PN to protect the display panel PN from static electricity entering the display panel PN.

[0180] In the following, reference will be made to Figures 6 to 9 An electrostatic discharge circuit ESD of the display device 100 according to an exemplary embodiment of the present disclosure is described.

[0181] Figure 6 is a schematic diagram of a display device according to an exemplary embodiment of the present disclosure. Figure 7 is an enlarged plan view of a display device according to an exemplary embodiment of the present disclosure. Fig. 8A and Figure 8B is a circuit diagram of an electrostatic discharge circuit of a display device according to an exemplary embodiment of the present disclosure. Fig. 9 is a plan view of an electrostatic discharge circuit of a display device according to an exemplary embodiment of the present disclosure. Specifically, Figure 6 1 is a schematic diagram for explaining a connection relationship of another configuration of a plurality of electrostatic discharge circuits ESD and a display panel PN. Figure 7 1 is a plan view enlarging a region adjacent to the first pad region PA1 in a region where the electrostatic discharge circuit ESD is provided. Fig. 8A is a circuit diagram of an electrostatic discharge circuit ESD, and Figure 8B is a circuit diagram illustrating a connection relationship between a data line DL and an electrostatic discharge circuit ESD. Figure 6 In the figure, for convenience of description, the data line DL, the high potential power line VL1 and the auxiliary high potential power line AVL1, and the low potential power line VL2 and the auxiliary low potential power line AVL2 are represented by different types of lines, respectively.

[0182] Reference Figure 6 and Figure 7 , multiple electrostatic discharge circuits ESD are provided on the display panel PN. The electrostatic discharge circuit ESD can protect multiple wirings from the static electricity entering the display panel PN. The electrostatic discharge circuit ESD can use the high potential power line VL1 or the low potential power line VL2 to protect the multiple wirings from being damaged by static electricity. If static electricity enters the multiple wirings, the insulating layer between the multiple wirings is damaged, resulting in a short circuit problem between the multiple wirings or disconnection of the multiple wirings.

[0183] The electrostatic discharge circuit ESD may be disposed on the first substrate 110 of the display panel PN together with a plurality of wirings. The electrostatic discharge circuit ESD may be disposed on the first substrate 110 so as to be adjacent to the upper region and the lower region of the display panel PN. Specifically, a plurality of electrostatic discharge circuits ESD may be disposed between a plurality of pad regions PA1 and PA2 and a plurality of pixel regions UPA on the first substrate 110 and between a plurality of pad regions PA1 and PA2 and a plurality of gate drive regions GA. For example, some of the plurality of electrostatic discharge circuits ESD may be disposed between the first pad region PA1 and the pixel region UPA and between the first pad region PA1 and the gate drive region GA, and other electrostatic discharge circuits ESD may be disposed between the second pad region PA2 and the pixel region UPA and between the second pad region PA2 and the gate drive region GA.

[0184] One end of each of the plurality of electrostatic discharge circuits ESD is electrically connected to any one of the plurality of wirings, and the other end is electrically connected to any one of the high potential power line VL1 or the low potential power line VL2. The electrostatic discharge circuit ESD may be connected between a wiring extending from the data pad DP and the gate pad GP among the plurality of first pad electrodes PAD1 and the high potential power line VL1, or between a wiring extending from the data pad DP and the gate pad GP and the low potential power line VL2.

[0185] For example, one end of some of the electrostatic discharge circuits ESD disposed adjacent to the upper region (i.e., the first pad region PA1) of the display panel PN may be electrically connected to the data line DL extending from the data pad DP, and the other end may be electrically connected to the auxiliary high potential power line AVL1 adjacent to the first pad region PA1. One end of other of the electrostatic discharge circuits ESD disposed adjacent to the first pad region PA1 may be electrically connected to the gate drive line GVL extending from the gate pad GP, and the other end may be electrically connected to the auxiliary high potential power line AVL1. One end of some of the electrostatic discharge circuits ESD disposed adjacent to the second pad region PA2 as the lower region of the display panel PN may be electrically connected to the data line DL, and the other end may be electrically connected to the auxiliary low potential power line AVL2. Other electrostatic discharge circuits ESD disposed adjacent to the second pad area PA2 may have one end electrically connected to the gate driving line GVL extending from the gate pad GP and the other end electrically connected to the auxiliary low potential power line AVL2 .

[0186] In this case, one data line DL may be commonly connected to an electrostatic discharge circuit ESD adjacent to the first pad area PA1 and an electrostatic discharge circuit ESD adjacent to the second pad area PA2. Similarly, one gate drive line GVL may be connected to an electrostatic discharge circuit ESD adjacent to the first pad area PA1 and an electrostatic discharge circuit ESD adjacent to the second pad area PA2. Static electricity entering one end of the gate drive line GVL and one end of the data line DL may be released through the electrostatic discharge circuit ESD adjacent to the first pad area PA1. Static electricity entering the other end of the gate drive line GVL and the other end of the data line DL may be released through the electrostatic discharge circuit ESD adjacent to the second pad area PA2.

[0187] Despite Figure 6 The electrostatic discharge circuit ESD is illustrated as being connected to the gate drive line GVL and the data line DL, but the electrostatic discharge circuit ESD can be electrically connected to wiring other than the gate drive line GVL and the data line DL, and static electricity entering the ends of the wiring other than the gate drive line GVL and the data line DL can be discharged through the electrostatic discharge circuit ESD, and is not limited to this.

[0188] Reference Fig. 8A , each of the plurality of electrostatic discharge circuits ESD includes a protection transistor ET, a first protection capacitor EC1, and a second protection capacitor EC2. A protection source electrode ESE and a protection drain electrode EDE of the protection transistor ET are connected to a first node N1 and a second node N2, respectively. The first protection capacitor EC1 is connected between the first node N1 and a protection gate electrode EGE of the protection transistor ET, and the second protection capacitor EC2 is connected between the second node N2 and the protection gate electrode EGE of the protection transistor ET.

[0189] Any one of the first node N1 and the second node N2 of the electrostatic discharge circuit ESD may be electrically connected to a plurality of wirings such as a data line DL and a gate drive line GVL, and the other of the first node N1 and the second node N2 of the electrostatic discharge circuit ESD may be electrically connected to any one of a high potential power line VL1 and a low potential power line VL2. For example, the first node N1 may be electrically connected to a plurality of wirings, and the second node N2 may be electrically connected to any one of the high potential power line VL1 or the low potential power line VL2. Alternatively, the second node N2 may be electrically connected to a plurality of wirings, and the first node N1 may be electrically connected to any one of the high potential power line VL1 or the low potential power line VL2.

[0190] If an abnormally high voltage is generated in the wiring connected to the first node N1 due to static electricity, a voltage is applied from the first protection capacitor EC1 to the protection gate electrode EGE of the protection transistor ET to turn on the protection transistor ET. Therefore, the turned-on protection transistor ET can discharge static electricity to the high potential power line VL1 or the low potential power line VL2. However, the configuration of the electrostatic discharge circuit ESD is exemplary and is not limited thereto.

[0191] Reference Figure 8B As described above, a pair of electrostatic discharge circuits ESD may be connected to one wiring. For example, a pair of electrostatic discharge circuits ESD may be electrically connected to a high potential power line VL1 and a low potential power line VL2, respectively, with one data line DL located therebetween. A first node N1 of a pair of electrostatic discharge circuits ESD may be connected to a wiring such as a data line DL, and a second node N2 of a pair of electrostatic discharge circuits ESD may be connected to a high potential power line VL1 and a low potential power line VL2, respectively, so that static electricity entering the end of a wiring such as a data line DL may be discharged through the pair of electrostatic discharge circuits ESD.

[0192] Reference Fig. 9 , a protection active layer EACT of the protection transistor ET is disposed on the first substrate 110. One end of the protection active layer EACT may be connected to the first node N1, and the other end may be connected to the second node N2.

[0193] The protection gate electrode EGE of the protection transistor ET is disposed on the protection active layer EACT. The protection gate electrode EGE may be disposed to overlap the remaining portion of the protection active layer EACT except for one end and the other end.

[0194] The protection source electrode ESE and the protection drain electrode EDE of the protection transistor ET are arranged on the protection gate electrode EGE. The protection source electrode ESE is electrically connected to one end of the protection active layer EACT to at least partially overlap with the protection gate electrode EGE. The protection drain electrode EDE is electrically connected to the other end of the protection active layer EACT to at least partially overlap with the protection gate electrode EGE.

[0195] The protection gate electrode EGE and the protection source electrode ESE of the protection transistor ET at least partially overlap to form a first protection capacitor EC1. The protection gate electrode EGE and the protection drain electrode EDE of the protection transistor ET at least partially overlap to form a second protection capacitor EC2.

[0196] At this time, when the pixel circuit formed in the plurality of pixel areas UPA is formed, the configuration of the electrostatic discharge circuit ESD may be formed together. The protection active layer EACT, the protection gate electrode EGE, the protection source electrode ESE, and the protection drain electrode EDE of the protection transistor ET may be formed of the same material as the configuration of the pixel circuit (e.g., the driving transistor DT). For example, the protection active layer EACT of the protection transistor ET and the active layer ACT of the driving transistor DT are formed together between the buffer layer 111 and the gate insulating layer 112. In addition, the protection gate electrode EGE of the protection transistor ET and the gate electrode GE of the driving transistor DT may be formed together between the gate insulating layer 112 and the first interlayer insulating layer 113. The protection source electrode ESE and the protection drain electrode EDE of the protection transistor ET and the source electrode SE and the drain electrode DE of the driving transistor DT may be formed together between the second interlayer insulating layer 114 and the first passivation layer 115a. However, the electrostatic discharge circuit ESD may be formed by a separate process, but is not limited thereto.

[0197] Therefore, in the display device 100 according to the exemplary embodiment of the present disclosure, the electrostatic discharge circuit ESD is provided in the region adjacent to the side line SRL to minimize static electricity entering the display panel PN through the side line SRL, the plurality of first pad electrodes PAD1, and the plurality of wirings. At this time, the electrostatic discharge circuit ESD may be connected to one end and the other end of each of the plurality of wirings. Therefore, static electricity entering the two ends of the plurality of wirings may be effectively discharged, and the reliability of the display device 100 may be improved.

[0198] Fig. 10A and Fig. 10B is a circuit diagram of an electrostatic discharge circuit of a display device according to another exemplary embodiment of the present disclosure. Fig.11 is a plan view of an electrostatic discharge circuit of a display device according to another exemplary embodiment of the present disclosure. Specifically, Fig. 10A is a circuit diagram of an electrostatic discharge circuit ESD, and Fig. 10B 1 is a circuit diagram illustrating a connection relationship between a data line DL and an electrostatic discharge circuit ESD. In addition to the configuration of the electrostatic discharge circuit ESD, Fig. 10A , Fig. 10B and Fig.11 The display device 1000 has Figures 1 to 9 The display device 100 has basically the same configuration.

[0199] Reference Fig. 10A and Fig. 10B, the electrostatic discharge circuit ESD includes a plurality of protection diodes ED. The electrostatic discharge circuit ESD connected between the plurality of wirings on the display panel PN and the high potential power line VL1 and the electrostatic discharge circuit ESD connected between the plurality of wirings and the low potential power line VL2 can each be composed of a plurality of protection diodes ED connected in series between a first node N1 and a second node N2. The first node N1 of the electrostatic discharge circuit ESD can be connected to any one of the plurality of wirings and the low potential power line VL2, and the second node N2 can be connected to one of the plurality of wirings and the high potential power line VL1. For example, the electrostatic discharge circuit ESD composed of a plurality of protection diodes ED can be connected between a data line DL and the high potential power line VL1 and between a data line DL and the low potential power line VL2.

[0200] When the abnormal voltage generated by static electricity is a positive voltage, static electricity can be discharged through the electrostatic discharge circuit ESD electrically connected to the high potential power line VL1. Conversely, when the abnormal voltage generated by static electricity is a negative voltage, static electricity can be discharged through the electrostatic discharge circuit ESD electrically connected to the low potential power line VL2.

[0201] In addition, Fig. 10B 2 , it is illustrated that the electrostatic discharge circuit ESD electrically connected to the high potential power line VL1 and the electrostatic discharge circuit ESD electrically connected to the low potential power line VL2 have different numbers of protection diodes ED. However, the number of protection diodes ED may vary according to design, but is not limited thereto.

[0202] Reference Fig.11 , a protection diode ED of an electrostatic discharge circuit ESD can be formed using a protection transistor ET. The protection gate electrode EGE of the protection transistor ET is electrically connected to one of the protection source electrode ESE and the protection drain electrode EDE to form a protection diode ED. For example, the protection gate electrode EGE and the protection source electrode ESE of the protection transistor ET are connected to form a protection diode ED in which current flows in only one direction from the protection source electrode ESE to the protection drain electrode EDE. However, according to the design, the protection drain electrode EDE may be connected to the protection gate electrode EGE instead of the protection source electrode ESE, but is not limited thereto.

[0203] For example, in the protection diode ED connected between the data line DL and the low potential power line VL2, the protection drain electrode EDE is connected to the data line DL, and the protection source electrode ESE is connected to the low potential power line VL2. In addition, the protection gate electrode EGE may overlap with the protection active layer EACT and may be electrically connected to the protection source electrode ESE. In the protection diode ED connected between the data line DL and the high potential power line VL1, the protection source electrode ESE is connected to the data line DL, and the protection drain electrode EDE is connected to the high potential power line VL1. In addition, the protection gate electrode EGE may overlap with the protection active layer EACT and may be electrically connected to the protection source electrode ESE.

[0204] At this time, if Fig.11 As shown, a pair of electrostatic discharge circuits ESD connected to a wiring can be arranged adjacent to each other. For example, a pair of electrostatic discharge circuits ESD can be arranged together in the upper area of ​​the display panel PN adjacent to the first pad area PA1, and can be arranged together in the lower area of ​​the display panel PN adjacent to the second pad area PA2. However, a pair of electrostatic discharge circuits ESD can be separately arranged in the upper area and the lower area of ​​the display panel PN, but are not limited to this. For example, one electrostatic discharge circuit ESD of a pair of electrostatic discharge circuits ESD can be arranged in the upper area of ​​the display panel PN adjacent to the first pad area PA1, and the other electrostatic discharge circuit ESD of a pair of electrostatic discharge circuits ESD can be arranged in the lower area of ​​the display panel PN adjacent to the second pad area PA2.

[0205] Therefore, in a display device 1000 according to another exemplary embodiment of the present disclosure, an electrostatic discharge circuit ESD configured by a plurality of protection diodes ED is included to protect a plurality of wirings from static electricity. The electrostatic discharge circuit ESD is composed of a plurality of protection diodes ED in which current flows only in one direction. When an abnormal voltage is generated in a plurality of wirings, due to the presence of static electricity, the static electricity can be released to the outside of the plurality of wirings through the plurality of protection diodes ED. Therefore, in a display device 1000 having a zero-frame structure susceptible to static electricity, a plurality of electrostatic discharge circuits ESD are formed in an area adjacent to the side line SRL to protect the display device 1000 from static electricity.

[0206] Exemplary embodiments of the present disclosure may also be described as follows:

[0207] According to one aspect of the present disclosure, a display device includes: a first substrate, in which a plurality of pixel areas and a plurality of gate drive areas are defined; a plurality of first pad electrodes, which are arranged on the first substrate and include a plurality of data pads and a plurality of gate pads; a plurality of wirings, which are arranged on the first substrate and connected to the plurality of data pads and the plurality of gate pads; and a pair of electrostatic discharge circuits, which are respectively connected to the plurality of wirings, wherein one of the pair of electrostatic discharge circuits is electrically connected to a plurality of high potential power lines, and the other of the pair of electrostatic discharge circuits is electrically connected to a plurality of low potential power lines.

[0208] The plurality of pixel regions may include a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, and wherein the first sub-pixel and the second sub-pixel are configured to emit light having the same color.

[0209] One red light emitting diode may be disposed in each of the first sub-pixel and the second sub-pixel, respectively, two green light emitting diodes may be disposed in the third sub-pixel, and two blue light emitting diodes may be disposed in the fourth sub-pixel.

[0210] Each red light-emitting diode can be connected to a driving transistor of each of the first subpixel and the second subpixel to be driven individually, the two green light-emitting diodes of the third subpixel can be connected in parallel to a driving transistor to be driven together, and the two blue light-emitting diodes of the fourth subpixel can be connected in parallel to a driving transistor to be driven together.

[0211] The display device may further include a first reflective plate corresponding to the first sub-pixel, a second reflective plate corresponding to the second sub-pixel, a third reflective plate corresponding to the third sub-pixel, and a fourth reflective plate corresponding to the fourth sub-pixel.

[0212] The first reflective plate may include a 1-1 reflective plate overlapping most of the first sub-pixel and a 1-2 reflective plate overlapping a red light-emitting diode of the first sub-pixel, and the second reflective plate may include a 2-1 reflective plate overlapping most of the second sub-pixel and a 2-2 reflective plate overlapping the red light-emitting diode of the second sub-pixel.

[0213] The third reflection plate may overlap the entire third sub-pixel, and the fourth reflection plate may overlap the entire fourth sub-pixel.

[0214] The plurality of first pad electrodes may be disposed in a first pad region adjacent to an upper edge of the first substrate and a second pad region adjacent to a lower edge of the first substrate.

[0215] The plurality of wirings may include: a plurality of data lines extending from the first pad region to the plurality of pixel regions; and a plurality of gate driving lines extending from the first pad region to the plurality of gate driving regions.

[0216] The display device may further include: a gate driver disposed in the plurality of gate driving regions. The plurality of gate driving lines may include wiring that transmits at least one of a clock signal, a start signal, a gate high voltage, and a gate low voltage to the gate driver.

[0217] The multiple first pad electrodes may also include: multiple high potential power pads, which are arranged in the first pad area and connected to multiple high potential power lines; and multiple low potential power pads, which are arranged in the second pad area and connected to multiple low potential power lines, and multiple data pads and multiple selection pads can be arranged in the first pad area.

[0218] A width of each of the gate pad, the high potential power pad, and the low potential power pad may be greater than a width of the data pad.

[0219] The display device may also include: a plurality of auxiliary high potential power lines extending in a direction perpendicular to the plurality of high potential power lines and electrically connected to the plurality of high potential power lines; and a plurality of auxiliary low potential power lines extending in a direction perpendicular to the plurality of low potential power lines and electrically connected to the plurality of low potential power lines.

[0220] One of the pair of electrostatic discharge circuits may be disposed adjacent to the first pad region, and the other of the pair of electrostatic discharge circuits may be disposed adjacent to the second pad region.

[0221] One of the pair of electrostatic discharge circuits may be disposed adjacent to one end of each of the plurality of wirings, and the other of the pair of electrostatic discharge circuits may be disposed adjacent to the other end of each of the plurality of wirings.

[0222] One of the pair of electrostatic discharge circuits can be connected to an auxiliary high potential power line adjacent to the first pad area among the multiple auxiliary high potential power lines, and the other electrostatic discharge circuit of the pair of electrostatic discharge circuits can be connected to an auxiliary low potential power line adjacent to the second pad area among the multiple auxiliary low potential power lines.

[0223] The pair of electrostatic discharge circuits may be disposed adjacent to any one of the first pad region and the second pad region.

[0224] Each of the pair of electrostatic discharge circuits may include: a protection transistor, wherein a protection source electrode and a protection drain electrode are connected between a first node and a second node; a first protection capacitor, which is connected between the first node and a protection gate electrode of the protection transistor; and a second protection capacitor, which is connected between the second node and the protection gate electrode, and either of the first node and the second node can be electrically connected to multiple wirings, and the other node can be electrically connected to any one of multiple high potential power lines and multiple low potential power lines.

[0225] The protection transistor can be configured with the following structure: a protection active layer is arranged on a first substrate, a protection gate electrode is arranged on the protection active layer, and a protection source electrode and a protection drain electrode are arranged on the protection gate electrode, the protection source electrode and the protection gate electrode can at least partially overlap to form a first protection capacitor, and the protection drain electrode and the protection gate electrode can at least partially overlap to form a second protection capacitor.

[0226] Each of the pair of electrostatic discharge circuits may include a plurality of protection diodes connected in series.

[0227] Each of the multiple protection diodes may include: a protection active layer, which is arranged on the first substrate; a protection gate electrode, which is arranged on the protection active layer; a protection source electrode, which is arranged on the protection gate electrode and is electrically connected to the protection active layer and the protection gate electrode; and a protection drain electrode, which is arranged on the protection gate electrode and is electrically connected to the protection active layer.

[0228] The display device may further include: a plurality of transistors disposed in each of the plurality of pixel regions; and a plurality of gate drive transistors disposed in each of the plurality of gate drive regions.

[0229] The plurality of transistors of the plurality of pixel regions may include an active layer formed of a semiconductor material, and the plurality of gate driving transistors of the plurality of gate drivers may include an active layer formed of a semiconductor material.

[0230] Active layers of transistors of pixel regions may be formed of any one of oxide semiconductor, amorphous silicon and polysilicon, and active layers of gate driver transistors of gate drivers may be formed of any one of oxide semiconductor, amorphous silicon and polysilicon.

[0231] Active layers of a plurality of gate driving transistors of the gate driver may be formed of different materials.

[0232] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided only for the purpose of illustration and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. All technical concepts within the equivalent scope of the present disclosure should be interpreted as falling within the scope of the present disclosure.

[0233] CROSS-REFERENCE TO RELATED APPLICATIONS

[0234] This application claims the benefit of priority to Korean Patent Application No. 10-2023-0027093 filed on February 28, 2023, in the Korean Intellectual Property Office, the entire contents of which are expressly incorporated herein for all purposes.

Claims

1. A display device, comprising: a plurality of pixel regions in which a plurality of pixels are arranged, and the plurality of pixel regions are arranged in a plurality of rows and a plurality of columns; as well as a plurality of gate drive regions, wherein gate drivers are disposed in the plurality of gate drive regions and the plurality of gate drive regions are between the plurality of pixel regions, The plurality of gate drive regions are disposed between a first group of pixel regions in odd-numbered columns and a second group of pixel regions in even-numbered columns among the plurality of pixel regions.

2. The display device according to claim 1, further comprising: A substrate in which the plurality of pixels are defined, wherein the substrate comprises: a first pad region disposed adjacent to one edge of the substrate; a second pad region disposed adjacent to another edge of the substrate; and a display region disposed between the first pad region and the second pad region and comprising the plurality of pixel regions and the plurality of gate drive regions; a plurality of first pad electrodes arranged to overlap the first pad region and the second pad region on one surface of the substrate; and A plurality of second pad electrodes are arranged on another surface of the substrate opposite to the one surface.

3. The display device according to claim 2, further comprising: a plurality of scan lines disposed in the display area and electrically connected to the gate driver; a plurality of data lines extending from one of the first pad region and the second pad region to the display region; a plurality of gate drive lines disposed in the display area and electrically connected to the gate driver; a plurality of power lines extending from one of the first pad region and the second pad region to the display region; as well as a plurality of auxiliary power lines, the plurality of auxiliary power lines being arranged in the display area, and The plurality of auxiliary power lines are arranged to cross the plurality of power lines, and the plurality of auxiliary power lines are electrically connected to the plurality of power lines.

4. The display device according to claim 3, wherein: The plurality of power lines include: a plurality of high potential power lines electrically connected to some of the plurality of first pad electrodes disposed in the first pad region; and a plurality of low potential power lines electrically connected to some of the plurality of first pad electrodes disposed in the second pad region, and Wherein, the plurality of auxiliary power lines include: a plurality of auxiliary high-potential power lines electrically connected to the plurality of high-potential power lines; and A plurality of auxiliary low-potential power lines are electrically connected to the plurality of low-potential power lines.

5. The display device according to claim 4, wherein: The plurality of auxiliary high potential power lines and the plurality of auxiliary low potential power lines are spaced apart from the plurality of first pad electrodes.

6. The display device according to claim 3, further comprising: A plurality of electrostatic discharge circuits are disposed adjacent to an uppermost pixel region and a lowermost pixel region among the plurality of pixel regions and are electrically connected to the plurality of data lines.

7. The display device according to claim 6, wherein: The plurality of electrostatic discharge circuits are electrically connected to at least one of the plurality of power lines and the plurality of auxiliary power lines, and The plurality of electrostatic discharge circuits are arranged adjacent to one of the first pad region and the second pad region.

8. The display device according to claim 7, wherein: The plurality of electrostatic discharge circuits are electrically connected to the plurality of gate driving lines.

9. The display device according to claim 2, further comprising: a plurality of side lines, the plurality of side lines being arranged on a side surface of the substrate, wherein the plurality of side lines cover the plurality of first pad electrodes, the side surface of the substrate and the plurality of second pad electrodes, and The plurality of first pad electrodes and the plurality of second pad electrodes are electrically connected to each other through the plurality of side lines.

10. The display device according to claim 9, further comprising: a side insulating layer disposed on the one surface of the substrate, a surface of the substrate opposite to the one surface, and a side surface of the substrate to cover the plurality of side lines; as well as a sealing member provided on the side surface of the substrate and the surface of the substrate opposite to the one surface to cover the side insulating layer, and Wherein, a side surface of the sealing member is formed to be flat.

11. The display device according to claim 2, wherein: The substrate comprises: a first substrate on which the plurality of pixels and the plurality of first pad electrodes are disposed; and A second substrate is bonded to a rear surface of the first substrate and the plurality of second pad electrodes are disposed on the second substrate.

12. The display device according to claim 1, further comprising: a plurality of micro-LEDs disposed in each of the plurality of pixels; a plurality of driving transistors, the plurality of driving transistors being disposed in the plurality of pixels; a plurality of reflective plates, the plurality of reflective plates being disposed on the plurality of driving transistors in the plurality of pixels; as well as an adhesive layer, the adhesive layer being arranged to cover the plurality of reflective plates, and Wherein, the plurality of micro LEDs are in contact with an upper surface of the adhesive layer.

13. The display device according to claim 12, wherein: Each of the plurality of micro-LEDs comprises: a first semiconductor layer, the first semiconductor layer being disposed on the bonding layer; a light-emitting layer, the light-emitting layer being disposed on the first semiconductor layer; a second semiconductor layer, wherein the second semiconductor layer is disposed on the light emitting layer; a first electrode, the first electrode being disposed on the first semiconductor layer; a second electrode, the second electrode being disposed on the second semiconductor layer; and an encapsulation layer, the encapsulation layer surrounding the first semiconductor layer, the light emitting layer, the second semiconductor layer, the first electrode and the second electrode, Part of a side surface of the first semiconductor layer is exposed from the encapsulation layer.

14. The display device according to claim 13, further comprising: a plurality of organic insulating layers, wherein the plurality of organic insulating layers are disposed on the plurality of micro LEDs; a first connection electrode disposed on the plurality of organic insulating layers and electrically connected to the second electrodes of the plurality of micro LEDs; as well as a second connection electrode disposed on the plurality of organic insulating layers and electrically connected to the first electrodes of the plurality of micro LEDs, wherein the second electrode is electrically connected to a plurality of high potential power lines through the first connecting electrode, and Wherein, the first electrode is electrically connected to the plurality of driving transistors and the plurality of reflection plates through the second connection electrode.

15. The display device according to claim 14, further comprising: A bank is provided on the plurality of organic insulating layers and the second connecting electrode.

16. The display device according to claim 14, wherein: Each of the plurality of pixels includes a plurality of sub-pixels, and The number of the plurality of reflection plates arranged in one pixel is greater than the number of the plurality of sub-pixels forming the one pixel.

17. A display device, comprising: A substrate, the substrate comprising a display area provided with a plurality of pixels; A gate driver, the gate driver being arranged in the display area; A plurality of first pad electrodes, the plurality of first pad electrodes being on the first surface of the substrate and connected to the plurality of pixels; a plurality of second pad electrodes, the plurality of second pad electrodes being on a second surface of the substrate opposite to the first surface; a plurality of side lines disposed along a side surface of the substrate and connecting the plurality of first pad electrodes to the plurality of second pad electrodes; and A side insulating layer is provided to cover the plurality of side lines and includes a black material.

18. The display device according to claim 17, wherein: The plurality of lateral wires include a metal material.

19. The display device according to claim 17, wherein: The substrate further includes a first pad region and a second pad region, wherein the first pad region is arranged adjacent to one edge of the substrate, and the second pad region is arranged adjacent to the other edge of the substrate. The display area is disposed between the first pad area and the second pad area and includes a plurality of pixel areas provided with the plurality of pixels and a plurality of gate drive areas provided with the gate driver. wherein the plurality of first pad electrodes are arranged to overlap the first pad region and the second pad region on the first surface of the substrate, and Wherein, the plurality of second pad electrodes are arranged on the second surface of the substrate.

20. The display device according to claim 19, wherein: The plurality of pixel regions are arranged in a plurality of rows and a plurality of columns, and The plurality of gate drive regions are disposed between a first group of pixel regions in odd-numbered columns and a second group of pixel regions in even-numbered columns among the plurality of pixel regions.

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