Driving chip, display module and display device

Abstract

The invention provides a driving chip, a display module and a display device. The display module comprises a display panel, a first gate drive circuit and a drive chip. The first gate drive circuit comprises a plurality of first shift registers which are arranged in a cascade mode, and the signal output end of each first shift register is electrically connected with the reset control end of at least one reset sub-circuit in the pixel circuit. The driving chip is configured to input a first clock signal to a clock signal end of the first gate driving circuit in a refresh frame stage; in the holding frame stage, a second clock signal is input to the clock signal end of the first gate drive circuit, and the frequency of the second clock signal is smaller than that of the first clock signal.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a driver chip, a display module and a display device. Background Art

[0002] With the development of organic light-emitting display technology, the pixel circuit of the display module has gradually transitioned from LTPS (Low Temperature Poly-Silicon) technology to LTPO (Low Temperature Polycrystalline Oxide) technology. However, compared with LTPS pixel circuits, LTPO pixel circuits require more sets of gate drive circuits to complete the drive, which easily leads to an increase in the power consumption of the display module. Summary of the invention

[0003] Some embodiments of the present disclosure provide a driving chip, a display module and a display device, which are beneficial to reducing the power consumption of the display module.

[0004] In a first aspect of the present disclosure, a display module is provided, comprising: a display panel, comprising a base substrate and a plurality of sub-pixels arranged in an array on the base substrate, each of the sub-pixels comprising a light-emitting device and a pixel circuit electrically connected to the light-emitting device; a first gate driving circuit, comprising a plurality of first shift registers arranged in cascade, a signal output end of the first shift register being electrically connected to a reset control end of at least one reset sub-circuit in the pixel circuit; and a driving chip, electrically connected to the first gate driving circuit, the driving chip being configured as follows: in a case where a current display cycle includes a refresh frame stage and a hold frame stage, a first clock signal is input to a clock signal end of the first gate driving circuit during the refresh frame stage; and a second clock signal is input to a clock signal end of the first gate driving circuit during the hold frame stage, the frequency of the second clock signal being less than the frequency of the first clock signal.

[0005] In some embodiments, the frame holding stage includes a first time period, a second time period and a third time period which are set in sequence, and the second clock signal includes: a first sub-clock signal, a second sub-clock signal and a third sub-clock signal, and the driving chip is configured as follows: in the first time period, a first sub-clock signal is input to the clock signal end of the first gate driving circuit, and the frequency of the first sub-clock signal is less than the frequency of the first clock signal; in the second time period, a second sub-clock signal is input to the clock signal end of the first gate driving circuit, and the frequency of the second sub-clock signal is greater than the frequency of the first sub-clock signal and less than the frequency of the first clock signal; in the third time period, a third sub-clock signal is input to the clock signal end of the first gate driving circuit, and the frequency of the third sub-clock signal is less than the frequency of the second sub-clock signal.

[0006] In some embodiments, the first sub-clock signal and the third sub-clock signal are first constant level signals, and the voltage value of the first constant level signal is approximately the same as the low level voltage value of the first clock signal; the frequency of the second sub-clock signal is one M times the frequency of the first clock signal, where M is an even number.

[0007] In some embodiments, the frequency of the second clock signal is one-N times the frequency of the first clock signal, where N is an even number.

[0008] In some embodiments, the display module also includes a light-emitting driving circuit, and a signal output end of the light-emitting driving circuit is electrically connected to a light-emitting control end in the pixel circuit; the driving chip is electrically connected to the light-emitting driving circuit and is configured to: input a first frame start signal to a signal input end of the first gate driving circuit, and input a light-emitting frame start signal to a signal input end of the light-emitting driving circuit; wherein, in the case where the current display cycle includes a refresh frame stage and a hold frame stage, a refresh frequency of the first frame start signal is greater than or equal to a current refresh frequency of the display panel, and is less than or equal to a refresh frequency of the light-emitting frame start signal; or, the first frame start signal is a second constant level signal in the hold frame stage, and a voltage of the second constant level signal is substantially the same as a high level voltage value of the first frame start signal.

[0009] In some embodiments, the refresh frame stage includes a refresh frame, the hold frame stage includes multiple hold frames, the first frame start signal starts from the refresh frame and is refreshed once every at least one hold frame, so that the refresh frequency of the first frame start signal is greater than the current refresh frequency of the display panel and less than the refresh frequency of the light-emitting frame start signal.

[0010] In some embodiments, the pixel circuit includes a driving subcircuit, a compensation subcircuit, a data writing subcircuit, a storage subcircuit, a first light-emitting control subcircuit, a second light-emitting control subcircuit, a first reset subcircuit, a second reset subcircuit, and a third reset subcircuit. The control end of the driving subcircuit is connected to the first node, the first connection end is connected to the second node, and the second connection end is connected to the third node; the control end of the compensation subcircuit is connected to the second scanning control end, the first connection end is connected to the first node, and the second connection end is connected to the third node; the first connection end of the storage subcircuit is connected to the first power supply voltage end, and the second connection end is connected to the first node; the control end of the first reset subcircuit is connected to the first reset control end, the first connection end is connected to the first initial voltage end, and the second connection end is connected to the third node; the control end of the second reset subcircuit is connected to the second reset control end, the first connection end is connected to the second initial voltage end, and the second connection end is connected to the anode; the control end of the third reset subcircuit is connected to the third reset control end, the first connection end is connected to the third initial voltage end, the control end of the data writing subcircuit is connected to the first scanning control end, the first connection end is connected to the data voltage end, and the second connection end of the data writing subcircuit and the third reset subcircuit is connected to the second node; the control ends of the first light-emitting control subcircuit and the second light-emitting control subcircuit are connected to the light-emitting control end, the first connection end of the first light-emitting control subcircuit is connected to the first power supply voltage end, and the second connection end is connected to the second node; the first connection end of the second light-emitting control subcircuit is connected to the third node, and the second connection end is connected to the anode of the light-emitting device. Wherein, at least one of the first reset control end, the second reset control end and the third reset control end is electrically connected to the signal output end of the first shift register.

[0011] In some embodiments, the signal output terminal of the first shift register is electrically connected to the first reset control terminal, the second reset control terminal and the third reset control terminal respectively.

[0012] In some embodiments, the signal output end of the first shift register is electrically connected to the second reset control end and the third reset control end respectively, the display module further comprises a second gate driving circuit, comprising a plurality of second shift registers arranged in cascade, the signal output end of the second shift register is electrically connected to the first reset control end. The driving chip is electrically connected to the second gate driving circuit, and is configured to: input a third clock signal to the clock signal end of the second gate driving circuit during the refresh frame phase; input a fourth clock signal to the clock signal end of the second gate driving circuit during the hold frame phase, the frequency of the fourth clock signal being less than the frequency of the third clock signal and the frequency of the second clock signal.

[0013] In some embodiments, the driver chip is further configured to: input a first frame start signal to the signal input terminal of the first gate drive circuit, and input a second frame start signal to the signal input terminal of the second gate drive circuit. Wherein, when the current display cycle includes a refresh frame stage and a hold frame stage, the refresh frequency of the second frame start signal is less than the refresh frequency of the first frame start signal; or, the first frame start signal and the second frame start signal are second constant level signals in the hold frame stage, and the voltage of the second constant level signal is substantially the same as the high level voltage value of the first frame start signal.

[0014] In some embodiments, the signal output end of the first shift register is electrically connected to the third reset control end, and the display module further includes: a second gate driving circuit and a third gate driving circuit; the second gate driving circuit includes a plurality of second shift registers arranged in cascade, and the signal output end of the second shift register is electrically connected to the first reset control end; the third gate driving circuit includes a plurality of third shift registers arranged in cascade, and the signal output end of the third shift register is electrically connected to the second reset control end. The driving chip is electrically connected to the second gate driving circuit and the third gate driving circuit respectively, and is configured as follows: in the refresh frame phase, a third clock signal is input to the clock signal end of the second gate driving circuit, and a fifth clock signal is input to the clock signal end of the third gate driving circuit; in the hold frame phase, a fourth clock signal is input to the clock signal end of the second gate driving circuit, and a sixth clock signal is input to the clock signal end of the third gate driving circuit. Wherein, the frequency of the fourth clock signal is less than the frequency of the third clock signal, the frequency of the sixth clock signal is less than the frequency of the fifth clock signal, and the frequencies of the fourth clock signal and the sixth clock signal are less than or equal to the frequency of the second clock signal.

[0015] In some embodiments, the driver chip is further configured to: input a first frame start signal to the signal input terminal of the first gate driver circuit, input a second frame start signal to the signal input terminal of the second gate driver circuit, and input a third frame start signal to the signal input terminal of the third gate driver circuit. Wherein, in the case where the current display cycle includes a refresh frame stage and a hold frame stage, the refresh frequencies of the second frame start signal and the third frame start signal are less than the refresh frequency of the first frame start signal; or, the first frame start signal, the second frame start signal and the third frame start signal are second constant level signals in the hold frame stage, and the voltage of the second constant level signal is substantially the same as the high level voltage value of the first frame start signal.

[0016] In some embodiments, the display module also includes: a fourth gate driving circuit, including a plurality of fourth shift registers arranged in cascade, and a signal output end of the fourth shift register is electrically connected to the first scan control end; a fifth gate driving circuit, including a plurality of fifth shift registers arranged in cascade, and a signal output end of the fifth shift register is electrically connected to the second scan control end; a light-emitting driving circuit, including a plurality of sixth shift registers arranged in cascade, and a signal output end of the sixth shift register is electrically connected to the light-emitting control end; and the driving chip is electrically connected to the fourth gate driving circuit, the fifth gate driving circuit and the light-emitting driving circuit, respectively.

[0017] In some embodiments, the base substrate includes a display area, a first border area and a second border area, the first border area is located on a first side of the display area, the second border area is located on a second side of the display area, the first side and the second side are opposite sides, and the plurality of sub-pixels are located in the display area; the fourth gate driving circuit is arranged in the first border area and the second border area; the fifth gate driving circuit, the first gate driving circuit and the third gate driving circuit are arranged in the first border area, and the fifth gate driving circuit is located on a side of the fourth gate driving circuit away from the display area, the third gate driving circuit is located on a side of the fifth gate driving circuit away from the display area, and the first gate driving circuit is located on a side of the third gate driving circuit away from the display area; the second gate driving circuit and the light-emitting driving circuit are arranged in the second border area, the second gate driving circuit is located on a side of the fourth gate driving circuit away from the display area, and the light-emitting driving circuit is located on a side of the second gate driving circuit away from the display area.

[0018] In a second aspect of the present disclosure, a driving chip is provided, comprising a memory and a processor, wherein the memory stores a computer program executable on the processor, and the processor executes the following steps of the computer program: in a case where a current display cycle includes a refresh frame stage and a hold frame stage, in the refresh frame stage, a first clock signal is input to a clock signal end of a first gate driving circuit; in the hold frame stage, a second clock signal is input to a clock signal end of the first gate driving circuit, and a frequency of the second clock signal is less than a frequency of the first clock signal; wherein the first gate driving circuit comprises a plurality of first shift registers arranged in cascade connection, and a signal output end of the first shift register is electrically connected to a reset control end of at least one reset subcircuit in a pixel circuit of a display panel.

[0019] In a third aspect of the present disclosure, a display device is provided, comprising the display module provided in the first aspect.

[0020] The display module provided by some embodiments of the present disclosure, when the current display cycle includes a refresh frame stage and a hold frame stage, reduces the power consumption of the first gate drive circuit by down-converting the clock signal of the first gate drive circuit connected to at least one reset sub-circuit in the pixel circuit during the hold frame stage, thereby reducing the power consumption of the display module.

[0021] The above description is only an overview of the technical solutions of some embodiments of the present disclosure. In order to more clearly understand the technical means of the embodiments of the present disclosure, they can be implemented according to the contents of the specification. In order to make the embodiments of the present disclosure more obvious and easy to understand, the specific implementation methods of some embodiments of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only used to illustrate exemplary embodiments and are not to be considered as limiting the embodiments of the present disclosure. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0023] Figure 1 A schematic diagram showing the structure of a display device according to some embodiments of the present disclosure is shown;

[0024] Figure 2 A schematic plan view of a display panel according to some embodiments of the present disclosure is shown;

[0025] Figure 3 A schematic diagram showing a driving architecture of a display module according to some embodiments of the present disclosure is shown;

[0026] Figure 4 A schematic diagram showing the structure of a pixel circuit in some embodiments of the present disclosure is shown;

[0027] Figure 5 A circuit diagram showing a pixel circuit of some embodiments of the present disclosure;

[0028] Figure 6 A timing diagram of a first gate driving circuit of some embodiments of the present disclosure is shown;

[0029] Figure 7 A timing diagram of a first gate driving circuit according to some other embodiments of the present disclosure is shown;

[0030] Figure 8 A timing diagram showing a light emitting frame start signal and three exemplary first frame start signals according to some embodiments of the present disclosure;

[0031] Fig. 9 A circuit diagram of a first shift register according to some embodiments of the present disclosure is shown;

[0032] Fig.10 Shows Figure 5 An exemplary timing diagram of a pixel circuit in a refresh frame;

[0033] Fig.11 A circuit diagram showing pixel circuits of other embodiments of the present disclosure;

[0034] Fig.12 A circuit diagram of a second shift register according to some embodiments of the present disclosure is shown;

[0035] Fig.13 Shows Fig.11 An exemplary timing diagram of a pixel circuit in a refresh frame;

[0036] Fig.14 A timing diagram of a second gate driving circuit of some embodiments of the present disclosure is shown;

[0037] Fig.15 shows a timing diagram of a second gate driving circuit of some other embodiments of the present disclosure;

[0038] Fig.16 A circuit diagram showing a pixel circuit according to some other embodiments of the present disclosure;

[0039] Fig.17 Shows Fig.16 An exemplary timing diagram of a pixel circuit in a refresh frame;

[0040] Fig.18 shows a timing diagram of a third gate driving circuit of some embodiments of the present disclosure;

[0041] Fig.19 shows a timing diagram of a third gate driving circuit of some other embodiments of the present disclosure;

[0042] Fig. 20 A schematic diagram showing the arrangement of gate drive circuits in some embodiments of the present disclosure is shown;

[0043] Fig.21 A timing diagram of a frame start signal according to some embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0044] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0045] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The words "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantitative restrictions, but indicate the existence of at least one. "At least one" includes one or more situations. "Include" or "comprising" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Electrically connected", "connected" or "connected" and similar words indicate electrical connections, whether direct or indirect. " / " represents a division sign, and "×" represents a multiplication sign.

[0046] In some embodiments of the present disclosure, the transistor may be a thin film transistor (TFT), a field effect transistor (MOS) or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as examples.

[0047] In some embodiments of the present disclosure, the control electrode of the transistor is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor may be symmetrical in structure, the source and drain thereof may be structurally indistinguishable, that is, the first electrode and the second electrode of the transistor in some embodiments of the present disclosure may be structurally indistinguishable. Exemplarily, the first electrode of the transistor may be the source, and the second electrode may be the drain.

[0048] In some embodiments of the present disclosure, the "operating level" refers to a voltage that can turn on the operated transistor included therein, and correspondingly, the "non-operating level" refers to a level that cannot turn on the operated transistor included therein (i.e., the transistor is cut off). Generally, for a square wave pulse signal used by a shift register during operation, the operating level corresponds to the level of the square wave pulse portion of the square wave pulse signal, while the non-operating level corresponds to the level of the non-square wave pulse portion.

[0049] In some embodiments of the present disclosure, the first node, the second node, the third node, etc. do not represent actual existing components, but represent the junction points of related electrical connections in the circuit diagram, that is, these nodes are nodes formed by the junction points of related electrical connections in the circuit diagram.

[0050] Figure 1Schematic diagram of the structure of the display device of some embodiments of the present disclosure is shown. Figure 1 As shown, some embodiments of the present disclosure provide a display device 1, which can be any device that displays either moving (e.g., video) or fixed (e.g., still images), and whether text or images. In some embodiments, the display device 1 can be a medium or large-sized display product such as a display screen, a television, a laptop computer, or a tablet computer. Of course, in other embodiments, the display device can also be a small-sized display product such as a mobile phone, a personal digital assistant (English: Personal Digital Assistant; abbreviated: PDA) or a wearable device.

[0051] In some embodiments, the display device may be an organic light emitting diode (OLED) display device, a quantum dot light emitting diode (QLED) display device, a micro light emitting diode (Micro LED) display device, etc., and the present disclosure does not make any specific limitations on this.

[0052] In some embodiments, the display device may be a low temperature polycrystalline oxide (LTPO) display device, which can support a variety of refresh rates, such as from 120 Hz to 1 Hz.

[0053] like Figure 1 As shown, the display device 1 includes a display module 10. The display module 10 may be a foldable display module or a non-foldable display module, which is not limited in the present disclosure.

[0054] In some embodiments, the display module 10 includes a display panel, a driver chip, and multiple gate driver circuits. It should be noted that the gate driver circuit can be integrated in the border area of ​​the display panel, or can be set independently of the display panel. The gate driver circuit integrated on the display panel can be referred to as GOA (English full name: Gate Driver on Array).

[0055] Figure 2 FIG. 2 shows a schematic plan view of a display panel of some embodiments of the present disclosure. Figure 2As shown, the display panel 10 includes a base substrate 101 and a plurality of sub-pixels p arranged in an array on the base substrate 101. Each sub-pixel p includes a light emitting device and a pixel circuit electrically connected to the light emitting device, and the pixel circuit is configured to drive the light emitting device to emit light.

[0056] The base substrate 101 may include a display area AA and a frame area NA. The display area AA is an area on the display panel 100 for displaying images, and the frame area NA is an area on the display panel 100 other than the display area AA. The frame area NA may be located on at least one side (e.g., one side, or multiple sides) of the display area AA. For example, the frame area NA may be arranged around the display area AA.

[0057] The display area AA is provided with sub-pixels p of multiple luminous colors, for example, each sub-pixel can display a single color. For example, the sub-pixels of multiple luminous colors may include a first sub-pixel emitting a first color light, a second sub-pixel emitting a second color light, and a third sub-pixel emitting a third color light. The first color, the second color, and the third color are three primary colors, for example, red, blue, and green.

[0058] by Figure 2 Taking the arrangement shown as an example, sub-pixels arranged in a row along the horizontal direction X can be called sub-pixels in the same row; sub-pixels arranged in a column along the vertical direction Y can be called sub-pixels in the same column. The display panel 10 also includes a plurality of gate lines and a plurality of data lines (not shown in the figure). The plurality of gate lines and the plurality of data lines cross each other to define a plurality of pixel areas distributed in an array in the display area. The gate line is configured to connect the gate drive circuit and the pixel circuit, and the data line is configured to transmit a data voltage signal to the pixel circuit.

[0059] Figure 3 Schematic diagram of the driving architecture of the display module of some embodiments of the present disclosure is shown. Figure 3As shown, the driving chip 300 is electrically connected to multiple groups of gate driving circuits 200, and is configured to provide gate driving signals (also referred to as GOA signals) to the gate driving circuits 200. The multiple groups of gate driving circuits 200 are electrically connected to the pixel circuits 110, respectively, and are configured to drive the pixel circuits 110 to control the light-emitting devices to emit light under the control of the gate driving signals. For example, the gate driving signal may include a frame start signal (STV), a clock signal (such as including at least one group of positive phase clock signal CK and negative phase clock signal CB), and a vertical synchronization signal (Vertical External Line, referred to as: VEL), etc. The positive phase clock signal CK and the clock signal negative phase CB are square wave signals with alternating high and low levels, and when the positive phase clock signal CK is at a low level, the negative phase clock signal CB is at a high level, and when the negative phase clock signal CB is at a low level, the positive phase clock signal CK is at a high level. In some embodiments, the high level period and the low level period of the positive phase clock signal CK may overlap with the low level period and the high level period of the negative phase clock signal CB, respectively. In other embodiments, the duration of the high level period of the positive phase clock signal CK may be greater than the duration of the low level period of the negative phase clock signal CB, the duration of the high level period of the negative phase clock signal CB may be greater than the duration of the corresponding low level period of the positive phase clock signal CK, and the high level periods of the positive phase clock signal CK and the negative phase clock signal CB may overlap. For example, when the positive phase clock signal CK is at a high level, the negative phase clock signal CB jumps from a high level to a low level, continues for a certain period of time, and then jumps back to a high level. When the positive phase clock signal CK is at a low level, the negative phase clock signal CB is at a high level; when the negative phase clock signal CB is at a high level, the positive phase clock signal CK jumps from a high level to a low level, continues for a certain period of time, and then jumps back to a high level. When the negative phase clock signal CB is at a low level, the positive phase clock signal CK is at a high level.

[0060] In some embodiments, one driver chip 300 may be provided, and the above-mentioned multiple gate driving circuits 200 may be electrically connected to the same driver chip 300. In other embodiments, multiple driver chips 300 may be provided, and each driver chip 300 is electrically connected to at least one gate driving circuit 200.

[0061] In some embodiments, the driver chip 300 may be a display driver integrated circuit (full name in English: Display Driver Integrated Circuit, abbreviated as: DDIC). In other embodiments, the driver chip 300 may also be a touch and display driver integrated circuit (Touch and Display Driver Integration, abbreviated as TDDI). The number of groups of gate driver circuits 200 included in the display module 1 is related to the pixel circuit 110 used. For example, for an LTPO pixel circuit, it can be driven by four groups of gate driver circuits 200, or it can be driven by five groups of gate driver circuits 200, or it can also be driven by six groups of gate driver circuits 200.

[0062] Figure 4 FIG. 2 shows a schematic diagram of the structure of a pixel circuit in some embodiments of the present disclosure. Figure 4 As shown, the pixel circuit 110 may include a storage subcircuit 114, a driving subcircuit 112, a compensation subcircuit 113, a data writing subcircuit 111, a first light-emitting control subcircuit 115, a second light-emitting control subcircuit 116, a first reset subcircuit 117, a second reset subcircuit 118 and a third reset subcircuit 119.

[0063] The control end of the driving subcircuit 112 is connected to the first node, the first connection end is connected to the second node, and the second connection end is connected to the third node. The control end of the compensation subcircuit 113 is connected to the second scan control end Gate_N, the first connection end is connected to the first node, and the second connection end is connected to the third node. The first connection end of the storage subcircuit 114 is connected to the first power supply voltage end ELVDD, and the second connection end is connected to the first node. The control end of the first reset subcircuit 117 is connected to the first reset control end Reset1, the first connection end is connected to the first initial voltage end vinit1, and the second connection end is connected to the third node. The control end of the second reset subcircuit 118 is connected to the second reset control end Reset2, the first connection end is connected to the second initial voltage end vinit2, and the second connection end is connected to the anode of the light emitting device EL (i.e., connected to Figure 4The control end of the third reset subcircuit 119 is connected to the third reset control end Reset3, and the first connection end is connected to the third initial voltage end vinit3. The control end of the data writing subcircuit 111 is connected to the first scanning control end Gate_P, and the first connection end is connected to the data voltage end. The second connection ends of the data writing subcircuit 111 and the third reset subcircuit 119 are connected to the second node. The control ends of the first light-emitting control subcircuit 115 and the second light-emitting control subcircuit 116 are connected to the light-emitting control end EM, the first connection end of the first light-emitting control subcircuit 115 is connected to the first power supply voltage end ELVDD, and the second connection end is connected to the second node, the first connection end of the second light-emitting control subcircuit 116 is connected to the third node, and the second connection end is connected to the anode of the light-emitting device EL. The cathode of the light-emitting device EL is connected to the second power supply voltage end VSS.

[0064] The first scan control terminal Gate_P is used to receive a first scan signal, and the data writing subcircuit 111 is configured to write data under the control of the first scan signal. The second scan control terminal Gate_N is used to receive a second scan signal, and the compensation subcircuit 113 is configured to compensate the threshold voltage of the transistor included in the driving subcircuit 112 under the second scan signal. The working levels of the first scan signal and the second scan signal are different. The light emitting control terminal EM is used to receive a light emitting control signal, and the first light emitting control subcircuit 115 and the second light emitting control subcircuit 116 are configured to control the light emitting device EL to emit light based on the light emitting control signal.

[0065] The first reset control terminal Reset1 is used to receive a first reset signal, and the first reset subcircuit 117 is configured to write a first initial voltage Vinit1 to the third node N3 under the control of the first reset signal to reset the third node N3. The second reset control terminal Reset2 is used to receive a second reset signal, and the second reset subcircuit 118 is configured to write a second initial voltage Vinit2 to the anode of the light-emitting device EL under the control of the second reset signal to reset the anode of the light-emitting device EL. The third reset control terminal Reset3 is used to receive a third reset signal, and the third reset subcircuit 119 is configured to write a third initial voltage Vinit3 to the second node N2 under the control of the third reset signal to reset the second node N2.

[0066] The first scanning control terminal Gate_P, the second scanning control terminal Gate_N and the light emitting control terminal EM can be driven by three different gate driving circuits 200. The first reset control terminal Reset1, the second reset control terminal Reset2 and the third reset control terminal Reset3 can be the same reset control terminal, or different reset control terminals. Accordingly, the first reset signal, the second reset signal and the third reset signal can be the same reset signal, or different reset signals.

[0067] Figure 5 A circuit diagram of a pixel circuit according to some embodiments of the present disclosure is shown. Figure 5 In the example, the first reset control terminal Reset1, the second reset control terminal Reset2 and the third reset control terminal Reset3 are the same reset control terminal Reset_H. Figure 5 As shown, the first reset subcircuit 117 includes a first transistor T1, the compensation subcircuit 113 includes a second transistor T2, the driving subcircuit 112 includes a third transistor, the data writing subcircuit 111 includes a fourth transistor T4, the first light-emitting control subcircuit 115 includes a fifth transistor T5, the second light-emitting control subcircuit 116 includes a sixth transistor T6, the second reset subcircuit 118 includes a seventh transistor T7, the third reset subcircuit 119 includes an eighth transistor T8, and the storage subcircuit 114 includes a storage capacitor Cst1. The pixel circuit is an 8T1C pixel circuit using LTPO technology, wherein the second transistor T2 is an N-type transistor such as an NMOS tube, and the other transistors are P-type transistors such as PMOS tubes.

[0068] It should be noted that one of the first and second electrodes of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7 and the eighth transistor T8 can be used as the first connection terminal of the sub-circuit to which it belongs, the other can be used as the second connection terminal of the sub-circuit to which it belongs, and the control electrode can be used as the control terminal of the sub-circuit to which it belongs.

[0069] exist Figure 5 In the corresponding pixel circuit, the function of the first reset subcircuit 117 is to write the first initial voltage into the second electrode (ie, Figure 5The first initial voltage Vinit1 is used to initialize the voltage of the second electrode of the third transistor T3. The magnitude of the first initial voltage Vinit1 will affect the charging and discharging of the third node N3 and thus affect the afterimage effect of the screen. The first initial voltage Vinit1 is generally a negative voltage (i.e., less than 0). If the first initial voltage Vinit1 is too high (close to 0), it will affect the reset effect of the third transistor T3, thereby affecting the afterimage effect and the display response time. If the first initial voltage Vinit1 is too negative, it will affect the voltage writing of the first node N1, resulting in a black state voltage V GMP In severe cases, it may even cause bright spots.

[0070] The function of the second reset subcircuit 118 is to write the second initial voltage Vinit2 into the anode of the light emitting device EL (i.e. Figure 5 The fourth node N4 in the light emitting device EL is used to initialize the voltage of the anode of the light emitting device EL, thereby improving the influence of the parasitic capacitance between the anode and the cathode of the light emitting device EL on the display.

[0071] The function of the third reset subcircuit 119 is to write the third initial voltage Vinit3 into the first electrode (i.e., Figure 5 The second node N2 in the third transistor T3 is used to initialize the voltage of the first electrode of the third transistor T3, so as to improve the flicker (VRR) problem during the refresh frequency switching process. It can be understood that due to the hysteresis of the third transistor T3, it is easy to cause the brightness of the display panel to change when the refresh frequency is switched. Writing the third initial voltage Vinit3 to the first electrode of the third transistor T3 can increase the source voltage of the third transistor T3 in the refresh frame stage, increase the threshold voltage (Vth) offset of the third transistor T3, so that the threshold voltage offset of the third transistor T3 remains consistent in the refresh frame stage and the hold frame stage, and improve the problem of brightness change when the display panel switches to different refresh frequencies, that is, improve the VRR problem.

[0072] In the related art, in order to reduce the power consumption of the display panel, a display panel using LTPO technology is used. In some application scenarios, the display panel can switch the refresh frequency, and one of the switching methods is to reduce the refresh frequency on the basis of the basic refresh frequency (i.e., base frequency), and generally the refresh frequency can be reduced by an integer multiple. When the refresh frequency is reduced by an integer multiple, it can be called interpolation frequency modulation. In the interpolation method, the display cycle of the basic refresh frequency includes a refresh frame. The display cycle after reducing the refresh frequency on the basis of the basic refresh frequency includes a refresh frame (Refresh frame) stage and a skip frame (Skip frame) stage, the refresh frame stage includes a refresh frame, the skip frame stage includes at least one skip frame, and the refresh frame and the skip frame have the same duration. In other words, by inserting a skip frame between adjacent refresh frames, the refresh frequency of the display panel is reduced, and by changing the number of skip frames inserted between adjacent refresh frames, the reduction multiple of the refresh frequency is changed. For example, the basic refresh frequency is 120HZ, and the refresh frequency is reduced to 60HZ after inserting a skip frame, and the refresh frequency is reduced to 40HZ after inserting two skip frames, and so on. The switching between two different refresh frequencies may be switching between a basic refresh frequency and a refresh frequency that is reduced from the basic refresh frequency, or may be switching between two refresh frequencies that are reduced from the same basic refresh frequency.

[0073] In the case where the display cycle includes a refresh frame stage and a hold frame stage, the display panel completes the data writing of the pixel circuits of all rows in the first refresh frame of the display cycle (such as 1 second), and no new data is written in the subsequent hold frames. Each pixel circuit still controls the light-emitting device EL to emit light according to the voltage on its storage capacitor Cst1 and the light-emitting control signal, thereby allowing the display panel to maintain the display state of the refresh frame.

[0074] In the display module provided by some embodiments of the present disclosure, when the display cycle includes a refresh frame stage and a hold frame stage, during the hold frame stage, the clock signal of the gate drive circuit connected to at least one reset sub-circuit in the pixel circuit is down-converted to reduce the power consumption of the gate drive circuit and the drive chip, thereby reducing the power consumption of the display module.

[0075] In some embodiments, the above-mentioned multiple groups of gate drive circuits 200 include a first gate drive circuit. The first gate drive circuit includes a plurality of first shift registers arranged in cascade. The signal output end of the first shift register is electrically connected to the reset control end of at least one reset subcircuit in the pixel circuit. For example, a first shift register of a level is electrically connected to at least one reset subcircuit of a row of sub-pixels through a gate line. For example, the number of reset subcircuits included in the pixel circuit can be set according to the needs of the actual product.

[0076] by Figure 4 Taking the corresponding pixel circuit as an example, the signal output end of the first shift register can be electrically connected to the reset control end of at least one of the first reset subcircuit 117, the second reset subcircuit 118 and the third reset subcircuit 119. For example, it can be electrically connected to the reset control end of any one of the three reset subcircuits, or simultaneously electrically connected to the reset control ends of two of the reset subcircuits, or respectively electrically connected to the reset control ends of the three reset subcircuits.

[0077] The first gate driving circuit is electrically connected to the driving chip 300, and the driving chip 300 provides a driving signal for it, such as a clock signal, a frame start signal, etc. In some embodiments, the driving chip 300 is configured to input a first clock signal to the clock signal end of the first gate driving circuit during the refresh frame stage when the current display cycle includes a refresh frame stage and a hold frame stage; and input a second clock signal to the above-mentioned clock signal end of the first gate driving circuit during the hold frame stage, and the frequency of the second clock signal is less than the frequency of the first clock signal. It should be noted that, for the sake of convenience of explanation, some embodiments of the present disclosure refer to the clock signal received by the first gate driving circuit during the refresh frame stage of the same display cycle as the first clock signal, and the clock signal received during the hold frame stage as the second clock signal.

[0078] It is understandable that, for the gate drive circuit, the higher the frequency of the input clock signal, the more times the transistor controlled by the clock signal in the gate drive circuit switches its switch state, resulting in higher energy consumption. Therefore, by reducing the frequency of the clock signal input to the first gate drive circuit in the hold frame stage compared to the refresh frame stage, the power consumption of the first gate drive circuit can be effectively reduced, and the power consumption of the driver chip 300 can also be reduced.

[0079] In the same display cycle, the frequency of the clock signal received by at least one clock signal terminal of the first gate driving circuit in the holding frame stage is lower than the frequency in the refreshing frame stage. The clock signal of the first gate driving circuit includes at least one set of mutually coordinated positive-phase clock signals HCK and negative-phase clock signals HCB. The positive-phase clock signal HCK and the negative-phase clock signal HCB are transmitted to different clock signal terminals of the first gate driving circuit by different clock signal lines.

[0080] In some embodiments, the first clock signal may include a positive-phase clock signal HCK in the refresh frame stage and an inverted-phase clock signal HCB in the refresh frame stage, and the second clock signal may include a positive-phase clock signal HCK in the hold frame stage and an inverted-phase clock signal HCB in the hold frame stage. For ease of distinction, the positive-phase clock signal HCK in the refresh frame stage is referred to as the HCK1 signal, the inverted-phase clock signal HCB in the refresh frame stage is referred to as the HCB1 signal, the positive-phase clock signal HCK in the hold frame stage is referred to as the HCK2 signal, and the inverted-phase clock signal HCB in the hold frame stage is referred to as the HCB2 signal. It can be understood that the HCK1 signal and the HCK2 signal are clock signals in different time periods (i.e., the refresh frame stage and the hold frame stage) transmitted on the same clock signal line, and the HCB1 signal and the HCB2 signal are clock signals in different time periods (i.e., the refresh frame stage and the hold frame stage) transmitted on the same clock signal line. For example, the frequency of the HCK2 signal may be less than the frequency of the HCK1 signal, and the frequency of the HCB2 signal may be less than the frequency of the HCB1 signal.

[0081] In other embodiments, the above-mentioned first clock signal may include a positive phase clock signal HCK in the refresh frame stage, and the above-mentioned second clock signal may include a positive phase clock signal HCK in the hold frame stage, and the frequency of the positive phase clock signal HCK received by the first gate drive circuit in the hold frame stage may be lower than the frequency of the positive phase clock signal HCK received in the refresh frame stage.

[0082] In some further embodiments, the above-mentioned first clock signal may include an inverted clock signal HCB in a refresh frame stage, the above-mentioned second clock signal may include an inverted clock signal HCB in a hold frame stage, and the frequency of the inverted clock signal HCB received by the first gate drive circuit in the hold frame stage may be lower than the frequency of the inverted clock signal HCB received in the refresh frame stage.

[0083] There are multiple ways to reduce the frequency of the clock signal of the first gate driving circuit during the frame holding stage, as long as the image of the display panel is maintained during the frame holding stage. Three exemplary frequency reduction methods are listed below for illustration.

[0084] First, the frequency of the second clock signal may be one N times the frequency of the first clock signal. For example, N may be an even number. For example, the frequency of the first clock signal is expressed as f0, and the frequency of the second clock signal may be 1 / 2, 1 / 4, 1 / 8, 1 / 16, 1 / 32 or 1 / 64 of f0, etc., as long as the normal output of the first gate drive circuit can be ensured. Figure 6 A timing diagram of a first gate driving circuit according to some embodiments of the present disclosure is shown. Figure 6Take a display cycle as an example, the display cycle includes a refresh frame stage and a hold frame stage, the clock signal of the first gate drive circuit includes a set of positive clock signals HCK and negative clock signals HCB, the first clock signal includes the positive clock signal HCK and negative clock signal HCB in the refresh frame stage, the second clock signal includes the positive clock signal HCK and negative clock signal HCB in the hold frame stage; HSTV represents the frame start signal of the first gate drive circuit; HOUT represents the output signal of the first gate drive circuit. Figure 6 As shown, after the refresh frame stage ends, the frequency of the positive clock signal HCK of the first gate drive circuit can be adjusted to one-N times of the refresh frame stage, and the frequency of the negative clock signal HCB can also be adjusted to one-N times of the refresh frame stage, and the above-adjusted frequency can be maintained during the entire hold frame stage.

[0085] The second type is that in order to achieve a more stable frequency reduction, the frame maintenance stage may include a transition sub-stage and a maintenance sub-stage. The transition sub-stage is located between the refresh frame stage and the maintenance sub-stage. In the transition sub-stage, the frequency of the second clock signal is gradually reduced from the frequency of the refresh frame stage to the target frequency, and the target frequency is maintained in the maintenance sub-stage. For example, the target frequency may be 1 / L0 times the frequency of the refresh frame stage. One or more transition frequencies may be set in the transition sub-stage. Taking setting two transition frequencies as an example, in the transition sub-stage, the frequency of the second clock signal is first reduced to 1 / L1 times the frequency of the refresh frame stage, and then reduced from 1 / L1 times to 1 / L2 times the frequency of the refresh frame stage, and then reduced to 1 / L0 times the frequency of the refresh frame stage in the maintenance sub-stage. For example, L0, L1, and L2 may be even numbers, L0>L2>L1.

[0086] The third type is that the frequency of the second clock signal decreases compared to the frequency of the first clock signal, and the frequency of the second clock signal changes dynamically. For example, the frame holding stage includes a first time period, a second time period, and a third time period that are sequentially set, and the second clock signal includes: a first sub-clock signal, a second sub-clock signal, and a third sub-clock signal, and the driver chip 300 is configured as follows: in the first time period, the first sub-clock signal is input to the clock signal end of the first gate drive circuit, and the frequency of the first sub-clock signal is less than the frequency of the first clock signal; in the second time period, the second sub-clock signal is input to the clock signal end of the first gate drive circuit, and the frequency of the second sub-clock signal is greater than the frequency of the first sub-clock signal and less than the frequency of the first clock signal; in the third time period, the third sub-clock signal is input to the clock signal end of the first gate drive circuit, and the frequency of the third sub-clock signal is less than the frequency of the second sub-clock signal. That is, the first sub-clock signal is the clock signal received by the first gate drive circuit in the first time period, the second sub-clock signal is the clock signal received by the first gate drive circuit in the second time period, and the third sub-clock signal is the clock signal received by the first gate drive circuit in the third time period. For example, the frequency of the first sub-clock signal and the frequency of the third sub-clock signal may be 1 / 8 times of f0, and the frequency of the second sub-clock signal may be 1 / 4 times of f0.

[0087] In some embodiments, in order to further reduce the power consumption caused by the frequent switching of the switch state of the transistor in the first gate drive circuit, the first sub-clock signal and the third sub-clock signal can be a first constant level signal, that is, the frequency of the first sub-clock signal and the third sub-clock signal is reduced to zero. The voltage value of the first constant level signal can be approximately the same as the low level voltage value of the first clock signal. The frequency of the second sub-clock signal is one-M times the frequency of the first clock signal, and M can be an even number. It should be noted that "approximately the same" in this article includes exactly the same and approximately the same, and approximately the same means that the difference between the two is within an acceptable deviation range.

[0088] It should be noted that, within the same display cycle, the duration of the first time period, the second time period and the third time period and the duration of the refresh frame phase can be set according to the needs of the actual application scenario. Figure 7 shows a timing diagram of a first gate driving circuit of some other embodiments of the present disclosure, Figure 7In the example, by inserting 59 skip frames between two adjacent refresh frames, the refresh frequency of the display panel is switched from 60 Hz (i.e., updating the display data 60 times in 1 second) to 1 Hz (i.e., updating the display data once in 1 second). A display cycle may include a refresh frame and 59 skip frames, the duration of the refresh frame stage is 1 / 60 seconds, and the total duration of the skip frame stage is 59×(1 / 60) seconds. On this basis, the 59 skip frames are divided into a first time period, a second time period, and a third time period. In some embodiments, the first time period may include a number of consecutive skip frames after the refresh frame and adjacent to the refresh frame, the second time period may include a number of consecutive skip frames after the first time period and adjacent to the last skip frame of the first time period, and the third time period may include the remaining skip frames of the display cycle. For example, the duration of the first time period and the duration of the third time period may be greater than the duration of the second time period to minimize power consumption. For example, the duration of the first time period may be the same as or different from the duration of the third time period, and may be set according to the needs of the actual application scenario.

[0089] For example, Figure 7 As shown, the first time period can be the 1st to 20th holding frames (20frame), the second time period can be the 21st to 39th holding frames (19frame), and the third time period can be the 40th to 59th holding frames (20frame). Accordingly, the duration of the first time period is 20×(1 / 60) seconds, the duration of the second time period is 19×(1 / 60) seconds, and the duration of the third time period is 20×(1 / 60) seconds. It should be noted that Figure 7 The 19 frames in the middle of the holding frame stage in FIG. 1 only show the timing of one holding frame among the 19 holding frames.

[0090] like Figure 7As shown, after the refresh frame stage ends, the positive phase clock signal HCK and the negative phase clock signal HCB of the first gate driving circuit are pulled down to a low level, and the two clock signals are maintained at the low level in the first time period, that is, the frequencies of the positive phase clock signal HCK and the negative phase clock signal HCB are reduced to a limit in the first time period. For example, the low level voltage here can be the first voltage VGL. After the first time period ends, the frequencies of the positive phase clock signal HCK and the negative phase clock signal HCB are respectively adjusted to one M times of the refresh frame stage, for example, they can be 1 / 2 times, 1 / 4 times, 1 / 8 times, 1 / 16 times, 1 / 32 times or 1 / 64 times the frequency of the refresh frame stage, and the positive phase clock signal HCK and the negative phase clock signal HCB maintain the above-adjusted frequencies in the second time period. At the end of the second time period, the positive phase clock signal HCK and the negative phase clock signal HCB are pulled down to a low level again, and maintained at a low level in the third time period.

[0091] In some embodiments, at least one of the first time period, the second time period, and the third time period may include a transition sub-time period and a maintenance sub-time period, respectively, and the transition sub-time period is located between the previous time period and the maintenance sub-time period. In the transition sub-time period, the frequency of the corresponding sub-clock signal is gradually adjusted from the frequency of the previous time period to the target frequency of the time period. Taking the second time period including the transition sub-time period and the maintenance sub-time period as an example, assuming that the target frequency of the second time period is 1 / 2 times the frequency of the refresh frame stage, the clock signal of the first time period (i.e., the first sub-clock signal) is a first constant level signal, and in the transition sub-time period, the second sub-clock signal can be adjusted from the first constant level signal to a high and low level signal with a frequency of 1 / 8 times the refresh frame stage, and then adjusted from 1 / 8 times to 1 / 4 times, and then adjusted from 1 / 4 times to 1 / 2 times, and the adjusted frequency is maintained in the maintenance sub-time period.

[0092] It is understandable that the driver chip 300 is configured to provide a frame start signal to the first gate driver circuit in addition to providing a clock signal to the first gate driver circuit. In some embodiments, in addition to reducing the frequency of the clock signal of the first gate driver circuit in the frame holding stage, the refresh frequency of the frame start signal of the first gate driver circuit can also be reduced when the display panel switches from a high refresh frequency to a low refresh frequency, thereby reducing the refresh frequency of the reset control terminal driven by the first gate driver circuit, which can effectively reduce the number of switching times of the transistor included in the corresponding reset subcircuit in the frame holding stage, so as to further reduce the power consumption of the display module.

[0093] The above-mentioned multiple groups of gate driving circuits 200 also include: a light-emitting driving circuit, and the signal output terminal of the light-emitting driving circuit is electrically connected to the light-emitting control terminal EM in the pixel circuit 110. The light-emitting driving circuit is electrically connected to the driving chip 300, and the driving chip 300 provides it with a gate driving signal, such as a clock signal, a frame start signal, etc. In order to facilitate distinction, the frame start signal of the first gate driving circuit is referred to as the first frame start signal, and the frame start signal of the light-emitting driving circuit is referred to as the light-emitting frame start signal.

[0094] In some embodiments, the driver chip 300 is configured to: input a first frame start signal to a signal input terminal of the first gate driver circuit, and input a light-emitting frame start signal to a signal input terminal of the light-emitting driver circuit. Wherein, when the current display cycle includes a refresh frame stage and a hold frame stage, the refresh frequency of the first frame start signal is greater than or equal to the current refresh frequency of the display panel, and less than or equal to the refresh frequency of the light-emitting frame start signal.

[0095] It can be understood that when the current display cycle includes a refresh frame stage and a hold frame stage, the current refresh frequency of the display panel is lower than the above-mentioned basic refresh frequency, and in order to enable the display panel to maintain the display state of the refresh frame stage during the hold frame stage, the refresh frequency of the light-emitting control signal is consistent with the basic refresh frequency.

[0096] In some embodiments, the refresh frequency of the first frame start signal may be greater than or equal to the current refresh frequency of the display panel, and less than the refresh frequency of the light frame start signal. For example, the current refresh frequency of the display panel is the first refresh frequency, the refresh frequency of the first frame start signal is the second refresh frequency, the refresh frequency of the light frame start signal is the third refresh frequency, the first refresh frequency is less than the basic refresh frequency, and the third refresh frequency is equal to the basic refresh frequency. On the basis that the second refresh frequency is greater than or equal to the first refresh frequency, the second refresh frequency may be 1 / K times the third refresh frequency, where K is an even number, for example, 1 / 2 times, 1 / 4 times, or 1 / 6 times, etc.

[0097] In some embodiments, the refresh frame stage includes a refresh frame, the hold frame stage includes a plurality of hold frames, and the first frame start signal may start from the refresh frame and be refreshed once every at least one hold frame, so that the refresh frequency of the first frame start signal is greater than the current refresh frequency of the display panel and less than the refresh frequency of the light-emitting frame start signal. The first frame start signal maintains a second constant level signal in the interval hold frame. In the case where the reset subcircuit driven by the first gate drive circuit is high-level cutoff, the voltage of the second constant level signal may be substantially the same as the high-level voltage value of the first frame start signal, for example, the voltage of the second constant level signal may be a second voltage VGH, and the second voltage VGH is greater than the first voltage VGL, that is, the first frame start signal maintains the second voltage VGH in the unrefreshed hold frame.

[0098] Figure 8 The timing diagrams of the light emitting frame start signal and three exemplary first frame start signals of some embodiments of the present disclosure are shown. Figure 8 In the example, the basic refresh frequency is 60Hz, and the adjusted current refresh frequency is 1Hz. The display cycle includes 60 frames, each frame is 1 / 60 seconds long, the first frame is the refresh frame, and the 2nd to 60th frames are the hold frames. ESTV represents the light frame start signal, and the light frame start signal will be refreshed in each frame from the 1st to the 60th frame, that is, it will jump to the working level to control the light-emitting device EL to continue to emit light in the hold frame. In the case where the first frame start signal is not frequency-reduced, the first frame start signal will also be refreshed in the 1st to 60th frames, that is, the refresh frequency is consistent with the light frame start signal, such as Figure 8 In the case where the first frame start signal is frequency-reduced by 1 / 2, the first frame start signal can be refreshed in the 1st frame (i.e., refresh frame), 3rd frame, 5th frame, ... 59th frame of the display cycle, and the second constant level signal is maintained in other holding frames, i.e., it is refreshed every other holding frame starting from the refresh frame, i.e., the refresh frequency of the first frame start signal is reduced to 1 / 2 times of the light-emitting frame start signal, such as Figure 8 In the case where the first frame start signal is frequency-reduced by 1 / 4, the first frame start signal can be refreshed in the 1st frame (i.e., refresh frame), 5th frame, 9th frame, ... 57th frame of the display cycle, and the second constant level signal is maintained in other holding frames, i.e., it is refreshed every three holding frames starting from the refresh frame, i.e., the refresh frequency of the first frame start signal is reduced to 1 / 4 times of the light-emitting frame start signal, such as Figure 8 The signal in HSTV3.

[0099] It should be noted that, in the holding frame refreshed by the first frame start signal, the frequency of the second clock signal is greater than zero. Taking the 1 / 4 times frequency reduction of the first frame start signal as an example, in the holding frame stage, the frequency of the second clock signal is greater than zero at least in the 5th frame, the 9th frame, ... the 57th frame. In some embodiments, in the holding frame where the first frame start signal is not refreshed, the second clock signal can be a first constant level signal, and in the holding frame refreshed by the first frame start signal, the frequency of the second clock signal is greater than zero and less than the frequency of the first clock signal, so as to ensure the output of the first shift register, thereby realizing the refresh of the reset control terminal of the connected reset subcircuit.

[0100] In other embodiments, the first frame start signal may also be a second constant level signal during the frame holding stage, so that the output signal of the first gate drive circuit maintains a high level during the frame holding stage, thereby causing the driven reset subcircuit to be in a cut-off state during the frame holding stage, which is beneficial to reducing the power consumption of the display module.

[0101] In some embodiments, in order to reduce the number of groups of the gate driving circuit 200 so as to realize a narrow frame, the first gate driving circuit can be configured to simultaneously drive the first reset subcircuit 117, the second reset subcircuit 118 and the third reset subcircuit 119. That is, the signal output terminal of the first shift register is electrically connected to the first reset control terminal, the second reset control terminal Reset2 and the third reset control terminal Reset3 respectively. For example, Figure 5 In the corresponding pixel circuit, the gate of the first transistor T1, the gate of the seventh transistor T7 and the gate of the eighth transistor T8 are connected to the same reset control terminal Reset_H and receive the same reset signal. At this time, the display module includes four groups of gate driving circuits.

[0102] Fig. 9 A circuit diagram of a first shift register according to some embodiments of the present disclosure is shown. Fig. 9 FIG. 4 is an exemplary circuit diagram of a first shift register when the number of gate drive circuit groups is four. Fig. 9 As shown, the first shift register 210 may include 16 transistors, namely a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15 and a sixteenth transistor T16, and three capacitors, namely C1, C2 and C3.

[0103] In the first shift register 210, the gate of the first transistor T1, the first electrode of the second transistor T2, the gate of the third transistor T3 and the fourteenth transistor T14, and the first electrode of the fourth transistor T4, the first electrode of the sixth transistor T6 and the gate of the seventh transistor T7 are all used as clock signal input terminals, except that the clock signals input by the gate of the first transistor T1, the first electrode of the second transistor T2, the third transistor T3 and the gate of the fourteenth transistor T14, and the clock signals input by the first electrode of the fourth transistor T4, the first electrode of the sixth transistor T6 and the gate of the seventh transistor T7 are respectively the positive phase clock signal HCK and the negative phase clock signal HCB. The input signals of the first shift register 210 also include the first frame start signal HSTV and the vertical synchronization signal VEL, and the other power signal input terminals also input the first voltage VGL or the second voltage VGH. It should be noted that, Fig. 9 The circuit of the first shift register 210 shown is for illustration only. In other embodiments, other applicable shift register circuits may also be used.

[0104] Fig.10 Shows Figure 5 An exemplary timing diagram of a pixel circuit in a refresh frame. Fig.10 As shown, Figure 5 The driving principle of the corresponding pixel circuit is as follows:

[0105] In the t1 phase, when the light control signal provided by the light control terminal EM, the first scanning signal provided by the first scanning control terminal Gate_P, and the second scanning signal provided by the second scanning control terminal Gate_N are at a high level, and the reset signal provided by the reset control terminal Reset_H is at a low level, Figure 5 The transistors T1, T2, T7 and T8 are all turned on, wherein the transistors T7 and T8 are turned on at the same time first, and then the transistor T1 is turned on; the transistors T4, T5 and T6 are all turned off. Then, the second initial voltage Vinit2 can be transmitted to the anode of the light emitting device EL (i.e. Figure 5 The fourth node N4 in the light emitting device EL is reset to reset the anode of the light emitting device EL, that is, the voltage of the fourth node N4 is equal to the second initial voltage Vinit2 at this time; the third initial voltage Vinit3 can be transmitted to the first electrode of the third transistor T3 (that is, Figure 5 The first initial voltage Vinit1 is transmitted to the second electrode of the third transistor T3 (i.e., the second node N2 in the circuit) to reset the first electrode of the third transistor T3, that is, the voltage of the second node N2 is equal to the third initial voltage Vinit3 at this time; and the first initial voltage Vinit1 can be transmitted to the second electrode of the third transistor T3 (i.e., Figure 5 The third node N3 in the circuit is then transmitted to the gate of the third transistor T3 (i.e. Figure 5The voltage of the first node N1 is equal to the first initial voltage Vinit1, and the first node N1 is reset. The stage t1 can also be called the first reset stage.

[0106] In the t2 phase, when the light control signal provided by the light control terminal EM, the second scanning signal provided by the second scanning control terminal Gate_N, and the reset signal provided by the reset control terminal Reset_H are at a high level, and the first scanning signal provided by the first scanning control terminal Gate_P is at a low level, Figure 5 The transistors T2 and T4 in the circuit are all turned on, and the transistors T1, T5, T6, T7 and T8 are all turned off. Under the holding effect of the storage capacitor Cst1, the gate of the third transistor T3 can be kept at the first initial voltage of the previous stage, and the driving transistor T3 can remain turned on. Furthermore, the data voltage signal output by the data voltage terminal Vata can be transmitted to the lower plate of the storage capacitor Cst1 and the gate of the third transistor T3 through the transistors T4, T3 and T2 in sequence, the storage capacitor Cst1 is charged, and the voltage of the gate of the third transistor T3 is updated from the first initial voltage Vinit1 to the data voltage, so that the third transistor T3 is gradually turned off. The t2 stage can also be called the data writing stage.

[0107] In the t3 phase, when the light control signal provided by the light control terminal EM and the first scanning signal provided by the first scanning control terminal Gate_P are at a high level, and the reset signal provided by the reset control terminal Reset_H and the second scanning signal provided by the second scanning control terminal Gate_N are at a low level, Figure 5 The transistors T1, T7 and T8 in the t3 are all turned on, and the transistors T2, T4, T5 and T6 are all turned off, so that the second node N2, the third node N3 and the fourth node N4 are reset. The t3 phase can also be called the second reset phase.

[0108] In the t4 phase, when the reset signal provided by the reset control terminal Reset_H and the first scan signal provided by the first scan control terminal Gate_P are at a high level, and the light control signal provided by the light control terminal EM and the second scan signal provided by the second scan control terminal Gate_N are at a low level, Figure 5 The transistors T5 and T6 in the t4 are turned on, and the transistors T1, T2, T4, T7 and T8 are all turned off, thereby controlling the light emitting device EL to emit light. The t4 phase can also be called a light emitting phase.

[0109] In some other embodiments, the first gate driving circuit can be configured to drive the second reset sub-circuit 118 and the third reset sub-circuit 119, that is, the signal output terminal of the first shift register 210 is respectively connected to the second reset sub-circuit 118 and the third reset sub-circuit 119. Figure 4The plurality of gate drive circuits 200 further include a second gate drive circuit for driving the first reset sub-circuit 117, and the second gate drive circuit is electrically connected to the driver chip 300. The second gate drive circuit includes a plurality of second shift registers arranged in cascade, and the signal output terminal of the second shift register is connected to the first reset sub-circuit 117. Figure 4 The first reset control terminal Reset1 is electrically connected to the .

[0110] Fig.11 FIG. 2 shows a circuit diagram of a pixel circuit of another embodiment of the present disclosure. Figure 5 The corresponding pixel circuit, Fig.11 The gates of the seventh transistor T7 and the eighth transistor T8 are connected to the same reset control terminal Reset_H, the gate of the first transistor T1 is connected to the reset control terminal Reset_P, and the two reset control terminals Reset_H and Reset_P are driven by two different groups of gate driving circuits respectively. That is, the second reset control terminal connected to the second reset subcircuit 118 and the third reset control terminal connected to the third reset subcircuit 119 are the same reset control terminal, and the first reset control terminal connected to the first reset subcircuit 117 is another reset control terminal. At this time, the number of groups of gate driving circuits set in the display module is five.

[0111] In some embodiments, the circuit of the second shift register may be different from the circuit of the first shift register, and the number of transistors included in the second shift register may be smaller than the number of transistors included in the first shift register. Fig.12 FIG. 4 shows a circuit diagram of a second shift register of some embodiments of the present disclosure. Fig.12As shown, the second shift register 220 may include 13 transistors, namely, a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12 and a thirteenth transistor T13, and three capacitors, namely, C1, C2 and C3. In the second shift register 220, the gate of the first transistor T1, the first electrode of the second transistor T2 and the gate of the third transistor T3, and the first electrode of the fourth transistor T4, the first electrode of the sixth transistor T6 and the gate of the seventh transistor T7 are all used as clock signal input terminals, except that the clock signal input to the gate of the first transistor T1, the first electrode of the second transistor T2 and the gate of the third transistor T3 is a clock signal, and the clock signals input to the first electrode of the fourth transistor T4, the first electrode of the sixth transistor T6 and the gate of the seventh transistor T7 are respectively a positive phase clock signal PCK and a negative phase clock signal PCB. The input signal of the second shift register 220 also includes the second frame start signal PSTV and the vertical synchronization signal VEL, and the other power signal input terminals also input the first voltage VGL or the second voltage VGH. It should be noted that: Fig.12 The circuit of the second shift register 220 shown is for illustration only. In other embodiments, other applicable shift register circuits may also be used.

[0112] Fig.13 Shows Fig.11 An exemplary timing diagram of a pixel circuit in a refresh frame. Fig.13 As shown, Reset_P and Reset_H are driven by different gate driving circuits, and the driving waveforms may be different to more accurately drive different reset sub-circuits in the pixel circuit.

[0113] When the number of groups of the gate drive circuit 200 is five, in addition to inputting the clock signal to the first gate drive circuit, the drive chip 300 is also configured to: input a third clock signal to the clock signal end of the second gate drive circuit in the refresh frame stage; and input a fourth clock signal to the clock signal end of the second gate drive circuit in the hold frame stage, wherein the frequency of the fourth clock signal is less than the frequency of the third clock signal. That is to say, in the hold frame stage, in addition to reducing the frequency of the clock signal of the first gate drive circuit, the clock signal of the second gate drive circuit is also reduced, which is beneficial to further reduce the power consumption of the display module. It should be noted that, similar to the first gate drive circuit, for the sake of convenience of explanation, some embodiments of the present disclosure refer to the clock signal received by the second gate drive circuit in the refresh frame stage of the same display cycle as the third clock signal, and the clock signal received in the hold frame stage as the fourth clock signal.

[0114] In some embodiments, taking into account the respective functional characteristics of the first reset sub-circuit 117, the second reset sub-circuit 118 and the third reset sub-circuit 119, the frequency of the fourth clock signal can also be lower than the frequency of the second clock signal, that is, the clock signal of the second gate drive circuit can be reduced more in frequency during the frame holding stage than the first gate drive circuit.

[0115] In some embodiments, the frequency of the fourth clock signal may be one N1 times the frequency of the third clock signal, and N1 may be an even number. Fig.14 A timing diagram of a second gate driving circuit according to some embodiments of the present disclosure is shown. Fig.14 Taking the example that the clock signal of the second gate drive circuit includes a group of positive phase clock signal PCK and negative phase clock signal PCB, the above-mentioned third clock signal includes the positive phase clock signal PCK and the negative phase clock signal PCB in the refresh frame stage, and the above-mentioned fourth clock signal includes the positive phase clock signal PCK and the negative phase clock signal PCB in the hold frame stage. Fig.14 PSTV in FIG. 1 represents the second frame start signal of the second gate driving circuit, and POUT represents the output signal of the second gate driving circuit. Fig.14 As shown, after the refresh frame stage ends, the frequency of the positive phase clock signal PCK of the second gate driving circuit can be adjusted to one-N1 times of the refresh frame stage, and the frequency of the negative phase clock signal PCB can also be adjusted to one-N times of the refresh frame stage, and the above adjusted frequencies are maintained during the entire hold frame stage. For example, when the clock signals of the first gate driving circuit and the second gate driving circuit have the same frequency in the refresh frame stage, the frequencies of the positive phase clock signal HCK and the negative phase clock signal HCB in the hold frame stage can be 1 / 8 times of the refresh frame stage, and the frequencies of the positive phase clock signal PCK and the negative phase clock signal PCB in the hold frame stage can be 1 / 16 times of the refresh frame stage.

[0116] In other embodiments, the fourth clock signal can be dynamically frequency modulated during the frame holding stage. For example, the frame holding stage includes a first time period, a second time period, and a third time period that are sequentially set, and the fourth clock signal includes a fourth sub-clock signal, a fifth sub-clock signal, and a sixth sub-clock signal. The driver chip 300 is configured to input a fourth sub-clock signal to the clock signal end of the second gate drive circuit in the first time period, and the frequency of the fourth sub-clock signal is less than the frequency of the third clock signal; in the second time period, input a fifth sub-clock signal to the clock signal end of the second gate drive circuit, and the frequency of the fifth sub-clock signal is greater than the frequency of the fourth sub-clock signal and less than the frequency of the third clock signal; in the third time period, input a sixth sub-clock signal to the clock signal end of the second gate drive circuit, and the frequency of the sixth sub-clock signal is less than the frequency of the fifth sub-clock signal. That is, the fourth sub-clock signal is the clock signal received by the second gate drive circuit in the first time period, the fifth sub-clock signal is the clock signal received by the second gate drive circuit in the second time period, and the sixth sub-clock signal is the clock signal received by the second gate drive circuit in the third time period.

[0117] Fig.15 The timing diagram of the second gate driving circuit of some other embodiments of the present disclosure is shown. Fig.15 Take the example that the clock signal of the second gate driving circuit includes a set of positive phase clock signal PCK and negative phase clock signal PCB. Fig.15 As shown in FIG. 1 , in the case where the first time period is the 1st to 20th holding frames, the second time period is the 21st to 39th holding frames, and the third time period is the 40th to 59th holding frames, Figure 7 It is shown that the timing of the first gate driving circuit is similar, the fourth sub-clock signal (i.e., the positive phase clock signal PCK and the reverse phase clock signal PCB in the first time period) and the sixth sub-clock signal (i.e., the positive phase clock signal PCK and the reverse phase clock signal PCB in the third time period) can be a first constant level signal, and the frequency of the fifth sub-clock signal (i.e., the positive phase clock signal PCK and the reverse phase clock signal PCB in the second time period) can be one-half of M1 in the refresh frame stage, for example, 1 / 2 times, 1 / 4 times, 1 / 8 times, 1 / 16 times, 1 / 32 times or 1 / 64 times, etc. M1 can be greater than M, for example, in the case where the frequency of the second sub-clock signal is 1 / 8 times of the refresh frame stage, the frequency of the fifth sub-clock signal can be reduced to 1 / 16 times of the refresh frame stage. In this way, the power consumption of the driver chip 300, the first gate driving circuit and the second gate driving circuit can be effectively reduced, thereby reducing the power consumption of the display module.

[0118] In the case where the display module includes the above-mentioned first gate driving circuit and the second gate driving circuit, in addition to inputting the above-mentioned first frame start signal to the first gate driving circuit, the driving chip 300 is further configured to: input the second frame start signal to the signal input terminal of the second gate driving circuit. In some embodiments, according to the functional characteristics of the first reset subcircuit 117, the second reset subcircuit 118 and the third reset subcircuit 119, when the current display cycle includes a refresh frame stage and a hold frame stage, the refresh frequency of the second frame start signal is less than the refresh frequency of the first frame start signal, which is beneficial to further reduce the power consumption of the display module while improving the VRR problem.

[0119] For example, the second frame start signal may be frequency-reduced by 1 / 8, i.e., the refresh frequency of the second frame start signal may be reduced to 1 / 8 times that of the light-emitting frame start signal, thereby frequency-reducing the output signal of the second shift register by 1 / 8 times; the first frame start signal may be frequency-reduced by 1 / 4, i.e., the refresh frequency of the first frame start signal may be reduced to 1 / 4 times that of the light-emitting frame start signal, thereby frequency-reducing the output signal of the first shift register by 1 / 4 times. It should be noted that the frequency-reduction method of the second frame start signal is similar to the frequency-reduction method of the first frame start signal, and the relevant description of the frequency-reduction of the first frame start signal may be referred to above, and will not be described in detail here.

[0120] It should also be noted that, in the holding frame refreshed by the second frame start signal, the frequency of the fourth clock signal is greater than 0. In some embodiments, in the holding frame where the second frame start signal is not refreshed, the fourth clock signal may be a first constant level signal, and in the holding frame refreshed by the second frame start signal, the frequency of the fourth clock signal may be greater than zero and less than the frequency of the third clock signal, so as to ensure the output of the second shift register, thereby realizing the refresh of the reset control terminal of the first reset sub-circuit 117.

[0121] In some other embodiments, the second frame start signal is a second constant level signal during the frame holding stage. That is, during the frame holding stage, the second frame start signal is not refreshed, and the second constant level signal is maintained, so that the output signal of the second shift register is maintained at a high level during the frame holding stage, thereby Fig.11 The first transistor T1 in the corresponding pixel circuit remains in a cut-off state during the frame holding stage to further reduce the power consumption of the display module.

[0122] In some other embodiments, the second reset subcircuit 118 and the third reset subcircuit 119 may also be driven by different gate drive circuits. The first gate drive circuit is configured to drive the third reset subcircuit 119, that is, the signal output terminal of the first shift register is connected to the third reset subcircuit 119. Figure 4The plurality of gate drive circuits 200 further include a second gate drive circuit for driving the first reset sub-circuit 117 and a third gate drive circuit for driving the second reset sub-circuit 118. The second gate drive circuit and the third gate drive circuit are electrically connected to the driver chip 300. The second gate drive circuit includes a plurality of second shift registers arranged in cascade connection. The signal output terminal of the second shift register is connected to the Figure 4 The third gate driving circuit includes a plurality of third shift registers arranged in cascade connection, and the signal output end of the third shift register is electrically connected to the first reset control end Reset1 of the gate driving circuit. Figure 4 The second reset control terminal Reset2 is electrically connected to the reset control terminal Reset2.

[0123] In some embodiments, the first shift register and the third shift register may adopt Figure 8 The shift register circuit shown, the second shift register can be used Fig.10 The shift register circuit is shown.

[0124] Fig.16 FIG. 2 shows a circuit diagram of a pixel circuit according to some other embodiments of the present disclosure. Fig.11 The corresponding pixel circuits differ in that: Fig.16 The gate of the seventh transistor T7 is connected to the reset control terminal Reset_H2, and the gate of the eighth transistor T8 is connected to the reset control terminal Reset_H1, which are different reset control terminals. Reset_H1 is driven by the first gate driving circuit, and Reset_H2 is driven by the third gate driving circuit. At this time, the number of gate driving circuits set in the display module is six. Fig.17 Shows Fig.16 An exemplary timing diagram of a pixel circuit in a refresh frame. Fig.17 As shown, since Reset_P, Reset_H1 and Reset_H2 are driven by different gate driving circuits, the driving waveforms may be different to more accurately drive three different reset sub-circuits in the pixel circuit.

[0125] In the case where the number of groups of gate drive circuits is six, in addition to inputting a clock signal to the first gate drive circuit, the drive chip 300 is further configured to: in the refresh frame stage, input a third clock signal to the clock signal end of the second gate drive circuit, and input a fifth clock signal to the clock signal end of the third gate drive circuit; in the hold frame stage, input a fourth clock signal to the clock signal end of the second gate drive circuit, and input a sixth clock signal to the clock signal end of the third gate drive circuit. Among them, the frequency of the fourth clock signal is less than the frequency of the third clock signal, the frequency of the sixth clock signal is less than the frequency of the fifth clock signal, and the frequencies of the fourth clock signal and the sixth clock signal are less than or equal to the frequency of the second clock signal. That is to say, in the hold frame stage, in addition to reducing the frequency of the clock signal of the first gate drive circuit, the clock signals of the second gate drive circuit and the third gate drive circuit are also reduced in frequency, which is conducive to further reducing the power consumption of the display module. It should be noted that, similar to the first gate drive circuit and the second gate drive circuit, for the sake of convenience, some embodiments of the present disclosure refer to the clock signal received by the third gate drive circuit in the refresh frame stage of the same display cycle as the fifth clock signal, and the clock signal received in the hold frame stage as the sixth clock signal.

[0126] In some embodiments, the frequency of the sixth clock signal is one N2 times the frequency of the fifth clock signal, and N2 may be an even number. Fig.18 A timing diagram of a third gate driving circuit according to some embodiments of the present disclosure is shown. Fig.18 Taking the example that the clock signal of the third gate drive circuit includes a group of positive phase clock signal HCK' and negative phase clock signal HCB', the above-mentioned fifth clock signal includes the positive phase clock signal HCK' and the negative phase clock signal HCB' of the refresh frame stage, and the above-mentioned sixth clock signal includes the positive phase clock signal HCK' and the negative phase clock signal HCB' of the hold frame stage. Fig.18 HSTV' in ' represents the third frame start signal of the third gate driving circuit, and HOUT' represents the output signal of the third gate driving circuit. Fig.18 As shown, after the refresh frame stage ends, the frequency of the positive clock signal HCK' of the third gate drive circuit can be adjusted to one-N2 times of the refresh frame stage, and the frequency of the negative clock signal HCB' can also be adjusted to one-N2 times of the refresh frame stage, and the above-adjusted frequency can be maintained throughout the entire hold frame stage.

[0127] Taking into account the functional characteristics of the first reset subcircuit 117, the second reset subcircuit 118 and the third reset subcircuit 119, in the frame holding stage, the display screen of the refresh frame stage is kept unchanged and no new data is written. In some embodiments, the frequency of the fourth clock signal and the sixth clock signal may be lower than the frequency of the second clock signal. That is to say, the clock frequency of the second gate drive circuit and the third gate drive circuit in the frame holding stage is reduced to a lower level than that of the first gate drive circuit, which is beneficial to further reduce the power consumption of the display module.

[0128] In other embodiments, the fourth clock signal may be less than the frequency of the second clock signal, and the frequency of the sixth clock signal may be equal to the frequency of the second clock signal. For example, in the refresh frame stage, the frequencies of the clock signals received by the first gate drive circuit, the second gate drive circuit, and the third gate drive circuit may also be the same, that is, the frequencies of the first clock signal, the third clock signal, and the fifth clock signal are the same, expressed as f0, the frequencies of the second clock signal and the sixth clock signal may be 1 / 8 times of f0, and the frequency of the fourth clock signal may be 1 / 16 times of f0.

[0129] In some other embodiments, the sixth clock signal can be dynamically frequency modulated during the frame holding stage. For example, the frame holding stage includes a first time period, a second time period, and a third time period that are sequentially set, and the sixth clock signal includes a seventh sub-clock signal, an eighth sub-clock signal, and a ninth sub-clock signal. The driver chip 300 is configured to input a seventh sub-clock signal to the clock signal terminal of the third gate drive circuit in the first time period, and the frequency of the seventh sub-clock signal is less than the frequency of the fifth clock signal; in the second time period, input an eighth sub-clock signal to the clock signal terminal of the third gate drive circuit, and the frequency of the eighth sub-clock signal is greater than the frequency of the seventh sub-clock signal and less than the frequency of the fifth clock signal; in the third time period, input a ninth sub-clock signal to the clock signal terminal of the third gate drive circuit, and the frequency of the ninth sub-clock signal is less than the frequency of the eighth sub-clock signal. That is, the seventh sub-clock signal is the clock signal received by the third gate drive circuit in the first time period, the eighth sub-clock signal is the clock signal received by the third gate drive circuit in the second time period, and the ninth sub-clock signal is the clock signal received by the third gate drive circuit in the third time period.

[0130] Fig.19 A timing diagram of a third gate driving circuit according to some other embodiments of the present disclosure is shown. Fig.19 Take the example that the clock signal of the third gate driving circuit includes a set of positive-phase clock signal HCK' and negative-phase clock signal HCB'. Fig.19 As shown in FIG. 1 , in the case where the first time period is the 1st to 20th holding frames, the second time period is the 21st to 39th holding frames, and the third time period is the 40th to 59th holding frames, Figure 7 The timing of the first gate drive circuit is shown as well as Fig.18 The timing of the second gate drive circuit shown is similar, the seventh sub-clock signal (i.e., the positive phase clock signal HCK' and the negative phase clock signal HCB' of the first time period) and the ninth sub-clock signal (i.e., the positive phase clock signal HCK' and the negative phase clock signal HCB' of the third time period) can be a first constant level signal, and the frequency of the eighth sub-clock signal (i.e., the positive phase clock signal HCK' and the negative phase clock signal HCB' of the second time period) can be one-half of M2 of the refresh frame stage, for example, 1 / 2 times, 1 / 4 times, 1 / 8 times, 1 / 16 times, 1 / 32 times or 1 / 64 times, etc. M2 can be greater than or equal to M, for example, when the frequency of the second sub-clock signal is reduced to 1 / 8 times of the refresh frame stage, and the frequency of the fifth sub-clock signal is reduced to 1 / 16 times of the refresh frame stage, the frequency of the eighth sub-clock signal can be reduced to 1 / 8 times of the refresh frame stage, or can be reduced more, such as reduced to 1 / 16 times or 1 / 32 times of the refresh frame stage, etc., which can be set according to the needs of the actual application scenario. In this way, the power consumption of the driving chip 300 , the first gate driving circuit, the second gate driving circuit and the third gate driving circuit can be effectively reduced, thereby reducing the power consumption of the display module.

[0131] When the display module includes the above-mentioned first gate driving circuit, the second gate driving circuit and the third gate driving circuit, the driving chip 300 is configured to input the above-mentioned first frame start signal to the first gate driving circuit, input the above-mentioned second frame start signal to the second gate driving circuit, and is also configured to input the third frame start signal to the signal input terminal of the third gate driving circuit.

[0132] In some embodiments, considering the functional characteristics of the first reset subcircuit 117, the second reset subcircuit 118, and the third reset subcircuit 119, when the current display cycle includes a refresh frame phase and a hold frame phase, the refresh frequency of the second frame start signal and the third frame start signal can be less than the refresh frequency of the first frame start signal, which is beneficial to further reduce the power consumption of the display module while improving the VRR problem. The refresh frequency of the second frame start signal can be the same as the refresh frequency of the third frame start signal, or can be different, and can be set according to the needs of the actual application scenario.

[0133] For example, the first frame start signal may be frequency-reduced by 1 / 4, and the second frame start signal and the third frame start signal may be frequency-reduced by 1 / 8. It should be noted that the frequency reduction method of the second frame start signal and the third frame start signal is similar to the frequency reduction method of the first frame start signal, and the relevant description of the frequency reduction of the first frame start signal can be referred to above, which will not be described in detail here.

[0134] In some other embodiments, the first frame start signal, the second frame start signal and the third frame start signal are second constant level signals in the frame holding stage. That is, in the frame holding stage, the first frame start signal, the second frame start signal and the third frame start signal are no longer refreshed and maintain the second constant level signal, and the output signals of the first shift register, the second shift register and the third shift register maintain a high level in the frame holding stage, so that Fig.15 The first transistor T1 , the seventh transistor T7 , and the eighth transistor T8 in the corresponding pixel circuit remain in a cut-off state during the frame holding stage to further reduce the power consumption of the display module.

[0135] In some embodiments, the display module further includes: a fourth gate driving circuit, a fifth gate driving circuit and a light-emitting driving circuit. The driving chip 300 is electrically connected to the fourth gate driving circuit, the fifth gate driving circuit and the light-emitting driving circuit respectively. The fourth gate driving circuit includes a plurality of fourth shift registers arranged in cascade, and the signal output end of the fourth shift register is electrically connected to the above-mentioned first scanning control end; the fifth gate driving circuit includes a plurality of fifth shift registers arranged in cascade, and the signal output end of the fifth shift register is electrically connected to the second scanning control end. The light-emitting driving circuit includes a plurality of sixth shift registers arranged in cascade, and the signal output end of the sixth shift register is electrically connected to the light-emitting control end. In some embodiments, the frame area NA of the base substrate 101 includes a first frame area NA1 and a second frame area NA2, the first frame area NA1 is located on the first side of the display area, and the second frame area NA2 is located on the second side of the display area, and the first side and the second side are opposite sides.

[0136] Fig. 20 FIG. 2 shows a schematic diagram of the arrangement of the gate drive circuit of some embodiments of the present disclosure. Fig. 20 As shown, the fourth gate driving circuit 204 can be arranged in the first frame area NA1 and the second frame area NA2, that is, bilateral driving is adopted. The first-level fourth shift register can drive a row of sub-pixels or multiple rows of sub-pixels, such as driving two rows of sub-pixels. The fifth gate driving circuit 205, the first gate driving circuit 201 and the third gate driving circuit 203 can be arranged in the first frame area NA1, and the fifth gate driving circuit 205 is located on the side of the fourth gate driving circuit 204 away from the display area AA, the third gate driving circuit 203 is located on the side of the fifth gate driving circuit 205 away from the display area AA, and the first gate driving circuit 201 is located on the side of the third gate driving circuit 203 away from the display area AA. The second gate driving circuit 202 and the light-emitting driving circuit 206 can be arranged in the second frame area NA2, the second gate driving circuit 202 is located on the side of the fourth gate driving circuit 204 away from the display area AA, and the light-emitting driving circuit 206 is located on the side of the second gate driving circuit 202 away from the display area AA.

[0137] Considering that the first shift register and the third shift register can use the same shift register circuit, and the clock signal can have the same frequency reduction multiple during the frame holding stage, the first gate drive circuit 201 and the third gate drive circuit 203 are arranged in the same side frame area and adjacent to each other, which is conducive to simplifying the design and manufacturing difficulty.

[0138] In some embodiments, considering that the fourth shift registers of each stage of the fourth gate driving circuit 204 output the second constant level signal in the holding frame stage, the second constant level signal is a level signal that controls the data writing sub-circuit 111 to be in the off state, Figure 5 Taking the corresponding pixel circuit as an example, the second constant level signal may be a high level signal.

[0139] In order to further reduce the power consumption of the display module, in some embodiments, the clock signal of the fourth gate driving circuit 204 can also be frequency-reduced in the frame-holding stage, so as to ensure that the fourth gate driving circuit 204 outputs the second constant level signal in the frame-holding stage. For example, the driver chip 300 is further configured to input a seventh clock signal to the clock signal of the fourth gate driving circuit 204 in the refresh frame stage, and input an eighth clock signal to the clock signal of the fourth gate driving circuit 204 in the frame-holding stage, and the frequency of the eighth clock signal is less than the frequency of the seventh clock signal.

[0140] It should be noted that, similar to the first gate drive circuit 201, the second gate drive circuit 202 and the third gate drive circuit 203, for the sake of convenience, some embodiments of the present disclosure refer to the clock signal received by the fourth gate drive circuit 204 in the refresh frame stage of the same display cycle as the seventh clock signal, and the clock signal received in the hold frame stage as the eighth clock signal. The frequency reduction method of the clock signal of the fourth gate drive circuit 204 can refer to the aforementioned description of the frequency reduction of the clock signal of the first gate drive circuit 201, which will not be described in detail here. Since the control end of the data write subcircuit 111 does not need to be refreshed in the hold frame stage, in some embodiments, the eighth clock signal can be a first constant level signal to further reduce power consumption.

[0141] In some embodiments, the driver chip 300 is further configured to input a fourth frame start signal to the signal input terminal of the fourth gate driver circuit 204 and a fifth frame start signal to the signal input terminal of the fifth gate driver circuit 205. In some embodiments, the pulse width of the fourth frame start signal may be smaller than the pulse width of the first frame start signal, the pulse width of the first frame start signal may be smaller than the pulse width of the fifth frame start signal, and the pulse width of the fifth frame start signal may be smaller than the pulse width of the light-emitting frame start signal. For example, when the operating levels of the output signals of the light-emitting driver circuit 206, the first gate driver circuit 201, and the fourth gate driver circuit 204 are low, and the operating level of the output signal of the fifth gate driver circuit 205 is high, the pulse widths of the light-emitting frame start signal and the fifth frame start signal may be the widths of high-level pulses, and the pulse widths of the first frame start signal and the fourth frame start signal may be the widths of low-level pulses.

[0142] Fig.21 A timing diagram of a frame start signal according to some embodiments of the present disclosure is shown. Fig.21 Taking the display module including four groups of gate driving circuits, namely the first gate driving circuit 201, the fourth gate driving circuit 204, the fifth gate driving circuit 205 and the light-emitting driving circuit 206 as an example, an exemplary timing diagram of the frame start signals of the four groups of gate driving circuits in the refresh frame stage and the hold frame stage is shown. Among them, the hold frame stage only illustrates the timing of one of the hold frames. Fig.21 In the figure, ESTV indicates the light frame start signal, NSTV indicates the fifth frame start signal, HSTV indicates the first frame start signal, and GSTV indicates the fourth frame start signal. Fig.21 As shown, the pulse width of the light frame start signal can be 96H, the pulse width of the fifth frame start signal can be 56H, the pulse width of the first frame start signal can be 8H, and the pulse width of the fourth frame start signal can be 1H. 1H is the charging time of a row of pixels. Taking a display panel with a refresh frequency of 60Hz and a total of 1125 pixel rows as an example, 1H is 1 / 60 / 1125 (seconds).

[0143] Some embodiments of the present disclosure provide a driving chip, including a memory and a processor, the memory storing a computer program that can be run on the processor, and the computer program is executed by the processor to perform the following steps: when the current display cycle includes a refresh frame stage and a hold frame stage, in the refresh frame stage, a first clock signal is input to the clock signal end of the first gate driving circuit; in the hold frame stage, a second clock signal is input to the clock signal end of the first gate driving circuit, and the frequency of the second clock signal is less than the frequency of the first clock signal; wherein the first gate driving circuit includes a plurality of first shift registers arranged in cascade connection, and the signal output end of the first shift register is electrically connected to the reset control end of at least one reset sub-circuit in the pixel circuit of the display panel.

[0144] It should be noted that, for the detailed description and technical effects of the driver chip provided in the embodiments of the present disclosure, reference may be made to the relevant description of the driver chip 300 in the above embodiment of the display module, which will not be repeated here.

[0145] In addition, those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure is limited to these examples. Based on the concept of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of different aspects of one or more embodiments of the present disclosure as described above, which are not provided in detail for the sake of simplicity.

[0146] Although the exemplary embodiments of the present disclosure have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present disclosure.

Claims

1. A display module, characterized in that: include: The display panel comprises a base substrate and a plurality of sub-pixels arranged in an array on the base substrate, each of the sub-pixels comprising a light-emitting device and a pixel circuit electrically connected to the light-emitting device; A first gate driving circuit comprises a plurality of first shift registers arranged in cascade connection, wherein a signal output terminal of the first shift register is electrically connected to a reset control terminal of at least one reset subcircuit in the pixel circuit; A driving chip is electrically connected to the first gate driving circuit, and the driving chip is configured as follows: when a current display cycle includes a refresh frame stage and a hold frame stage, a first clock signal is input to a clock signal end of the first gate driving circuit during the refresh frame stage; and a second clock signal is input to a clock signal end of the first gate driving circuit during the hold frame stage, and a frequency of the second clock signal is less than a frequency of the first clock signal.

2. The display module according to claim 1, characterized in that: The frame holding stage includes a first time period, a second time period and a third time period which are sequentially arranged, the second clock signal includes: a first sub-clock signal, a second sub-clock signal and a third sub-clock signal, and the driver chip is configured as follows: In the first time period, a first sub-clock signal is input to a clock signal terminal of the first gate driving circuit, wherein a frequency of the first sub-clock signal is less than a frequency of the first clock signal; In the second time period, a second sub-clock signal is input to the clock signal terminal of the first gate driving circuit, wherein the frequency of the second sub-clock signal is greater than the frequency of the first sub-clock signal and less than the frequency of the first clock signal; In the third time period, a third sub-clock signal is input to the clock signal terminal of the first gate driving circuit, and the frequency of the third sub-clock signal is lower than the frequency of the second sub-clock signal.

3. The display module according to claim 2, characterized in that: The first sub-clock signal and the third sub-clock signal are first constant-level signals, and a voltage value of the first constant-level signal is substantially the same as a low-level voltage value of the first clock signal; The frequency of the second sub-clock signal is one-M times the frequency of the first clock signal, where M is an even number.

4. The display module according to claim 1, characterized in that: The frequency of the second clock signal is one N times the frequency of the first clock signal, where N is an even number.

5. The display module according to claim 1, characterized in that: The display module further comprises a light-emitting driving circuit, wherein a signal output terminal of the light-emitting driving circuit is electrically connected to a light-emitting control terminal in the pixel circuit; The driving chip is electrically connected to the light-emitting driving circuit, and is configured to: input a first frame start signal to a signal input terminal of the first gate driving circuit, and input a light-emitting frame start signal to a signal input terminal of the light-emitting driving circuit; Among them, when the current display cycle includes a refresh frame stage and a hold frame stage, the refresh frequency of the first frame start signal is greater than or equal to the current refresh frequency of the display panel, and less than or equal to the refresh frequency of the light-emitting frame start signal; or, the first frame start signal is a second constant level signal in the hold frame stage, and the voltage of the second constant level signal is approximately the same as the high level voltage value of the first frame start signal.

6. The display module according to claim 5, characterized in that: The refresh frame stage includes a refresh frame, the hold frame stage includes multiple hold frames, the first frame start signal starts from the refresh frame and is refreshed once every at least one hold frame, so that the refresh frequency of the first frame start signal is greater than the current refresh frequency of the display panel and less than the refresh frequency of the light-emitting frame start signal.

7. The display module according to any one of claims 1 to 6, characterized in that: The pixel circuit includes a driving subcircuit, a compensation subcircuit, a data writing subcircuit, a storage subcircuit, a first light-emitting control subcircuit, a second light-emitting control subcircuit, a first reset subcircuit, a second reset subcircuit and a third reset subcircuit; The control end of the driving subcircuit is connected to the first node, the first connection end is connected to the second node, and the second connection end is connected to the third node; the control end of the compensation subcircuit is connected to the second scanning control end, the first connection end is connected to the first node, and the second connection end is connected to the third node; the first connection end of the storage subcircuit is connected to the first power supply voltage end, and the second connection end is connected to the first node; The control end of the first reset subcircuit is connected to the first reset control end, the first connection end is connected to the first initial voltage end, and the second connection end is connected to the third node; The control end of the second reset subcircuit is connected to the second reset control end, the first connection end is connected to the second initial voltage end, and the second connection end is connected to the anode of the light emitting device; The control end of the third reset subcircuit is connected to the third reset control end, the first connection end is connected to the third initial voltage end, the control end of the data write subcircuit is connected to the first scan control end, the first connection end is connected to the data voltage end, and the second connection ends of the data write subcircuit and the third reset subcircuit are connected to the second node; The control ends of the first light-emitting control subcircuit and the second light-emitting control subcircuit are connected to the light-emitting control end, the first connection end of the first light-emitting control subcircuit is connected to the first power supply voltage end, and the second connection end is connected to the second node; the first connection end of the second light-emitting control subcircuit is connected to the third node, and the second connection end is connected to the anode of the light-emitting device; Wherein, at least one of the first reset control terminal, the second reset control terminal and the third reset control terminal is electrically connected to the signal output terminal of the first shift register.

8. The display module according to claim 7, characterized in that: The signal output terminal of the first shift register is electrically connected to the first reset control terminal, the second reset control terminal and the third reset control terminal respectively.

9. The display module according to claim 7, characterized in that: The signal output end of the first shift register is electrically connected to the second reset control end and the third reset control end respectively, the display module further includes a second gate driving circuit, including a plurality of second shift registers arranged in cascade connection, and the signal output end of the second shift register is electrically connected to the first reset control end; The driving chip is electrically connected to the second gate driving circuit and is configured as follows: during the refresh frame stage, a third clock signal is input to the clock signal end of the second gate driving circuit; during the hold frame stage, a fourth clock signal is input to the clock signal end of the second gate driving circuit, and the frequency of the fourth clock signal is less than the frequency of the third clock signal and the frequency of the second clock signal.

10. The display module according to claim 9, characterized in that: The driving chip is further configured to: input a first frame start signal to a signal input terminal of the first gate driving circuit, and input a second frame start signal to a signal input terminal of the second gate driving circuit; Among them, when the current display cycle includes a refresh frame stage and a hold frame stage, the refresh frequency of the second frame start signal is less than the refresh frequency of the first frame start signal; or, the first frame start signal and the second frame start signal are second constant level signals in the hold frame stage, and the voltage of the second constant level signal is approximately the same as the high level voltage value of the first frame start signal.

11. The display module according to claim 7, characterized in that: The signal output terminal of the first shift register is electrically connected to the third reset control terminal, The display module further includes: a second gate driving circuit and a third gate driving circuit; The second gate driving circuit includes a plurality of second shift registers arranged in cascade connection, and a signal output terminal of the second shift register is electrically connected to the first reset control terminal; The third gate driving circuit comprises a plurality of third shift registers arranged in cascade connection, and a signal output terminal of the third shift register is electrically connected to the second reset control terminal; The driving chip is electrically connected to the second gate driving circuit and the third gate driving circuit respectively, and is configured to: input the third clock signal to the clock signal terminal of the second gate driving circuit and input the fifth clock signal to the clock signal terminal of the third gate driving circuit in the refresh frame phase; input the fourth clock signal to the clock signal terminal of the second gate driving circuit and input the sixth clock signal to the clock signal terminal of the third gate driving circuit in the hold frame phase; Among them, the frequency of the fourth clock signal is less than the frequency of the third clock signal, the frequency of the sixth clock signal is less than the frequency of the fifth clock signal, and the frequencies of the fourth clock signal and the sixth clock signal are less than or equal to the frequency of the second clock signal.

12. The display module according to claim 11, characterized in that: The driving chip is further configured to: input a first frame start signal to a signal input terminal of the first gate driving circuit, input a second frame start signal to a signal input terminal of the second gate driving circuit, and input a third frame start signal to a signal input terminal of the third gate driving circuit; Among them, when the current display cycle includes a refresh frame stage and a hold frame stage, the refresh frequency of the second frame start signal and the third frame start signal is less than the refresh frequency of the first frame start signal; or, the first frame start signal, the second frame start signal and the third frame start signal are second constant level signals in the hold frame stage, and the voltage of the second constant level signal is approximately the same as the high level voltage value of the first frame start signal.

13. The display module according to claim 11, characterized in that: Also includes: a fourth gate driving circuit, comprising a plurality of fourth shift registers arranged in cascade connection, wherein a signal output terminal of the fourth shift register is electrically connected to the first scanning control terminal; a fifth gate driving circuit, comprising a plurality of fifth shift registers arranged in cascade connection, wherein a signal output terminal of the fifth shift register is electrically connected to the second scanning control terminal; A light-emitting driving circuit, comprising a plurality of sixth shift registers arranged in cascade connection, wherein a signal output end of the sixth shift register is electrically connected to the light-emitting control end; The driving chip is electrically connected to the fourth gate driving circuit, the fifth gate driving circuit and the light emitting driving circuit respectively.

14. The display module according to claim 13, characterized in that: The base substrate comprises a display area, a first frame area and a second frame area, the first frame area is located at a first side of the display area, the second frame area is located at a second side of the display area, the first side and the second side are opposite sides, and the plurality of sub-pixels are located in the display area; The fourth gate driving circuit is arranged in the first frame area and the second frame area; The fifth gate driving circuit, the first gate driving circuit and the third gate driving circuit are arranged in the first border area, and the fifth gate driving circuit is located on a side of the fourth gate driving circuit away from the display area, the third gate driving circuit is located on a side of the fifth gate driving circuit away from the display area, and the first gate driving circuit is located on a side of the third gate driving circuit away from the display area; The second gate driving circuit and the light emitting driving circuit are arranged in the second border area. The second gate driving circuit is located on a side of the fourth gate driving circuit away from the display area. The light emitting driving circuit is located on a side of the second gate driving circuit away from the display area.

15. A driver chip, characterized in that: The invention comprises a memory and a processor, wherein the memory stores a computer program executable on the processor, and the processor executes the following steps: In the case where the current display cycle includes a refresh frame stage and a hold frame stage, during the refresh frame stage, a first clock signal is input to the clock signal end of the first gate drive circuit; during the hold frame stage, a second clock signal is input to the clock signal end of the first gate drive circuit, and the frequency of the second clock signal is less than the frequency of the first clock signal; wherein the first gate drive circuit includes a plurality of first shift registers arranged in cascade, and a signal output end of the first shift register is electrically connected to a reset control end of at least one reset sub-circuit in a pixel circuit of the display panel.

16. A display device, characterized in that: A display module comprising any one of claims 1-14.

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