Pixel driving circuit for field sequential display and writing method

Abstract

The invention discloses a pixel driving circuit for field sequential display and a writing method, the pixel driving circuit comprises pixel units arranged in multiple rows and multiple columns, each pixel unit comprises a driving module and a reset module, and each reset module comprises a third transistor and a first reference signal line; the connection mode of the third transistor is configured as follows: the grid electrode of the third transistor is coupled with the second source and drain electrode, or the grid electrode of the third transistor is coupled with the first source and drain electrode; the first source and drain electrode of the third transistor is coupled to the driving module, and the second source and drain electrode of the third transistor is coupled to the first reference signal line, the third transistor and the third transistor. The method has the advantages that reset signal lines are saved by connecting the grid electrode and the source drain electrode of the third transistor, the number of used signal lines is reduced, the number of metal layers can be reduced in layout preparation, and therefore the layout preparation difficulty is lowered.

Description

Technical Field

[0001] The present invention relates to the field of pixel display technology, and in particular to a pixel driving circuit and a writing method for field sequential display. Background Art

[0002] Field sequential or color sequential display driving technology directly utilizes the RGB three-color light source to mix colors through the residual effect of human visual pause to achieve full-color display effect. No color filter is required, which improves the utilization rate of the light source on the one hand and reduces the power consumption of the light source on the other hand. The backlight can be turned on only after all the screen data is written and the liquid crystal is deflected to a stable state, otherwise there will be a chaotic picture, so a lot of time needs to be reserved for the liquid crystal to deflect before the backlight is turned on. This makes it difficult to achieve high brightness and high frequency display within the average time, and at the same time, the requirements for backlight brightness specifications and life are increased, which increases the cost.

[0003] In order to achieve a stable high refresh rate and high brightness, the present invention provides a pixel driving circuit and a writing method for field sequential display. Summary of the invention

[0004] The object of the present invention is to provide a pixel driving circuit and a writing method for field sequential display, so as to reduce the voltage variation range of a data signal line.

[0005] The object of the present invention is to realize a pixel driving circuit and writing method for field sequential display through the following technical scheme, including a pixel unit arranged in multiple rows and columns, the pixel unit including a driving module and a reset module, the reset module including a third transistor and a first reference signal line; The connection mode of the third transistor is configured as the gate of the third transistor is coupled to the second source and drain, or the gate of the third transistor is coupled to the first source and drain; The first source and drain of the third transistor are coupled to the driving module, and the second source and drain of the third transistor are coupled to the first reference signal line. Further, the driving module includes a second transistor and a pixel electrode, the gate of the second transistor is coupled to the transfer signal line, the first source and drain of the second transistor are coupled to the second source and drain of the first transistor, the second source and drain of the second transistor are coupled to one end of the pixel electrode, and the second source and drain of the second transistor are also coupled to the first source and drain of the third transistor. Furthermore, the pixel unit also includes a pre-storage module; the pre-storage module includes a first transistor and a pre-storage capacitor, the first source and drain of the first transistor are coupled to the data signal line, the gate of the first transistor is coupled to the row gate signal line, and the second source and drain of the first transistor is coupled to one end of the pre-storage capacitor.

[0006] Further, the other end of the pre-storage capacitor and the other end of the pixel electrode of the pixel unit located in the odd-numbered columns are both coupled to the second common signal line; The other end of the pre-storage capacitor and the other end of the pixel electrode of the pixel unit located in the even-numbered column are both coupled to the first common signal line; A first AC driving signal is input to the pixel units located in the even columns through the first common signal line, and a second AC driving signal is input to the pixel units located in the odd columns through the second common signal line, wherein the first AC driving signal and the second AC driving signal have the same frequency and opposite polarity.

[0007] Furthermore, the driving module further includes a holding capacitor, wherein the holding capacitor is coupled to the second source and drain of the second transistor; and the other end of the holding capacitor is coupled to the second reference signal line.

[0008] Furthermore, when preparing the layout of the pixel unit, the layout includes a light shielding layer, an active layer, a source-drain layer, an intermediate metal layer, a transparent conductive layer and a color conductive layer; The light shielding layer is arranged on the glass substrate, a first insulating layer is arranged on the light shielding layer, an active layer is arranged on the first insulating layer, the active layer constitutes the gate of the first transistor and the gate of the second transistor; a row gate signal line and a transfer signal line are also formed on the light shielding layer; A second insulating layer is disposed on the active layer, and a source-drain layer is disposed on the second insulating layer, wherein the source-drain layer is connected to the active layer through a through hole, wherein the source-drain layer and the active layer constitute a channel region, a first end, and a second end of the first transistor, and the source-drain layer and the active layer also constitute a channel region, a first end, and a second end of the second transistor, and the source-drain layer and the active layer constitute a channel region, a first end, and a second end of a third transistor, wherein the channel region of the third transistor is connected to the first end; A third insulating layer is provided on the source-drain layer, and an intermediate metal layer is provided on the third insulating layer, wherein the intermediate metal layer constitutes a first reference signal line and a data signal line; and an overlapping portion of the intermediate metal layer and the source-drain layer forms a pre-storage capacitor; A fourth insulating layer is arranged on the intermediate metal layer, and a transparent conductive layer is arranged on the fourth insulating layer, the transparent conductive layer constituting a pixel electrode; the intermediate metal layer is connected to the color conductive layer through a conductive material, and the color conductive layer forms a common signal line.

[0009] Furthermore, the color conductive layer of the pixel units located in odd columns forms a second common signal line; and the color conductive layer of the pixel units located in even columns forms a first common signal line.

[0010] The present invention also provides a pixel driving circuit writing method for field sequential display, comprising: First programming stage: By controlling the potential change of the data signal line and the row gate signal line, the data signal line writes the data signal voltage to the pre-storage capacitor through the first transistor; Second programming stage: By changing the potential of the first reference signal line, the first reference signal line completes the reset of the pixel electrode and the holding capacitor through the third transistor; Transfer phase: By controlling the level change of the transfer signal line, the first common signal line and the second common signal line, the amount of charge transferred from the pre-storage capacitor to the pixel electrode is completed to write the preset data signal voltage into the pixel electrode; The first common signal line outputs a first AC driving signal, and the second common signal line outputs a second AC driving signal, wherein the first AC driving signal and the second AC driving signal have the same frequency and opposite polarities.

[0011] The present invention has the following advantages: The present invention connects the gate of the third transistor to the first source and drain or the second source and drain so that the third transistor forms a diode structure, thereby reducing the use of a reset signal line, and the first reference signal line connected to the second source and drain now presents the same change state in each cycle. Therefore, the improvement of the third transistor structure can reduce the use of signal lines, increase the aperture ratio, and reduce the difficulty of controlling the first reference signal line.

[0012] The present invention connects the gate of the third transistor to the first source and drain or the second source and drain; in traditional layout preparation, it is necessary to first use a gate metal layer to prepare the gate of the third transistor, and then cover the metal layer with an insulating layer, and then prepare the first source and drain and the second source and drain of the third transistor through another metal layer; now the channel region is directly connected to the first end or the second end, which is equivalent to directly connecting the gate of the transistor to the first end or the second end through the channel region, thereby reducing the use of a gate metal layer and a insulating layer, thereby saving the number of layers and processes for layout preparation.

[0013] The present invention also replaces the common signal line driven by DC in the prior art with two AC signal lines respectively connected to odd columns and even columns, and the AC drive signal of the first common signal line has the same frequency but opposite polarity as the AC drive signal of the second common signal line; in the reset stage, the first reference signal line resets the pixel electrodes of the odd columns and the even columns to 0 or Vop_max; so that the voltage difference range across the pixel electrode can reach (-Vop_max, +Vop_max), thereby achieving the pixel voltage required by the pixel electrode when working in the frame; thereby, the voltage pre-written into the pre-storage capacitor of the data signal line can be reduced, thereby reducing the data voltage variation range of the data signal line. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 is a circuit diagram of Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the layout of the first embodiment of the present invention; Figure 3 is a timing diagram of the first embodiment of the present invention; Figure 4 is a circuit diagram of Embodiment 2 of the present invention; Figure 5 This is a schematic diagram of the layout of the second embodiment of the present invention; Figure 6 is a timing diagram of the second embodiment of the present invention; In the figure: 1-light shielding layer, 2-active layer, 3-source and drain layer, 4-intermediate metal layer, 5-transparent conductive layer, 6-color conductive layer. DETAILED DESCRIPTION

[0015] The present invention is further described below in conjunction with the accompanying drawings, but the protection scope of the present invention is not limited to the following description.

[0016] It should be noted that the directions or positional relationships indicated by "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, or are the directions or positional relationships in which the inventive product is usually placed when in use, or are the directions or positional relationships commonly understood by those skilled in the art. Such terms are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the present invention.

[0017] It should be noted that, in the absence of conflict, the embodiments of the present invention and the features and technical solutions in the embodiments may be combined with each other. Example

[0018] In the first embodiment, a pixel driving circuit for field sequential display is provided, including a pixel unit arranged in multiple rows and columns, the pixel unit includes a pre-storage module, a driving module and a reset module, the reset module includes a third transistor T3 and a first reference signal line Vref1, the gate and the second source and drain of the third transistor T3 are coupled to the first reference signal line Vref1; The pre-storage module includes a first transistor T1 and a pre-storage capacitor Cs1, a first source and a drain of the first transistor T1 are coupled to a data signal line Data, a gate of the first transistor T1 is coupled to a row gate signal line Scan, and a second source and a drain of the first transistor T1 are coupled to one end of the pre-storage capacitor Cs1; The driving module includes a second transistor T2, a holding capacitor Cs2 and a pixel electrode Clc, wherein the gate of the second transistor T2 is coupled to the transfer signal line Tran, the first source and drain of the second transistor T2 are coupled to the second source and drain of the first transistor T1, the second source and drain of the second transistor T2 are coupled to the pixel electrode Clc and one end of the holding capacitor Cs2; the other end of the holding capacitor Cs2 is coupled to the second reference signal line Vref2.

[0019] The other end of the pre-storage capacitor Cs1 of the pixel unit located in the odd column and the other end of the pixel electrode Clc are both coupled to the second common signal line Vcom_even; the other end of the pre-storage capacitor Cs1 of the pixel unit in the even column and the other end of the pixel electrode Clc are both coupled to the first common signal line Vcom_odd, and the first AC drive signal is input to the pixel unit located in the even column through the first common signal line Vcom_odd, and the second AC drive signal is input to the pixel unit located in the odd column through the second common signal line Vcom_even, wherein the first AC drive signal and the second AC drive signal have the same frequency and opposite polarity.

[0020] When preparing the layout of the pixel unit, Figure 2 As shown, the layout includes a light shielding layer 1, an active layer 2, a source-drain layer 3, an intermediate metal layer 4, a transparent conductive layer 5 and a color conductive layer 6; A light shielding layer 1 is arranged on a glass substrate, a first insulating layer is arranged on the light shielding layer 1, an active layer 2 is arranged on the first insulating layer, and the active layer 2 constitutes a gate of a first transistor T1 and a gate of a second transistor T2; a row gate signal line Scan and a transfer signal line Tran are also formed on the light shielding layer 1; A second insulating layer is disposed on the active layer 2, and a source-drain layer 3 is disposed on the second insulating layer. The source-drain layer 3 is connected to the active layer 2 through a through hole. The source-drain layer 3 and the active layer 2 constitute the channel region, the first end, and the second end of the first transistor T1. The source-drain layer 3 and the active layer 2 also constitute the channel region, the first end, and the second end of the second transistor T2. The source-drain layer 3 and the active layer 2 constitute the channel region, the first end, and the second end of the third transistor T3. The channel region of the third transistor T3 is connected to the first end. A third insulating layer is arranged on the source-drain layer 3, and an intermediate metal layer 4 is arranged on the third insulating layer, and the intermediate metal layer 4 constitutes a first reference signal line Vref1 and a data signal line Data; the overlapping portion of the intermediate metal layer 4 and the source-drain layer 3 forms a pre-storage capacitor Cs1; a fourth insulating layer is arranged on the intermediate metal layer 4, and a transparent conductive layer 5 is arranged on the fourth insulating layer, and the transparent conductive layer 5 constitutes a pixel electrode Clc; the intermediate metal layer 4 is connected to the color conductive layer 6 through a conductive material, and the color conductive layer 6 forms a common signal line.

[0021] In some specific embodiments, the color conductive layer 6 of the pixel units located in odd columns forms the second common signal line Vcom_even; and the color conductive layer 6 of the pixel units located in even columns forms the first common signal line Vcom_odd.

[0022] The present invention connects the gate of the third transistor T3 to the first source-drain or the second source-drain so that the third transistor T3 forms a diode structure, thereby reducing the use of a reset signal line. Thus, the improvement of the third transistor T3 can reduce the use of signal lines and increase the aperture ratio. At the same time, the gate of the third transistor T3 is connected to the second source and drain; when preparing the layout, the channel region of the third transistor T3 is directly connected to the first end or the second end, which is equivalent to directly connecting the gate of the transistor to the first end or the second end through the channel region, thereby reducing the use of the gate metal layer for forming the third transistor T3, thereby saving the layout preparation process.

[0023] During operation, the timing diagram for the pixel units located in odd columns is configured as follows: Figure 3 As shown, First programming stage: By controlling the potential change of the data signal line Data and the row gate signal line Scan, the data signal line Data writes the data signal voltage to the pre-storage capacitor Cs1 through the first transistor T1; The row gate signal line Scan jumps to a high level, and the first transistor T1 is turned on, so that the data signal line Data writes the data signal voltage of the n+1th frame into the pre-storage capacitor Cs1; After writing is completed, the row gate signal line Scan jumps to a low level, and the first transistor T1 is turned off; Second programming stage: Through the potential change of the first reference signal line Vref1, the level of the first reference signal line Vref1 jumps from the 0 level to the Vop_manx level, and the third transistor T3 is turned on, so that the first reference signal line Vref1 completes the reset of the pixel electrode Clc and the holding capacitor Cs2 through the third transistor T3, and at this time, the potential of the pixel electrode Clc is reset to Vop_max, and Vop_max is the voltage corresponding to the maximum grayscale; Furthermore, the first reference signal line Vref1 changes at the same level in the nth frame or the n+1th frame, thereby reducing the difficulty of the driving chip in controlling the first reference signal line Vref1; Transfer phase: By controlling the level change of the transfer signal line Tran and the second common signal line Vcom_even, the charge amount transferred from the pre-storage capacitor Cs1 to the pixel electrode Clc is completed, and the preset data signal voltage is written into the pixel electrode Clc; The transfer signal line Tran jumps to a high level, and the second transistor T2 is turned on, so that the pre-storage capacitor Cs1 transfers charges to the pixel electrode Clc through the second transistor T1; The transfer signal line Tran jumps to a low level, the second transistor T2 is turned off, and the level of the second common signal line Vcom_even jumps to a low level. At this time, the potential of the lower plate of the pixel electrode Clc is the same as that of the second common signal line Vcom_even, and the pixel electrode Clc releases excess charge through the second common signal line Vcom_even until the voltage of the pixel electrode Clc reaches the preset data signal voltage.

[0024] In this embodiment, the voltage range that the data signal line Data needs to output is calculated according to the charge conservation principle; taking the pixel unit of the odd column as an example, at the display time of the nth frame, the data signal voltage of the n+1th frame is written to the pre-storage capacitor Cs1, that is, a positive polarity voltage needs to be written; in the transfer stage, when the pixel voltage Vpixel of the pixel electrode Clc is Vop_max, the pixel voltage Clc has been reset to Vop_max in the second programming stage, and thus the following formula can be obtained according to the charge conservation principle: (Vcs1-(Vop_max))*Cs1=((Vop_max)- (Vop_max)) *(Cs2+Clc); That is, Vcs1-Vop_max = 0, so Vcs1 = Vop_max; Where: Vcs1: data signal voltage pre-written into the pre-storage capacitor Cs1; Vop_max: Vpixel / reset voltage; Cs1: capacitance value of pre-storage capacitor Cs1; Cs2: the capacitance value of holding capacitor Cs2; Clc: capacitance value of pixel electrode Clc.

[0025] In the transfer phase, when the pixel voltage Vpixel of the pixel electrode Clc is 0, the pixel voltage Clc has been reset to Vop_max in the second programming phase, and the following formula can be obtained according to the charge conservation principle: (Vcs1-0)*Cs1=(0- (Vop_max))*(Cs2+Clc), Vcs1-0=0- (Vop_max), Vcs1=-Vop_max; It can be obtained that in the positive polarity frame, the required voltage range of the data signal line Data is (-Vop_max, +Vop_max); Similarly, in the negative polarity frame, the pixel voltage Vpixel of the pixel electrode Clc varies in the range of (-Vop_max, 0). Similarly, the pixel electrode Clc is reset to Vop_max in the reset phase. According to the above steps, the voltage variation range of the data signal line Data is calculated to be (-Vop_max, +Vop_max).

[0026] Therefore, the voltage variation range of the data signal line Data during the entire working process is (-Vop_max, +Vop_max), while in the prior art, the voltage variation range of the data signal line Data needs to be 4*Vop_max; the use of this embodiment can reduce the voltage variation range by one half, and the reduction of the voltage range of the data signal line Data can further reduce the power consumption of the driving chip and the control row gate signal line output unit. Example

[0027] like Figure 4 and Figure 5 As shown, the present invention also provides a second embodiment. In the second embodiment, the gate of the third transistor T3 of the pixel unit is coupled to the first source and drain of the third transistor T3. At this time, during layout preparation, the channel region of the third transistor T3 is connected to the first end.

[0028] During operation, the timing diagram for the pixel units located in odd columns is configured as follows: Figure 6 As shown, the second programming stage: The level of the first reference signal line Vref1 jumps from the Vopmanx level to the 0 level. At this time, the first source and drain of the third transistor T3 are at a high level, and the second source and drain of the third transistor T3 are at a 0 level, so that a voltage difference is formed at both ends. The third transistor T3 is turned on, so that the first reference signal line Vref1 completes the resetting of the pixel electrode Clc and the holding capacitor Cs2 through the third transistor T3. At this time, the potential of the pixel electrode Clc is reset to the 0 level.

[0029] In this embodiment, the voltage range that the data signal line Data needs to output is calculated according to the charge conservation principle; taking the pixel unit of the odd column as an example, at the display time of the nth frame, the data signal voltage of the n+1th frame is written to the pre-storage capacitor Cs1, that is, a positive polarity voltage needs to be written; In the transfer phase, when the pixel voltage Vpixel of the pixel electrode Clc is equal to Vop_max, the pixel voltage Clc has been reset to a 0 level in the second programming phase, and the following formula can be obtained according to the charge conservation principle: (Vcs1-(Vop_max))*Cs1=((Vop_max)- (0)) *(Cs2+Clc); That is, Vcs1-Vop_max-Vop_max = 0, and Vcs1 = 2*Vop_max; Where: Vcs1: data signal voltage pre-written into the pre-storage capacitor Cs1; Vop_max: Vpixel; Cs1: capacitance value of pre-storage capacitor Cs1; Cs2: the capacitance value of holding capacitor Cs2; Clc: capacitance value of pixel electrode Clc.

[0030] When the pixel voltage Vpixel of the pixel electrode Clc is 0, the pixel voltage Clc has been reset to 0 in the second programming stage, and the following formula can be obtained according to the charge conservation principle: (Vcs1-0)*Cs1=(0- (0))*(Cs2+Clc), Vcs1-0=0- (0), Vcs1=2*Vop_max; It can be obtained that in the positive polarity frame, the voltage range of the required data signal line Data is (0, 2*Vop_max); Similarly, in the negative polarity frame, the pixel voltage Vpixel of the pixel electrode Clc varies in the range of (0, 2*Vop_max). Similarly, the pixel electrode Clc is reset to level 0 in the reset phase. According to the above steps, the voltage variation range of the data signal line Data is calculated to be (0, 2*Vop_max). Similarly, the voltage variation range of the data signal line Data is 2*Vop_max. Example

[0031] The present invention further provides a third embodiment, which is a pixel driving circuit writing method for field sequential display, which is applied to the first and second embodiments, including a circuit obtained by deforming the first and second embodiments; First programming stage: By controlling the potential change of the data signal line Data and the row gate signal line Scan, the data signal line Data writes the data signal voltage to the pre-storage capacitor Cs1 through the first transistor T1; Second programming stage: By changing the potential of the first reference signal line Vref1, the first reference signal line Vref1 completes the reset of the pixel electrode Clc and the holding capacitor Cs2 through the third transistor T3; Transfer phase: By controlling the level changes of the transfer signal line Tran, the first common signal line Vcom_odd and the second common signal line Vcom_even, the charge amount transferred from the pre-storage capacitor Cs1 to the pixel electrode Clc is completed, and the preset data signal voltage is written into the pixel electrode Clc; The first common signal line Vcom_odd outputs a first AC driving signal, and the second common signal line Vcom_even outputs a second AC driving signal, wherein the first AC driving signal and the second AC driving signal have the same frequency and opposite polarities.

[0032] The common signal line driven by direct current in the prior art is replaced with two alternating current signal lines respectively connected to odd columns and even columns, and the alternating current driving signal of the first common signal line Vcom_odd has the same frequency as the alternating current driving signal of the second common signal line Vcom_even but has opposite polarity; in the reset stage, the first reference signal line Vref1 will reset the pixel electrodes Clc of the odd columns and the even columns to 0 or Vop_max; so that the voltage difference across the pixel electrode Clc can be between (-Vop_max, +Vop_max), thereby achieving the pixel voltage Vpixel required by the pixel electrode Clc when working in the frame; thereby, the voltage pre-written into the pre-storage capacitor Cs1 by the data signal line Data can be reduced, thereby reducing the data voltage variation range of the data signal line Data.

[0033] The above embodiments only express preferred implementation modes, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention. It should be pointed out that, for ordinary technicians in this field, several modifications and improvements can be made without departing from the invention, and these all belong to the protection scope of the invention.

Claims

1. A pixel driving circuit for field sequential display, characterized in that: It includes pixel units arranged in multiple rows and columns, the pixel units include a driving module and a reset module, the reset module includes a third transistor T3 and a first reference signal line Vref1; The connection mode of the third transistor T3 is configured as the gate of the third transistor T3 is coupled to the second source and drain, or the gate of the third transistor T3 is coupled to the first source and drain; A first source and a drain of the third transistor T3 are coupled to the driving module, and a second source and a drain of the third transistor T3 are coupled to the first reference signal line Vref1 .

2. A pixel driving circuit for field sequential display according to claim 1, characterized in that: The driving module includes a second transistor T2 and a pixel electrode Clc, the gate of the second transistor T2 is coupled to the transfer signal line Tran, the second source and drain of the second transistor T2 is coupled to one end of the pixel electrode Clc, and the second source and drain of the second transistor T2 is also coupled to the first source and drain of the third transistor T3.

3. A pixel driving circuit for field sequential display according to claim 2, characterized in that: The pixel unit also includes a pre-storage module; The pre-storage module includes a first transistor T1 and a pre-storage capacitor Cs1, the first source and drain of the first transistor T1 are coupled to the data signal line Data, the gate of the first transistor T1 is coupled to the row gate signal line Scan, the second source and drain of the first transistor T1 are coupled to one end of the pre-storage capacitor Cs1, and the second source and drain of the first transistor T1 are also coupled to the first source and drain of the second transistor T2.

4. A pixel driving circuit for field sequential display according to claim 3, characterized in that: The other end of the pre-storage capacitor Cs1 of the pixel unit located in the odd column and the other end of the pixel electrode Clc are both coupled to the second common signal line Vcom_even; The other end of the pre-storage capacitor Cs1 of the pixel unit located in the even-numbered column and the other end of the pixel electrode Clc are both coupled to the first common signal line Vcom_odd; A first AC driving signal is input to the pixel units located in even columns through the first common signal line Vcom_odd, and a second AC driving signal is input to the pixel units located in odd columns through the second common signal line Vcom_even. The first AC driving signal and the second AC driving signal have the same frequency and opposite polarity.

5. The pixel driving circuit for field sequential display according to claim 2, characterized in that: The driving module further includes a holding capacitor Cs2 , wherein the holding capacitor Cs2 is coupled to the second source and drain of the second transistor T2 ; the other end of the holding capacitor Cs2 is coupled to the second reference signal line Vref2 .

6. A pixel driving circuit for field sequential display according to claim 4, characterized in that: When preparing a layout of a pixel unit, the layout comprises a light shielding layer (1), an active layer (2), a source-drain layer (3), an intermediate metal layer (4), a transparent conductive layer (5) and a color conductive layer (6); The light shielding layer (1) is arranged on a glass substrate, a first insulating layer is arranged on the light shielding layer (1), an active layer (2) is arranged on the first insulating layer, the active layer (2) constitutes a gate of a first transistor T1 and a gate of a second transistor T2; a row gate signal line Scan and a transfer signal line Tran are also formed on the light shielding layer (1); A second insulating layer is provided on the active layer (2), and a source-drain layer (3) is provided on the second insulating layer, the source-drain layer (3) is connected to the active layer (2) via a through hole, the source-drain layer (3) and the active layer (2) constitute the channel region, the first end and the second end of the first transistor T1, and together with the active layer (2) also constitute the channel region, the first end and the second end of the second transistor T2, and together with the active layer (2) constitute the channel region, the first end and the second end of the third transistor T3, the channel region of the third transistor (T3) being connected to the first end; A third insulating layer is arranged on the source-drain layer (3), and an intermediate metal layer (4) is arranged on the third insulating layer, wherein the intermediate metal layer (4) forms a first reference signal line Vref1 and a data signal line Data; the overlapping portion of the intermediate metal layer (4) and the source-drain layer (3) forms a pre-storage capacitor Cs1; A fourth insulating layer is arranged on the intermediate metal layer (4), and a transparent conductive layer (5) is arranged on the fourth insulating layer, wherein the transparent conductive layer (5) constitutes a pixel electrode (Clc); The intermediate metal layer (4) is connected to the color conductive layer (6) via a conductive material, and the color conductive layer (6) forms a common signal line.

7. A pixel driving circuit for field sequential display according to claim 6, characterized in that: The color conductive layer (6) of the pixel units located in odd columns forms a second common signal line Vcom_even; the color conductive layer (6) of the pixel units located in even columns forms a first common signal line Vcom_odd.

8. A pixel driving circuit writing method for field sequential display, applied to any pixel driving circuit according to claim 1 to claim 7, characterized in that: include: First programming stage: By controlling the potential change of the data signal line Data and the row gate signal line Scan, the data signal line Data writes the data signal voltage to the pre-storage capacitor Cs1 through the first transistor T1; Second programming stage: By changing the potential of the first reference signal line Vref1, the first reference signal line Vref1 completes the reset of the pixel electrode Clc and the holding capacitor Cs2 through the third transistor T3; Transfer phase: By controlling the level changes of the transfer signal line Tran, the first common signal line Vcom_odd and the second common signal line Vcom_even, the charge amount transferred from the pre-storage capacitor Cs1 to the pixel electrode Clc is completed, and the preset data signal voltage is written into the pixel electrode Clc; The first common signal line Vcom_odd outputs a first AC driving signal, and the second common signal line Vcom_even outputs a second AC driving signal, wherein the first AC driving signal and the second AC driving signal have the same frequency and opposite polarities.

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