Refresh control circuit and memory

Abstract

The invention relates to the field of semiconductor circuit design, in particular to a refresh control circuit and a memory, and the refresh control circuit comprises a switching identification signal generation circuit which is configured to generate a refresh operation signal when a refresh operation indication signal indicates that the memory is in a fine-grained refresh mode; counting full-array refresh commands received by the memory when the memory is in the fine-grained refresh mode, and generating and outputting a switching control identifier in an effective level when the count value of the full-array refresh commands is an odd number; the mode switching control circuit is configured to generate and output a refresh operation indication signal based on a refresh mode indication signal and a switching control identifier, the refresh mode indication signal indicates that the memory is switched to a normal refresh mode, and if the switching control signal is in an effective level, the memory is switched to a normal refresh mode. And keeping the level of the output refresh operation indication signal unchanged so as to indicate the memory to continue performing fine-grained refresh based on the next full-array refresh command.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor circuit design, and in particular to a refresh control circuit and a memory. Background Art

[0002] The fifth-generation double data rate synchronous dynamic random access memory (DDR5 SDRAM) is a high-bandwidth memory. DDR5 usually contains two refresh modes and two types of refresh commands. The two refresh modes include: normal refresh mode and fine-grained refresh mode (compared with the normal refresh mode, the fine-grained refresh mode has fewer activated word lines in each tRFC, for example, one tRFC in the normal refresh mode performs 4 ACTIVEs, while one tRFC in the fine-grained refresh mode performs 2 ACTIVEs); the two types of refresh commands include: full array refresh command REFab and same array refresh command REFsb (full array refresh command REFab is used to refresh all arrays of the memory, and same array refresh command REFsb is used to refresh the target array of the memory). The full array refresh command REFab can usually be executed in both refresh modes, while the same array refresh command REFsb can only be executed in the fine-grained refresh mode. If the same array refresh command is issued in the normal refresh mode, the current same array refresh command will be blocked because the same array refresh command cannot be executed.

[0003] For DDR5, before the memory switches from fine-grained refresh mode to normal refresh mode, it is recommended that the memory controller issue an even number of full array refresh commands REFab or an even number of same array refresh commands REFsb. If the condition is not met, the memory controller will issue an additional full array refresh command REFab before the refresh mode of the memory is changed, and this additional full array refresh command REFab is not included in the calculation of the average refresh interval (tREFI1).

[0004] In addition, this additional full array refresh command REFab may cause the memory to repeatedly refresh some arrays when the refresh mode is frequently switched, resulting in a waste of refresh resources of the memory. Summary of the invention

[0005] The embodiments of the present disclosure provide a refresh control circuit and a memory, which use an additional full-array refresh command as a full-array refresh command in a fine-grained refresh mode to perform a refresh operation, so that the full-array refresh command executed by the memory in the fine-grained refresh mode is an even number, thereby better maintaining the frequent switching of the memory between different refresh modes and avoiding the waste of refresh resources of the memory caused by the additional full-array refresh command.

[0006] An embodiment of the present disclosure provides a refresh control circuit, comprising: a switch identification signal generating circuit, receiving a refresh operation indication signal and a full array refresh command, wherein the refresh operation indication signal indicates that the memory to which it belongs performs a normal refresh or a fine-grained refresh; the switch identification signal generating circuit is configured to, when the refresh operation indication signal indicates that the memory to which it belongs is in a fine-grained refresh mode, count the full array refresh commands received by the memory to which it belongs during the fine-grained refresh mode, and when the count value of the full array refresh command is an odd number, generate and output a switch control indication at a valid level; a mode switching control circuit, coupled to the switch identification signal generating circuit, receiving the refresh mode indication signal and the switch control indication, and generating and outputting a refresh operation indication signal based on the refresh mode indication signal and the switch control indication; wherein the refresh mode indication signal indicates that the memory to which it belongs is currently in a normal refresh mode or in a fine-grained refresh mode; and the mode switching control circuit is configured to, when the refresh mode indication signal indicates that the memory to which it belongs switches to a normal refresh mode, if the switch control signal is at a valid level, maintain the level of the output refresh operation indication signal unchanged, so as to instruct the memory to continue to perform a fine-grained refresh based on a next full array refresh command.

[0007] This embodiment uses the additional full-array refresh command as the full-array refresh command in the fine-grained refresh mode to perform a refresh operation, so that the full-array refresh command executed by the memory in the fine-grained refresh mode is an even number, thereby better maintaining the frequent switching of the memory between different refresh modes and avoiding the waste of memory refresh resources caused by the additional full-array refresh command.

[0008] Optionally, the switching identification signal generating circuit includes: a first AND logic circuit, a first input end for receiving a refresh operation indication signal, a second input end for receiving a full array refresh command, and is configured to generate and output a counting identification based on the full array refresh command when the refresh operation indication signal indicates that the memory to which it belongs performs a fine-grained refresh; a counting module, configured to receive the counting identification and count based on the counting identification to generate a counting result, and when the counting result is an odd number, generate and output a valid switching control identification.

[0009] Optionally, the counting module includes: a first trigger, a clock end for receiving a counting flag, an input end connected to an inverting output end, an output end for outputting a switching control flag, and in an initial state, the switching control flag output by the first trigger is at an invalid level.

[0010] Optionally, the mode switching control circuit includes: a first OR logic circuit, a first input end for receiving a refresh mode indication signal, and a second input end for receiving a switching control identifier; a first delay circuit, an input end connected to an output end of the first OR logic circuit, and an output end for outputting a refresh operation indication signal.

[0011] Optionally, the mode switching control circuit is further configured to flip the level of the output refresh operation indication signal when the fine-grained refresh operation executed based on the next full-array refresh command is completed.

[0012] Optionally, the mode switching control circuit includes: a first OR logic circuit, a first input end for receiving a refresh mode indication signal, and a second input end for receiving a switching control identifier; a first delay circuit, an input end connected to an output end of the first OR logic circuit; a latch, an input end connected to an output end of the first delay circuit, a control end for receiving a refresh window signal, and an output end for outputting a refresh operation indication signal.

[0013] Optionally, the switching identification signal generating circuit is also used to receive an identical array refresh identification signal, wherein, when the corresponding memory performs a refresh operation based on the identical array refresh command and each time the last array in the storage array group performs a refresh, an identical array refresh identification signal is generated; the switching identification signal generating circuit is configured to, when the refresh operation indication signal indicates that the corresponding memory is in a fine-grained refresh mode, count the identical array refresh identification signals received by the corresponding memory during the fine-grained refresh mode, and when the count value of the identical array refresh identification signal is an odd number, generate and output a switching control identification at a valid level.

[0014] Optionally, the switching identification signal generating circuit includes: a first AND logic circuit, a first input end of which is used to receive a refresh operation indication signal, and a second input end of which is used to receive a full array refresh command; a second OR logic circuit, a first input end of which is connected to the output end of the first AND logic circuit, a second input end of which is used to receive the same array refresh identification signal, and an output end of which is used to output a counting identification; a counting module, configured to receive a counting identification and count based on the counting identification to generate a counting result, and when the counting result is an odd number, generate and output a valid switching control identification.

[0015] Optionally, the counting module includes: a first trigger, a clock end for receiving a counting flag, an input end connected to an inverting output end, an output end for outputting a switching control flag, and in an initial state, the switching control flag output by the first trigger is at an invalid level.

[0016] Optionally, the refresh control circuit further includes: a refresh identification signal generating circuit, configured to generate an identical array refresh identification signal.

[0017] Optionally, the refresh identification signal generating circuit includes: N latches, N is the number of storage arrays in each storage array group in the corresponding memory, and the N latches are arranged in a one-to-one correspondence with the N storage arrays in each storage array group, the set end of each latch is used to receive the same array refresh command corresponding to the corresponding storage array, and the output end of each latch is used to output the corresponding array refresh identification signal; a second AND logic circuit includes N input ends, and the N input ends are connected to the output ends of the N latches in a one-to-one correspondence, and the output end is used to output the same array refresh identification signal; a second delay circuit, the input end is used to receive the same array refresh identification signal, and the output end is connected to the input end of the first inverter; the output end of the first inverter is used to output a reset control signal, and the reset end of each latch is coupled to the output end of the first inverter.

[0018] Optionally, the latch includes: a first OR-NOT logic circuit, a first input terminal serving as a set terminal of the latch, for receiving the same array refresh command corresponding to the corresponding storage array, a second input terminal connected to an output terminal of the second OR-NOT logic circuit, and an output terminal connected to a first input terminal of the second OR-NOT logic circuit; a second input terminal of the second OR-NOT logic circuit serving as a reset terminal of the latch, connected to an output terminal of a second inverter, an input terminal of the second inverter serving as an output terminal of the latch, and an output terminal serving as an output terminal of the latch, for outputting a corresponding array refresh identification signal.

[0019] Optionally, the refresh identification signal generating circuit also includes: a third OR-NOT logic circuit, a first input terminal for receiving a full array refresh command, and a second input terminal for receiving a self-refresh command; a third AND logic circuit, a first input terminal connected to the output terminal of the third OR-NOT logic circuit, a second input terminal for receiving a reset control signal, and an output terminal connected to the reset terminal of each latch.

[0020] Another embodiment of the present disclosure further provides a memory, including the refresh control circuit provided in the above embodiment, so as to use an additional full-array refresh command as a full-array refresh command in a fine-grained refresh mode to perform a refresh operation, so that the full-array refresh command executed by the memory in the fine-grained refresh mode is an even number, thereby better maintaining the frequent switching of the memory between different refresh modes and avoiding the waste of refresh resources of the memory caused by the additional full-array refresh command. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 A schematic diagram of a refresh control circuit based on a full array refresh command according to an embodiment of the present disclosure;

[0023] Figure 2 An embodiment of the present disclosure provides Figure 1 A schematic diagram showing a principle of performing a refresh operation by using an additional full array refresh command as a full array refresh command in a fine-grained refresh mode;

[0024] Figure 3 An embodiment of the present disclosure provides Figure 1 A schematic diagram of the structure of an exemplary switching identification signal generating circuit;

[0025] Figure 4 An embodiment of the present disclosure provides Figure 3 A schematic diagram of the structure of a counting module of an example;

[0026] Figure 5 A schematic diagram of the structure of a mode switching control circuit provided in an embodiment of the present disclosure;

[0027] Figure 6 A schematic diagram of the structure of another refresh control circuit based on a full array refresh command provided by an embodiment of the present disclosure;

[0028] Figure 7 A schematic diagram of the structure of a mode switching control circuit including a latch provided in an embodiment of the present disclosure;

[0029] Figure 8 An embodiment of the present disclosure provides Figure 7 A schematic diagram showing the principle of generating a refresh operation indication signal by an exemplary mode switching control circuit;

[0030] Fig. 9 A schematic diagram of a refresh control circuit based on a full array refresh command and a same array refresh command according to an embodiment of the present disclosure;

[0031] Fig.10 An embodiment of the present disclosure provides Fig. 9 A schematic diagram showing a principle of performing a refresh operation by using an additional full array refresh command as a full array refresh command in a fine-grained refresh mode;

[0032] Fig.11 An embodiment of the present disclosure provides Fig. 9 A schematic diagram of the structure of an exemplary switching identification signal generating circuit;

[0033] Fig.12 A structural schematic diagram of another refresh control circuit based on a full array refresh command and a same array refresh command provided in an embodiment of the present disclosure;

[0034] Fig.13 An embodiment of the present disclosure provides Fig.12 A schematic diagram of an example refresh control circuit;

[0035] Fig.14 A schematic diagram of the structure of a refresh identification signal generating circuit provided in one embodiment of the present disclosure;

[0036] Fig.15 A schematic diagram of the structure of a latch provided in one embodiment of the present disclosure;

[0037] Fig.16 A schematic diagram of the working principle of a refresh identification signal generating circuit provided in an embodiment of the present disclosure;

[0038] Fig.17 A schematic diagram of the structure of another refresh identification signal generating circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] As can be seen from the background technology, before the memory switches from the fine-grained refresh mode to the normal refresh mode, it is recommended that the memory controller issues an even number of full array refresh commands REFab or an even number of arrays of the same array refresh commands REFsb. If the conditions are not met, the memory controller will issue an additional full array refresh command REFab before the refresh mode of the memory is changed, and this additional full array refresh command REFab is not included in the calculation of the average refresh interval (tREFI1). In addition, this additional full array refresh command REFab will cause the memory to repeatedly refresh some arrays when the refresh mode is frequently switched, resulting in a waste of memory refresh resources.

[0040] An embodiment of the present disclosure provides a refresh control circuit to use an additional full-array refresh command as a full-array refresh command in a fine-grained refresh mode to perform a refresh operation, so that the full-array refresh command executed by the memory in the fine-grained refresh mode is an even number, thereby better maintaining the frequent switching of the memory between different refresh modes and avoiding the waste of refresh resources of the memory caused by the additional full-array refresh command.

[0041] It can be understood by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for the convenience of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments can be combined with each other and referenced to each other without contradiction.

[0042] Figure 1 A schematic diagram of the structure of a refresh control circuit based on a full array refresh command provided in this embodiment, Figure 2 The embodiment provided Figure 1 The schematic diagram of the principle of using an additional full array refresh command as a full array refresh command in fine-grained refresh mode to perform a refresh operation is shown in the example. Figure 3 The embodiment provided Figure 1 A schematic diagram of the structure of an exemplary switching identification signal generating circuit, Figure 4 The embodiment provided Figure 3 A schematic diagram of the structure of a counting module is shown as an example. Figure 5 A schematic diagram of the structure of the mode switching control circuit provided in this embodiment, Figure 6 A schematic diagram of another refresh control circuit based on a full array refresh command provided in this embodiment, Figure 7 A schematic diagram of the structure of a mode switching control circuit including a latch provided in this embodiment, Figure 8 The embodiment provided Figure 7 A schematic diagram showing the principle of generating a refresh operation indication signal by an exemplary mode switching control circuit, Fig. 9 A schematic diagram of the structure of a refresh control circuit based on a full array refresh command and a same array refresh command provided in this embodiment, Fig.10 The embodiment provided Fig. 9 The schematic diagram of the principle of using an additional full array refresh command as a full array refresh command in fine-grained refresh mode to perform a refresh operation is shown in the example. Fig.11 The embodiment provided Fig. 9 A schematic diagram of the structure of an exemplary switching identification signal generating circuit, Fig.12A schematic diagram of another refresh control circuit based on a full array refresh command and a same array refresh command provided in this embodiment, Fig.13 The embodiment provided Fig.12 A schematic diagram of a refresh control circuit of an example, Fig.14 A schematic diagram of a refresh identification signal generating circuit provided in this embodiment is shown in FIG. Fig.15 A schematic diagram of the structure of a latch provided in this embodiment, Fig.16 A schematic diagram of the working principle of the refresh identification signal generating circuit provided in this embodiment, Fig.17 This is a schematic diagram of the structure of another refresh identification signal generating circuit provided in this embodiment. The refresh control circuit provided in this embodiment is described in detail in conjunction with the accompanying drawings, as follows:

[0043] For refresh control of existing circuits, the memory refresh mode is changed by coding the MRW command to MR4_OP <4> Specifically, when MR4_OP <4> = "0", the memory performs normal refresh (Normal Refresh); when MR4_OP <4> = "1", the memory performs fine-grained refresh (FGR). The present disclosure performs fine-grained refresh (FGR) on the original MR4_OP <4> The signal is processed to perform refresh control on the memory.

[0044] refer to Figure 1 , the refresh control circuit 100 includes: a switching identification signal generating circuit 101 for receiving a refresh operation indication signal MR4_OP <4> _1 and the full array refresh command CMD_REFab, wherein the refresh operation indication signal MR4_OP <4> _1 is used to indicate that the memory to which it belongs performs a normal refresh or a fine-grained refresh.

[0045] In one example, when the refresh operation indication signal MR4_OP <4> _1="1", the memory performs fine-grained refresh. When the refresh operation indication signal MR4_OP <4> _1="0", the memory performs normal refresh. The following description of this embodiment is specifically described in the setting mode of this example to facilitate those skilled in the art to understand the technical solution of the present disclosure, and does not constitute a limitation on this embodiment; in other embodiments, it can also be set that when the refresh operation indication signal = "1", the memory performs normal refresh, and when the refresh operation indication signal is "0", the memory performs fine-grained refresh.

[0046] The switch identification signal generating circuit 101 is configured to, when the refresh operation indication signal MR4_OP <4> _1 indicates that when the memory is in the fine-grained refresh mode, the full array refresh commands CMD_REFab received by the memory during the fine-grained refresh mode are counted, and when the count value of the full array refresh command CMD_REFab is an odd number, a switching control flag FGR_CMD_ODD at a valid level is generated and output.

[0047] For the switching control flag, in the example of the present disclosure, the effective level of the switching control flag FGR_CMD_ODD is taken as a high level "1" as an example for illustration, so as to facilitate technical personnel in the field to understand the technical solution of the present disclosure, and does not constitute a limitation of the present embodiment; in other embodiments, the effective level of the switching control flag can also be set to a high level "0".

[0048] Continue to refer Figure 1 The refresh control circuit 100 further includes: a mode switching control circuit 102 coupled to the switching identification signal generating circuit 101, configured to receive the switching control identification FGR_CMD_ODD generated by the identification signal generating circuit 101, and receive the refresh mode indication signal MR4_OP <4> _0, wherein the refresh mode indication signal MR4_OP <4> _0 is used to indicate that the memory is currently in normal refresh mode or in fine-grained refresh mode, that is, MR4_OP mentioned above <4> signal, accordingly, when the refresh mode indication signal MR4_OP <4> _0="0", the memory is currently in fine-grained refresh mode. When the refresh mode indication signal MR4_OP <4> _0="1", the memory is currently in normal refresh mode.

[0049] The mode switching control circuit 102 is configured to, based on the refresh mode indication signal MR4_OP <4> _0 and the switch control flag FGR_CMD_ODD generate and output the refresh operation instruction signal MR4_OP <4> _1, where the refresh mode indication signal MR4_OP <4> _0 indicates that the memory is switched to normal mode. If the switch control signal is at a valid level, the refresh operation indication signal MR4_OP is maintained. <4> The level of _1 remains unchanged to instruct the corresponding memory to continue to perform fine-grained refresh based on the next full array refresh command CMD_REFab.

[0050] Specific reference Figure 2During the normal refresh operation of the memory, the refresh operation indication signal MR4_OP <4> _1 and the refresh mode indication signal MR4_OP <4> _0 is the same, and based on the background technology, it can be known that before the memory switches from the fine-grained refresh mode to the normal mode, it is recommended that the full array refresh command CMD_REFab issued by the storage controller is an even number, and the refresh mode switching of the memory is performed normally at this time; when the full array refresh command CMD_REFab issued by the storage controller is an odd number, at this time, before the refresh mode of the memory is changed, the storage controller will issue an additional full array refresh command CMD_REFab, and the identification generating circuit 101 generates a switching control identification FGR_CMD_ODD at a valid level based on the odd number of full array refresh commands CMD_REFab, and the switching control identification FGR_CMD_ODD at a valid level will refresh the mode indication signal MR4_OP <4> The level of MR4_OP is extended to generate the refresh operation indication signal MR4_OP. <4> _1, wherein the specific delay duration is t1, t1 includes the time when the switching control flag FGR_CMD_ODD is at an effective level and the refresh time based on the memory based on the next full array refresh command CMD_REFab, so that when the memory controller issues an additional (next) full array refresh command CMD_REFab, the refresh operation indication signal MR4_OP of the memory <4> _1 indicates that the memory performs fine-grained refresh; at this time, the memory performs fine-grained refresh based on the additional (next) full array refresh command CMD_REFab, so that the full array refresh command CMD_REFab executed by the memory in the fine-grained refresh mode is an even number, and then the refresh mode switching of the memory is performed normally. It can be seen that in this embodiment, by using the additional full array refresh command CMD_REFab as the full array refresh command CMD_REFab in the fine-grained refresh mode for refresh operation, the full array refresh command CMD_REFab executed by the memory in the fine-grained refresh mode is an even number, thereby better maintaining the frequent switching of the memory between different refresh modes and avoiding the waste of refresh resources of the memory caused by the additional full array refresh command.

[0051] For the switching identification signal generating circuit, in some embodiments, refer to Figure 3The switching identification signal generating circuit 101 includes: a first AND logic circuit 201, a first input terminal for receiving a refresh operation indication signal MR4_OP <4> _1, the second input terminal is used to receive the full array refresh command CMD_REFab, the first AND logic circuit 201 is configured to, when the refresh operation indication signal MR4_OP <4> _1 indicates that the memory to which it belongs performs fine-grained refresh, and generates and outputs a counting mark MR4_OP_OR based on the full array refresh command CMD_REFab. The counting module 203 is configured to receive the counting mark MR4_OP_OR and count based on the counting mark to generate a counting result, and when the counting result is an odd number, generate and output a valid switching control mark FGR_CMD_ODD.

[0052] In one example, refer to Figure 4 The counting module 203 can be set based on the first trigger 204. Specifically, the clock terminal CK of the first trigger 204 is used to receive the counting mark MR4_OP_OR, the input terminal D is connected to the inverting output terminal Q-, and the output terminal Q is used to output the switching control mark FGR_CMD_ODD. In the initial state, the switching control mark FGR_CMD_ODD output by the first trigger 204 is in an invalid state.

[0053] As for the working principle of the first trigger 204, specifically, the count mark MR4_OP_OR received by the clock end is at the effective edge, that is, when the memory performs fine-grained refresh, it receives the full array refresh command CMD_REFab, and the first trigger 204 outputs based on the input data. When the input data of the input terminal D is "0", the output terminal Q output switching control mark FGR_CMD_ODD is "0", and the output data of the inverting output terminal Q-connected to the input terminal is "1"; when the input data of the input terminal D is "1", the output terminal Q output switching control mark FGR_CMD_ODD is "0", and the output data of the inverting output terminal Q-connected to the input terminal is "1"; when the input data of the input terminal D is "1", the output terminal Q output switching control mark FGR_CMD_ODD is "0", and the output data of the inverting output terminal Q-connected to the input terminal is "1". _ODD is "1", and the output data of the inverting output terminal Q-connected to the input terminal is "0", that is, the switching control flag FGR_CMD_ODD output by the first trigger 204 realizes the jump between "0" and "1" based on the effective edge of the input signal MR4_OP_OR of the clock terminal CK, and when the control receives the full array refresh command CMD_REFab as an odd number, the switching control flag FGR_CMD_ODD output by the first trigger 204 is "1", thereby realizing the counting of the full array refresh command CMD_REFab received when performing fine-grained refresh on the memory.

[0054] For the mode switching circuit, in some embodiments, reference Figure 5, the mode switching circuit 102 comprises: a first OR logic circuit 401, a first input terminal for receiving the refresh mode indication signal MR4_OP <4> _0, the second input end is used to receive the switching control flag FGR_CMD_ODD; the first delay circuit 402, the input end is connected to the output end of the first OR logic circuit 401, and the output end is used to output the refresh operation indication signal MR4_OP <4> _1.

[0055] Based on the above, it can be known that the switch control flag FGR_CMD_ODD at the effective level will refresh the mode indication signal MR4_OP <4> The level of MR4_OP is extended to generate the refresh operation indication signal MR4_OP. <4> _1, wherein the specific delay time is t1, t1=t11+t12, t11 is the refresh mode indication signal MR4_OP <4> _0 indicates the time that the switching control flag FGR_CMD_ODD remains at a valid level after the memory is switched to the normal refresh mode, and t12 is the refresh time of the memory based on the next full array refresh command CMD_REFab. Figure 5 In the circuit shown, the level extension of t11 is implemented based on the first OR logic circuit 401, and the level extension of t12 is implemented based on the first delay circuit 402, that is, the delay time of the first delay circuit 402 for the input signal is set to the refresh time of the memory based on the next full array refresh command CMD_REFab, so as to realize fine-grained refresh of the memory based on the additional (next) full array refresh command CMD_REFab.

[0056] In other embodiments, since both the delay circuit and the refresh control circuit are greatly affected by PVT (process, voltage, temperature) factors, the delay time of a single delay unit in different memories is different, and the pulse width time of the refresh window signal generated by the refresh control circuit is also different. Therefore, the time of tl2 cannot be accurately controlled; in addition, the execution time of the refresh operation corresponding to different refresh modes is also different (based on the fact that each refresh command can select to perform one or more refresh operations according to the refresh mode, the execution time of the corresponding refresh operation in different modes is also different), so the time of t12 is uncontrollable. If the time set for t12 is very short, it cannot completely cover the refresh operation window corresponding to the next refresh command. If the time set for t12 is very long, it may increase the power consumption of the circuit and may even cover the next multiple refresh commands. On this basis, the mode switching control circuit 102 is also configured to output the refresh operation indication signal MR4_OP when the fine-grained refresh operation executed based on the next full-array refresh command is completed. <4> _1 level flip, that is, refresh operation indication signal MR4_OP <4> _1 will instruct the memory to perform a normal refresh operation and the memory's refresh mode change is complete.

[0057] Specifically, refer to Figure 6 The mode switching circuit 102 is also used to receive the refresh window signal WIN_REF. Specifically, the mode switching control circuit 102 includes: a first OR logic circuit 401, a first input terminal for receiving a refresh mode indication signal MR4_OP <4> _1, the second delay circuit 402, the input end is connected to the output end of the first OR logic circuit 401, the latch, the input end of the latch is connected to the output end of the first delay circuit 401, the control end is used to receive the refresh window signal WIN_REF, and the output end is used to output the refresh operation indication signal MR4_OP <4> _1.

[0058] The refresh window signal WIN_REF is a refresh window opened by the memory based on each full array refresh command CMD_REFab, and corresponding memory cells are opened in the refresh window to perform a refresh operation of the memory.

[0059] refer to Figure 7In one example, the latch can be implemented based on a D latch 403. Specifically, the input terminal D of the D latch 403 is connected to the output terminal of the first delay circuit 401, and the output terminal Q is used to output the refresh operation indication signal MR4_OP. <4> _1, the control end CK, i.e., the control end of the latch, is used to receive the refresh window signal WIN_REF, and the control end CK of the D latch 403 is configured to output the signal of the input end D from the output end Q based on the low-level refresh window signal WIN_REF (i.e., after the current refresh operation is completed), that is, when the memory completes the refresh operation and the refresh window signal WIN_REF jumps to a low level, based on the extended refresh mode indication signal received at the input end D (at this time, the extended refresh mode indication signal has been set to a low level based on the current full array refresh command REFab), the output refresh operation indication signal MR4_OP is set to a low level. <4> _1 level flips.

[0060] for Figure 7 Example, how it works refer to Figure 8 The output signal A of the first OR logic circuit 401 generates an output signal B after the first delay 402, and the output signal B is used as the input signal of the D latch 403. The output signal B received by the input terminal D is sampled based on the low-level refresh window signal WIN_REF to generate the refresh operation indication signal MR4_OP <4> _1, at this time, the refresh operation execution signal MR4_OP <4> The high level time of _1 covers the refresh window signal WIN_REF opened by the additional (next) full array refresh command CMD_REFab, so as to realize the fine-grained refresh of the memory based on the additional (next) full array refresh command CMD_REFab; in addition, based on the low level refresh window signal WIN_REF sampling output signal B to make the refresh operation indication signal MR4_OP <4> The level of _1 is flipped, making the time of t12 mentioned above controllable.

[0061] It should be noted that for Figure 7 For example, the delay time t2 of the first delay circuit 402 needs to be set to be greater than the delay time between the additional (next) full array refresh command CMD_REFab and its corresponding refresh window signal WIN_REF, so as to ensure that the output signal B remains at a high level before the corresponding refresh window signal WIN_REF is at a valid level (high level); in addition, the delay time t2 can also be set to be no greater than the refresh time of the memory based on the next full array refresh command CMD_REFab, that is, any value of the valid time of the refresh window signal WIN_REF.

[0062] In some embodiments, the refresh control circuit 100 is also used to control the refresh of the memory when the same array refresh mode switches to the normal refresh mode.

[0063] Specifically, refer to Fig. 9 The switching identification signal generating circuit 101 is also used to receive the same array refresh identification signal REFsb_CNT. For the same array refresh identification signal REFsb_CNT, when the memory to which it belongs performs a refresh operation based on the same array refresh command CMD_REFsb, and each time the last array in the storage array group performs a refresh, a same array refresh identification signal REFsb_CNT is generated, that is, the same array refresh identification signal REFsb_CNT indicates that the memory completes a refresh of the entire array in the same array refresh mode.

[0064] The switch identification signal generating circuit 101 is configured to, when the refresh operation indication signal MR4_OP <4> _1 indicates that the memory is in the fine-grained refresh mode, the same array refresh identification signal REFsb_CNT received by the memory during the fine-grained refresh mode is counted, and when the count value of the same array refresh identification signal is an odd number, a switching control identification FGR_CMD_ODD at a valid level is generated and output.

[0065] The function of the mode control circuit 102 is the same as Figure 1 The function of the mode control circuit 102 is described in detail above and will not be described in detail in this embodiment.

[0066] Specific reference Fig.11During the normal refresh operation of the memory, the refresh operation indication signal MR4_OP <4> _1 and the refresh mode indication signal MR4_OP <4> _0 has the same value, and based on the background technology, it can be known that before the memory switches from the fine-grained refresh mode to the normal mode, it is recommended that the same array refresh command CMD_REFsb issued by the storage controller is an even array (that is, the number of the same array refresh identification signal REFsb_CNT is an even number), and the refresh mode switching of the memory is executed normally at this time; when the same array refresh command CMD_REFsb issued by the storage controller is an odd array (that is, the number of the same array refresh identification signal REFsb_CNT is an odd number), before the refresh mode of the memory is changed, the storage controller will issue an additional full array refresh command CMD_REFab, and the identification generation circuit 101 generates a switching control identification FGR_CMD_ODD at a valid level based on the odd number of the same array refresh identification signal REFsb_CNT, and the switching control identification FGR_CMD_ODD at a valid level will refresh the mode indication signal MR4_OP <4> The level of MR4_OP is extended to generate the refresh operation indication signal MR4_OP. <4> _1, wherein the specific delay duration is t3, t3 includes the time when the switching control flag FGR_CMD_ODD is at an effective level and the refresh time based on the memory based on the next full array refresh command CMD_REFab, so that when the memory controller issues an additional full array refresh command CMD_REFab, the refresh operation indication signal MR4_OP of the memory <4> _1 indicates that the memory performs fine-grained refresh; at this time, the memory performs fine-grained refresh based on the additional full array refresh command CMD_REFab, so that the full array refresh command CMD_REFab and the same array refresh command CMD_REFsb group executed by the memory in the fine-grained refresh mode are even numbers, and then the refresh mode switching of the memory is performed normally. It can be seen that this embodiment uses the additional full array refresh command CMD_REFab as the full array refresh command CMD_REFab in the fine-grained refresh mode to perform a refresh operation, so that the full array refresh command CMD_REFab and the same array refresh command CMD_REFsb group executed by the memory in the fine-grained refresh mode are even numbers, thereby better maintaining the frequent switching of the memory between different refresh modes and avoiding the waste of refresh resources of the memory caused by the additional full array refresh command.

[0067] for Fig. 9 The switching identification signal generating circuit shown in FIG. Fig.10The identification signal generating circuit 101 includes: a first AND logic circuit 201, a first input terminal for receiving a refresh operation indication signal MR4_OP <4> _1, the second input end is used to receive the full array refresh command CMD_REFab. The second OR logic circuit 202, the first input end is connected to the output end of the first AND logic circuit 201, the second input end is used to receive the same array refresh identification signal REFsb_CNT, and the output end is used to output the counting identification MR4_OP_OR. The counting module 203 is configured to receive the counting identification MR4_OP_OR and count based on the counting identification to generate a counting result, and when the counting result is an odd number, generate and output a valid switching control identification FGR_CMD_ODD.

[0068] In one example, refer to Figure 4 The counting module 203 can be set based on the first trigger 204. Specifically, the clock terminal CK of the first trigger 204 is used to receive the counting mark MR4_OP_OR, the input terminal D is connected to the inverting output terminal Q-, and the output terminal Q is used to output the switching control mark FGR_CMD_ODD. In the initial state, the switching control mark FGR_CMD_ODD output by the first trigger 204 is in an invalid state.

[0069] As for the working principle of the first trigger 204, specifically, the count mark MR4_OP_OR received by the clock end is at the effective edge, that is, when the memory performs fine-grained refresh, it receives the full array refresh command CMD_REFab, and the first trigger 204 outputs based on the input data. When the input data of the input terminal D is "0", the output terminal Q output switching control mark FGR_CMD_ODD is "0", and the output data of the inverting output terminal Q-connected to the input terminal is "1"; when the input data of the input terminal D is "1", the output terminal Q output switching control mark FGR_CMD_ODD is "0", and the output data of the inverting output terminal Q-connected to the input terminal is "1"; when the input data of the input terminal D is "1", the output terminal Q output switching control mark FGR_CMD_ODD is "0", and the output data of the inverting output terminal Q-connected to the input terminal is "1". _ODD is "1", and the output data of the inverting output terminal Q-connected to the input terminal is "0", that is, the switching control flag FGR_CMD_ODD output by the first trigger 204 realizes the jump between "0" and "1" based on the effective edge of the input signal MR4_OP_OR of the clock terminal CK, and when the control receives the full array refresh command CMD_REFab as an odd number, the switching control flag FGR_CMD_ODD output by the first trigger 204 is "1", thereby realizing the counting of the full array refresh command CMD_REFab received when performing fine-grained refresh on the memory.

[0070] The functions of the first AND logic circuit 201 and the counting module 203 are as follows: Figure 3 The examples are the same, and this embodiment will not be repeated. Fig.10The example implements the common counting of the full array refresh command CMD_REFab and the same array refresh identification signal REFsb_CNT through the OR logic circuit 202, so that the full array refresh command CMD_REFab and the same array refresh command CMD_REFsb group executed by the memory in the fine-grained refresh mode are even.

[0071] Based on the above, it can be known that the switch control flag FGR_CMD_ODD at the effective level will refresh the mode indication signal MR4_OP <4> The level of MR4_OP is extended to generate the refresh operation indication signal MR4_OP. <4> _1, wherein the specific delay duration is t1, t1=t31+t32, t31 is the refresh mode indication signal MR4_OP <4> _0 indicates the time during which the switching control flag FGR_CMD_ODD remains at a valid level after the memory is switched to the normal refresh mode, and t32 is the refresh time of the memory based on the next full array refresh command CMD_REFab.

[0072] In some embodiments, the delay circuit and the refresh control circuit are greatly affected by PVT (process, voltage, temperature) factors. The delay time of a single delay unit in different memories is different, and the pulse width time of the refresh window signal generated by the refresh control circuit is also different. Therefore, the time of t32 cannot be accurately controlled; in addition, the execution time of the refresh operation corresponding to different refresh modes is also different (based on the fact that each refresh command can select to perform one or more refresh operations according to the refresh mode, the execution time of the corresponding refresh operation in different modes is also different), so the time of t32 is uncontrollable. If the time set for t32 is very short, it cannot completely cover the refresh operation window corresponding to the next refresh command. If the time set for t32 is very long, it may increase the power consumption of the circuit and may even cover the next multiple refresh commands. On this basis, the mode switching control circuit 102 is also configured to output the refresh operation indication signal MR4_OP when the fine-grained refresh operation executed based on the next full-array refresh command is completed. <4> _1 level flip, that is, refresh operation indication signal MR4_OP <4> _1 will instruct the memory to perform a normal refresh operation and the memory's refresh mode change is complete.

[0073] Specifically, refer to Fig.12The mode switching circuit 102 is also used to receive the refresh window signal WIN_REF. Specifically, the mode switching control circuit 102 includes: a first OR logic circuit 401, a first input terminal for receiving a refresh mode indication signal MR4_OP <4> _1, the second delay circuit 402, the input end is connected to the output end of the first OR logic circuit 401, the latch, the input end of the latch is connected to the output end of the first delay circuit 401, the control end is used to receive the refresh window signal WIN_REF, and the output end is used to output the refresh operation indication signal MR4_OP <4> _1.

[0074] refer to Figure 7 In one example, the latch can be implemented based on a D latch 403. Specifically, the input terminal D of the D latch 403 is connected to the output terminal of the first delay circuit 401, and the output terminal Q is used to output the refresh operation indication signal MR4_OP. <4> _1, the control terminal CK, i.e., the control terminal of the latch, is used to receive the refresh window signal WIN_REF, and the control terminal CK of the D latch 403 is configured to output the signal of the input terminal D from the output terminal Q based on the low-level refresh window signal WIN_REF (i.e., after the current refresh operation is completed), that is, when the memory completes the refresh operation and the refresh window signal WIN_REF jumps to a low level, based on the extended refresh mode indication signal received at the input terminal D (at this time, the extended refresh mode indication signal has been set to a low level based on the current full array refresh command REFab), the output refresh operation indication signal MR4_OP is set to a low level. <4> _1 level flips.

[0075] for Fig.12 Example, how it works refer to Fig.13 , based on the low-level refresh window signal WIN_REF, the received signal of the sampling input terminal D is generated to generate the refresh operation indication signal MR4_OP <4> _1, at this time, the refresh operation execution signal MR4_OP <4> The high level time of _1 covers the refresh window signal WIN_REF opened by the additional (next) full array refresh command CMD_REFab, so as to realize the fine-grained refresh of the memory based on the additional (next) full array refresh command CMD_REFab; in addition, the output signal B is sampled based on the low level refresh window signal WIN_REF to trigger the refresh operation indication signal MR4_OP <4> The level of _1 is flipped, making the time of t32 mentioned above controllable.

[0076] In some embodiments, the refresh control circuit 100 further includes: a refresh identification signal generating circuit, configured to generate the same array refresh identification signal REFsb_CNT.

[0077] In one example, refer to Fig.14The refresh identification signal generating circuit 103 includes: N latches 301, N is the number of storage arrays in each storage array group in the memory, and the N latches 301 are set in one-to-one correspondence with the N storage arrays in each storage array group, and the set end of each latch 301 is used to receive the same array refresh command CMD_REFsb corresponding to the corresponding storage array, and the output end of each latch 301 is used to output the corresponding array refresh identification signal WIN_SB_REF. The second AND logic circuit 302 includes N input ends, and the N input ends are connected to the output ends of the N latches 301 in one-to-one correspondence, and the output end is used to output the same array refresh identification signal REFsb_CNT. The second delay circuit 303 has an input end for receiving the same array refresh identification signal REFsb_CNT, and an output end connected to the input end of the first inverter 304. The output end of the first inverter 304 is used to output the reset control signal REFsb_CNT_PULL, and the reset end of each latch is coupled to the output end of the first inverter.

[0078] refer to Figure 14 to Figure 16 For the memory, each memory includes M memory array groups (BankGroup), each memory array group (BankGroup) includes N memory arrays (Bank), that is, each memory includes M*N memory arrays. In addition, Fig.14 The example is illustrated by taking the example that each storage array group includes 4 storage arrays (storage array A, storage array B, storage array C and storage array D) to help those skilled in the art understand the technical solution of the present disclosure, and does not constitute a limitation of this embodiment.

[0079] The set end of latch S1 is used to receive the same array refresh command CMD_REFsb corresponding to storage array A <0> The reset terminal is used to receive the reset control signal REFsb_CNT_PULL, and the output terminal is used to output the array refresh identification signal WIN_SB_REF0. The set terminal of latch S2 is used to receive the same array refresh command CMD_REFsb corresponding to the storage array B. <1> The reset terminal is used to receive the reset control signal REFsb_CNT_PULL, and the output terminal is used to output the array refresh identification signal WIN_SB_REF1. The set terminal of latch S3 is used to receive the same array refresh command CMD_REFsb corresponding to the storage array C. <2> The reset terminal is used to receive the reset control signal REFsb_CNT_PULL, and the output terminal is used to output the array refresh identification signal WIN_SB_REF2. The set terminal of latch S4 is used to receive the same array refresh command CMD_REFsb corresponding to the storage array D. <3> The reset end is used to receive the reset control signal REFsb_CNT_PULL, and the output end is used to output the array refresh identification signal WIN_SB_REF3.

[0080] For each latch 301, in one example, the latch 301 is implemented based on an SR latch, specifically, refer to Fig.15 , the latch 301 includes: a first or-not logic circuit 310, the first input end is used as the set end of the latch 301, for receiving the same array refresh command CMD_REFsb corresponding to the corresponding storage array, the second input end is connected to the output end of the second or-not logic circuit 320, and the output end is connected to the first input end of the second or-not logic circuit 320; the second input end of the second or-not logic circuit 320 is used as the reset end of the latch 301, connected to the output end of the second inverter 330, the input end of the second inverter is used to receive the reset control signal REFsb_CNT_PULL, and the output end is used as the output end of the latch 301, for outputting the corresponding array refresh identification signal WIN_SB_REF. It should be noted that, Fig.15 The signal flow of latch S1 is illustrated as an example, and those skilled in the art may replace it with the signal flow of latch S2, latch S3 or latch S4 accordingly.

[0081] It should also be noted that in other embodiments, the latch can also be implemented based on the RS latch. Those skilled in the art can Fig.15 The connection mode of the latch 301 is modified in the example, and if the effect is not different from that of the present embodiment, it should all fall within the protection scope of the present disclosure.

[0082] refer to Fig.16 , the latch 301 sets the output terminal based on the same array refresh command CMD_REFsb to generate the corresponding array refresh identification signal WIN_SB_REF, a single same array refresh command CMD_REFsb is used to refresh the same storage array of all storage array groups, and completing the refresh of the same storage array group requires 4 corresponding same array refresh commands CMD_REFsb to complete 4 refreshes, when the last storage array is refreshed, the same array refresh identification signal REFsb_CNT output by the second AND logic circuit 302 is set to "1", after the second After the delay circuit 303 delays t4, the reset control signal REFsb_CNT_PULL output by the first inverter is set to "0", and the reset control signal REFsb_CNT_PULL feedback controls the latch 301 to set the corresponding array refresh identification signal WIN_SB_REF to "0", and the same array refresh identification signal REFsb_CNT output by the second AND logic circuit 302 is set to "0", that is, the memory completes the refresh of a storage array group, and the refresh identification signal generating circuit 103 generates a valid pulse of the same array refresh identification signal REFsb_CNT. Among them, the delay t4 of the second delay circuit 303 can be set to any value.

[0083] In addition, the same array refresh identification signal REFsb_CNT must complete the refresh of a storage array group for the memory. In order to prevent the refresh mode change from interfering with the generation of the same array refresh identification signal REFsb_CNT, in some embodiments, the reference Fig.17 , the refresh identification signal generating circuit 103 further includes: a third OR logic circuit 304, a first input end for receiving the full array refresh command CMD_REFab, and a second input end for receiving the self-refresh command CMD_SREF; a third AND logic circuit 305, a first input end connected to the output end of the third OR logic circuit 304, a second input end for receiving the reset control signal REFsb_CNT_PULL, and an output end connected to the reset end of each latch 301. That is, if the memory changes the refresh mode during the process of refreshing based on the same array refresh command CMD_REFsb, the refresh identification signal generating circuit 103 directly resets the latch 301 based on the self-refresh command CMD_SREF and the full array refresh command CMD_REFab, thereby not generating the same array refresh identification signal REFsb_CNT, so as to ensure that the memory completes the refresh of a storage array group before generating the same array refresh identification signal REFsb_CNT.

[0084] In this embodiment, the additional (next) full array refresh command CMD_REFab is used as the full array refresh command CMD_REFab in the fine-grained refresh mode for refresh operation, so that the full array refresh command CMD_REFab executed by the memory in the fine-grained refresh mode and the same array refresh command CMD_REFsb group are even numbers, thereby better maintaining the frequent switching of the memory between different refresh modes and avoiding the waste of memory refresh resources caused by the additional full array refresh command.

[0085] It should be noted that the features disclosed in the refresh control circuit provided in the above embodiments can be arbitrarily combined without conflict to obtain a new refresh control circuit embodiment.

[0086] Another embodiment of the present disclosure provides a memory, including the refresh control circuit provided in the above embodiment, so as to use the additional (next) full array refresh command as the full array refresh command in the fine-grained refresh mode to perform a refresh operation, so that the full array refresh commands executed by the memory in the fine-grained refresh mode are even, thereby better maintaining the frequent switching of the memory between different refresh modes and avoiding the waste of refresh resources of the memory caused by the additional full array refresh command.

[0087] Specific reference Figure 2During the normal refresh operation of the memory, the refresh operation indication signal MR4_OP <4> _1 and the refresh mode indication signal MR4_OP <4> _0 is the same, and based on the background technology, it can be known that before the memory switches from the fine-grained refresh mode to the normal mode, it is recommended that the full array refresh command CMD_REFab issued by the storage controller is an even number, and the refresh mode switching of the memory is performed normally at this time; when the full array refresh command CMD_REFab issued by the storage controller is an odd number, at this time, before the refresh mode of the memory is changed, the storage controller will issue an additional full array refresh command CMD_REFab, and the identification generating circuit 101 generates a switching control identification FGR_CMD_ODD at a valid level based on the odd number of full array refresh commands CMD_REFab, and the switching control identification FGR_CMD_ODD at a valid level will refresh the mode indication signal MR4_OP <4> The level of MR4_OP is extended to generate the refresh operation indication signal MR4_OP. <4> _1, wherein the specific delay duration is t1, t1 includes the time when the switching control flag FGR_CMD_ODD is at an effective level and the signal transmission delay, so that when the memory controller issues the next full array refresh command CMD_REFab, the memory refresh operation indication signal MR4_OP <4> _1 indicates that the memory performs fine-grained refresh; at this time, the memory performs fine-grained refresh based on the additional full array refresh command CMD_REFab, so that the full array refresh command CMD_REFab executed by the memory in the fine-grained refresh mode is an even number, and then the refresh mode switching of the memory is performed normally. It can be seen that in this embodiment, by using the additional full array refresh command CMD_REFab as the full array refresh command CMD_REFab in the fine-grained refresh mode for refresh operation, the full array refresh command CMD_REFab executed by the memory in the fine-grained refresh mode is an even number, thereby better maintaining the frequent switching of the memory between different refresh modes and avoiding the waste of refresh resources of the memory caused by the additional full array refresh command.

[0088] Specific reference Fig.10During the normal refresh operation of the memory, the refresh operation indication signal MR4_OP <4> _1 and the refresh mode indication signal MR4_OP <4> _0 has the same value, and based on the background technology, it can be known that before the memory switches from the fine-grained refresh mode to the normal mode, it is recommended that the same array refresh command CMD_REFsb issued by the storage controller is an even array (that is, the number of the same array refresh identification signal REFsb_CNT is an even number), and the refresh mode switching of the memory is executed normally at this time; when the same array refresh command CMD_REFsb issued by the storage controller is an odd array (that is, the number of the same array refresh identification signal REFsb_CNT is an odd number), before the refresh mode of the memory is changed, the storage controller will issue an additional full array refresh command CMD_REFab, and the identification generation circuit 101 generates a switching control identification FGR_CMD_ODD at a valid level based on the odd number of the same array refresh identification signal REFsb_CNT, and the switching control identification FGR_CMD_ODD at a valid level will refresh the mode indication signal MR4_OP <4> The level of MR4_OP is extended to generate the refresh operation indication signal MR4_OP. <4> _1, wherein the specific delay duration is t3, t3 includes the time when the switching control flag FGR_CMD_ODD is at an effective level and the refresh time based on the memory based on the next full array refresh command CMD_REFab, so that when the memory controller issues an additional full array refresh command CMD_REFab, the refresh operation indication signal MR4_OP of the memory <4> _1 indicates that the memory performs fine-grained refresh; at this time, the memory performs fine-grained refresh based on the additional full array refresh command CMD_REFab, so that the full array refresh command CMD_REFab and the same array refresh command CMD_REFsb group executed by the memory in the fine-grained refresh mode are even numbers, and then the refresh mode switching of the memory is performed normally. It can be seen that this embodiment uses the additional full array refresh command CMD_REFab as the full array refresh command CMD_REFab in the fine-grained refresh mode to perform a refresh operation, so that the full array refresh command CMD_REFab and the same array refresh command CMD_REFsb group executed by the memory in the fine-grained refresh mode are even numbers, thereby better maintaining the frequent switching of the memory between different refresh modes and avoiding the waste of refresh resources of the memory caused by the additional full array refresh command.

[0089] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present disclosure, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present disclosure.

Claims

1. A refresh control circuit, characterized in that: include: A switching identification signal generating circuit receives a refresh operation indication signal and a full array refresh command, wherein the refresh operation indication signal indicates that the memory to which it belongs performs a normal refresh or a fine-grained refresh; The switching flag signal generating circuit is configured to, when the refresh operation indication signal indicates that the memory is in the fine-grained refresh mode, count the full array refresh commands received by the memory during the fine-grained refresh mode, and when the count value of the full array refresh command is an odd number, generate and output a switching control flag at a valid level; a mode switching control circuit, coupled to the switching identification signal generating circuit, receiving the refresh mode indication signal and the switching control identification, and generating and outputting the refresh operation indication signal based on the refresh mode indication signal and the switching control identification; wherein the refresh mode indication signal indicates that the memory is currently in the normal refresh mode or in the fine-grained refresh mode; The mode switching control circuit is configured to, when the refresh mode indication signal instructs the memory to switch to the normal refresh mode, maintain the level of the output refresh operation indication signal unchanged if the switching control signal is at a valid level, so as to instruct the memory to continue to perform fine-grained refresh based on the next full array refresh command.

2. The refresh control circuit according to claim 1, characterized in that: The switching identification signal generating circuit comprises: A first AND logic circuit, having a first input terminal for receiving the refresh operation indication signal and a second input terminal for receiving the full array refresh command, configured to generate and output a counting identifier based on the full array refresh command when the refresh operation indication signal indicates that the memory to which it belongs performs a fine-grained refresh; The counting module is configured to receive the counting identifier and perform counting based on the counting identifier to generate a counting result, and when the counting result is an odd number, generate and output a valid switching control identifier.

3. The refresh control circuit according to claim 1, characterized in that: The mode switching control circuit comprises: A first OR logic circuit, wherein the first input terminal is used to receive the refresh mode indication signal, and the second input terminal is used to receive the switching control identifier; The first delay circuit has an input end connected to the output end of the first OR logic circuit, and an output end used to output the refresh operation indication signal.

4. The refresh control circuit according to claim 1, characterized in that: The mode switching control circuit is further configured to flip the level of the output refresh operation indication signal when the fine-grained refresh operation executed based on the next full-array refresh command is completed.

5. The refresh control circuit according to claim 4, characterized in that: The mode switching control circuit comprises: A first OR logic circuit, wherein the first input terminal is used to receive the refresh mode indication signal, and the second input terminal is used to receive the switching control identifier; A first delay circuit, an input end of which is connected to the output end of the first OR logic circuit; A latch, wherein the input end is connected to the output end of the first delay circuit, the control end is used to receive the refresh window signal, and the output end is used to output the refresh operation indication signal.

6. The refresh control circuit according to claim 1, characterized in that: include: The switching identification signal generating circuit is further used to receive a same array refresh identification signal, wherein the same array refresh identification signal is generated when the corresponding memory performs a refresh operation based on the same array refresh command and each time the last array in the storage array group performs a refresh; The switching identification signal generating circuit is configured to, when the refresh operation indication signal indicates that the memory is in the fine-grained refresh mode, count the same array refresh identification signals received by the memory during the fine-grained refresh mode, and when the count value of the same array refresh identification signal is an odd number, generate and output the switching control identification at a valid level.

7. The refresh control circuit according to claim 6, characterized in that: The switching identification signal generating circuit comprises: A first AND logic circuit, wherein the first input terminal is used to receive the refresh operation indication signal, and the second input terminal is used to receive the full array refresh command; A second OR logic circuit, wherein the first input end is connected to the output end of the first AND logic circuit, the second input end is used to receive the same array refresh identification signal, and the output end is used to output a counting identification; The counting module is configured to receive the counting identifier and perform counting based on the counting identifier to generate a counting result, and when the counting result is an odd number, generate and output a valid switching control identifier.

8. The refresh control circuit according to claim 2 or 7, characterized in that: The counting module includes: a first trigger, a clock end for receiving the counting mark, an input end connected to an inverting output end, an output end for outputting the switching control mark, and in an initial state, the switching control mark output by the first trigger is at an invalid level.

9. The refresh control circuit according to claim 6, characterized in that: Also includes: The refresh identification signal generating circuit is used to generate the same array refresh identification signal.

10. The refresh control circuit according to claim 9, characterized in that: The refresh identification signal generating circuit comprises: N latches, N being the number of storage arrays in each storage array group in the memory, and the N latches being arranged in one-to-one correspondence with the N storage arrays in each storage array group, the set end of each latch being used to receive the same array refresh command corresponding to the corresponding storage array, and the output end of each latch being used to output a corresponding array refresh identification signal; A second AND logic circuit includes N input terminals, and the N input terminals are connected to the output terminals of the N latches in a one-to-one correspondence, and the output terminal is used to output the same array refresh identification signal; A second delay circuit, whose input end is used to receive the same array refresh identification signal, and whose output end is connected to the input end of the first inverter; The output terminal of the first inverter is used to output a reset control signal, and the reset terminal of each latch is coupled to the output terminal of the first inverter.

11. The refresh control circuit according to claim 10, characterized in that: The latch comprises: A first OR logic circuit, wherein the first input terminal is used as the set terminal of the latch and is used to receive the same array refresh command corresponding to the corresponding storage array, the second input terminal is connected to the output terminal of the second OR logic circuit, and the output terminal is connected to the first input terminal of the second OR logic circuit; The second input end of the second OR-NOT logic circuit serves as the reset end of the latch and is connected to the output end of the second inverter. The input end of the second inverter is used to receive the reset control signal, and the output end serves as the output end of the latch and is used to output the corresponding array refresh identification signal.

12. The refresh control circuit according to claim 10, characterized in that: The refresh identification signal generating circuit further includes: A third NOR logic circuit, wherein the first input terminal is used to receive the full array refresh command, and the second input terminal is used to receive a self-refresh command; The third AND logic circuit has a first input terminal connected to the output terminal of the third OR logic circuit, a second input terminal for receiving the reset control signal, and an output terminal connected to the reset terminal of each latch.

13. A memory, characterized in that: The refresh control circuit comprises the refresh control circuit according to any one of claims 1 to 12.

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