Signal processing method based on memristor array and related equipment

Abstract

One or more embodiments of the invention provide a memristor array-based signal processing method and related equipment. The method comprises the following steps: mapping an input signal into an input voltage signal, and inputting the input voltage signal into a mapped memristor array; the mapped memristor array obtains an output current based on the input voltage signal; wherein the mapped memristor array is obtained through the following steps that a discrete Fourier transform expression X = WNx for signal conversion is determined, x represents an input signal, X represents an output signal, and WN represents a twiddle factor; converting the expression into a complex matrix vector multiplication expression; # imgabs0 # imgabs1 # Re () represents a real part of the complex number, and Im () represents an imaginary part of the complex number; and mapping the operation matrix # imgabS2 < 2 > to the memristor array to obtain the memristor array after mapping. According to the invention, the operation efficiency of the DFT module or the IDFT module can be improved, and the signal processing efficiency is further improved.

Description

Technical Field

[0001] One or more embodiments of the present application relate to the technical field of signal analysis and signal processing, and in particular, to a signal processing method based on a memristor array and related equipment. Background Art

[0002] With the introduction of massive antennas and the increase in RF bandwidth, the energy efficiency of baseband signal processing has become one of the key challenges in 5G / 6G systems. Orthogonal Frequency Division Multiplexing (OFDM) technology is an important part of the physical layer and is the standard modulation choice for 5G NR systems, and will continue to be used in 6G. In OFDM, the Discrete Fourier Transform (DFT) is the module that consumes the most resources because it needs to continuously process the spectrum of the entire working band. Currently, the bandwidth of 5G has reached 400MHz, and the bandwidth will be higher in the future 6G. The complexity and high computational latency of DFT have become the main limiting factors for the development of high-speed, low-latency communications.

[0003] Fast Fourier Transform (FFT), as an efficient algorithm for DFT, significantly improves the calculation speed. However, as the number of calculation points increases, the implementation of Cooley-Tukey algorithm, one of the most commonly used methods in Fast Fourier Transform (FFT), will face scalability challenges. Although related technologies propose to use hardware acceleration platforms (such as graphics processing units, graphics processing units, and field programmable gate arrays, field programmable gate arrays, etc.) to accelerate FFT calculations, these platforms may also bring energy consumption and delay problems during calculations. Summary of the invention

[0004] In view of this, an object of one or more embodiments of the present application is to provide a signal processing method based on a memristor array and related devices to solve the problems of the background technology.

[0005] Based on the above objectives, one or more embodiments of the present application provide a signal processing method based on a memristor array, including:

[0006] Mapping an input signal into an input voltage signal, and inputting the input voltage signal into the mapped memristor array;

[0007] The mapped memristor array obtains an output current based on the input voltage signal;

[0008] The mapped memristor array is obtained by the following steps:

[0009] Determine the discrete Fourier transform expression of the signal conversion X = W N x, x represents the input signal, X represents the output signal, W N represents the rotation factor;

[0010] Convert it into a complex matrix-vector multiplication expression;

[0011]

[0012] Re() represents the real part of a complex number, and Im() represents the imaginary part of a complex number;

[0013] The operation matrix Mapping to the memristor array to obtain the mapped memristor array.

[0014] Optionally, the operation matrix G X Mapping to the memristor array, comprising:

[0015] According to the operation matrix The calculated value of the element in is used to calculate the conductance value of the memristor in the memristor array by the following formula;

[0016]

[0017] Wherein, B represents the conductance value array of the memristor array, λ1 represents a scaling factor, which is used to map the operation matrix into the memristor conductance range, Φ represents a moving matrix, which is used to indicate the moving distance of each element in the operation matrix. B max and B min represents the conductance value range of the memristor in the memristor array, G max and G min Indicates the maximum and minimum element values ​​of the operation matrix.

[0018] Optionally, the input signal includes a time domain signal or a frequency domain signal.

[0019] Optionally, mapping the input signal to an input voltage signal includes:

[0020] According to the input signal, the input voltage signal is obtained by the following formula;

[0021]

[0022] Wherein, x represents the input signal, λ2 represents the mapping scale factor, and N represents the numerical range of the input signal.

[0023] Optionally, the mapped memristor array obtains an output current based on the input voltage signal, comprising:

[0024] The mapped memristor array obtains the output current based on the input voltage signal through the following formula;

[0025]

[0026] Optionally, mapping the input signal to an input voltage signal includes:

[0027] According to the input signal, the input voltage signal is obtained by the following formula;

[0028] V in =λ2(xx min );

[0029] Among them, x min Indicates the minimum value of the input voltage.

[0030] Optionally, the mapped memristor array obtains an output current based on the input voltage signal, comprising:

[0031] The mapped memristor array obtains the output current based on the input voltage signal through the following formula;

[0032]

[0033] Optionally, mapping the input signal to an input voltage signal includes:

[0034] Equalizing the input signal using a contraction coefficient to obtain an equalized input signal;

[0035] Mapping the equalized input signal into an input voltage signal;

[0036] The shrinkage coefficient is obtained by the following steps:

[0037] receiving a pilot signal;

[0038] According to the pilot signal, the contraction coefficient is calculated by the following formula, wherein the contraction coefficient includes a horizontal axis contraction coefficient and a vertical axis contraction coefficient;

[0039]

[0040] Among them, e I represents the horizontal axis contraction coefficient, e Q represents the vertical axis contraction coefficient, i represents the number of known pilot points, j represents the number of pilot signals received by each known pilot point, and s i,Irepresents the I-axis coordinate of the i-th sample of the known pilot point received by the receiver, s i,Q represents the Q-axis coordinate of the i-th sample of the known pilot point received by the receiving end, a represents the correct I-axis coordinate of the known pilot point, and c represents the correct Q-axis coordinate of the known pilot point.

[0041] Based on the same inventive concept, one or more embodiments of the present application further provide a signal processing device based on a memristor array, comprising:

[0042] A first mapping module, used for mapping an input signal into an input voltage signal, and inputting the input voltage signal into the mapped memristor array;

[0043] The mapped memristor array is used to obtain an output current based on the input voltage signal;

[0044] The mapped memristor array is obtained by the following steps:

[0045] Determine the discrete Fourier transform expression of the signal conversion X = W N x, x represents the input signal, X represents the output signal, W N represents the rotation factor;

[0046] Convert it into a complex matrix-vector multiplication expression;

[0047]

[0048] Re() represents the real part of a complex number, and Im() represents the imaginary part of a complex number;

[0049] The operation matrix Mapping to the memristor array to obtain the mapped memristor array.

[0050] Optionally, it also includes:

[0051] A signal conversion module, used for converting the output current into a voltage signal;

[0052] The signal output module is used to modulate the voltage signal into an output voltage signal.

[0053] From the above description, it can be seen that the signal processing method based on the memristor array provided by one or more embodiments of the present application maps the input signal into an input voltage signal, and inputs the input voltage signal into the mapped memristor array; the mapped memristor array obtains the output current based on the input voltage signal. The mapped memristor array is obtained by the following steps: Determine the discrete Fourier transform expression X=W for signal conversion N x, x represents the input signal, X represents the output signal, W Nrepresents the rotation factor; convert it into a complex matrix-vector multiplication expression; Re() represents the real part of the complex number, Im() represents the imaginary part of the complex number; the operation matrix Mapping to the memristor array to obtain a mapped memristor array.

[0054] The technical solution provided by one or more embodiments of the present application converts the calculation expression of DFT into the expression form of complex matrix-vector multiplication, converts the rotation factors of DFT into operation matrices and maps them to the memristor array, fully utilizes the matrix operation capability of the memristor array, integrates the memristor module circuit, so as to improve the operation efficiency of the DFT module and further improve the efficiency of signal processing.

[0055] A signal processing device based on a memristor array provided in the present application can implement the steps of the above-mentioned signal processing method based on a memristor array, and therefore also has the beneficial effects of the above-mentioned signal processing method based on a memristor array. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] In order to more clearly illustrate one or more embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only one or more embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0057] Figure 1 A flowchart of a signal processing method based on a memristor array according to one or more embodiments of the present application;

[0058] Figure 2 A schematic diagram of the structure of a signal processing device based on a memristor array according to one or more embodiments of the present application;

[0059] Figure 3 A schematic diagram of mapping pilot signals according to one or more embodiments of the present application;

[0060] Figure 4 A schematic diagram of a circuit structure of a computing unit based on a memristor array according to one or more embodiments of the present application;

[0061] Figure 5 A schematic diagram of the structure of a programmable memristor unit in one or more embodiments of the present application;

[0062] Figure 6 The overall circuit architecture embodiment of one or more DFT (or IDFT) devices of the present application;

[0063] Figure 7This is a schematic diagram of the hardware structure of one or more electronic devices for this application. DETAILED DESCRIPTION

[0064] In order to make the objectives, technical solutions and advantages of the present disclosure more clearly understood, the present disclosure is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0065] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in one or more embodiments of the present application should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in one or more embodiments of the present application do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0066] As described in the background technology section, improving the computational efficiency of DFT is a technical problem that needs to be solved urgently. However, no effective technical solution has been proposed in the related art.

[0067] Memristor (e.g., resistive random access memory, phase change memory, conductive bridge memory, etc.) is a non-volatile device whose conductivity state can be adjusted by applying external stimuli. As a two-terminal device, memristor has the characteristics of adjustable resistance and non-volatility, so it is widely used in storage and computing. According to Kirchhoff's current law and Ohm's law, an array composed of memristors can complete multiplication and accumulation calculations in parallel, and storage and calculation occur in each device in the array. Based on this computing architecture, storage and computing can be realized without the need for large amounts of data movement.

[0068] In the process of implementing the present disclosure, the applicant discovered that the memory computing architecture represented by the memristor array based on the crossbar switch has shown significant advantages in executing VMM operations and can be an ideal choice for solving the above-mentioned problems.

[0069] refer to Figure 1 The signal processing method based on the memristor array of one or more embodiments of the present application comprises the following steps:

[0070] Step S101: mapping an input signal into an input voltage signal, and inputting the input voltage signal into the mapped memristor array.

[0071] Step S102: the mapped memristor array obtains an output current based on the input voltage signal.

[0072] The mapped memristor array is obtained through the following steps:

[0073] Step S201: Determine the discrete Fourier transform expression X=W for signal conversion N x, x represents the input signal, X represents the output signal, W N represents the rotation factor.

[0074] Step S202: Convert it into a complex matrix-vector multiplication expression.

[0075]

[0076] Re() represents the real part of a complex number, and Im() represents the imaginary part of a complex number;

[0077] Step S203: Operation matrix Mapping to the above memristor array to obtain the memristor array after the above mapping.

[0078] The expression of DFT algorithm is:

[0079]

[0080] in, represents the rotation factor,

[0081] The matrix form of the above expression can be expressed as:

[0082] X=W N x;

[0083] in,

[0084] It is understandable that the larger the value of N, the larger the scale of the Fourier transform, which means that complex matrix operations are required. In traditional computer systems, matrix operations usually consume a lot of resources.

[0085] In the related technology, the FFT algorithm is mainly used for calculation. FFT is an efficient DFT algorithm, and its basic idea is to use the periodicity, symmetry and reducibility of the rotation factors to decompose the long sequence DFT operation into multiple short sequence DFT operations.

[0086] The calculation process of the FFT algorithm includes:

[0087] Extract every n points from a discrete signal sequence of length N to form n new sequences;

[0088]

[0089] in,

[0090] Substitute it into the expression of the DFT algorithm:

[0091]

[0092] After simplification, we can get:

[0093]

[0094] According to this formula, the N-point DFT is decomposed into n small-point DFTs with a point number of N / n according to the basis n. After calculation, n frequency domain sequences with a length of N / n are obtained, which are expressed as X1[m], X2[m],…, X n [m](m=0,1,2,…,N / n-1), the above formula can be rearranged as:

[0095]

[0096] make According to the periodicity of the rotation factor:

[0097]

[0098] You can get:

[0099]

[0100] The matrix expression of the above formula is:

[0101]

[0102] in X N is an n-dimensional column vector.

[0103] The operations from the second level to the nth level are the same as the above process.

[0104] Similarly, the IDFT algorithm expression is:

[0105]

[0106] The matrix form is:

[0107]

[0108] The calculation process is the same as that of DFT.

[0109] In order to reduce complex matrix operations, the related art uses the Cooley-Tukey algorithm and uses a butterfly operation with a base of 2 to avoid matrix multiplication operations. However, in the face of large-scale FFT operations, the number of levels increases significantly, requiring the circuit to have powerful data temporary storage and scheduling capabilities.

[0110] In the process of implementing the present application, the applicant found that the high-radix FFT operation can be divided into two parts: the smaller radix operation after the radix n decomposition and the radix synthesis operation. Both of these vector-matrix operations can be efficiently performed using a memristor cross array. The size of the decomposed radix depends on the size of the memristor array. Therefore, the applicant proposed to use a memristor array to implement the operation of the DFT module.

[0111] Considering that the input and output data types of the DFT module are both complex symbol combinations, the complex matrix-vector multiplication can be expressed as:

[0112]

[0113] Combined with the expression of complex matrix-vector multiplication, this application converts the algorithm expression of DFT into:

[0114]

[0115] Re() represents the real part of a complex number, and Im() represents the imaginary part of a complex number.

[0116] Through the above transformation, the rotation factors in the DFT algorithm can be mapped to the memristor array, realizing the integration of memristors and effectively utilizing the matrix computing capabilities of memristors, thereby improving the computational efficiency of the DFT module.

[0117] Due to the characteristics of the rotation factor, W N and The real parts of are the same, and the imaginary parts are opposite to each other. Since the rotation factor matrix is ​​a symmetric matrix, Therefore, the expression of the IDFT algorithm can be expressed as:

[0118]

[0119] It can be understood that the calculation of a signal sequence IDFT module can be regarded as the conjugate calculation of the signal sequence DFT module, and the forward transform and inverse transform of the Fourier transform can be performed in the same circuit calculation unit. It is easy for those skilled in the art to understand that the signal processing method based on the memristor array of the present application can be used for both DFT calculation and IDFT calculation.

[0120] In step S101, the input signal may be a time domain signal or a frequency domain signal. When the input signal is a time domain signal, the corresponding output signal is a frequency domain signal; when the input signal is a frequency domain signal, the corresponding output signal is a time domain signal.

[0121] According to the formula above In this step, the input signal x is mapped into a voltage signal. Specifically, in this application, the real part and the imaginary part of the input signal x are respectively mapped into voltage signals and then input into the memristor array in parallel.

[0122] The memristor array after mapping in step S101 is mapped with a matrix The matrix Related to the rotation factors. Considering that the rotation factors involved in each calculation are different, and the use of memristors for storage and calculation may result in a large amount of time and energy consumption due to frequent resistance changes, in an embodiment of the present application, a memory may be selected to store all basic rotation factors.

[0123] In the 1T1R (one transistor one resistor) structure of the memristor array, the drain current is controlled by the gate-source voltage to realize the switching function. The input numerical vector for matrix calculation has positive and negative values. If the positive voltage and the negative voltage correspond to the positive value and the negative value in the numerical matrix, respectively, the input voltage vector will be composed of the positive voltage and the negative voltage. In the embodiment of the present application, in order to avoid the confusion of the gate-source voltage, the input signal can be mapped to the positive voltage value.

[0124] Therefore, in the embodiment of the present application, when the input signal amplitude is known (such as the input signal of the transmitting end), the mapping relationship expression of the input voltage signal can be:

[0125]

[0126] Where x represents the input signal, λ2 represents the mapping scale factor, and N represents the numerical range of the input signal. In the embodiment of the present application, the input signal can be a numerical vector of length n. When the amplitude of the input signal is known, the amplitude range of the operation data is known, and it is mapped to the corresponding constellation point, and its amplitude range is positive and negative symmetric. In the above formula, add the numerical vector The purpose is to ensure that the value of the input vector remains non-negative.

[0127] In this case, the output current vector can be expressed as:

[0128]

[0129] The result of the matrix operation can be expressed as the output value of the current circuit:

[0130]

[0131] The result of the matrix operation is obtained by adding and subtracting the three components α, β, and γ. Among them, α is related to the output current and can be obtained by the gain All parameters in β are fixed values, where I is a unit vector, which is calculated every time the resistance of the memristor array changes; γ is composed of the sum of the input numerical vectors.

[0132] In the embodiment of the present application, when the input signal amplitude is unknown (such as the input signal at the receiving end), the mapping relationship expression of the input voltage signal can be:

[0133] V in =λ2(a n×1 -a min );

[0134] In this case, the output current vector can be expressed as:

[0135] I out,n×1 =λ1λ2[B n×n ·a n×1 -a min (B n×n +Φ)+Φa n×1 ];

[0136] The result of the matrix operation can be expressed as the output value of the current circuit:

[0137]

[0138] Considering that the non-ideality of memristor array calculation affects the performance of communication systems mainly because the constellation cluster shrinks toward the origin, resulting in an increase in bit error rate. The larger the mapping error of the memristor, the more obvious the impact on the performance of the communication system.

[0139] Therefore, in the embodiment of the present application, the applicant proposes a memristor array calculation equalization method based on Monte Carlo pilot to optimize system performance. Without considering the channel frequency selective fading, the transmitter adds the known Monte Carlo pilot to the frequency domain signal, and the receiver uses the Monte Carlo method to analyze the received pilot, calculate the shrinkage coefficient and equalize the other received data.

[0140] For the same known pilot signal, the received pilot signal will be distributed in a two-dimensional Gaussian distribution with the original pilot signal as the center after passing through the Gaussian channel. Figure 3 As shown in part (a), due to the non-ideality of the memristor array, the signal amplitude decreases and the constellation points shrink inward.

[0141] According to the Monte Carlo method, the in-phase component and the orthogonal component of the received pilot signal point are equalized respectively. Based on this, the average converged pilot signal point can be approximated, and its accuracy depends on the number of received pilot points, such as Figure 3 As shown in part (b).

[0142] Then, the shrinkage coefficient is obtained by averaging the ratio of the in-phase and quadrature components of the pilot signal, Figure 3 As shown in part (c), the pilot signal can be equalized by shrinking the coefficient. Its expression can be:

[0143]

[0144] Among them, e I represents the horizontal axis contraction coefficient, e Q represents the vertical axis contraction coefficient, i represents the number of known pilot points, j represents the number of pilot signals received by each known pilot point, and s i,I represents the I-axis coordinate of the i-th sample of the known pilot point received by the receiver, s i,Q represents the Q-axis coordinate of the i-th sample of the known pilot point received by the receiving end, a represents the correct I-axis coordinate of the known pilot point, and c represents the correct Q-axis coordinate of the known pilot point.

[0145] Based on this, the received signal can be equalized to compensate for the constellation point shrinkage problem caused by the memristor array calculation.

[0146] The output current in step S102 is determined by Ohm's law and Kirchhoff's law, which can be expressed as: In an embodiment of the present application, the output current can be converted into a current signal and finally modulated into an output voltage signal, and the output voltage signal is equivalent to a matrix operation result.

[0147] The mapping process of the memristor array is specifically as follows: Steps S201 to S202. In the embodiment of the present application, the memristor array is used to map the matrix Each memristor maps the matrix to achieve exact matrix operations.

[0148] In the embodiment of the present application, the mapping relationship between the elements in the matrix and the conductance values ​​of the memristor can be expressed as:

[0149]

[0150] Wherein, B represents the conductance value array of the memristor array, λ1 represents a scaling factor, which is used to map the operation matrix into the memristor conductance range, Φ represents a moving matrix, which is used to indicate the moving distance of each element in the operation matrix. B max and B min represents the conductance value range of the memristor in the memristor array, G max and G min Indicates the maximum and minimum element values ​​of the operation matrix.

[0151] In the expression of the above mapping relationship, the purpose of setting Φ is to ensure that the conductance values ​​of the memristor are all in the positive range. The conductance value range of the memristor is set according to the resistance R_on of the memristor in the on state and the resistance R_off of the memristor in the off state, which can be the adjacent values ​​of R_on and R_off. The setting of the scaling factor is used to map the matrix value range to the memristor conductance range.

[0152] It can be understood that the method can be executed by any device, equipment, platform, or device cluster having computing and processing capabilities.

[0153] It should be noted that the method of one or more embodiments of the present application can be performed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of one or more embodiments of the present application, and the multiple devices will interact with each other to complete the described method.

[0154] It should be noted that the above describes specific embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0155] Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present application also provides a signal processing device based on a memristor array.

[0156] like Figure 2 As shown, the above device comprises:

[0157] A first mapping module 11, used for mapping an input signal into an input voltage signal, and inputting the input voltage signal into the mapped memristor array;

[0158] The mapped memristor array 12 is used to obtain an output current based on the input voltage signal;

[0159] The mapped memristor array is obtained by the following steps:

[0160] Determine the discrete Fourier transform expression of the signal conversion X = W N x, x represents the input signal, X represents the output signal, W N represents the rotation factor;

[0161] Convert it into a complex matrix-vector multiplication expression;

[0162]

[0163] Re() represents the real part of a complex number, and Im() represents the imaginary part of a complex number;

[0164] The operation matrix Mapping to the memristor array to obtain the mapped memristor array.

[0165] In the embodiments of the present application, the following may also be included:

[0166] A signal conversion module 13, used for converting the output current into a voltage signal;

[0167] The signal output module 14 is used to modulate the voltage signal into an output voltage signal.

[0168] In the embodiments of the present application, the following may also be included:

[0169] The single-pole double-throw switch 15 is used to switch the memristor array operation or the conductivity modulation.

[0170] In the embodiments of the present application, the following may also be included:

[0171] The transimpedance amplifier 16 is used to facilitate the cascading between memristors by converting current into voltage.

[0172] The computing unit circuit structure based on the memristor array in one or more embodiments of the present application is as follows: Figure 4 shown.

[0173] Figure 4 Part (a) is a first mapping module, which may be composed of at least one programmable memristor unit and is used to map the input voltage signal. According to the input voltage mapping expression above:

[0174]

[0175] The output voltage of this module can be expressed as:

[0176]

[0177] in, an represents the input signal, v ab,n =V in .

[0178] In the embodiments of the present application, Figure 5 As shown, the programmable memristor unit includes four metal oxide semiconductor field effect transistors (MOSFETs), which are marked as a, b, c, and d. The two MOSFETs on the left (a and c) are P-type MOSFETs, and the two MOSFETs on the right (b and d) are N-type MOSFETs. These MOSFETs are controlled by a control voltage, which is introduced from the top and bottom and connected to the gates of the P-type and N-type MOSFETs, respectively. The size of the applied control voltage determines which side of the switch is activated. When the control voltage is lower than the threshold voltage of the P-type MOSFET, a and c are turned on, while b and d are turned off. This means that the P-type MOSFET is turned on at a low voltage, and the current can pass through the path of a and c to form a path. This mechanism can be regarded as two double-throw switches (SPDT), which allows the circuit to dynamically change its connection path, thereby realizing programmable functions.

[0179] The present application uses the above-mentioned programmable memristor unit to replace the ordinary resistor to represent the resistor R f The reason is that λ2 in this application may be different in different communication computing scenarios, requiring the resistor R f Can be adjusted flexibly.

[0180] Figure 4 Part (b) is a memristor array, in which the memristors store the mapped conductance information. In the memristor conductance modulation stage, C b,1 Control the corresponding column of the memristor array to perform conductivity modulation process, C b,2 The control memristor array is isolated from the peripheral circuit. The pulse modulation signal and the conductivity measurement signal are connected from the terminal V set Input, while from terminal I read The current signal is read to determine the corresponding memristor conductance. During the computation phase, the memristor conductance does not need to be changed.

[0181] Figure 4Part (c) includes a transimpedance amplifier and a single-pole double-throw switch. The transimpedance amplifier can be used to promote the cascading between memristors by converting current into voltage. As a feedback resistor, the calculation and conductance modulation functions of the memristor must be implemented separately. Therefore, the present application improves the transimpedance amplifier using a programmable memristor unit, and separates the memristor calculation and conductance modulation through a single-pole double-throw switch, thereby enabling adjustable feedback gain in the transimpedance amplifier.

[0182] Figure 4 In part (d), the transimpedance amplifier with adjustable feedback gain converts the output current of the memristor array into a voltage signal. The conversion relationship is: v d,n =-I out,n R d , R d =1 / λ1λ2.

[0183] Figure 4 Parts (e) and (f) are used to calculate the final output voltage signal. The calculation expression of part (e) is:

[0184]

[0185] in,

[0186] The above formula can also be expressed as:

[0187] The calculation expression of part (f) is:

[0188] v out,n =-(v e +v d,n +V f,n );

[0189] Another V f =[V f,1 ,V f,2 ,…,V f,n ],

[0190] The above formula can be expressed as:

[0191]

[0192] I is a unit vector.

[0193] V f The calculation only needs to be performed once after each conductance modulation of the memristor array.

[0194] Thus, a voltage signal equivalent to the result of the matrix operation can be obtained at the output end.

[0195] The overall circuit architecture diagram of one or more DFT (or IDFT) devices of the present application is shown in FIG. Figure 6 As shown, the device includes a control module for modulating the memristors of the memristor array and the programmable memristor unit so as to avoid the adjustment of the memristor array in the subsequent calculation process, and only the programmable memristor unit needs to be fine-tuned according to the mapping of the input data. The random access memory is used to store the complex valued data and then transmit it to the rotation factor processing unit. The rotation factor processing unit mainly undertakes two tasks: combining the real and imaginary parts of the complex data into a column vector [Re(x),Im(x)] T ; or in the basis synthesis operation, call the corresponding rotation factor from the read-only memory and add the result to [Re(x),Im(x)] T After multiplication, the data is output. When the calculation unit completes the calculation, the data is transferred back to the random access memory. All the above operations are controlled by the central control unit.

[0196] For the convenience of description, the above devices are described in terms of functions and modules. Of course, when implementing one or more embodiments of the present application, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0197] The apparatus of the above-mentioned embodiment is used to implement the corresponding method in the above-mentioned embodiment, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0198] Figure 7 A more specific schematic diagram of the hardware structure of an electronic device provided in this embodiment is shown, and the device may include: a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040 are connected to each other through the bus 1050 in the device.

[0199] The processor 1010 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of the present application.

[0200] The memory 1020 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 may store an operating system and other application programs. When the technical solution provided in the embodiment of the present application is implemented by software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0201] The input / output interface 1030 is used to connect the input / output module to realize information input and output. The input / output module can be configured in the device as a component (not shown in the figure), or it can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, etc.

[0202] The communication interface 1040 is used to connect a communication module (not shown) to realize communication interaction between the device and other devices. The communication module can realize communication through a wired mode (such as USB, network cable, etc.) or a wireless mode (such as mobile network, WIFI, Bluetooth, etc.).

[0203] The bus 1050 includes a path that transmits information between the various components of the device (eg, the processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040).

[0204] It should be noted that, although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040 and the bus 1050, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above device may also only include the components necessary for implementing the embodiment of the present application, and does not necessarily include all the components shown in the figure.

[0205] The electronic device of the above embodiment is used to implement the corresponding method in the above embodiment, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0206] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0207] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present disclosure (including the claims) is limited to these examples. Based on the concept of the present disclosure, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of different aspects of one or more embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0208] In addition, to simplify the description and discussion, and in order not to make one or more embodiments of the present application difficult to understand, the known power / ground connections to the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device can be shown in the form of a block diagram to avoid making one or more embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform on which one or more embodiments of the present application will be implemented (that is, these details should be fully within the scope of understanding of those skilled in the art). In the case of elaborating specific details (e.g., circuits) to describe exemplary embodiments of the present disclosure, it is obvious to those skilled in the art that one or more embodiments of the present application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0209] Although the present disclosure has been described in conjunction with specific embodiments of the present disclosure, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0210] One or more embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of one or more embodiments of the present application should be included in the scope of protection of this disclosure.

Claims

1. A signal processing method based on a memristor array, characterized in that: include: Mapping an input signal into an input voltage signal, and inputting the input voltage signal into the mapped memristor array; The mapped memristor array obtains an output current based on the input voltage signal; The mapped memristor array is obtained by the following steps: Determine the discrete Fourier transform expression of the signal conversion X = W N x, x represents the input signal, X represents the output signal, W N represents the rotation factor; Convert it into a complex matrix-vector multiplication expression; Re() represents the real part of a complex number, and Im() represents the imaginary part of a complex number; The operation matrix Mapping to the memristor array to obtain the mapped memristor array.

2. The method according to claim 1, characterized in that The operation matrix G X Mapping to the memristor array, comprising: According to the operation matrix The calculated value of the element in is used to calculate the conductance value of the memristor in the memristor array by the following formula; Wherein, B represents the conductance value array of the memristor array, λ1 represents a scaling factor, which is used to map the operation matrix into the memristor conductance range, Φ represents a moving matrix, which is used to indicate the moving distance of each element in the operation matrix. B max and B min represents the conductance value range of the memristor in the memristor array, G max and G min Indicates the maximum and minimum element values ​​of the operation matrix.

3. The method according to claim 2, characterized in that The input signal includes a time domain signal or a frequency domain signal.

4. The method according to claim 3, characterized in that Mapping the input signal to an input voltage signal includes: According to the input signal, the input voltage signal is obtained by the following formula; Wherein, x represents the input signal, λ2 represents the mapping scale factor, and N represents the numerical range of the input signal.

5. The method according to claim 4, characterized in that The mapped memristor array obtains an output current based on the input voltage signal, including: The mapped memristor array obtains the output current based on the input voltage signal through the following formula; 6. The method according to claim 3, characterized in that: Mapping the input signal to an input voltage signal includes: According to the input signal, the input voltage signal is obtained by the following formula; V in =λ2(xx min ); Among them, x min Indicates the minimum value of the input voltage.

7. The method according to claim 6, characterized in that The mapped memristor array obtains an output current based on the input voltage signal, including: The mapped memristor array obtains the output current based on the input voltage signal through the following formula; 8. The method according to claim 1, characterized in that Mapping the input signal to an input voltage signal includes: Equalizing the input signal using a contraction coefficient to obtain an equalized input signal; Mapping the equalized input signal into an input voltage signal; The shrinkage coefficient is obtained by the following steps: receiving a pilot signal; According to the pilot signal, the contraction coefficient is calculated by the following formula, wherein the contraction coefficient includes a horizontal axis contraction coefficient and a vertical axis contraction coefficient; Among them, e I represents the horizontal axis contraction coefficient, e Q represents the vertical axis contraction coefficient, i represents the number of known pilot points, j represents the number of pilot signals received by each known pilot point, and s i,I represents the I-axis coordinate of the i-th sample of the known pilot point received by the receiver, s i,Q represents the Q-axis coordinate of the i-th sample of the known pilot point received by the receiving end, a represents the correct I-axis coordinate of the known pilot point, and c represents the correct Q-axis coordinate of the known pilot point.

9. A signal processing device based on a memristor array, characterized in that: include: A first mapping module, used for mapping an input signal into an input voltage signal, and inputting the input voltage signal into the mapped memristor array; The mapped memristor array is used to obtain an output current based on the input voltage signal; The mapped memristor array is obtained by the following steps: Determine the discrete Fourier transform expression of the signal conversion X = W N x, x represents the input signal, X represents the output signal, W N represents the rotation factor; Convert it into a complex matrix-vector multiplication expression; Re() represents the real part of a complex number, and Im() represents the imaginary part of a complex number; The operation matrix Mapping to the memristor array to obtain the mapped memristor array.

10. The device according to claim 9, characterized in that Also includes: A signal conversion module, used for converting the output current into a voltage signal; The signal output module is used to modulate the voltage signal into an output voltage signal.

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