Parallel packaging structure of vertical semiconductor device
By adopting a two-chip stacked parallel design in the packaging structure of vertical semiconductor devices and connecting the drain through the intermediate metal layer, the problem of chip area is solved, and the application of greater power and better current is achieved and heat dissipation performance.
Patent Information
- Application Number
- CN202411552850.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-01
- Publication Date
- 2025-02-11
AI Technical Summary
Due to the limited chip area of the existing vertical semiconductor devices, it is difficult to achieve higher power applications.
Using a parallel package structure arranged with two stacks, the lower and upper chips are stacked in parallel, and the drains of the two chips are connected through an intermediate metal layer to increase the area of the intermediate metal layer to reduce the resistance.
It reduces the chip area limitation, improves current processing capacity, enhances the heat dissipation ability of the device, and realizes higher power applications.
Smart Images
Figure CN119419199A_ABST
Abstract
Description
Technical Field
[0001] The present application belongs to the technical field of semiconductor devices, and in particular, relates to a parallel packaging structure of vertical semiconductor devices. Background Art
[0002] In high-power applications, power semiconductor devices such as vertical metal oxide semiconductor field effect transistors (MOSFET) and insulated gate bipolar transistors (IGBT) often need to occupy a large PCB area to achieve low loss and heat dissipation requirements. However, in new applications such as drones, power tools, electric vehicles, etc., it is necessary to achieve high-power applications on a smaller PCB area. Surface mount package devices are an existing small package structure and are used in the above applications.
[0003] A traditional surface mount package device structure such as Figure 1A , as shown in 1B, where Figure 1A is a cross-sectional schematic diagram. Figure 1B 1 is a top view of the corresponding structure. The structure has a first type of metal pin 136 located at the bottom, a drain metal base plate 134 connected thereto, and a second type of metal pin 135 and a third type of metal pin 138 not connected thereto. A vertical power device chip 130 is provided on the drain metal base plate 134. The chip bottom metal layer at the bottom of the vertical power device chip 130 and the drain metal base plate 134 are connected to each other through a chip bonding material 131. The top of the vertical power device chip 130 has two parts of a solderable metal layer 132, which are connected to two sections of the top metal sheet 133 through solder 139 respectively, and then connected to the second type of metal pin 135 and the third type of metal pin 138. In addition, it also includes a molding material 140 that wraps the chip 130 and the top metal sheet 133.
[0004] However, a certain safety distance ( Figure 1B In a, b), the maximum chip area is limited by the package area. For example, in a 5mm*6mm surface mount package device, the maximum chip area is 11-14mm 2 The limited chip area limits the maximum current and power dissipation of the device, making it difficult to achieve higher power applications. Summary of the invention
[0005] The technical problem solved by the present application is: how to increase the maximum current and dissipated power of semiconductor devices.
[0006] The present application provides a parallel packaging structure of a vertical semiconductor device, the parallel packaging structure includes a source metal base plate, a lower chip, an intermediate metal layer, an upper chip and a top metal layer stacked from bottom to top, the source metal base plate is connected to the source of the lower chip, the top metal layer is connected to the source metal base plate and the source of the upper chip, the intermediate metal layer is connected to the drain of the lower chip and the drain of the upper chip, and the projection of the lower chip on the intermediate metal layer and / or the projection of the upper chip on the intermediate metal layer are located within the range of the intermediate metal layer.
[0007] Optionally, the parallel packaging structure further includes a gate metal base plate located at the same layer as the source metal base plate, and the gate metal base plate is respectively connected to the gate of the lower chip and the gate of the upper chip.
[0008] Optionally, the first chip channel region of the lower chip is located on a side of the lower chip facing the source metal base plate.
[0009] Optionally, the parallel packaging structure further includes a bottom heat sink, and the bottom heat sink is arranged on the bottom surface of the source metal base plate.
[0010] Optionally, the second chip channel region of the upper chip is located on a side of the upper chip facing the top metal layer.
[0011] Optionally, the parallel packaging structure further includes a top heat dissipation metal layer, and the top heat dissipation metal layer is arranged on the top surface of the top metal layer.
[0012] Optionally, the parallel packaging structure further includes a top heat sink, and the top heat sink is arranged on the top surface of the top heat dissipation metal layer.
[0013] Optionally, the parallel packaging structure also includes a first type of metal pin located on the same layer as the source metal base plate, the first type of metal pin is arranged and connected to the edge of the source metal base plate, and the edge of the top metal layer is bent and extended downward and connected to the first type of metal pin.
[0014] Optionally, the parallel packaging structure further includes a second type of metal pin located at the same layer as the source metal base plate, and the edge of the intermediate metal layer is bent, extends downward and is connected to the second type of metal pin.
[0015] Optionally, the parallel packaging structure further includes a third type of metal pin located at the same layer as the source metal base plate, the third type of metal pin is connected to the gate metal base plate, and the gate of the upper chip is connected to the gate metal base plate via a gate metal sheet or a metal lead.
[0016] The present application provides a parallel packaging structure of a vertical semiconductor device, which has the following technical effects:
[0017] By stacking two chips in parallel, the chip area can be reduced while increasing the area of the middle metal layer between the two chips, reducing the resistance between the middle metal layer and the chip, improving the current handling capability, and avoiding poor contact or miscontact caused by displacement. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] Figure 1A It is a cross-sectional schematic diagram of a surface mount package device structure in the prior art;
[0019] Figure 1B A top view of a bonding structure of a surface mount package device structure in the prior art;
[0020] Figure 2A is a schematic cross-sectional view of a parallel packaging structure of a vertical semiconductor device according to one or more embodiments;
[0021] Figure 2B is a circuit diagram of a parallel packaging structure of vertical semiconductor devices according to one or more embodiments;
[0022] Figure 2C A top view of a bonding structure of an upper chip of a parallel packaging structure of a vertical semiconductor device according to one or more embodiments;
[0023] Figure 2D A top view of a bonding structure of a lower chip of a parallel packaging structure of a vertical semiconductor device according to one or more embodiments;
[0024] Figure 3A A schematic diagram of current direction of a parallel packaging structure of a vertical semiconductor device according to one or more embodiments;
[0025] Figure 3B A schematic diagram of heat transfer direction of a parallel packaging structure of a vertical semiconductor device according to one or more embodiments;
[0026] Figure 4A A top view of another bonding structure of an upper chip of a parallel packaging structure of a vertical semiconductor device according to one or more embodiments;
[0027] Figure 4B A top view of another bonding structure of an upper chip of a parallel packaging structure of a vertical semiconductor device according to one or more embodiments;
[0028] Figure 5A , Figure 5B , Figure 5C , Figure 5D, Figure 5E is a schematic flow chart of a method for manufacturing a parallel packaging structure of a vertical semiconductor device according to one or more embodiments;
[0029] Fig. 6A , Figure 6B , Figure 6C , Fig.6D , Fig. 6E is another schematic flow chart of a method for manufacturing a parallel packaging structure of a vertical semiconductor device according to one or more embodiments;
[0030] Fig. 7A , Figure 7B , Figure 7C The diagram is a schematic diagram of the manufacturing process of a top metal heat dissipation layer of a parallel packaging structure of a vertical semiconductor device according to one or more embodiments.
[0031] The corresponding relationship between the reference numerals and the component names is as follows:
[0032] Source metal base plate -10, first type metal pin -11, second type metal pin -12, third type metal pin -13, lower chip -20, first chip channel region -21, bottom gate metal sheet -22, middle metal layer -30, upper chip -40, gate -401, gate metal sheet -41, metal lead -42, second chip channel region -43, top metal layer -50, gate metal base plate -60, bottom heat sink -70, top heat sink metal layer -80, top heat sink -90, molding material layer -100. DETAILED DESCRIPTION
[0033] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.
[0034] Before describing the various embodiments of the present application in detail, the technical concept of the present application is first briefly described: a certain safety distance is usually required between the edge of the current vertical power device chip and the drain metal base plate, which limits the chip area, thereby limiting the maximum current and dissipated power of the device. To this end, the parallel packaging structure of the vertical semiconductor device provided by the present application adopts a two-layer stacking setting to stack two chips up and down and connect them in parallel, which can reduce the limitation of the chip area, while increasing the area of the middle metal layer between the two chips, reducing the resistance between the middle metal layer and the chip, improving the current handling capacity, and avoiding poor contact or miscontact caused by displacement. The specific principles of the parallel packaging structure of the vertical semiconductor device of the present application are described in combination with more embodiments below.
[0035] Specifically, Figure 2A As shown, the parallel packaging structure of the vertical semiconductor device of the present embodiment includes a source metal base plate 10, a lower chip 20, an intermediate metal layer 30, an upper chip 40 and a top metal layer 50 stacked from bottom to top, the source metal base plate 10 connects the source of the lower chip 20, the top metal layer 50 connects the source metal base plate 10 and the source of the upper chip 40, the intermediate metal layer 30 connects the drain of the lower chip 20 and the drain of the upper chip 40, and the projection of the lower chip 20 on the intermediate metal layer 30 and / or the projection of the upper chip 40 on the intermediate metal layer 30 are located within the range of the intermediate metal layer 30. Among them, as Figure 2B As shown, the lower chip 20 and the upper chip 40 are connected in parallel, and the current flows from the middle metal layer 30 to the lower chip 20 and the upper chip 40 respectively, and finally flows out from the top metal layer 50 and the source metal base plate 10 and then is collected.
[0036] Exemplarily, the bottom of the lower chip 20 is arranged upward, and the drain metal at the bottom of the lower chip 20 is connected to the lower surface of the intermediate metal layer 30 through the solder layer; the bottom of the upper chip 40 is arranged downward, and the drain metal at the bottom of the upper chip 40 is connected to the upper surface of the intermediate metal layer 30 through the solder layer. Figure 2C As shown, the area of the intermediate metal layer 30 is larger than that of the lower chip 20 and completely contacts the bottom of the lower chip 20, thereby minimizing the contact resistance and current distribution resistance therein. Figure 2D As shown, the area of the intermediate metal layer 30 is larger than that of the upper chip 40, and it completely contacts the bottom of the upper chip 40, so that the contact resistance and current distribution resistance therein can be minimized. In addition, the area of the intermediate metal layer 30 is large, which can prevent the upper chip 40 and the intermediate metal layer 30 from shifting and causing miscontact.
[0037] Furthermore, the area of the top metal layer 50 and the area of the source metal base plate 10 are both smaller than the area of the middle metal layer 30, so that the middle metal layer 30 connected in series on the parallel device has a larger area, less resistance, and a larger current handling capacity, while the top metal layer 50 and the source metal base plate 10 connected in series on a single chip have a smaller area, greater resistance, and a smaller current handling capacity, and have a more optimized resistance distribution and current handling capacity. Figure 3A As shown, the current passes through the middle metal layer 30 and is divided into the upper chip 40 and the lower chip 20. Therefore, the use of a larger area of the middle metal layer 30 in this embodiment is beneficial to the current handling capacity and the heat dissipation capacity of the device.
[0038] In one or more embodiments, the parallel packaging structure further includes a first type of metal pin 11 located at the same layer as the source metal base plate 10, the first type of metal pin 11 is arranged and connected to the edge of the source metal base plate 10, and the edge of the top metal layer 50 is bent and extended downward and connected to the first type of metal pin 11. Figure 2B As shown, the first type of metal pin 11 plays the role of collecting current, which is equivalent to the source of the device.
[0039] In one or more embodiments, the parallel packaging structure further includes a second type of metal pin 12 located at the same layer as the source metal base plate 10, and the edge of the intermediate metal layer 30 is bent and extended downward and connected to the second type of metal pin 12. Figure 2B As shown, the second type metal pin 12 acts as the drain of the device.
[0040] In one or more embodiments, the parallel packaging structure further includes a gate metal base plate 60 located at the same layer as the source metal base plate 10 , and the gate metal base plate 60 is connected to the gate of the lower chip 20 and the gate of the upper chip 40 respectively.
[0041] Furthermore, the parallel packaging structure also includes a third type of metal pin 13 located at the same layer as the source metal base plate 10 , the third type of metal pin 13 is connected to the gate metal base plate 60 , and the third type of metal pin 13 acts as a device gate.
[0042] In one or more embodiments, Figure 3B As shown, the first chip channel region 21 of the lower chip 20 is located on the side of the lower chip 20 facing the source metal base plate 10. The second chip channel region 43 of the upper chip 40 is located on the side of the upper chip 40 facing the top metal layer 50. Since the highest temperature of the chip is in the chip channel region at the top of the chip when it is working, the chip channel regions of the two chips are arranged back to back so that the distance between them is farther, which is not easy to form heat accumulation, and is conducive to dissipating the heat of the chip channel region to the outside.
[0043] Exemplarily, the parallel package structure further includes a bottom heat sink 70, which is disposed on the bottom surface of the source metal base plate 10, which is conducive to heat dissipation of the lower chip 20. The parallel package structure also includes a top heat dissipation metal layer 80 and a top heat sink 90, and the top heat dissipation metal layer 80 is disposed on the top surface of the top metal layer 50, which is conducive to heat dissipation of the upper chip 40 and improves the heat dissipation capacity of the device.
[0044] Exemplarily, the gate 401 of the upper chip 40 is connected to the gate metal base plate 60 through the gate metal sheet 41 or the metal lead 42. Figure 4AAs shown, the connection is made through the gate metal sheet 41, which is beneficial to reducing the conduction resistance of the gate. In some embodiments, the gate 401 on the top of the upper chip 40 may be located at the upper right corner of the chip (consistent with the lower chip 20) and connected to the gate metal base plate 60 through a longer metal lead 42, such as Figure 4B As shown. In this embodiment, the gate metal positions of the upper chip 40 and the lower chip 20 are consistent, which is conducive to the consistency of the chip structure. In some embodiments, the upper chip 40 and the lower chip 20 can even be set as the same chip, which is conducive to reducing the types of raw materials.
[0045] In one or more embodiments, the parallel packaging structure also includes a molding material layer 100, which covers most of the structure of the parallel packaging structure, including a lower chip 20, an intermediate metal layer 30, an upper chip 40 and a top metal layer 50, wherein a top heat dissipation metal layer 80, a first type of metal pin 11, a second type of metal pin 12, a third type of metal pin 13, and a source metal base plate 10 are exposed outside the molding material layer 100, and the surfaces of these structures may have a tin alloy plating layer.
[0046] In some embodiments, a solderable metal layer is provided on the gate metal and drain metal at the top of the lower chip 20 and the upper chip 40. The solderable metal layer can be a metal combination layer of Ti-Ni-Ag, Ni-Pd-Au, Ti-Cu, Ti-Ni-Au, etc. The top heat dissipation metal layer 80, the middle metal layer 30, the first metal pin 11, the second metal pin 12, the third metal pin 13, and the source metal base plate 10 are all made of copper metal material.
[0047] In some embodiments, the top heat dissipation metal layer 80 may be omitted to reduce process complexity.
[0048] In some embodiments, in addition to omitting the top heat dissipation metal layer 80, further, it is possible not to use metal bonding to connect the upper chip 40 and the first type of metal pins 11 through the top metal layer 50, but to use aluminum tape, aluminum wire or copper wire bonding to connect the upper chip 40 and the first type of metal pins 11. This method can further reduce process complexity and prevent process problems caused by inter-layer tilt and height misalignment.
[0049] In one or more embodiments, a method for manufacturing a parallel packaging structure of a vertical semiconductor device includes the following steps:
[0050] The first step is to provide a metal frame, wherein the metal frame includes a first type metal pin 11, a second type metal pin 12, a third type metal pin 13, a source metal base plate 10, and a gate metal base plate 60, such as Figure 5A shown.
[0051] Step 2: Place the lower chip 20 on the metal frame, with the top of the lower chip 20 facing downward, the source metal of the lower chip 20 contacts the source metal base plate 10, and the gate metal of the lower chip 20 contacts the gate metal base plate 60, as shown in FIG. Figure 5B shown.
[0052] Typically, solder is formed at the connection between the lower chip 20 and the source metal base plate 10 and the gate metal base plate 60 before bonding. In some embodiments, solder bumps may also be formed on the chip in advance.
[0053] Step 3: Arrange an intermediate metal layer 30 above the lower chip 20, such as Figure 5C shown.
[0054] Typically, before the intermediate metal layer 30 is provided, solder is formed on the drain metal at the bottom of the lower chip 20 and the second metal pin 12 in advance, and then the intermediate metal layer 30 is bonded.
[0055] Step 4: Place the upper chip 40 above the middle metal layer 30, with the top of the chip facing upwards, as shown in FIG. Figure 5D shown.
[0056] Generally, solder is formed on the intermediate metal layer 30 before the upper chip 40 is disposed.
[0057] In the fifth step, a top metal layer 50 and a gate metal sheet 41 are formed on the upper chip 40, such as Figure 5E shown.
[0058] Typically, before setting the top metal layer 50 and the gate metal sheet 41, solder is formed on the source metal and gate metal above the upper chip 40, as well as the first type of metal pins 11 and the gate metal base plate 60, and then metal bonding is performed.
[0059] The sixth step is to finally form a packaged device.
[0060] The steps of finally forming the packaged device, such as rib cutting, electroplating, and plastic sealing, are the existing traditional processes of surface mount packaging. Those skilled in the art can make corresponding supplements and changes based on the disclosed process flow.
[0061] In one or more embodiments, a method for manufacturing a parallel packaging structure of a vertical semiconductor device includes the following steps:
[0062] The first step is to provide a metal frame, wherein the metal frame includes a first metal pin 11, a second metal pin 12, a third metal pin 13, an intermediate metal layer 30, and a gate metal base plate 60, wherein the intermediate metal layer 30 and the second metal pin 12 are connected to each other. Fig. 6Ashown.
[0063] Step 2: Place the lower chip 20 on the middle metal layer 30 above the metal frame, with the top of the chip facing upward, and the drain metal of the lower chip 20 contacts the middle metal layer 30, such as Figure 6B shown.
[0064] Typically, solder is formed in advance at the connection between the lower chip 20 and the middle metal layer 30 before bonding.
[0065] Step 3: Form a source metal base plate 10 and a bottom gate metal sheet 22 above the lower chip 20, such as Figure 6C shown.
[0066] Typically, before setting the source metal base plate 10 and the bottom gate metal sheet 22, solder is formed on the source metal and gate metal above the chip 20 below, as well as the first type of metal pins 11 and the gate metal base plate 60, and then metal bonding is performed.
[0067] The fourth step is to invert the metal frame, and then place the upper chip 40 on the middle metal layer 30 above the metal frame, with the top of the chip facing upward, and the drain metal of the chip contacts the middle metal layer 30, as shown in FIG. Fig.6D shown.
[0068] Usually, solder is formed at the connection between the chip and the intermediate metal layer 30 in advance, and then bonding is performed.
[0069] In the fifth step, a top metal layer 50 and a gate metal sheet 41 are formed on the upper chip 40, such as Fig. 6E shown.
[0070] Typically, before setting the top metal layer 50 and the gate metal sheet 41, solder is formed on the source metal and gate metal above the upper chip 40, as well as the first type of metal pins 11 and the gate metal base plate 60, and then metal bonding is performed.
[0071] The sixth step is to finally form a packaged device.
[0072] The steps of finally forming the packaged device, such as rib cutting, electroplating, and plastic sealing, are the existing traditional processes of surface mount packaging. Those skilled in the art can make corresponding supplements and changes based on the disclosed process flow.
[0073] Furthermore, this embodiment provides a method for manufacturing a top heat dissipation metal layer 80 of a parallel packaging structure of a vertical semiconductor device:
[0074] Step 1: forming a molding material layer 100, such as Fig. 7A shown.
[0075] In the second step, a notch is formed on the top of the molding material layer 100 to expose the top metal layer 50, such as Figure 7B shown.
[0076] In the third step, a top heat dissipation metal layer 80 is formed above the top metal layer 50, such as Figure 7C shown.
[0077] The specific implementation methods of the present application are described in detail above. Although some embodiments have been shown and described, those skilled in the art should understand that these embodiments can be modified and improved without departing from the principles and spirit of the present application whose scope is defined by the claims and their equivalents. These modifications and improvements should also be within the scope of protection of the present application.
Claims
1. A parallel packaging structure of a vertical semiconductor device, characterized in that: The parallel packaging structure includes a source metal base plate, a lower chip, an intermediate metal layer, an upper chip and a top metal layer stacked from bottom to top, the source metal base plate is connected to the source of the lower chip, the top metal layer is connected to the source metal base plate and the source of the upper chip, the intermediate metal layer is connected to the drain of the lower chip and the drain of the upper chip, and the projection of the lower chip on the intermediate metal layer and / or the projection of the upper chip on the intermediate metal layer are located within the range of the intermediate metal layer.
2. The parallel packaging structure of a vertical semiconductor device according to claim 1, characterized in that: The parallel packaging structure further includes a gate metal bottom plate located at the same layer as the source metal bottom plate, and the gate metal bottom plate is respectively connected to the gate of the lower chip and the gate of the upper chip.
3. The parallel packaging structure of vertical semiconductor devices according to claim 1, characterized in that: The first chip channel region of the lower chip is located on a side of the lower chip facing the source metal base plate.
4. The parallel packaging structure of vertical semiconductor devices according to claim 3, characterized in that: The parallel packaging structure further includes a bottom heat sink, which is arranged on the bottom surface of the source metal base plate.
5. The parallel packaging structure of vertical semiconductor devices according to claim 1, characterized in that: The second chip channel region of the upper chip is located on a side of the upper chip facing the top metal layer.
6. The parallel packaging structure of vertical semiconductor devices according to claim 5, characterized in that: The parallel packaging structure further includes a top heat dissipation metal layer, and the top heat dissipation metal layer is arranged on the top surface of the top metal layer.
7. The parallel packaging structure of vertical semiconductor devices according to claim 6, characterized in that: The parallel packaging structure further includes a top heat sink, which is disposed on the top surface of the top heat dissipation metal layer.
8. The parallel packaging structure of vertical semiconductor devices according to claim 1, characterized in that: The parallel packaging structure also includes a first type of metal pin located at the same layer as the source metal base plate, the first type of metal pin is arranged and connected to the edge of the source metal base plate, and the edge of the top metal layer is bent and extended downward and connected to the first type of metal pin.
9. The parallel packaging structure of vertical semiconductor devices according to claim 1, characterized in that: The parallel packaging structure also includes a second type of metal pin located at the same layer as the source metal base plate, and the edge of the intermediate metal layer is bent, extended downward and connected to the second type of metal pin.
10. The parallel packaging structure of vertical semiconductor devices according to claim 2, characterized in that: The parallel packaging structure also includes a third type of metal pin located at the same layer as the source metal base plate, the third type of metal pin is connected to the gate metal base plate, and the gate of the upper chip is connected to the gate metal base plate through a gate metal sheet or a metal lead.