SiC MOSFET hard switching loss measurement method and system without current sensor

Abstract

The invention discloses a SiC MOSFET hard switching loss measurement method and system without a current sensor, which cancel current measurement on the basis of a double-pulse measurement method and obtain a current waveform by analyzing voltage waveform change characteristics. Wherein the measurement of the drain-source voltage is very simple and convenient, the layout and the size of the converter are not influenced, and the measurement time is very short. The method can be popularized to any topology with an equivalent half-bridge commutation loop.

Description

Technical Field

[0001] The present invention relates to the technical field of power electronics, and in particular to a method and system for measuring SiC MOSFET hard switch loss without a current sensor. Background Art

[0002] SiC MOSFET has excellent electrical and thermal properties. Compared with Si devices, it has lower switching losses and allows higher switching frequencies, thereby reducing the volume of passive devices and achieving higher efficiency and power density, making it widely used in the automotive, aerospace and military fields. However, SiC devices are still the main source of power converter losses, and the accurate assessment of their losses has a significant impact on the cooling system. The device loss is divided into conduction loss and switching loss. The conduction loss can be calculated from the on-resistance given in the data sheet; but the switching loss is not easy to obtain because the switching loss is also affected by the drive circuit, complementary tube, and power loop parasitic parameters. Therefore, even under the same operating conditions, the actual loss is often different from the results given in the data sheet, and the difference is even large.

[0003] There are two mainstream switching loss measurement methods: electrical measurement and thermal measurement. The electrical measurement method is mainly a double pulse test to measure the drain-source voltage and drain-source current of the device. The switching loss is the integral of the voltage-current product calculated within the defined switching time. The advantage of this method is that the measurement time is short and there are few additional peripherals. But the disadvantage is that due to the faster switching speed of SiC devices, high-bandwidth probes and oscilloscopes are required, as well as the time delay between the voltage probe and the current probe. The thermal measurement method measures the heat dissipation of the device under test to determine its total loss without measuring the transient process of the switch, so the bandwidth requirement of the measurement equipment is not high; but it depends on the accuracy of the thermal resistance network model and the extraction of the conduction loss, and the measurement time is very long. The common disadvantage of the two methods is that the loss measurement results are only applicable to the prototype used for the test and cannot be used in the actual power converter, because even if the switching devices are the same, the power circuit and the drive circuit cannot be exactly the same. It is also impractical to build a test platform in an actual converter. Thermal measurement requires a large heat sink, and the converter design process does not reserve space for additional measurement equipment. The current probe in electrical measurement is limited by the bandwidth and power device packaging, making the coaxial shunt a better choice, but it is invasive and will introduce additional parasitic inductance and change the original power circuit of the converter. Summary of the invention

[0004] The technical problem to be solved by the present invention is to provide a method and system for measuring the hard switching loss of SiCMOSFET without a current sensor in view of the shortcomings of the prior art, so as to measure the hard switching loss of the device without affecting the volume of the converter and the power circuit.

[0005] In order to solve the above technical problems, the technical solution adopted by the present invention is: a method for measuring the hard switching loss of SiCMOSFET without a current sensor, which is measured by a double pulse test platform, wherein the double pulse test platform includes a half-bridge circuit, and both ends of the half-bridge circuit are connected to a DC source; the half-bridge circuit includes two SiC MOSFETs connected in series in the same phase; the upper SiC MOSFET of the half-bridge circuit is connected in parallel with the load inductor; the method includes:

[0006] The SiC MOSFET hard turn-off loss is calculated using the following formula:

[0007]

[0008] The SiC MOSFET hard turn-on loss is calculated using the following formula:

[0009]

[0010] Among them, t vr_off is the voltage rise time when turning off, V dc is the DC source voltage, t vr_off is the voltage rise time when the lower tube is turned off, t cf_off is the rapid drop time of the current when the lower tube is turned off, V dc is the DC bus voltage, I load is the load current at the switching moment, Q oss1 is the amount of charge stored in the upper tube junction capacitance;

[0011]

[0012] tcr_on is the rapid rise time of the current when the lower tube of the half-bridge circuit is turned on, t rr_on is the reverse recovery time, t vf_on It is the voltage rapid drop time when the lower tube of the half-bridge circuit is turned on, ΔV max It is the maximum value of the voltage on the parasitic inductance of the loop when the drain-source current rises rapidly during the hard turn-on period. As an inventive concept, the present invention also provides a SiC MOSFET hard switching loss measurement system without a current sensor, including a memory, a processor and a computer program stored in the memory; the processor executes the computer program to implement the steps of the above method.

[0013] Compared with the prior art, the present invention has the following beneficial effects: the present invention can reduce the influence of the measuring equipment on the overall layout and design of the converter, and reduce the time taken for measurement. Based on the double pulse measurement method, the present invention cancels the current measurement and obtains the current waveform by analyzing the change characteristics of the voltage waveform. The measurement of the drain-source voltage is very simple, does not affect the layout and volume of the converter, and the measurement time is very short. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1 This is the schematic diagram of the equivalent circuit of the double pulse test platform;

[0015] Figure 2(a) is a simplified schematic diagram of the hard shutdown process;

[0016] Figure 2(b) is a simplified schematic diagram of the hard switching process;

[0017] Figure 2(c) shows the waveform of the hard shutdown process;

[0018] Figure 2(d) shows the waveform of the hard switching process;

[0019] Figure 3 (a) is a simplified schematic diagram of the hard turn-off waveform;

[0020] Figure 3 (b) is a simplified schematic diagram of the hard-on waveform;

[0021] Figure 4 is the actual voltage waveform and its fitting function;

[0022] Figure 5(a) shows R g =1Ω,I ds =20A,V ds =Comparison between the proposed method and experimental results under 500~800V working conditions;

[0023] Figure 5(b) shows R g =1Ω,I ds =5~20A,V ds =Comparison between the proposed method and experimental results under 800V condition;

[0024] Figure 5(c) shows R g =4.7Ω,I ds =5~20A,V ds =Comparison between the proposed method and experimental results under 800V condition;

[0025] Figure 5(d) shows R g =1Ω,I ds =5~20A,V ds =800V, comparison between the proposed method and experimental results after the parasitic inductance of the power circuit is increased;

[0026] Figure 5(e) shows R g =1Ω,I ds =15~60A,V ds =800V, the proposed method is compared with the experimental results after replacing the device under test. DETAILED DESCRIPTION

[0027] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] The working principle of the proposed method is analyzed based on the double pulse test circuit:

[0029] The equivalent circuit of the double pulse test platform is as follows: Figure 1 As shown, it includes SiC devices S1, S2, device package lead inductance L s1 , L s2 , L d1 , L d2 , device junction capacitance C ds1 , C ds2 , decoupling capacitor C de Its parasitic inductance L de , PCB line inductance L PCB(Dev-Dec) , L PCB(Dec-Bus) , load inductance L load , DC source V dc For convenience, L σ Replace L PCB(Dev-Dec) , L de , L d1 and L s1 The sum of the drain-source voltage and drain-source current of the device under test is named v ds2 and i ds2 The principle of double pulse test is: send two pulse drive signals to the tested tube S2, the first pulse charges the load inductor to a specified current, and observe the first pulse turn-off moment and the second pulse turn-on moment, so as to obtain the hard switching characteristics of the device under the specified voltage and current.

[0030] L σ =L PCB(Dev-Dec) +L de +L d1 +L s1 (1)

[0031] A simplified schematic diagram of the hard shutdown process is shown in Figure 2(a), and the corresponding voltage and current waveforms are shown in Figure 2(c).

[0032] Before t1: the lower tube S2 is turned on, the DC source charges the load inductor, and the load current rises linearly, reaching the set current value at time t1.

[0033] Between t1 and t2: the load current is divided into two parts, one part still flows through the channel of S2 and the junction capacitance C ds2 The other part flows through the junction capacitance C of S1. ds1 , causing the voltage across its two ends to drop. At time t2, v ds2 Reach bus voltage, C ds1 The charge is completely discharged.

[0034] Between t2 and t3: the channel current of the lower tube S2 gradually decreases until the current is 0; the body diode of the upper tube S1 is turned on, and its current gradually increases to the load current. The large current change rate causes a large voltage component to be generated on the parasitic inductance of the loop. This voltage is applied to S2 together with the DC bus voltage, resulting in v ds2 A voltage overshoot occurs on the

[0035]

[0036] After t3: the load current is completely commutated to the body diode of S1, and the junction capacitance C ds2 It resonates with the parasitic inductance of the loop at a high frequency. The resonant frequency is

[0037]

[0038] It is also worth noting that the equivalent circuit between the two points measured by the voltage probe is the package lead inductance L d2 , L s2 and junction capacitance C ds2 At the resonant frequency f r Therefore, the drain-source current i ds2 Leading drain-source voltage v ds2 Ninety degrees.

[0039] A simplified schematic diagram of the hard switching process is shown in Figure 2(b), and the corresponding voltage and current waveforms are shown in Figure 2(d).

[0040] Before t4: the load inductor current continues to flow through the body diode of the upper tube S1.

[0041] Between t4 and t5: the channel of the lower tube S2 is turned on, and the load current gradually migrates from the body diode of S1. At this time, a large additional voltage component is generated on the parasitic inductance of the loop to cancel the DC bus voltage, making v ds2 The voltage is lower than the bus voltage, and its expression is the same as equation (2). At t5, the load current is completely transferred.

[0042] Between t5 and t6: the charge stored in the body diode of S1 is released to form a reverse recovery current, which flows through S2 together with the load current. At this time, the voltage across S2 is v ds2The voltage is still high and the reverse recovery ends at time t6.

[0043] Between t6 and t7: Junction capacitance C of S2 ds2 Discharge through its own channel, while decoupling capacitor C de The junction capacitance C of S1 ds1 Charging. ds2 It drops rapidly and reaches zero at time t7.

[0044] After t7: The DC source continues to charge the load inductance, accompanied by the parasitic capacitance C ds1 Resonates with the parasitic inductance of the loop.

[0045] At this time, the equivalent circuit between the two points measured by the voltage probe is the package lead inductance L d2 , L s2 and on-resistance R ds(on) The series connection is close to pure inductance because of the high resonant frequency and small on-resistance. ds2 Leading drain-source current i ds2 Ninety degrees.

[0046] Through the analysis of the above commutation process, it can be found that the voltage and current changes in each stage are related. Therefore, the current waveform can be obtained by analyzing the voltage waveform.

[0047] Based on the above analysis of the commutation process, the loss measurement method of the embodiment of the present invention is described:

[0048] The voltage waveform and the current waveform are fitted with functions in stages. In order to simplify the fitting function, the zero point of the horizontal axis of each stage is established at its own starting point.

[0049] The simplified diagram of hard shutdown waveform is as follows: Figure 3 (a) shown.

[0050] During the period from t1 to t2, the load current is fed to C ds2 Charging and C ds1 Discharge, v ds2 Approximately linear increase, i ds2 Equal to the load current minus the current given to C ds1 The discharge current decreases linearly at a small rate of change; Figure 3 The purple shaded area in (a) is equal to C ds1 The amount of stored charge can be obtained from the data sheet. The voltage and current fitting function expression and loss size at this stage are:

[0051]

[0052] where t vr_offis the voltage rise time when turned off, which can be approximately considered as v ds2 From 5% to 100% of V dc Time spent.

[0053] During the period from t2 to t3, v ds2 Ignore the oscillation voltage, approximate the DC side voltage V dc .i ds2 It decreases linearly to zero at a large rate of change. The voltage and current function expressions and loss magnitude at this stage are:

[0054]

[0055] where t cf_off is the rapid drop time of the channel current when it is turned off, which can be considered as the time from t vr_off End to i ds2 The time it takes for the current to drop to zero. However, since the current waveform is not actually obtained, it is necessary to find the current zero point through the voltage characteristics. As mentioned above, after t3 (that is, the channel is completely turned off), the loop parasitic inductance and junction capacitance C ds2 Resonance occurs. Therefore, half the resonance cycle from the first valley of the voltage oscillation waveform is the zero crossing point of the corresponding current.

[0056] The hard turn-off loss calculation expression is:

[0057]

[0058] The simplified diagram of the hard-on waveform is as follows: Figure 3 (b) as shown.

[0059] During the period from t4 to t5, the load current quickly transfers to the S2 channel. ds2 It is approximately linearly rising. The voltage drop on the parasitic inductance of the loop is ΔV(t). The voltage and current function expression and loss size at this stage are:

[0060]

[0061] where t cr_on is the rapid rise time of the channel current of S2 when it is turned on, which can be considered as the time from v ds2 Equal to 95% of V dc to ds2 is equal to the time taken by the load current. ds2 The time when the load current reaches the load also needs to be obtained through the voltage change characteristics. Decoupling capacitors usually use ceramic capacitors or film capacitors with small parasitic inductance and are placed close to the half bridge. σ Approximately equal to L s1 +L d1 According to the principle of flux conservation, the integral of ΔV(t) over time is equal to Lσ with I load The product of . Based on this simultaneous equation, solve t cr_on , as follows

[0062]

[0063] During the period from t5 to t6, the body diode of S1 is reverse biased and withstands a small reverse voltage, releasing the charge stored during forward conduction. The voltage of S2 remains at V dc -ΔV max In the period from t6 to t7, S1 reverse recovery ends and the junction capacitance C ds1 The charging current and the load current flow through the channel of S2, and the junction capacitance C ds2 The charge on the capacitor is released through the internal channel of S2, v ds2 It is approximately a linear decrease. Since the reverse recovery current is small, only the junction capacitance C is considered during the t5 to t7 period. ds1 Charging current. According to the actual waveform, it can be seen that in this stage i ds2 It is similar to a sine wave with half a cycle superimposed by the DC component. The current fitting function expression is:

[0064]

[0065] The actual voltage waveform is similar to the upper base and waist of a right-angled trapezoid, which is close to a cubic function, such as Figure 4 In order to reduce the number of undetermined coefficients in the fitting function, the symmetry center of the cubic function falls on the ordinate axis. dc -ΔV max ) and (t rr_on +t vf_on ,0) and its slope is at t rr_on When the time is equal to zero, we can get the simultaneous equations (10). The coefficients to be determined are obtained as equation (11).

[0066]

[0067] The loss expression from t5 to t7 is:

[0068]

[0069] where t rr_on ,t vf_on They are reverse recovery time and v ds2 Fast fall time. t rr_on It can be considered that from t cr_on From the end of v ds2 Time taken to start the plunge, t vf_on It can be considered that from v ds2 Start to drop to Vds2 Equal to 5% of V dc The time spent.

[0070] The hard turn-on loss calculation expression is:

[0071]

[0072] From the hard-off and hard-on loss calculation expressions, we can see that the variable V dc and I load Determined by the actual working conditions, variable Q oss1 The remaining variables are provided by the device data sheet and are obtained entirely from voltage measurements without the need for current sensors.

[0073] As shown in Figure 5, the experimental results show that the method for measuring SiC MOSFET hard switching loss without current sensor provided by the embodiment of the present invention can measure the hard switching loss of the device without using a current probe and without affecting the volume and layout of the converter. The measurement error of the total loss is within 5%, meeting the accuracy requirement.

[0074] Example 2

[0075] Embodiment 2 of the present invention provides a measurement system corresponding to the above-mentioned embodiment 1. The measurement system may be a processing device for a client, such as a mobile phone, a laptop computer, a tablet computer, a desktop computer, etc., to execute the method of the above-mentioned embodiment.

[0076] The measurement system of this embodiment includes a memory, a processor, and a computer program stored in the memory; the processor executes the computer program in the memory to implement the steps of the method in the above-mentioned embodiment 1.

[0077] In some implementations, the memory may be a high-speed random access memory (RAM), and may also include a non-volatile memory, such as at least one disk memory.

[0078] In some other implementations, the processor may be a central processing unit (CPU), a digital signal processor (DSP), or other general-purpose processors of various types, which are not limited herein.

[0079] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

[0080] Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims

1. A method for measuring the hard switching loss of SiC MOSFET without a current sensor, using a double pulse test platform for measurement, wherein the double pulse test platform comprises a half-bridge circuit, wherein both ends of the half-bridge circuit are connected to a DC source; the half-bridge circuit comprises two SiC MOSFETs connected in series in phase; the upper SiC MOSFET of the half-bridge circuit is connected in parallel with a load inductor; and the method is characterized in that: The method includes: The SiC MOSFET hard turn-off loss is calculated using the following formula: The SiC MOSFET hard turn-on loss is calculated using the following formula: Among them, t vr_off is the voltage rise time when turning off, V dc is the DC source voltage, Among them, t vr_off is the voltage rise time when the lower tube is turned off, t cf_off is the rapid drop time of the current when the lower tube is turned off, V dc is the DC bus voltage, I load is the load current at the switching moment, Q oss1 is the amount of charge stored in the upper tube junction capacitance; t cr_on is the rapid rise time of the current when the lower tube of the half-bridge circuit is turned on, t rr_on is the reverse recovery time, t vf_on It is the voltage rapid drop time when the lower tube of the half-bridge circuit is turned on, ΔV max It is the maximum value of the voltage on the parasitic inductance of the loop when the drain-source current rises rapidly during hard turn-on.

2. The method for measuring SiC MOSFET hard switching loss without current sensor according to claim 1, characterized in that: t vr_off v ds2 From 5% V dc to 100% V dc Time spent; ds2 is the drain-source voltage of the lower tube.

3. The method for measuring SiC MOSFET hard switching loss without current sensor according to claim 1 or 2, characterized in that: t cf_off For vr_off The drain-source current from the end to the lower tube i ds2 The time it takes to drop to zero.

4. The method for measuring SiC MOSFET hard switching loss without current sensor according to any one of claims 1 to 3, characterized in that: t rr_on It is from t cr_on The drain-source voltage v ds2 Time taken to start the plunge, t vf_on is the drain-source voltage v from the lower tube ds2 Start to drop to V ds2 Equal to 5% V dc The time spent.

5. The method for measuring SiC MOSFET hard switching loss without current sensor according to claim 1, characterized in that: t cr_on is the drain-source voltage of the lower tube v ds2 Equal to 95% V dc The drain-source current to the lower tube is i ds2 Equal to the time taken by the load current.

6. A current sensor-free SiC MOSFET hard switching loss measurement system, comprising a memory, a processor, and a computer program stored in the memory; characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 5.

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