Single-drive grid cascade type high-voltage SiC MOSFET power module circuit

Abstract

A single-drive grid cascade type high-voltage MOSFET module circuit comprises an MOSFET, a static voltage-sharing resistor, a high-voltage capacitor, a high-voltage avalanche diode, a transient voltage suppression (TVS) diode, a drive resistor and a piezoresistor (MOV), and the single-drive grid cascade type high-voltage MOSFET module circuit is simple in structure drive and has the advantages of being good in switching characteristic, excellent in dynamic and static voltage-sharing effect, small in module loss and the like.

Description

Technical Field

[0001] The present invention relates to the technology in the field of power electronic circuit modularization, in particular to a single-drive gate cascade high-voltage MOSFET module circuit. Background Art

[0002] The existing SiC MOSFET power devices have low withstand voltage per chip. To achieve high voltage, multiple low-voltage devices need to be cascaded. Most cascade methods use multiple trigger signals to trigger synchronously, and multiple trigger signals need to be isolated separately, which increases circuit complexity and cost. The power density cannot reach a high level. The control mechanism is complex and due to differences in individual parameters, there may be differences in the turn-on and turn-off timing, resulting in unbalanced voltage and current on the device. Currently, the more mainstream cascade methods are mainly divided into passive buffering, voltage clamping, gate pulse control, and MMC multi-level circuits. The mainstream topology lacks a new circuit structure that is single-driven, easy to implement, and has a good voltage balancing effect. Summary of the invention

[0003] In view of the above-mentioned deficiencies in the prior art, the present invention proposes a single-drive gate cascade high-voltage SiCMOSFET module circuit, which has a simple structure drive and has excellent switching characteristics, superior dynamic and static voltage balancing effects, and low module loss.

[0004] The present invention is achieved through the following technical solutions:

[0005] The present invention relates to a single-drive gate cascade high-voltage SiC MOSFET module circuit, comprising: three layers of SiC MOSFET and corresponding static voltage-equalizing resistors, high-voltage capacitors, high-voltage avalanche diodes, transient voltage suppression (TVS) diodes, driving resistors and varistor (MOV), wherein: the drain terminal of the bottom SiC MOSFET is connected to the source terminal of the top SiC MOSFET, the high-voltage end of each layer of static voltage-equalizing resistors is connected to the anode terminal of the corresponding high-voltage avalanche diode, the anode terminal is connected to the drain terminal of the corresponding SiC MOSFET, the high-voltage end of each layer of high-voltage capacitors is connected to the cathode terminal of the high-voltage avalanche diode, the cathode terminal of the transient voltage suppression (TVS) diode is respectively connected to the gate terminal of the corresponding SiC MOSFET, the gate terminal of each layer of SiC MOSFET is connected in series with a patch driving resistor, and the drain terminal is connected to the high-voltage end of the corresponding varistor. The varistor (MOV) is connected in parallel to the drain-source of each layer of SiC MOSFET.

[0006] An acceleration capacitor is connected in parallel between the drain and source of the bottom SiC MOSFET to effectively improve the turn-on time of the module. Technical Effects

[0007] The present invention controls the cascaded SiC MOSFET device through a single gate driver, simplifies the complexity of the drive system, and increases the power density of the system. When the power module is in the on state, the drive is applied to the bottom SiC MOSFET to reduce its drain voltage, that is, the source voltage of the middle SiC MOSFET is reduced, and the drive unit cooperates with the SiC MOSFET so that the drive signal is forward-conducted through the high-voltage avalanche diode and gradually applied to the gates of the middle and top SiC MOSFETs, further turning on the module as a whole; when the power module is in the off state, the high-voltage avalanche diode blocks the drive signal, and the gates of the middle and top SiC MOSFETs cannot receive the drive signal, and the module is cut off as a whole. Compared with the prior art, the present invention can effectively reduce the parasitic inductance in the circuit, has a good voltage balancing effect, small voltage and current overshoot, good on-off characteristics, improves the power density of the power module, and does not require complicated isolated multi-trigger gate drive. Different from the traditional drain-source voltage balancing, the gate voltage balancing electrically isolates the three units of the circuit drive, cascaded SiC MOSFET, and voltage balancing, reducing mutual electrical interference. A protection unit is also applied on the gate voltage equalization side to protect the SiC MOSFET from voltage overshoot and prevent SiC MOSFET insulation breakdown. An acceleration capacitor is used to accelerate the conduction of the SiC MOSFET, reduce the tail time, effectively reduce switching losses, and improve overall efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 It is a schematic diagram of the circuit topology of the present invention;

[0009] In the picture: R p1 -R p3 is the varistor MOV, R l1 -R l3 is the discharge resistor, R g1 -R g3 is the driving resistor, C e1 -C e3 is the voltage-equalizing capacitor, D e1 -D e3 For high voltage avalanche diode, D g1 -D g2 is a high-voltage avalanche diode, Q1-Q3 are high-voltage SiC MOSFETs, Z2-Z3 are transient suppression diodes TVS, R e1 -R e3 Static voltage balancing resistor;

[0010] Figure 2 A schematic diagram of circuit analysis for opening the SiC MOSFET power module circuit of the present invention;

[0011] In the figure: (a) (b) (c) (d) are schematic diagrams of circuit analysis for opening each layer of SiC MOSFET power module;

[0012] Figure 3 A schematic diagram of circuit analysis for shutting down the SiC MOSFET power module circuit of the present invention;

[0013] In the figure: (a)(b)(c)(d) are schematic diagrams of circuit analysis for shutting down each layer of SiC MOSFET power module;

[0014] Figure 4 A schematic diagram of turning on and off the SiC MOSFET power module circuit of the present invention;

[0015] Figure 5 A flow chart of the power module test of the present invention;

[0016] Figure 6 It is the waveform diagram of the actual switch of the SiC MOSFET power module circuit of the present invention, V3 V2 V1 are the drain-to-ground voltages of Q3 Q2Q1 respectively;

[0017] In the figure: (a) switching waveform without acceleration capacitor module, (b) switching waveform of parallel acceleration capacitor module. DETAILED DESCRIPTION

[0018] like Figure 1 As shown, this embodiment relates to a single-drive gate cascade type high-voltage SiC MOSFET power module circuit, which uses three layers of 2kV SiC MOSFET cascade to realize a 6kV power module, including: three layers of SiC MOSFET Q1-Q3 and their corresponding static voltage balancing resistors R e1 -R e3 , high voltage capacitor C e1 -C e3 , High voltage avalanche diode D e1 -D e3 , transient voltage suppression diode (TVS) Z2-Z3, driving resistor R g1 -R g3 and varistor (MOV) R p1 -R p3 , where: the drain terminal of the bottom SiC MOSFET is connected to the source terminal of the top SiC MOSFET, and each layer has a static voltage-sharing resistor R e1 -R e3 The high voltage end and the corresponding high voltage avalanche diode D e1 -D e3 The anode terminal of each layer is connected to the drain terminal of the corresponding SiC MOSFET. e1 -C e3The high voltage end of the Z2-Z3 is connected to the cathode end of the high voltage avalanche diode. The cathode ends of the transient voltage suppression diodes (TVS) Z2-Z3 are connected to the gate ends of the corresponding SiC MOSFETs. The gate end of each layer of SiC MOSFET is connected in series with a chip drive resistor R g1 -R g3 , the drain terminal and the corresponding varistor R p1 -R p3 The high-voltage end of the SiC MOSFET is connected to the bottom layer, and an acceleration capacitor C is connected in parallel between the drain and source of the SiC MOSFET.

[0019] The voltage U of the voltage-equalizing capacitor under long-term operation C It will present a step-like rise, which is very detrimental to the stability of the module circuit operation. Therefore, each high-voltage capacitor C e1 -C e3 Connect a bleeder resistor R in parallel at both ends l1 -R l3 , a certain amount of charge is discharged in each cycle to slow down or even balance the charge increment in each cycle, so that a constant clamping voltage value is maintained on the high-voltage capacitor.

[0020] like Figure 2-3 As shown, the layer-by-layer opening and closing process of the single-drive gate cascade high-voltage SiC MOSFET power module circuit of this embodiment is shown. The opening stage includes: a pre-charging stage, a bottom layer, a middle layer and a top layer opening stage, and the closing stage includes a bottom layer and a top layer closing stage, a discharge voltage stage and a dynamic voltage balancing stage.

[0021] like Figure 2 As shown in (a), the pre-charging stage refers to: the three SiC MOSFETs Q1-Q3 are all in the off state, and the voltage-equalizing resistors R1-R3 play a voltage-equalizing role in static state. Each device bears 1 / 3 of the line voltage. Assuming that there is no charge in the capacitor initially, after the power module bears the voltage, each capacitor is gradually charged to the corresponding voltage level through the front high-voltage avalanche diode. After that, the diode is turned off and the power module turns to steady state. When the driving signal is applied to Q1, the parasitic capacitance between the gate and the source is charged during the time t0-t1, and V gs1 Gradually rises. At t1, V gs1 Reaching the threshold voltage V th When Q1 starts to conduct, V ds1 Start to descend;

[0022] like Figure 2 (b) shows that the bottom layer opening stage refers to: t1-t2 time V gs1 Continue to rise, C gs Continue charging, V ds1 The voltage continues to drop, but since there is no conduction during this period, the voltage change is small during this time.gs1 Reaching the Miller platform voltage V m When the Miller platform begins, V gs1 、V ds1 unchanged, continue charging for a period of time after V ds1 It continues to decrease and gradually reaches 0. During this period, since the entire power module circuit is not fully turned on and is still in the cut-off state, the voltage shared on other layers of MOSFET will increase slightly, which does not affect the analysis process of the power module;

[0023] like Figure 2 (c) shows that the middle layer opening stage refers to: t3-t4 time V gs1 、V ds1 Continue to change, at t5, V ds1 After it is lower than the driving voltage, the driving voltage passes through D g2 C for Q2 gs Charging, at this time Q2 continues the process of the second mode mentioned above: t5-t6 time V gs2 Rise, V ds2 Decreases and reaches the threshold voltage V at time t6 gs2 Then it starts to decline. t6-t7 continues to charge, t7-t8 enters Miller platform V gs2 、V ds2 It remains unchanged for a period of time. During the time t8-t9, the voltage of Q2 continues to drop and gradually decreases to 0. As in mode 2, the voltage on Q3 increases slightly.

[0024] like Figure 2 As shown in (d), the top layer opening stage refers to: V at a certain time between t8 and t9 ds2 After it is lower than the driving voltage, the driving voltage passes through D g3 C for Q3 gs At this time, Q3 continues the process of the second mode mentioned above until it reaches its threshold voltage at time t9, V ds3 Start to descend, t9-t 10 As the MOSFET voltage V ds From mode 1 to mode 4, the drain-source voltage of the power module gradually decreases to 0, t 10 Afterwards the power module is fully switched on.

[0025] like Figure 3As shown in (a), the bottom-level turn-off stage refers to: the circuit is fully turned on and is equivalent to three SiC MOSFETs in parallel with a large resistor, which can be regarded as an open circuit. Since the parameters of the three SiC MOSFETs are consistent during selection, the voltage is evenly distributed on the three SiC MOSFETs, and this is also a steady state. t1-t2 When the drive voltage changes from positive to negative, the drive diodes are all in the cut-off state, Q1 begins to turn off, and V gs1 Starts to decrease, V ds1 It starts to rise until it passes the Miller platform (t2-t3). During t3-t5, Q1 continues to be turned off, and C gs The charge on Q1 is discharged through the driving resistor. At this time, since Q2 and Q3 are still in the on state, most of the voltage is added on both sides of Q1, and the value is greater than one-third of the line voltage.

[0026] like Figure 3 (b), the top-level shutdown stage refers to: V ds1 After rising, V gs2 Gradually bear the reverse pressure, Q2 starts to close at t4, V ds2 Rising, Q2 turns off at t7, and similarly at V ds2 After rising, V gs3 Gradually bearing the reverse pressure, Q3 starts to turn off at t6, and the power module is completely turned off at t8;

[0027] like Figure 3 As shown in (c), the discharge voltage stage refers to: as the drain-source voltage V ds The voltage of the power module gradually rises to the line voltage. At this time, the circuit is basically turned off and begins to dynamically balance the voltage. The SiC MOSFET Q1 at the bottom layer first reaches 1 / 3 of the line voltage. When it continues to rise, the overshoot voltage is discharged through the dynamic voltage-balancing circuit on the gate side.

[0028] like Figure 3 As shown in (d), the dynamic voltage balancing stage refers to: each layer discharges the overshoot voltage through resistors and capacitors, and Q3 finally reaches 1 / 3 of the external power supply voltage, so it may not need to be discharged. At this point, the circuit is completely turned off, and the internal process is the voltage balancing process of the three gate voltage balancing circuits. After a period of time, the power module returns to the state before it is turned on: the three capacitors are charged to one-third of the line voltage, the high-voltage avalanche diode is cut off, and the three high-voltage resistors are voltage balanced. From mode 5 to mode 8, the drain-source voltage of the cascade module gradually rises to the external power supply voltage, and the power module is completely turned off after t8.

[0029] In the bottom and top shutdown stages, the voltage discharge stage, and the dynamic voltage balancing stage, the circuit undergoes a series of state transitions, forming a dynamic voltage balancing process. The entire process is full of dynamism and complexity. Through precise control and coordination, the circuit can smoothly switch between different modes to achieve voltage balancing and effective energy management. This dynamic balancing design can play a key role in SiC MOSFET power modules to ensure system stability and efficiency.

[0030] like Figure 4 As shown in the figure, the layer-by-layer opening means that when the voltage of the bottom SiC MOSFET Q1 drops to about 0V, the voltage of the middle MOSFET Q2 starts to drop; when the voltage of SiCMOSFET Q2 drops to about 0V, the voltage of the top SiC MOSFET Q3 starts to drop; until all SiC MOSFETs are turned on. The power module is also turned off layer by layer. When the voltage of the bottom MOSFET Q1 rises to a predetermined voltage, the voltage of the middle SiCMOSFET Q2 starts to rise, until the predetermined voltage is reached, the voltage of the top SiCMOSFET Q3 starts to rise; until all SiC MOSFET tubes are turned off.

[0031] After specific experiments, the bus voltage is set to 5kV, the driving voltage is 25V, the driving resistance is 5Ω, and the current is 25A. The turn-off time of the resistive and inductive loads is 190ns and 90ns, respectively, and the turn-on time is 150ns and 90ns, respectively. Under the actual double pulse test, that is, when considering the parasitic inductance and capacitance in the circuit, the turn-on and turn-off time will change slightly. The actual turn-off time is 100ns and the turn-on time is 50ns, which can achieve the effect of fast switching.

[0032] The acceleration capacitor is used to solve the "tail" time caused by the turn-on delay. The change of the drive over time shows a typical RC charging characteristic. There will be a delay in reaching the turn-on voltage. The drive cannot be quickly supplied to the top SiC MOSFET, which manifests as a long "tail" when turning on. The tail time is about 300ns. After adding the parallel acceleration capacitor, the turn-on "tail" is significantly improved, and the "tail" time is reduced to about 150ns. The turn-on time of the power module is about 50ns, and the turn-off time is about 100ns.

[0033] like Figure 6As shown in (a)(b), the power module is built and the waveform of each tube voltage is obtained by measurement. The technical information described is: the opening of the power module is the same as the analysis. When the voltage of the bottom SiCMOSFET Q1 drops to a certain value, the middle SiC MOSFET Q2 can be turned on. After the middle SiC MOSFET Q2 drops completely, the top SiC MOSFET Q3 starts to turn on. During the period when the voltage of Q1 drops, the voltage shared on Q2 and Q3 will increase, but it will not affect the opening of the entire module. The module opening time is 50ns. Since the SiC MOSFET drive shows a typical resistance-capacitance charging characteristic over time, there will be a delay in reaching the opening voltage. The drive cannot be quickly given to the top SiC MOSFET, which is manifested as a long "tail" when turning on. The tail time is about 300ns. When the module is turned off, the bottom SiCMOSFET Q1 is turned off first, and there will be a period of overshoot after turning off. Q2 and Q3 are turned off in turn, and the turn-off time is 100ns. After adding the parallel acceleration capacitor, the turn-on "tailing" is significantly improved, and the "tailing" time is reduced to about 150ns. The turn-on time of the power module is about 50ns, and the turn-off time is about 100ns.

[0034] When the external voltage is 2kV and the driving voltage is 20V, the power module circuit is tested with a double pulse load, and the turn-on and turn-off times are 50ns and 100ns respectively.

[0035] Compared with the prior art, the present invention applies an efficient voltage balancing and protection unit on the gate side. The voltage balancing unit reversely clamps the voltage of the high-voltage capacitor through a high-voltage avalanche diode, so that the steady-state voltage of the power module is maintained at a constant preset voltage. The voltage on a single SiC MOSFET is clamped by the voltage balancing unit each time it is turned on, which can stabilize the dynamic voltage of the power module. In addition, the high-voltage capacitor does not need to be repeatedly charged and discharged, thereby reducing the loss of the power module and effectively improving the dynamic voltage balancing problem in the power module; when statically cut off, the high-voltage avalanche diode isolates the high-voltage capacitor from the static voltage balancing resistor, equivalently cutting off the connection between the high-voltage capacitor and the circuit. In the topology, there is only a cascade of the voltage balancing resistor and the SiCMOSFET. Since the resistance value of the selected voltage balancing resistor is much smaller than the off resistance of the SiC MOSFET, the static voltage division of the SiC MOSFET is determined by the voltage balancing resistor. The voltage balancing unit ensures that the voltage of each device is evenly distributed during steady state and transient state. By connecting the varistor MOV in parallel at both ends of the voltage balancing resistor, when certain faults occur in the cascade module, that is, when the voltage borne by a certain SiC MOSFET exceeds its rated value and overshoot occurs, the voltage at both ends of the capacitor will also be charged to the corresponding level. At this time, the voltage will break down the varistor MOV. After the MOV is broken down by high voltage, it will have a low resistance value, and the current will be discharged through the MOV. No new current will flow through the capacitor, and its clamping voltage will not rise, further protecting the corresponding SiC MOSFET. By adding an acceleration capacitor to the circuit, connected in parallel on both sides of the high-voltage avalanche diode of the gate, the turn-on time of the module can be effectively improved. During the shutdown period of the module, the acceleration capacitor is charged, which is equivalent to a part of the voltage balancing capacitor and accumulates energy. During the opening period of the module, since the acceleration capacitor is not clamped by the reverse high-voltage avalanche diode, it can discharge the SiC MOSFET through the gate drive resistor, accelerate the conduction of the SiC MOSFET, effectively reduce the switching loss, and improve the overall efficiency.

[0036] In summary, the device has a simple structure and a fast switching speed, and can significantly reduce the switching loss and improve the overall efficiency of the power module.

[0037] The above-mentioned specific implementation can be partially adjusted in different ways by those skilled in the art without departing from the principle and purpose of the present invention. The protection scope of the present invention shall be based on the claims and shall not be limited by the above-mentioned specific implementation. Each implementation scheme within its scope shall be subject to the constraints of the present invention.

Claims

1. A single drive gate cascade type high voltage SiC MOSFET power module circuit, characterized in that: include: Three layers of SiC MOSFET and their corresponding static balancing resistors, high-voltage capacitors, high-voltage avalanche diodes, transient voltage suppression diodes (TVS), driving resistors and varistors, wherein: the drain terminal of the bottom SiC MOSFET is connected to the source terminal of the top SiC MOSFET, the high-voltage end of each layer of static balancing resistors is connected to the anode terminal of the corresponding high-voltage avalanche diode, the anode terminal is connected to the drain terminal of the corresponding SiC MOSFET, the high-voltage end of each layer of high-voltage capacitors is connected to the cathode terminal of the high-voltage avalanche diode, the cathode terminals of the three transient voltage suppression diodes (TVS) are respectively connected to the gate terminals of the corresponding SiC MOSFET, the gate terminal of each layer of SiC MOSFET is connected in series with a patch driving resistor, the drain terminal is connected to the high-voltage end of the corresponding varistor, and the varistor (MOV) is connected in parallel to the drain-source terminal of each layer of SiC MOSFET; A discharge resistor is connected in parallel at both ends of each high-voltage capacitor; Acceleration capacitors are connected in parallel on both sides of the high-voltage avalanche diode.

2. The layer-by-layer opening driving method of the single-drive gate cascade high-voltage SiC MOSFET power module circuit according to claim 1 is characterized in that: include: Pre-charging stage, bottom, middle and top layer turn-on stage, bottom and top layer turn-off stage, voltage discharge stage and dynamic voltage balancing stage; The layer-by-layer turning on means that the voltages of the bottom, middle and top SiC MOSFETs decrease in sequence until all SiC MOSFETs are turned on, or increase in sequence until all SiC MOSFETs are turned off.

3. The layer-by-layer activation driving method according to claim 2, characterized in that: The pre-charging stage means that all SiC MOSFETs in the circuit are in the off state, and the voltage-equalizing resistor plays a voltage-equalizing role in static state. Each device bears 1 / 3 of the line voltage. Assuming that there is no charge in the capacitor initially, after the module bears the voltage, each capacitor is gradually charged to the corresponding voltage level through the front high-voltage avalanche diode. The diode is cut off and turned on, and the module switches to a steady state. When a driving signal is applied to the bottom SiC MOSFET, the parasitic capacitance between the gate and the source is charged during the t0-t1 time, and Vgs1 gradually rises. At t1, when Vgs1 reaches the threshold voltage Vth, the bottom MOSFET starts to turn on and Vds1 starts to decrease.

4. The layer-by-layer activation driving method according to claim 3 is characterized in that: The bottom layer turn-on stage refers to: during the time t1-t2, Vgs1 continues to rise, Cgs continues to charge, and Vds1 continues to decrease. However, since there is no conduction during this period, the voltage change during this time is small. During the time t2-t3, when Vgs1 reaches the Miller platform voltage Vm, it begins to enter the Miller platform. Vgs1 and Vds1 remain unchanged for a period of time. After charging for a period of time, Vds1 continues to decrease and gradually reaches 0. During this period, since the entire power module circuit is not fully turned on and is still in the off state, the voltage shared on other layers of MOSFET will increase slightly, which will not affect the analysis process of the module.

5. The layer-by-layer activation driving method according to claim 4 is characterized in that: The middle-layer opening stage refers to: during t3-t4, Vgs1 and Vds1 continue to change; at t5, after Vds1 is lower than the driving voltage, the driving voltage charges the Cgs of the middle-layer SiC MOSFET. At this time, the middle-layer SiC MOSFET continues the process of the aforementioned bottom-layer opening stage: during t5-t6, Vgs2 rises and Vds2 drops; at t6, it reaches the threshold voltage Vgs2 and then starts to drop; during t6-t7, it continues to charge; during t7-t8, it enters the Miller platform and Vgs2 and Vds2 remain unchanged for a period of time; during t8-t9, the voltage of the middle-layer MOSFET continues to drop and gradually decreases to 0; as in the bottom-layer opening stage, the voltage on the top-layer SiC MOSFET increases slightly.

6. The layer-by-layer activation driving method according to claim 5, characterized in that: The top-layer turn-on stage refers to: after Vds2 is lower than the driving voltage at a certain moment during t8-t9, the driving voltage charges Cgs of the top-layer SiC MOSFET. At this time, the top-layer SiC MOSFET continues the aforementioned bottom-layer turn-on stage process until it reaches its threshold voltage at t9, and Vds3 begins to decrease. During t9-t10, the voltage of the top-layer SiC MOSFET gradually decreases to 0, as the voltage Vds of the SiC MOSFET layer by layer continues to decrease.

7. The layer-by-layer activation driving method according to claim 6, characterized in that: The bottom-layer turn-off stage refers to: the circuit is fully turned on and is equivalent to three SiC MOSFETs in parallel with a large resistor, which can be regarded as an open circuit. Since the parameters of the three-layer SiC MOSFET are consistent during selection, that is, the voltage is evenly distributed in a steady state; t1-t2 when the driving voltage changes from positive to negative, the driving diodes are all in the cut-off state, the bottom-layer SiC MOSFET begins to turn off, Vgs1 begins to decrease, and Vds1 begins to rise until it passes the Miller platform (t2-t3). During t3-t5, the bottom-layer SiC MOSFET continues to be turned off, and the charge on Cgs is discharged through the driving resistor. At this time, since the middle-layer SiC MOSFET and the top-layer SiC MOSFET are still in the on state, most of the voltage is applied to both sides of the bottom-layer SiC MOSFET, and the value is greater than one-third of the line voltage.

8. The layer-by-layer activation driving method according to claim 7, characterized in that: The top-layer turn-off stage means that after Vds1 rises, Vgs2 gradually bears the reverse pressure, the middle-layer SiC MOSFET starts to turn off at t4, Vds2 rises, and the middle-layer SiC MOSFET is turned off at t7. Similarly, after Vds2 rises, Vgs3 gradually bears the reverse pressure, and the top-layer MOSFET starts to turn off at t6, until the module is completely turned off at t8.

9. The layer-by-layer activation driving method according to claim 8, characterized in that: The voltage discharge stage means that as the drain-source voltage Vds of the MOSFET layer by layer continues to rise, the voltage of the cascade module gradually rises to the line voltage. At this time, the circuit is basically turned off and begins to dynamically balance the voltage. The bottom SiC MOSFET first reaches 1 / 3 of the line voltage. When it continues to rise, the overshoot voltage is discharged through the dynamic voltage balancing circuit on the gate side.

10. The layer-by-layer activation driving method according to claim 9, characterized in that: The dynamic voltage balancing stage refers to: each layer discharges the overshoot voltage through resistors and capacitors, and the top-layer SiC MOSFET finally reaches 1 / 3 of the external power supply voltage, so it may not need to be discharged. At this point, the circuit is completely turned off, and the internal process is the voltage balancing process of the three gate voltage balancing circuits. After a period of time, the cascade module returns to the state before it is turned on: the three capacitors are charged to one-third of the line voltage, the high-voltage avalanche diode is cut off, and the three high-voltage resistors are voltage-balanced.

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