Successive approximation analog-to-digital converter circuit and reference voltage circuit thereof

Abstract

The present application relates to a successive approximation analog-to-digital converter circuit and a reference voltage circuit thereof, the successive approximation analog-to-digital converter circuit comprising: an analog-to-digital conversion section for converting an analog signal into a digital signal according to a reference voltage; the reference voltage circuit is used for providing reference voltage for the analog-to-digital conversion part and comprises a starting circuit and an operational amplifier circuit, and two output ends of the starting circuit are respectively connected with two input ends of the operational amplifier circuit; the operational amplifier circuit comprises a seventh PMOS (P-channel Metal Oxide Semiconductor) tube, a tenth PMOS tube, an eleventh PMOS tube, a ninth NMOS (N-channel Metal Oxide Semiconductor) tube, a twelfth NMOS tube, a differential amplifier and a magnetic tunnel junction, a grid electrode of the seventh PMOS tube and a grid electrode of the tenth PMOS tube are connected with an output end of the differential amplifier, and a grid electrode of the ninth NMOS tube and a grid electrode of the twelfth NMOS tube are respectively connected with two input ends of the differential amplifier. The problem that in an existing successive approximation type analog-to-digital converter circuit, a reference voltage circuit cannot provide stable voltage for an analog-to-digital converter is solved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a successive approximation analog-to-digital converter circuit and a reference voltage circuit thereof. Background Art

[0002] With the continuous development of application fields such as 5G communication systems and the Internet of Things and the continuous development of CMOS technology, the performance of the original communication equipment can no longer meet the growing demand for communication applications. This has prompted communication equipment to develop in the direction of providing higher communication bandwidth, faster data transmission rate, and more stable performance in a changing environment. Among the many types of ADCs, the successive approximation analog to digital converter (SAR ADC) has a more balanced performance in terms of sampling rate, accuracy, energy efficiency, etc. Therefore, among the many types of ADCs, SAR ADC can be applied to portable / battery-powered instruments, pen input quantizers, industrial control, and data / signal acquisition, etc., with its low power consumption, high resolution, high accuracy, and relatively simple structure compared to other ADCs, becoming one of the most widely used ADCs at present. Under the dual pressure of rising user demand and Moore's Law continuously promoting the improvement of integration, SAR ADC is facing new challenges of evolving to higher accuracy, lower power consumption, and more stable conversion.

[0003] However, the reference voltage circuit in the current successive approximation analog-to-digital converter circuit cannot provide a relatively stable voltage to the analog-to-digital converter, and thus the analog-to-digital conversion stability of the successive approximation analog-to-digital converter circuit is relatively low. Summary of the invention

[0004] The present invention provides a successive approximation type analog-to-digital converter circuit and a reference voltage circuit thereof to solve the problem that the reference voltage circuit in the current successive approximation type analog-to-digital converter circuit cannot provide a relatively stable voltage to the analog-to-digital converter, thereby causing the analog-to-digital conversion stability of the successive approximation type analog-to-digital converter circuit to be low.

[0005] In a first aspect, the present invention provides a successive approximation analog-to-digital converter circuit, comprising: An analog-to-digital conversion section for converting an analog signal into a digital signal according to a reference voltage; A reference voltage circuit for providing the reference voltage to the analog-to-digital conversion part, wherein the reference voltage circuit comprises a start-up circuit and an operational amplifier circuit, wherein two output terminals of the start-up circuit are respectively connected to two input terminals of the operational amplifier circuit; The operational amplifier circuit includes a seventh PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a ninth NMOS tube, a twelfth NMOS tube, a differential amplifier and a magnetic tunnel junction, the source of the seventh PMOS tube and the tenth PMOS tube are connected to a power supply, the source of the ninth NMOS tube is grounded, the source of the twelfth NMOS tube is grounded through the magnetic tunnel junction, the drain of the seventh PMOS tube is connected to the drain of the ninth NMOS tube, the drain of the ninth NMOS tube is connected to the gate, and the gate of the seventh PMOS tube and the gate of the ninth NMOS tube are respectively used as the two input ends of the operational amplifier circuit, the drain of the tenth PMOS tube is connected to the drain of the twelfth NMOS tube, the drain and gate of the twelfth NMOS tube are connected and serve as the output end of the reference voltage circuit, the gate of the seventh PMOS tube and the gate of the tenth PMOS tube are connected to the output end of the differential amplifier, the gate of the ninth NMOS tube and the gate of the twelfth NMOS tube are respectively connected to the two input ends of the differential amplifier, the gate of the eleventh PMOS tube is connected to the gate of the tenth PMOS tube, and the source and drain of the eleventh PMOS tube are both connected to the power supply.

[0006] In a second aspect, the present invention provides a reference voltage circuit, which is the reference voltage circuit in the successive approximation analog-to-digital converter circuit described in the first aspect.

[0007] In a third aspect, the present invention provides a data acquisition device, comprising: Data acquisition sensors, used to sense the external environment to generate analog signals; The successive approximation analog-to-digital converter circuit described in the first aspect is used to convert the analog signal into a digital signal.

[0008] Compared with the related art, the reference voltage circuit of the present invention adopts a magnetic tunnel junction as a load, which can realize adaptive temperature compensation, and the reference voltage circuit can provide a stable reference voltage to the analog-to-digital conversion part, so that the successive approximation analog-to-digital converter circuit can realize stable analog-to-digital conversion. Therefore, in the embodiment of the present invention, a magnetic tunnel junction reference voltage circuit adaptive temperature compensation successive approximation analog-to-digital converter circuit is provided, which can ensure the stability of analog-to-digital conversion within a wide temperature range (large temperature change), improve the reliability of digital output results, and solve the problem that the reference voltage circuit in the current successive approximation analog-to-digital converter circuit cannot provide a relatively stable voltage to the analog-to-digital converter, and thus the analog-to-digital conversion stability of the successive approximation analog-to-digital converter circuit is low.

[0009] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a schematic diagram of a successive approximation analog-to-digital converter circuit provided in an embodiment of the present invention; Figure 2 is a schematic diagram of a dynamic comparator provided in an embodiment of the present invention; Figure 3 is a schematic diagram of a reference voltage circuit provided in an embodiment of the present invention; Figure 4 A temperature characteristic diagram of the mobility and threshold voltage of an NMOS tube in a successive approximation analog-to-digital converter circuit provided in one embodiment of the present invention; Figure 5 A graph showing the variation of the drain current with the gate-source voltage when the NMOS tube is in the saturation region in the successive approximation analog-to-digital converter circuit provided by one embodiment of the present invention; Figure 6 This is the temperature characteristic image of the magnetic tunnel junction (MTJ); Figure 7 The output reference voltage of the reference voltage circuit provided in the embodiment of the present invention varies with the power supply voltage under a wide temperature range when the load is a resistor, and the Monte Carlo simulation result of the reference voltage when the power supply voltage is 0.9V under normal temperature conditions (27°C); Figure 8 The output reference voltage of the reference voltage circuit provided in the embodiment of the present invention varies with the power supply voltage under a wide temperature range when the load is MTJ, and the Monte Carlo simulation result of the reference voltage when the power supply voltage is 0.9V under normal temperature conditions (27°C); Fig. 9 A graph showing a change in a reference voltage output by the reference voltage circuit with a power supply voltage when the MTJ in the reference voltage circuit has different temperature coefficients in the successive approximation analog-to-digital converter circuit provided in an embodiment of the present invention; Fig.10 The figure is a comparison diagram of linearity under different loads in a reference voltage circuit in a successive approximation analog-to-digital converter circuit provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0011] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0012] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with general skills in the technical field to which this application belongs. The words "one", "a", "the", "these" and the like in this application do not indicate a quantitative limitation, and they may be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there may be three relationships, for example, "A and / or B" may mean: A exists alone, A and B exist at the same time, and B exists alone. Generally, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0013] In an embodiment of the present invention, a successive approximation analog-to-digital converter circuit is provided. Figure 1 is a schematic diagram of a successive approximation analog-to-digital converter circuit provided in an embodiment of the present invention, such as Figure 1 As shown, the successive approximation analog-to-digital converter circuit in this embodiment includes: an analog-to-digital conversion part for converting an analog signal into a digital signal according to a reference voltage and a reference voltage circuit (also referred to as a Beta multiplier or a Beta multiplier reference voltage circuit) for providing a reference voltage to the analog-to-digital conversion part.

[0014] The analog-to-digital conversion part may include a sampling and holding circuit, a comparator, a logic control module, a successive approximation register, a data output register and a digital-to-analog converter.

[0015] At the circuit structure level, the output end of the sampling and holding circuit and the output end of the digital-to-analog converter are respectively connected to the positive input end and the negative input end of the comparator, the output end of the comparator is connected to the input end of the logic control module, the output end of the logic control module is connected to the input end of the successive approximation register, the output end of the successive approximation register is respectively connected to the input end of the data output register and the first input end of the digital-to-analog converter, and the output end of the reference voltage circuit is connected to the second input end of the digital-to-analog converter.

[0016] At the data processing level, the sampling and holding circuit is used to receive an external analog signal and discretize the analog signal in the time domain. The comparator is used to compare the output of the sampling and holding circuit with the output of the digital-to-analog converter and output the comparison result. The logic control module is used to enable the successive approximation register according to the output of the comparator and the clock signal. The successive approximation register is used to output a digital signal corresponding to the analog signal through a data output register. The digital-to-analog converter is used to output a reference signal based on the digital signal and a reference voltage.

[0017] It should be noted that the architecture of the analog-to-digital conversion part can adopt a relatively mature analog-to-digital conversion architecture in the prior art.

[0018] Among them, the digital-to-analog converter may include a latch, a switch circuit, a resistor network and a summing circuit; the input and output ends of the latch are respectively connected to the output end of the successive approximation register and the control end of the switch circuit, the latch outputs a control signal of the switch circuit according to the digital signal, the output end of the reference voltage circuit is connected to the input end of the summing circuit through the switch circuit and the resistor network, the output end of the summing circuit is connected to the negative input end of the comparator, and the summing circuit is used to output a reference signal according to the reference voltage signal.

[0019] Specifically, the switching circuit includes multiple switches in parallel, the first ends of the multiple switches are connected to the output end of the reference voltage circuit, the resistor network includes multiple resistors in parallel, the second ends of the multiple switches are respectively connected to the first ends of the multiple resistors, the second ends of the multiple resistors are connected to the input end of the summing circuit, and the latch has multiple outputs to control the multiple switches respectively.

[0020] Reference Figure 1 In the digital-to-analog converter part, the switch circuit is exemplarily composed of n+1 switches connected in parallel (S 0 To S n ), the resistor network consists of n+1 parallel resistors (with resistance values ​​of R / 2 0 To R / 2 n ), each switch corresponds to each resistor, and the corresponding switches and resistors are connected in series. The latch has a total of n+1 outputs (D 0 To D n ). For example, the output D of the latch 0 For control switch S 0 , switch S 0 The resistance is R / 2 0 The resistor in series, the latch output D n For control switch S n , switch S n The resistance is R / 2 nThe summing circuit may use an operational amplifier A, the second end of each resistor is connected to the positive input terminal of the operational amplifier A, the negative input terminal of the operational amplifier A is grounded, the positive input terminal of the operational amplifier A is also connected to the output terminal through a resistor, and the output terminal of the operational amplifier A constitutes the output terminal of the digital-to-analog converter.

[0021] When the digital-to-analog converter of the above structure is used, the relationship between the reference signal and the reference voltage is:

[0022] in, v o represents the reference signal, V REF represents the reference voltage, n Indicates the maximum number of latch outputs. D i Represents the i-th output of the latch.

[0023] The sample-and-hold circuit works when the internal switch is closed. The sample-and-hold circuit may include two switches and a first-order RC circuit, wherein the first-order RC circuit is arranged between the two switches, that is, a resistor in the RC circuit is connected in series between the two switches, and the resistor in the RC circuit is grounded through a capacitor.

[0024] The comparator is preferably a dynamic comparator formed by a latch, which compares the output of the sampling and holding circuit with the output of the digital-to-analog converter when the clock signal is at a falling edge.

[0025] Specifically, refer to Figure 2The dynamic comparator includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a fifth PMOS tube P1-P5 and a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube N1-N6; the sources of the fourth PMOS tube P4, the first PMOS tube P1 and the fifth PMOS tube P5 are connected to the power supply VDD, the sources of the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube N1-N6 are grounded, the gate of the first PMOS tube P1 is used to access the clock signal CLK, the drain of the first PMOS tube P1 is connected to the sources of the second PMOS tube P2 and the third PMOS tube P3 and forms a first node NET1, the gate VIP of the second PMOS tube P2 serves as the positive input terminal of the dynamic comparator, the gate VIN of the third PMOS tube serves as the negative input terminal of the dynamic comparator, and the gate VIN of the second PMOS tube P The drain of the fourth PMOS tube P4 is connected to the drain of the second NMOS tube N2 and the gate of the third NMOS tube N3 to form a second node NET2, the drain of the third PMOS tube P3 is connected to the drain of the third NMOS tube N3 and the gate of the second NMOS tube N2 to form a third node NET3; the gate of the fourth PMOS tube P4, the gate of the fifth NMOS tube N5 and the drain of the first NMOS tube N1 are all connected to the second node NET2, the drain of the fourth PMOS tube P4 is connected to the drain of the fifth NMOS tube N5 and form a first output node CP of the dynamic comparator, the gate of the first NMOS tube N1 is used to access the clock signal CLK, the gate of the fifth PMOS tube P5, the gate of the sixth NMOS tube N6 and the drain of the fourth NMOS tube N4 are all connected to the third node NET3, the drain of the fifth PMOS tube P5 is connected to the drain of the sixth NMOS tube N6 and form a second output node CN of the dynamic comparator, and the gate of the fourth NMOS tube N4 is used to access the clock signal CLK. The first output node CP and the second output node CN together constitute the output end of the dynamic comparator and are connected to the input end of the logic control module. The dynamic comparator selectively outputs a corresponding signal at the first output node CP or the second output node CN based on the comparison result.

[0026] The logic control module mainly includes components such as dynamic latches, D flip-flops and delay circuits. The logic control module generates corresponding enable signals to the successive approximation register through sampling signals, clock signals and the output signals of the comparator, and controls the digital signal output of the successive approximation register.

[0027] The successive approximation register is composed of cascaded D flip-flops, and the output signal of the logic control module controls the D flip-flops to output digital signals to the data output register and the latch in the digital-to-analog converter.

[0028] The data output register outputs the digital signal output by the successive approximation register through the storage circuit when the read signal is high, thereby realizing the conversion from analog signal to digital signal.

[0029] It should be noted that the analog-to-digital conversion part in the successive approximation analog-to-digital converter circuit is not the focus of improvement of the present invention, and its overall architecture is an existing mature technology. At the same time, the existing mature sampling and holding circuit, logic control module, successive approximation register, data output register and digital-to-analog converter can be selected for construction. The working principle and specific structure of each part are mature technologies, so the working principle and specific structure of each part are not specifically introduced above. The focus of the present invention is to optimize the reference voltage circuit in the successive approximation analog-to-digital converter circuit.

[0030] The reference voltage circuit comprises a start-up circuit and an operational amplifier circuit, and two output terminals of the start-up circuit are respectively connected to two input terminals of the operational amplifier circuit.

[0031] Among them, refer to Figure 3 The operational amplifier includes a seventh PMOS tube P7, a tenth PMOS tube P10, an eleventh PMOS tube P11, a ninth NMOS tube N9, a twelfth NMOS tube N12 and a magnetic tunnel junction MTJ. The sources of the seventh PMOS tube P7 and the tenth PMOS tube P10 are connected to the power supply VDD, the source of the ninth NMOS tube N9 is grounded, the source of the twelfth NMOS tube N12 (the tenth node NET10) is grounded through the magnetic tunnel junction MTJ (the T1 end of the magnetic tunnel junction MTJ is connected to the tenth node NET10 and the T2 end is connected to the ground), the drain of the seventh PMOS tube P7 is connected to the drain of the ninth NMOS tube N9, the drain and gate of the ninth NMOS tube N9 are connected, and the seventh PMOS tube The gate of P7 and the gate of the ninth NMOS tube N9 are respectively used as two input terminals of the operational amplifier circuit, the drain of the tenth PMOS tube P10 is connected to the drain of the twelfth NMOS tube N12, the drain and gate of the twelfth NMOS tube N12 are connected and serve as the output terminal VREF of the reference voltage circuit, the gate of the seventh PMOS tube P7 and the gate of the tenth PMOS tube P10 are connected to the output terminal of the differential amplifier, the gate of the ninth NMOS tube N9 and the gate of the twelfth NMOS tube N12 are respectively connected to the two input terminals of the differential amplifier, the gate of the eleventh PMOS tube P11 is connected to the gate of the tenth PMOS tube P10, and the source and drain of the eleventh PMOS tube P11 are both connected to the power supply VDD.

[0032] The differential amplifier may include an eighth PMOS tube P8, a ninth PMOS tube P9, a tenth NMOS tube N10 and an eleventh NMOS tube N11, the sources of the eighth PMOS tube P8 and the ninth PMOS tube P9 are connected to the power supply VDD, the sources of the tenth NMOS tube N10 and the eleventh NMOS tube N11 are grounded, the gate of the eighth PMOS tube P8 is connected to the gate of the ninth PMOS tube P9 and constitutes a ninth node NET9, the drain of the eighth PMOS tube P8 is connected to the ninth node NET9 and the drain of the tenth NMOS tube N10, the drain of the ninth PMOS tube P9 is connected to the drain of the eleventh NMOS tube N11 and constitutes a seventh node NET7, the gate of the seventh PMOS tube P7 and the gate of the tenth PMOS tube P10 are both connected to the seventh node NET7, the gate of the tenth NMOS tube N10 is connected to the gate of the twelfth NMOS tube N12, and the gate of the eleventh NMOS tube N11 is connected to the gate of the ninth NMOS tube N9 and constitutes an eighth node NET8.

[0033] The startup circuit may include a sixth PMOS tube P6, a seventh NMOS tube N7 and an eighth NMOS tube N8, the source of the sixth PMOS tube P6 is connected to the power supply VDD, the source of the seventh NMOS tube N7 is grounded, the drain of the sixth PMOS tube P6 and the drain of the seventh NMOS tube N7 are connected and form a sixth node NET6, the gate of the sixth PMOS tube P6 and the gate of the eighth NMOS tube N8 are both connected to the sixth node NET6, the gate of the seventh NMOS tube N7 is connected to the source of the eighth NMOS tube N8, and the drain and source of the eighth NMOS tube N8 are respectively connected to the gate of the seventh PMOS tube P7 and the gate of the ninth NMOS tube N9. The startup circuit is composed of two NMOS tubes and one PMOS tube, and the MOS tube is in a saturation region and connected to the operational amplifier circuit.

[0034] As follows, the operation process of the successive approximation analog-to-digital converter circuit in the above embodiment is described through a specific example.

[0035] In the above-mentioned successive approximation analog-to-digital converter circuit: the sampling and holding circuit is used to discretize the continuous analog signal from real life in the time domain dimension to become a discrete analog signal; the comparator module compares the discrete analog signal with the output result of the digital-to-analog converter, and sends the comparison result COMPB to the dynamic latch in the logic control module; the logic control module processes the comparator result COMPB, the sampling signal SAMPLEB, and the clock signal CLK through the dynamic latch, D flip-flop, and delay circuit respectively, and finally outputs the result to the successive approximation register to control the output of the digital signal; the successive approximation memory is composed of cascaded D flip-flops, etc., and the signal from the logic control module is output as a digital signal result through the D flip-flop; the data output register is composed of a latch, and when the read signal is high, the digital result is output; the digital-to-analog converter module integrates an n-bit digital input latch, a receiving reference voltage V REF A resistor network as input and a summing circuit, V REF The output of the AND latch passes through the resistor network to generate an analog output signal v o (output of the digital-to-analog converter) and used as one of the input signals of the comparator. V REF and v o There is a specific functional relationship between them: (1) The reference voltage circuit consists of a startup circuit and an operational amplifier, and uses MTJ (magnetic tunnel junction) as a load to generate a reference voltage with a low temperature coefficient. Compared with the traditional reference voltage circuit, this reference voltage circuit significantly reduces V REF The sensitivity to VDD. By setting a differential amplifier, the degree to which the source-drain voltage of the ninth NMOS transistor N9 and the twelfth NMOS transistor N12 fluctuates with VDD can be weakened. The left part is the startup circuit, which is composed of three MOS transistors. The gate potential of the seventh NMOS transistor N7 is maintained at VDD-V THPTo VDD range, effectively prevent the possibility of current zeroing phenomenon in the reference voltage circuit. The eighth NMOS tube N8 acts as a switch, guiding the current from the gate of the seventh PMOS tube P7 and the tenth PMOS tube P10 to the gate of the ninth NMOS tube N9 and the twelfth NMOS tube N12. Under normal working conditions, the current flowing through the eighth NMOS tube N8 is almost zero. The drain voltage of the ninth NMOS tube N9 and the twelfth NMOS tube N12 is used as the input signal of the differential amplifier, and the output of the differential amplifier is connected to the gate of the seventh PMOS tube P7 and the tenth PMOS tube P10. It is worth noting that the gate and drain of the tenth PMOS tube P10 no longer follow the diode connection method. This change enables the drain voltage of the tenth PMOS tube P10 to maintain the same potential level as the drain voltage of the twelfth NMOS tube N12, thereby ensuring that the drain voltages of the ninth NMOS tube N9 and the twelfth NMOS tube N12 are accurately adjusted to be equal through the action of the amplifier, ensuring the output V REF Stability to VDD changes. In addition, the design also uses the eleventh PMOS tube P11 with source and drain interconnected as an equivalent critical capacitor, which further enhances the stability of the output reference voltage. It should be noted that since the twelfth NMOS tube N12 is connected to a load, the width-to-length ratio between the twelfth NMOS tube N12 and the tenth NMOS tube N10 is k; the width-to-length ratio of the seventh PMOS tube P7 and the tenth PMOS tube P10 is k1 times that of the differential amplifier MOS tube, and k≠k1. Assume that the width-to-length ratio of the tenth NMOS tube N10 is , the width-to-length ratio of the twelfth NMOS tube N12 , then there is a relationship between the two: (2) Reference Figure 3 The ninth NMOS tube N9, the eleventh NMOS tube N11 and the eighth PMOS tube P8 respectively form a current mirror. The ninth PMOS tube P9, the tenth NMOS tube N10 and the twelfth NMOS tube N12 form a current mirror. There are three pairs of current mirrors, and their currents are assumed to be I 1 、I 2 、 I 3 , the current flowing through the MTJ is assumed to be I REF , then these currents have the following relationship: (3) Moreover, the gate and drain of the ninth NMOS tube N9 and the gate and drain of the twelfth NMOS tube N12 are at the same potential respectively. V GS1 andV GS2 MTJ is in high impedance state at this time, and its resistance is R AP . From this we can get: (4) When the MOS tube is in the saturation region, there is a drain current formula: (5) The drain current is I D , , is the electron mobility, is the capacitance of the gate oxide layer, the gate-source voltage V GS , threshold voltage V TH , electron mobility and the gate oxide capacitance It can also be expressed as: , (6) Therefore, equation (5) can be transformed into the equation for gate-source voltage: (7) Substituting equation (7) into equation (4) yields: (8) From equation (2), equation (8) can be transformed into I REF Equation (9), k is the ratio of the width to length ratio of the twelfth NMOS transistor N12 to the tenth NMOS transistor N10: (9) Substituting (9) into equation (7): (10) To obtain a reference voltage that is independent of temperature, the equation (10) should be differentiated with temperature as the independent variable. The partial derivative should be equal to 0: (11) It can be deduced from equation (11) that the output of the reference voltage circuit and the temperature-independent load should satisfy the following equation: (12) In MTJ, the mechanism of TMR effect is spin-related tunneling effect. By applying an external magnetic field, the magnetization direction of the two ferromagnetic layers can be changed, so that the tunneling resistance changes, resulting in the emergence of TMR effect. The resistance value of MTJ in high resistance state and low resistance state is expressed as RAP and R P , then the spin polarization of the two ferromagnetic layer electrodes in the MTJ can be defined as: (13) TMR can be quantified as an equation that is negatively correlated with temperature, (14) in, TMR 0 is the TMR ratio at zero temperature, and Q represents the probability of the appearance of magnons during the tunneling process, which are used as fitting parameters. β AP =Sk B T / E m ,in S is the spin parameter, k B is the Boltzmann constant, E m Curie temperature of ferromagnetic electrodes E m = 3k B T / (S+1) related, E c is the cutoff energy of the magnon energy. From equation (14), it can be concluded that TMR is negatively correlated with temperature T, which results in a reduced sensitivity to temperature. From equation (13), it can be deduced that TMR is negatively correlated with temperature T. R AP is positively correlated, so the resistance value of MTJ in high resistance state R AP It shows a negative correlation with temperature. Figure 6 The simulation results show the same trend.

[0036] Depend on Figure 4 It can be seen that the threshold voltage and mobility of the MOS tube both show a downward trend with increasing temperature, that is, both have negative temperature coefficients. Figure 7 It can be seen that when the load is a common resistor, its temperature characteristics are regarded as ideal, that is, the temperature coefficient is 0, and the output reference voltage is V REF The temperature characteristics of are mainly affected by the twelfth NMOS tube N12. Since the mobility and threshold voltage of the MOS tube are affected by temperature to different degrees, the threshold voltage is more affected by temperature. From equation (11), it can be concluded that the output voltage when the load is a resistor is V REFWhen VDD=0.9, there is a positive temperature coefficient as the temperature rises. Therefore, the ordinary resistor is replaced with the MTJ with a negative temperature coefficient to compensate for the positive temperature coefficient of the MOS tube, thereby achieving compensation for the output voltage.

[0037] From the above derivation, it can be seen that the MTJ resistance when the resistance of the magnetic tunnel junction is in the high resistance state is R AP When the reference voltage is set properly, the reference voltage circuit outputs the reference voltage V REF The temperature dependency can be reduced, that is, the reference voltage output by the reference voltage circuit is less affected by temperature.

[0038] In addition, the differential amplifier attenuates the power supply voltage VDD to the output reference voltage V REF The impact of V REF The differential amplifier is an operational amplifier. The drain voltage of the ninth NMOS tube N9 and the twelfth NMOS tube N12 is used as the input signal of the differential amplifier to "virtually short", so that the input signal potential is equal. The output end of the differential amplifier is connected to the gate of the seventh PMOS tube P7 and the tenth PMOS tube P10, ensuring that the drain voltage of the ninth NMOS tube N9 and the twelfth NMOS tube N12 is accurately adjusted to be equal through the action of the amplifier, ensuring the stability of the output VREF to the change of VDD, so that the output reference voltage V REF The sensitivity to VDD is reduced and the linearity is improved.

[0039] In summary, the reference voltage circuit uses a magnetic tunnel junction as a load, which can realize adaptive temperature compensation, and the reference voltage circuit can provide a stable reference voltage to the analog-to-digital conversion part, so that the successive approximation analog-to-digital converter circuit can realize stable analog-to-digital conversion. Therefore, in the embodiment of the present invention, a magnetic tunnel junction reference voltage circuit adaptive temperature compensation successive approximation analog-to-digital converter circuit is provided, which can ensure the stability of analog-to-digital conversion within a wide temperature range (large temperature change), improve the reliability of digital output results, and solve the problem that the reference voltage circuit in the current successive approximation analog-to-digital converter circuit cannot provide a relatively stable voltage to the analog-to-digital converter, and thus the analog-to-digital conversion stability of the successive approximation analog-to-digital converter circuit is low.

[0040] The performance of the successive approximation analog-to-digital converter circuit and its device characteristics are described in detail as follows.

[0041] Figure 4 The temperature characteristic diagram of the mobility and threshold voltage of the NMOS tube in the successive approximation analog-to-digital converter circuit provided by one embodiment of the present invention. Figure 4 The majority carriers in NMOS are electrons. As the temperature increases, the probability of carriers being scattered in the channel increases. Therefore, the mobility of NMOS decreases with increasing temperature; the threshold voltage also shows a decreasing trend with increasing temperature.

[0042] Figure 5 The following is a graph showing the variation of the drain current with the gate-source voltage when the NMOS tube is in the saturation region in the successive approximation analog-to-digital converter circuit provided by one embodiment of the present invention. The drain current of the NMOS tube in the saturation region has a functional relationship with the gate-source voltage:

[0043] With gate-source voltage V GS The drain current I D shows an upward trend, when the gate-source voltage V GS When fixed, temperature changes can affect mobility and threshold voltage V TH , they all decrease with increasing temperature, but the threshold voltage V TH The impact on NMOS is greater, so the drain current of NMOS I D The overall trend is increasing with the increase of temperature.

[0044] The MTJ used as a load in the reference voltage circuit has a more special temperature characteristic. The MTJ consists of two magnetic material layers, namely the pinned layer (PL) and the free layer (FL) and the oxide barrier layer (BL). The magnetic orientation of the pinned layer is not easy to change, while the magnetic orientation of the free layer is relatively easy to change. The resistance state of the MTJ is determined by the relative magnetic orientation of the two ferromagnetic layers. When the magnetic orientations of the two ferromagnetic layers are in the same direction (Parallel, P-state) or in opposite directions (Anti-parallel, AP-state), the MTJ is in a low resistance state or a high resistance state, respectively. Therefore, the MTJ can be used as a storage unit for binary data, with the low resistance state as logic "0" and the high resistance state as logic "1". Figure 6 This is the temperature characteristic image of the magnetic tunnel junction (MTJ). When the MTJ is in a high-resistance state, its resistance changes with the voltage difference between the two ends. The simulation image shows that when the voltage difference between the two ends of the MTJ is fixed, its resistance changes with the temperature. When the temperature rises, the MTJ resistance shows a decreasing trend. That is, the resistance temperature coefficient of the MTJ in the high-resistance state is negative, so the MTJ compensates for the positive temperature coefficient of the NMOS formed by temperature.

[0045] When the load of the reference voltage circuit in the successive approximation analog-to-digital converter circuit provided by the embodiment of the present invention is a resistor (the magnetic tunnel junction is replaced by a resistor), the output reference voltage changes with the power supply voltage under a wide temperature range and the Monte Carlo simulation result of the reference voltage when the power supply voltage is 0.9V under normal temperature conditions (27°C) are shown in the figure below. Figure 7 As shown. The x-axis of the image is the power supply voltage, the y-axis is the output reference voltage, and the z-axis is the temperature. From the image, it can be seen that when the power supply voltage is at least 0.7V, a stable reference voltage can be output. When the power supply voltage is 0.9V, the reference voltage at room temperature is simulated by Monte Carlo simulation, and the sampling is 5000 times. The average reference voltage under this condition is 501.681mV, and the variance is 172.963mV, which is in a relatively unstable state.

[0046] When the load of the reference voltage circuit in the successive approximation analog-to-digital converter circuit provided by the embodiment of the present invention is MTJ, the output reference voltage changes with the power supply voltage under a wide temperature range and the Monte Carlo simulation result of the reference voltage when the power supply voltage is 0.9V under normal temperature conditions (27°C) are shown in the figure. Figure 8 As shown. The x-axis of the image is the power supply voltage, the y-axis is the output reference voltage, and the z-axis is the temperature. From the image, it can be seen that when the power supply voltage is at least 0.6V, a stable reference voltage can be output. When the power supply voltage is 0.9V, the reference voltage at room temperature is simulated by Monte Carlo simulation, and the sampling is 5000 times. The average reference voltage under this condition is 454.6mV, the variance is 6.882mV, and the stability is greatly improved.

[0047] like Fig. 9 The figure shows a comparison of linearity under different loads in the reference voltage circuit in the successive approximation analog-to-digital converter circuit provided by an embodiment of the present invention. When the load of the reference voltage circuit is a resistor, the linearity of the output reference voltage is 2.3% / V within a certain power supply voltage range. When the load is replaced by an MTJ, the stable reference voltage output power supply voltage range is expanded, and the linearity is reduced to 0.57% / V within this range, and the output voltage is more stable.

[0048] like Fig.10 The figure shows the simulation results of noise and power supply rejection ratio of the reference voltage circuit in the successive approximation analog-to-digital converter circuit provided by the embodiment of the present invention when the load is a resistor and a magnetic tunnel junction respectively. It can be seen from the figure that under normal temperature, the output noise is reduced from 260.3uV / sqrt(Hz)@10Hz when the resistor is used as the load to 69.7uV / sqrt(Hz)@10Hz when the MTJ is used as the load; the power supply rejection ratio is increased from 31.7dB@10Hz when the resistor is used as the load to 62.1dB@10Hz. The beta multiplier structure disclosed in the present invention has improved output result stability.

[0049] It can be seen from the above description that the successive approximation analog-to-digital converter circuit in the above embodiment has the following technical effects.

[0050] 1. The stability of analog-to-digital conversion can be guaranteed within a wide temperature range, improving the reliability of digital output results.

[0051] 2. The beta multiplier uses MTJ as the load, which reduces the temperature coefficient and improves the linearity within a certain power supply voltage range. The output noise and power supply rejection ratio are also reduced accordingly. No peripheral circuits are introduced, which reduces power consumption and area overhead.

[0052] 3. In the present invention, the reference voltage is provided as one of the inputs of the comparator through a digital-to-analog converter, and there is a functional relationship between the two. When the reference voltage is relatively stable within a wide temperature range, the comparator input will become more stable accordingly, reducing the voltage difference between the two inputs caused by temperature and ensuring the correctness of the comparison structure.

[0053] A reference voltage circuit is also provided in an embodiment of the present invention. The reference voltage circuit is a reference voltage circuit in a successive approximation analog-to-digital converter circuit provided in an embodiment of the present invention.

[0054] Specifically, the reference voltage circuit includes a start-up circuit and an operational amplifier circuit, and two output terminals of the start-up circuit are respectively connected to two input terminals of the operational amplifier circuit.

[0055] The operational amplifier circuit includes a seventh PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a ninth NMOS tube, a twelfth NMOS tube, a differential amplifier and a magnetic tunnel junction. The sources of the seventh PMOS tube and the tenth PMOS tube are connected to a power supply, the source of the ninth NMOS tube is grounded, the source of the twelfth NMOS tube is grounded through a magnetic tunnel junction, the drain of the seventh PMOS tube is connected to the drain of the ninth NMOS tube, the drain and the gate of the ninth NMOS tube are connected, the gate of the seventh PMOS tube and the gate of the ninth NMOS tube are respectively used as two input ends of the operational amplifier circuit, the drain of the tenth PMOS tube is connected to the drain of the twelfth NMOS tube, the drain and the gate of the twelfth NMOS tube are connected and serve as the output end of the reference voltage circuit, the gate of the seventh PMOS tube and the gate of the tenth PMOS tube are connected to the output end of the differential amplifier, the gate of the ninth NMOS tube and the gate of the twelfth NMOS tube are respectively connected to the two input ends of the differential amplifier, the gate of the eleventh PMOS tube is connected to the gate of the tenth PMOS tube, and the source and drain of the eleventh PMOS tube are both connected to the power supply.

[0056] The differential amplifier includes an eighth PMOS tube, a ninth PMOS tube, a tenth NMOS tube and an eleventh NMOS tube, the sources of the eighth PMOS tube and the ninth PMOS tube are connected to a power supply, the sources of the tenth NMOS tube and the eleventh NMOS tube are grounded, the gate of the eighth PMOS tube is connected to the gate of the ninth PMOS tube and forms a ninth node, the drain of the eighth PMOS tube is connected to the ninth node and the drain of the tenth NMOS tube, the drain of the ninth PMOS tube is connected to the drain of the eleventh NMOS tube and forms a seventh node, the gate of the seventh PMOS tube and the gate of the tenth PMOS tube are both connected to the seventh node, the gate of the tenth NMOS tube is connected to the gate of the twelfth NMOS tube, and the gate of the eleventh NMOS tube is connected to the gate of the ninth NMOS tube and forms an eighth node.

[0057] The startup circuit includes a sixth PMOS tube, a seventh NMOS tube and an eighth NMOS tube, the source of the sixth PMOS tube is connected to the power supply, the source of the seventh NMOS tube is grounded, the drain of the sixth PMOS tube and the drain of the seventh NMOS tube are connected to form a sixth node, the gate of the sixth PMOS tube and the gate of the eighth NMOS tube are both connected to the sixth node, the gate of the seventh NMOS tube is connected to the source of the eighth NMOS tube, and the drain and source of the eighth NMOS tube are respectively connected to the gate of the seventh PMOS tube and the gate of the ninth NMOS tube.

[0058] It can be seen from the above description of the successive approximation analog-to-digital converter circuit that the reference voltage circuit has the effect of achieving a stable output reference voltage through wide temperature adaptive temperature compensation.

[0059] In an embodiment of the present invention, a data acquisition device is also provided, comprising a data acquisition sensor and a successive approximation analog-to-digital converter circuit provided in an embodiment of the present invention. The data acquisition sensor is used to sense the external environment to generate an analog signal; the successive approximation analog-to-digital converter circuit is used to convert the analog signal into a digital signal.

[0060] Exemplarily, the data acquisition sensor may be a distance sensor, a temperature sensor, a humidity sensor, etc. Correspondingly, the data acquisition device may be a distance detection device, a temperature detection device, a humidity detection device, etc. The above data acquisition device adopts the successive approximation analog-to-digital converter circuit provided by the embodiment of the present invention, and can stably convert the collected analog signal into a digital signal.

[0061] It should be understood that the specific embodiments described herein are only used to explain the application, rather than to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

[0062] Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

Claims

1. A successive approximation analog-to-digital converter circuit, characterized in that: include: An analog-to-digital conversion section for converting an analog signal into a digital signal according to a reference voltage; A reference voltage circuit for providing the reference voltage to the analog-to-digital conversion part, wherein the reference voltage circuit comprises a start-up circuit and an operational amplifier circuit, wherein two output terminals of the start-up circuit are respectively connected to two input terminals of the operational amplifier circuit; The operational amplifier circuit includes a seventh PMOS tube, a tenth PMOS tube, an eleventh PMOS tube, a ninth NMOS tube, a twelfth NMOS tube, a differential amplifier and a magnetic tunnel junction, the source of the seventh PMOS tube and the tenth PMOS tube are connected to a power supply, the source of the ninth NMOS tube is grounded, the source of the twelfth NMOS tube is grounded through the magnetic tunnel junction, the drain of the seventh PMOS tube is connected to the drain of the ninth NMOS tube, the drain of the ninth NMOS tube is connected to the gate, and the gate of the seventh PMOS tube and the gate of the ninth NMOS tube are respectively used as the two input ends of the operational amplifier circuit, the drain of the tenth PMOS tube is connected to the drain of the twelfth NMOS tube, the drain and gate of the twelfth NMOS tube are connected and serve as the output end of the reference voltage circuit, the gate of the seventh PMOS tube and the gate of the tenth PMOS tube are connected to the output end of the differential amplifier, the gate of the ninth NMOS tube and the gate of the twelfth NMOS tube are respectively connected to the two input ends of the differential amplifier, the gate of the eleventh PMOS tube is connected to the gate of the tenth PMOS tube, and the source and drain of the eleventh PMOS tube are both connected to the power supply.

2. The successive approximation analog-to-digital converter circuit according to claim 1, characterized in that: The differential amplifier includes an eighth PMOS tube, a ninth PMOS tube, a tenth NMOS tube and an eleventh NMOS tube, the sources of the eighth PMOS tube and the ninth PMOS tube are connected to a power supply, the sources of the tenth NMOS tube and the eleventh NMOS tube are grounded, the gate of the eighth PMOS tube is connected to the gate of the ninth PMOS tube and forms a ninth node, the drain of the eighth PMOS tube is connected to the ninth node and the drain of the tenth NMOS tube, the drain of the ninth PMOS tube is connected to the drain of the eleventh NMOS tube and forms a seventh node, the gate of the seventh PMOS tube and the gate of the tenth PMOS tube are both connected to the seventh node, the gate of the tenth NMOS tube is connected to the gate of the twelfth NMOS tube, and the gate of the eleventh NMOS tube is connected to the gate of the ninth NMOS tube and forms an eighth node.

3. The successive approximation analog-to-digital converter circuit according to claim 1, characterized in that: The startup circuit includes a sixth PMOS tube, a seventh NMOS tube and an eighth NMOS tube, the source of the sixth PMOS tube is connected to a power supply, the source of the seventh NMOS tube is grounded, the drain of the sixth PMOS tube and the drain of the seventh NMOS tube are connected to form a sixth node, the gate of the sixth PMOS tube and the gate of the eighth NMOS tube are both connected to the sixth node, the gate of the seventh NMOS tube is connected to the source of the eighth NMOS tube, and the drain and source of the eighth NMOS tube are respectively connected to the gate of the seventh PMOS tube and the gate of the ninth NMOS tube.

4. The successive approximation analog-to-digital converter circuit according to claim 1, characterized in that: The analog-to-digital conversion part includes a sampling and holding circuit, a comparator, a logic control module, a successive approximation register, a data output register and a digital-to-analog converter; The output end of the sampling and holding circuit and the output end of the digital-to-analog converter are respectively connected to the positive input end and the negative input end of the comparator, the output end of the comparator is connected to the input end of the logic control module, the output end of the logic control module is connected to the input end of the successive approximation register, the output end of the successive approximation register is respectively connected to the input end of the data output register and the first input end of the digital-to-analog converter, and the output end of the reference voltage circuit is connected to the second input end of the digital-to-analog converter; The sampling and holding circuit is used to receive an external analog signal and perform time domain discretization on the analog signal. The comparator is used to compare the output of the sampling and holding circuit with the output of the digital-to-analog converter and output the comparison result. The logic control module is used to enable and control the successive approximation register according to the output of the comparator and the clock signal. The successive approximation register is used to output a digital signal corresponding to the analog signal through the data output register. The digital-to-analog converter is used to output a reference signal according to the digital signal and the reference voltage.

5. The successive approximation analog-to-digital converter circuit according to claim 4, characterized in that: The digital-to-analog converter includes a latch, a switch circuit, a resistor network and a summing circuit; The input end and the output end of the latch are respectively connected to the output end of the successive approximation register and the control end of the switch circuit. The latch outputs the control signal of the switch circuit according to the digital signal. The output end of the reference voltage circuit is connected to the input end of the summing circuit through the switch circuit and the resistor network. The output end of the summing circuit is connected to the negative input end of the comparator. The summing circuit is used to output the reference signal according to the reference voltage signal.

6. The successive approximation analog-to-digital converter circuit according to claim 5, characterized in that: The switch circuit includes a plurality of switches connected in parallel, the first ends of the plurality of switches are connected to the output end of the reference voltage circuit, the resistor network includes a plurality of resistors connected in parallel, the second ends of the plurality of switches are respectively connected to the first ends of the plurality of resistors, the second ends of the plurality of resistors are respectively connected to the input end of the summing circuit, and the latch has a plurality of outputs to respectively control the plurality of switches; The relationship between the reference signal and the reference voltage is: ， in, v o represents the reference signal, V REF represents the reference voltage, n Indicates the maximum number of latch outputs. D i Represents the i-th output of the latch.

7. The successive approximation analog-to-digital converter circuit according to claim 4, characterized in that: The comparator is a dynamic comparator, which compares the output of the sample-and-hold circuit with the output of the digital-to-analog converter when the clock signal is at a falling edge.

8. The successive approximation analog-to-digital converter circuit according to claim 7, characterized in that: The dynamic comparator includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube and a fifth PMOS tube, and a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube; The sources of the fourth PMOS tube, the first PMOS tube and the fifth PMOS tube are connected to a power supply, the sources of the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube are grounded, the gate of the first PMOS tube is used to access the clock signal, the drain of the first PMOS tube is connected to the sources of the second PMOS tube and the third PMOS tube and constitutes a first node, the gate of the second PMOS tube serves as the positive input terminal of the dynamic comparator, the gate of the third PMOS tube serves as the negative input terminal of the dynamic comparator, the drain of the second PMOS tube is connected to the drain of the second NMOS tube and the gate of the third NMOS tube and constitutes a second node, and the drain of the third PMOS tube is connected to the drain of the third NMOS tube and the gate of the second NMOS tube and constitutes a third node; The gate of the fourth PMOS tube, the gate of the fifth NMOS tube and the drain of the first NMOS tube are all connected to the second node, the drain of the fourth PMOS tube is connected to the drain of the fifth NMOS tube and constitutes the first output node of the dynamic comparator, the gate of the first NMOS tube is used to access the clock signal, the gate of the fifth PMOS tube, the gate of the sixth NMOS tube and the drain of the fourth NMOS tube are all connected to the third node, the drain of the fifth PMOS tube is connected to the drain of the sixth NMOS tube and constitutes the second output node of the dynamic comparator, and the gate of the fourth NMOS tube is used to access the clock signal.

9. A reference voltage circuit, characterized in that: The reference voltage circuit is a reference voltage circuit in the successive approximation analog-to-digital converter circuit according to any one of claims 1 to 8.

10. A data acquisition device, characterized in that: include: Data acquisition sensors, used to sense the external environment to generate analog signals; The successive approximation analog-to-digital converter circuit according to any one of claims 1 to 8 is used to convert the analog signal into a digital signal.

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