Device terminal structure introduced with isolating ring and preparation method thereof

Abstract

The invention relates to the technical field of MOS semiconductors, and discloses a device terminal structure introducing an isolating ring, which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a field oxide layer, and is characterized in that the semiconductor epitaxial layer comprises an N substrate layer and an N drift layer, and the N drift layer forms an active region, a main junction and a multi-region junction terminal expansion structure through ion implantation; a plurality of P-type isolating rings are formed in the main junction through ion implantation; and a plurality of P-type expansion rings and an N-type outer isolation ring are formed in the multi-region junction terminal expansion structure through ion implantation. By segmenting the main junction and introducing the P-type isolating ring, a current path formed by the charging and discharging effect of the terminal structure in the switching process of the power device is blocked from the physical level, a strong electric field and leakage current are prevented from being formed at the sensitive position of the main junction, and the phenomenon that the main junction and cells close to the active region are damaged in advance during high-speed switching is avoided.

Description

Technical Field

[0001] The invention relates to the technical field of MOS semiconductors, and in particular to a device terminal structure introducing an isolation ring and a preparation method thereof. Background Art

[0002] Silicon Carbide high-voltage power devices have better electrothermal properties than traditional silicon devices and can work normally in more demanding environments, so they have broad application prospects in photovoltaic power generation, electric vehicles, aerospace and other fields. In order to meet the development needs of high energy efficiency, high power density and small and lightweight power electronic systems, SiC power devices are developing in the direction of high voltage, high power, high frequency and low loss.

[0003] The existing patent discloses a new MOSFET terminal structure and its preparation method (publication number CN118610094A), which relates to the field of semiconductor technology. In the technology disclosed in the patent, a single main junction is equipped with a multi-region junction terminal extension (JTE) or field limiting ring (FLR) terminal structure. Due to the limited number of partitions, the concentration mutation between different regions of the former is easy to introduce new electric field spikes, resulting in the efficiency of the surface electric field being much lower than that of the ideal terminal; and during the rapid switching process of the power device, the charging and discharging effect of the terminal structure is prone to instantaneous overvoltage or overheating damage. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a device terminal structure introducing an isolation ring and a preparation method thereof, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a device terminal structure introducing an isolation ring includes a drain, a semiconductor epitaxial layer, a source, a gate and a field oxide layer, wherein the semiconductor epitaxial layer includes an N substrate layer and an N drift layer, the N drift layer is formed by ion implantation to form an active region, a main junction and a multi-region junction terminal extension structure, and a plurality of P-type isolation rings are formed inside the main junction by ion implantation; A plurality of P-type expansion rings and an N-type outer isolation ring are formed inside the multi-region junction terminal expansion structure by ion implantation.

[0006] A method for preparing a device terminal structure introducing an isolation ring comprises the following steps: S1, preparation of epitaxial layer and growth of a silicon oxide film on the silicon surface; S2, photolithography pattern on the surface of the epitaxial layer, and etching grooves by etching method; S3, using ion implantation technology to implant doping elements into the silicon substrate to form an active region, a main junction region and a terminal structure; S4, gate oxidation and gate electrode deposition, as well as source and drain metallization processing; S5. Conduct electrical performance tests on MOSFET devices, including threshold voltage, leakage current, and switching speed.

[0007] Furthermore, in the step S1, the silicon wafer needs to be placed in oxygen or water vapor at a temperature of 0.1 to 0.1 degrees Celsius to oxidize the silicon surface to form a SiO2 layer.

[0008] Furthermore, in the step S2, a photoresist is coated on the surface of the silicon oxide layer to form a photosensitive layer, and the electrode pattern is transferred to the photoresist layer through a mask under ultraviolet light to form a desired pattern.

[0009] Furthermore, in step S4, a metal layer is deposited on the surface of silicon oxide as a gate electrode by evaporation, sputtering and chemical vapor deposition.

[0010] Furthermore, in step S5, the reliability of the switching performance of the terminal structure is determined by analyzing the difference in threshold voltage, leakage current, and switching speed between the device with the high-resistance field plate added and the device without the high-resistance field plate added. In the formula, represents the reliability performance coefficient of the terminal structure, It represents the threshold voltage difference between the device with high resistance field plate and the device without high resistance field plate. It represents the leakage current difference between the device with high resistance field plate and the device without high resistance field plate. It represents the switching speed difference between the device with high resistance field plate added and the device without high resistance field plate added; when When , it means that the switching performance of the terminal structure containing the high-resistance field plate meets the requirements; when When , it means that the switching performance of the terminal structure containing the high-resistance field plate does not meet the requirements. Beneficial effects: 1. The present invention segments the main junction and introduces a P-type isolation ring to physically block the current path formed by the charging and discharging effect of the terminal structure during the switching process of the power device, thereby preventing the formation of a strong electric field and leakage current at the sensitive position of the main junction, and avoiding the phenomenon of premature damage to the main junction and cells adjacent to the active area during high-speed switching.

[0011] 2. The present invention provides an additional discharge channel for the large current caused by the high-speed charge and discharge effect by additionally introducing a high-resistance field plate above the terminal structure, thereby further improving the switching reliability of the power device.

[0012] 3. The present invention can accurately test the electrical performance of MOSFET devices by detecting threshold voltage, leakage current, and switching speed, thereby improving the production efficiency of MOS devices while ensuring the yield rate of the devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 It is a structural schematic diagram of Embodiment 1 of the present invention; Figure 2 It is a structural diagram of Embodiment 2 of the present invention.

[0014] In the figure: 1, drain; 2, N substrate layer; 3, N drift layer; 4, source; 5, gate; 6, P-type isolation ring; 7, field oxide layer; 8, P-type expansion ring; 9, N-type outer isolation ring; 10, high-resistance field plate. DETAILED DESCRIPTION

[0015] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0016] Example 1 like Figure 1 As shown, according to one aspect of the present invention, a device terminal structure with an isolation ring is provided, comprising a drain 1, a semiconductor epitaxial layer, a source 4, a gate 5 and a field oxide layer 7, wherein the semiconductor epitaxial layer comprises an N substrate layer 2 and an N drift layer 3, and the N drift layer 3 is formed into an active region, a main junction and a multi-region junction terminal extension structure by ion implantation, characterized in that: a plurality of P-type isolation rings 6 are formed inside the main junction by ion implantation; a plurality of P-type extension rings 9 and an N-type outer isolation ring 9 are formed inside the multi-region junction terminal extension structure by ion implantation. The main junction is segmented and an isolation ring structure (P-type isolation ring 6) is introduced, so that the current path formed by the charging and discharging effect of the terminal structure during the switching process of the power device is blocked from a physical level, so as to prevent the formation of a strong electric field and leakage current at the sensitive position of the main junction, and protect the main junction and the cells adjacent to the active region from being damaged prematurely during high-speed switching.

[0017] Example 2 like Figure 2 As shown, the terminal structure of high-power device switching reliability includes a drain 1, a semiconductor epitaxial layer, a source 4, a gate 5 and a field oxide layer 7, wherein the semiconductor epitaxial layer includes an N substrate layer 2 and an N drift layer 3, and the N drift layer 3 is formed into an active region, a main junction and a multi-region junction terminal extension structure by ion implantation, and a high-resistance field plate 10 is deposited inside the field oxide layer 7, and the high-resistance field plate 10 is used to provide an additional current discharge channel during the device switching process. By additionally introducing a high-resistance field plate 10 above the terminal structure, an additional discharge channel is provided for the large current caused by the high-speed charge and discharge effect, and the switching reliability of the power device is further improved.

[0018] Example 3 A method for preparing a device terminal structure introducing an isolation ring comprises the following steps: Step 1: Preparation of epitaxial layer and growth of a silicon oxide film on the silicon surface. The silicon wafer needs to be placed in oxygen or water vapor at a temperature of 900°C to 1100°C to oxidize the silicon surface to form a SiO2 layer.

[0019] Step 2: Photolithography the pattern on the surface of the epitaxial layer, and etching the grooves by etching. Apply photoresist to the surface of the silicon oxide layer to form a photosensitive layer, and transfer the electrode pattern to the photoresist layer through a mask under ultraviolet light to form the desired pattern.

[0020] Step 3: Using ion implantation technology to implant doping elements into the silicon substrate to form an active region, a main junction region and a terminal structure; Step 4: Gate oxidation and gate electrode deposition, as well as source and drain metallization. A metal layer is deposited on the surface of silicon oxide as a gate electrode by evaporation, sputtering and chemical vapor deposition.

[0021] Step 5: Conduct electrical performance tests on MOSFET devices, including threshold voltage, leakage current, and switching speed.

[0022] In this embodiment, the reliability of the switching performance of the terminal structure is determined by analyzing the difference in threshold voltage, leakage current, and switching speed between the device with the high-resistance field plate 10 added and the device without the high-resistance field plate 10 added. In the formula, represents the reliability performance coefficient of the terminal structure, represents the threshold voltage difference between the device with the high resistance field plate 10 added and the device without the high resistance field plate 10 added, represents the leakage current difference between the device with the high resistance field plate 10 added and the device without the high resistance field plate 10 added, represents the switching speed difference between the device with the high resistance field plate 10 added and the device without the high resistance field plate 10 added; when When , it means that the switching performance of the terminal structure containing the high-resistance field plate 10 meets the requirements; when When , it means that the switching performance of the terminal structure containing the high-resistance field plate 10 does not meet the requirements.

[0023] The device X with the high resistance field plate 10 added and the excellent device Y with the same specification without the high resistance field plate 10 were tested. The threshold voltage difference between the device with the high resistance field plate 10 and the device without the high resistance field plate 10 was taken as (Unit: V, voltage difference = |threshold voltage of the device with high resistance field plate 10 added - threshold voltage of the device without high resistance field plate 10 added|).

[0024] The difference in leakage current between the device with the high resistance field plate 10 added and the device without the high resistance field plate 10 added is (Nanoamperes, leakage current difference = | leakage current of the device with high resistance field plate 10 added - leakage current of the device without high resistance field plate 10 added |).

[0025] The switching speed difference between the device with the high resistance field plate 10 added and the device without the high resistance field plate 10 is (Picoseconds, switching speed difference = switching speed of the device without adding high-resistance field plate 10 - switching speed of the device with adding high-resistance field plate 10), then: The device X with the high-resistance field plate 10 added is tested with the excellent device Y with the same specifications but without the high-resistance field plate 10 added. The reliability coefficient of the terminal structure of the device X with the high-resistance field plate 10 is , that is, the switching performance of the terminal structure containing the high-resistance field plate 10 device X meets the requirements. Comparing multiple sets of data, we have: It can be seen from the above table that when the sample of the implementation data tends to infinity, a critical line will appear to determine whether the tested device meets the requirements, and the critical line is 70%.

[0026] Then when When , it means that the switching performance of the terminal structure containing the high resistance field plate 10 meets the requirements; when When , it means that the switching performance of the terminal structure containing the high-resistance field plate 10 does not meet the requirements.

[0027] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A device terminal structure introducing an isolation ring, comprising a drain (1), a semiconductor epitaxial layer, a source (4), a gate (5) and a field oxide layer (7), wherein the semiconductor epitaxial layer comprises an N substrate layer (2) and an N drift layer (3), and the N drift layer (3) is formed into an active region, a main junction and a multi-region junction terminal extension structure by ion implantation, characterized in that: A plurality of P-type isolation rings (6) are formed inside the main junction by ion implantation; A plurality of P-type expansion rings (9) and an N-type outer isolation ring (9) are formed inside the multi-region junction terminal expansion structure by ion implantation.

2. The device terminal structure with an isolation ring as claimed in claim 1, characterized in that: A high-resistance field plate (10) is deposited inside the field oxide layer (7), and the high-resistance field plate (10) is used to provide an additional current discharge channel during the device switching process.

3. A method for preparing a device terminal structure with an isolation ring according to any one of claims 1 to 2, characterized in that: The following steps are involved: S1, preparation of epitaxial layer and growth of a silicon oxide film on the silicon surface; S2, photolithography pattern on the surface of the epitaxial layer, and etching grooves by etching method; S3, using ion implantation technology to implant doping elements into the silicon substrate to form an active region, a main junction region and a terminal structure; S4, gate oxidation and gate electrode deposition, as well as source and drain metallization processing; S5. Conduct electrical performance tests on MOSFET devices, including threshold voltage, leakage current, and switching speed.

4. The device terminal structure with an isolation ring and the method for preparing the same according to claim 3, characterized in that: In the step S1, the silicon wafer needs to be placed in oxygen or water vapor at a temperature of 900° C. to 1100° C. to oxidize the silicon surface to form a SiO2 layer.

5. The device terminal structure with an isolation ring and the method for preparing the same according to claim 3, characterized in that: In the step S2, a photoresist is coated on the surface of the silicon oxide layer to form a photosensitive layer, and the electrode pattern is transferred to the photoresist layer through a mask under ultraviolet light to form a desired pattern.

6. The device terminal structure with an isolation ring and the method for preparing the same according to claim 3, characterized in that: In the step S4, a metal layer is deposited on the surface of silicon oxide as a gate electrode by evaporation, sputtering and chemical vapor deposition.

7. The device terminal structure with an isolation ring and the method for preparing the same according to claim 3, characterized in that: In step S5, the reliability of the switching performance of the terminal structure is determined by analyzing the difference in threshold voltage, leakage current, and switching speed between a device with a high-resistance field plate (10) added and a device without a high-resistance field plate (10) added, and: In the formula, represents the reliability performance coefficient of the terminal structure, represents the threshold voltage difference between a device with a high-resistance field plate (10) added and a device without a high-resistance field plate (10) added, represents the leakage current difference between a device with a high-resistance field plate (10) added and a device without a high-resistance field plate (10) added, Indicates the switching speed difference between a device with a high-resistance field plate (10) added and a device without a high-resistance field plate (10) added; when When , it indicates that the switching performance of the terminal structure containing the high-resistance field plate (10) meets the requirements; when When , it means that the switching performance of the terminal structure containing the high-resistance field plate (10) does not meet the requirements.

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