Chip and manufacturing method thereof
By making the dies to be integrated on the same wafer and performing non-planar integration, the problem of high design complexity of non-planar integrated chips is solved, and process consistency and design simplification are achieved.
Patent Information
- Application Number
- CN202411606023.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-11
- Publication Date
- 2025-02-11
AI Technical Summary
In non-planar integrated chip design, due to the differences in the production conditions of multiple grains, the process deviation range that chip design needs to cover is greatly increased and the design complexity is increased.
By making each of the dies to be integrated for the target chip on the same wafer, and selecting the target dies from each cut dies according to the configuration information of the target chip, they are integrated with each other in a non-planar manner to form Target chip.
Since each grain comes from the same wafer, maintaining good process consistency can effectively reduce the complexity of chip design and simplify the timing analysis process.
Smart Images
Figure CN119421498A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a chip and a method for manufacturing the same. Background Art
[0002] As advanced processes slowly slow down, it becomes increasingly difficult to shrink the chip design area, and issues such as the yield and cost of large chip designs become increasingly prominent. For this reason, more and more chips are integrated using non-planar integration. Non-planar integration can stack multiple small grains, thereby bringing performance, power consumption, and area advantages. However, in the scenario of non-planar integration, due to the differences in the process production conditions of multiple grains, the process deviation range that needs to be covered by chip design is greatly increased, and the design complexity is greatly increased. Summary of the invention
[0003] In view of this, the embodiments of the present invention provide a chip and a manufacturing method thereof, a timing analysis method and device for a chip, an electronic device, and a storage medium, which can effectively reduce the complexity of chip design.
[0004] In a first aspect, an embodiment of the present invention provides a chip, comprising at least two dies, wherein the at least two dies are integrated with each other in a non-planar manner; and the at least two dies are obtained by cutting and processing the same wafer.
[0005] In one embodiment, the at least two dies are located in the same exposure region of the same wafer or in two exposure regions adjacent to each other in the same wafer.
[0006] In a second aspect, an embodiment of the present invention further provides a chip manufacturing method, comprising: making each to-be-integrated grain required for a target chip on the same wafer, wherein the number of the to-be-integrated grains is at least two; slicing and cutting the wafer to obtain corresponding cut grains; selecting a target grain from each of the cut grains according to the composition information of the target chip; and integrating each of the target grains with each other in a non-planar manner to obtain the target chip.
[0007] In one embodiment, manufacturing each to-be-integrated grain required for the target chip on the same wafer includes: manufacturing each to-be-integrated grain required for the target chip in the same exposure area of the wafer, and the wafer includes at least one exposure area.
[0008] In one embodiment, the method of producing each of the to-be-integrated grains required by the target chip in the same exposure area of the wafer includes: determining the number of each of the to-be-integrated grains distributed in the same exposure area of the wafer according to preset conditions, wherein the preset conditions include: the required number of each of the to-be-integrated grains by the target chip, or the required number of each of the to-be-integrated grains by the target chip and the yield of each of the to-be-integrated grains; and producing each of the to-be-integrated grains in the same exposure area of the wafer according to the number of each of the to-be-integrated grains distributed in the same exposure area.
[0009] In one embodiment, each of the grains to be integrated required by the target chip includes at least two grain types, and each of the grain types includes at least one grain to be integrated; the required number of each of the grains to be integrated by the target chip includes: the number of grains to be integrated required by each of the grain types in the target chip; the yield of the grains to be integrated includes: the yield of the grains to be integrated of each of the grain types; determining the number of each of the grains to be integrated distributed in the same exposure area of the wafer according to preset conditions includes: determining the number of grains to be integrated under each of the grain types in the same exposure area of the wafer according to the preset conditions.
[0010] In one embodiment, at least two grain groups are arranged in the exposure area, each of the grain groups has the same structure, and each of the grain groups includes all the grains to be integrated required for the target chip; determining the number of each grain to be integrated distributed in the same exposure area of the wafer according to preset conditions includes: determining the number of each grain to be integrated in each grain group according to the preset conditions to obtain the number of grains in the group; and determining the number of each grain to be integrated distributed in the same exposure area according to the number of grains in the group.
[0011] In one embodiment, selecting the target grain from each of the cut grains according to the composition information of the target chip includes: selecting the target grain from each of the cut grains according to the composition information of the target chip and the positional relationship of each of the grains to be integrated on the wafer.
[0012] In one embodiment, selecting the target grain from the cut grains according to the composition information of the target chip and the positional relationship between the grains to be integrated on the wafer includes: determining the positional relationship between the grains to be integrated according to the coordinates of the grains to be integrated on the wafer, wherein the positional relationship includes at least one of the following: located in the same exposure area, located in adjacent exposure areas, and located on the same wafer; selecting the target grain from the cut grains according to the composition information of the target chip, the positional relationship between the grains to be integrated, and a preset priority, wherein the preset priority decreases in the following order: the target grains located in the same exposure area, the target grains located in adjacent exposure areas, and the target grains located on the same wafer.
[0013] In one embodiment, the selecting the target grain from each of the cut grains according to the composition information of the target chip, the positional relationship between each of the grains to be integrated, and the preset priority includes: searching each of the cut grains for the target grains located in the same exposure area according to the composition information of the target chip; if there are target grains that are not found, continuing to search each of the cut grains for the target grains located in adjacent exposure areas according to the composition information of the target chip; if there are target grains that are not found, continuing to search each of the cut grains for the target grains located on the same wafer according to the composition information of the target chip.
[0014] In one embodiment, at least two grain groups are arranged in the exposure area, each of the grain groups has the same structure, and each of the grain groups includes all the to-be-integrated grains required for the target chip; searching for each of the cut grains in the same exposure area according to the composition information of the target chip comprises: searching for the target grain in each of the cut grains in the same exposure area in ascending order of distance from the target grain that has been found according to the composition information of the target chip; and continuing to search for the target grain in each of the cut grains according to the composition information of the target chip. Searching for the target grain located in the adjacent exposure area among the cut grains includes: searching for the target grain in each of the cut grains according to the composition information of the target chip and in the order of the distance from the target grain that has been found in the adjacent exposure area from small to large; continuing to search for the target grain located on the same wafer among each of the cut grains according to the composition information of the target chip includes: continuing to search for the target grain in each of the cut grains according to the composition information of the target chip and in the order of the distance from the target grain that has been found on the same wafer from small to large.
[0015] In one embodiment, the target grains are integrated with each other in a non-planar manner to obtain the target chip, including: according to the composition information of the target chip, each target grain is divided into at least two sets, and the structures of the target grains belonging to the same set are the same; the target grains belonging to different sets are integrated with each other in a non-planar manner to obtain the target chip.
[0016] In one embodiment, the target grains belonging to different sets are integrated with each other in a non-planar manner to obtain the target chip, including: wafer reconstructing the target grains in at least one of the sets, and each set obtains a corresponding reconstructed wafer; based on each of the reconstructed wafers, the target grains belonging to different sets are integrated with each other in a non-planar manner to obtain the target chip.
[0017] In one embodiment, before slicing the wafer to obtain corresponding cut grains, the method also includes: testing each of the to-be-integrated grains on the wafer; determining the failed grains among the to-be-integrated grains based on the test results; slicing the wafer to obtain corresponding cut grains includes: slicing the wafer and removing the failed grains to obtain the cut grains.
[0018] In a third aspect, an embodiment of the present invention further provides a timing analysis method for a chip, comprising: obtaining design indication information of a target chip, wherein the design indication information is used to indicate that the target chip is obtained by non-planar integration of at least two grains, and the at least two grains are formed by cutting after processing of the same wafer; according to the design indication information, taking the target chip as a target grain, and performing timing analysis on the target grain.
[0019] In one embodiment, the design indication information is further used to indicate that the at least two dies are located in the same exposure region of the same wafer or in two exposure regions adjacent to each other in the same wafer.
[0020] In a fourth aspect, an embodiment of the present invention further provides a timing analysis device for a chip, comprising: an acquisition unit, used to acquire design indication information of a target chip, wherein the design indication information is used to indicate that the target chip is obtained by non-planar integration of at least two grains, and the at least two grains are formed by cutting after processing of the same wafer; a timing analysis unit, used to treat the target chip as a grain to be analyzed according to the design indication information, and perform timing analysis on the grain to be analyzed.
[0021] In one implementation, the design indication information is further used to indicate that the at least two dies are located in the same exposure region of the same wafer or in two exposure regions adjacent to each other in the same wafer.
[0022] In a fifth aspect, an embodiment of the present invention further provides an electronic device, comprising: a processor and a memory, wherein the processor is electrically connected to the memory; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to implement any one of the timing analysis methods for chips provided in the embodiments of the present invention.
[0023] In a sixth aspect, an embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the timing analysis method for a chip provided in any embodiment of the present invention.
[0024] The chip, chip manufacturing method, chip timing analysis method and device, electronic device, and computer-readable storage medium provided by the embodiments of the present invention, since the grains forming the chip are all derived from the same wafer, the grains can maintain good process consistency during the chip processing. Therefore, when designing the chip, each grain in the chip can be approximately regarded as one grain, and the process deviation of each grain can be approximately regarded as the process deviation within the same grain. Therefore, the existing method of performing timing analysis on one grain can be used to perform timing analysis on non-planar integrated chips without considering the complex situation of the superposition of process deviations of different grains. Therefore, the complexity of chip design can be effectively reduced. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0026] Figure 1 A schematic diagram of the structure of a chip provided by an embodiment of the present invention; Figure 2 A schematic diagram of the structure of an exposure area in an embodiment of the present invention; Figure 3 A comparison effect diagram of the process deviation of each grain in the non-planar integrated chip provided by the embodiment of the present invention and the process deviation of each grain in the non-planar integrated chip in the prior art; Figure 4 A flow chart of a chip manufacturing method provided by an embodiment of the present invention; Figure 5 A schematic diagram of the structure of a grain group in an embodiment of the present invention; Figure 6 A schematic diagram of the distribution of the grains to be integrated in the exposure areas of the same wafer in an embodiment of the present invention; Figure 7 A schematic diagram of manufacturing a die to be integrated and integrating it in a non-planar manner using a reconstructed wafer in an embodiment of the present invention; Figure 8 A detailed flow chart of a chip manufacturing method provided by an embodiment of the present invention; Fig. 9 A flow chart of a timing analysis method for a chip provided by an embodiment of the present invention; Fig.10 A schematic structural diagram of a timing analysis device for a chip provided by an embodiment of the present invention; Fig.11 A schematic structural diagram of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0027] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0028] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0029] The embodiments of the present invention provide a chip, which can effectively reduce the complexity of chip design.
[0030] like Figure 1 As shown, an embodiment of the present invention provides a chip 10, which may include at least two dies 20, and the at least two dies 20 are integrated with each other in a non-planar manner; the at least two dies 20 are obtained by cutting after processing the same wafer.
[0031] The chip 10 provided by the embodiment of the present invention may include at least two crystal grains 20, which are integrated with each other in a non-planar manner, and at least two crystal grains 20 are obtained by cutting after processing the same wafer. Since the crystal grains 20 forming the chip 10 are all from the same wafer, the process consistency between the crystal grains 20 can be maintained well during the chip processing process. Therefore, when designing the chip, each crystal grain in the chip can be approximately regarded as one crystal grain, and the process deviation of each crystal grain can be approximately regarded as the process deviation within the same crystal grain, so that the existing method of performing timing analysis on one crystal grain can be used to perform timing analysis on the non-planar integrated chip 10 without considering the complex situation of the process deviations of different crystal grains superimposed on each other, so that the complexity of chip design can be effectively reduced.
[0032] Specifically, in an embodiment of the present invention, at least two grains 20 included in the chip 10 may be grains of the same type or grains of different types, and each grain 20 may be integrated with each other in a non-planar manner to form a chip. Here, grains of the same type may refer to grains of the same structure, and grains of different types may refer to grains of different structures. For example, in one example, the chip 10 may be obtained by the non-planar integration of two grains dieA and dieA of the same structure, and in another example, the chip 10 may also be obtained by the non-planar integration of two grains dieA and dieB of different structures. In an embodiment of the present invention, each grain is integrated with each other in a non-planar manner, for example, each grain may be integrated together in a 2.5D, 3D, or 3.5D manner. Among them, the non-planar integration may be achieved, for example, by through silicon vias (TSV), adapter plates, hybrid bonding, and the like.
[0033] The dies included in the chip can be distributed in a variety of ways on the same wafer, and the embodiments of the present invention do not limit this. For example, in one embodiment of the present invention, at least two dies of the chip can be located in the same exposure area (shot) of the same wafer or in two adjacent exposure areas of the same wafer. Figure 2 As shown, the exposure area EP may refer to a small area on the wafer targeted by each exposure operation in the photolithography process of semiconductor processing, and each exposure area EP may include one or more grains, such as die1, die2, die3, etc. For example, in one example, a stepper lithography machine or a scanning lithography machine can expose a small area of 22 milliseconds × 22 mm each time. To complete the lithography on the entire wafer, it is necessary to change the relative position between the wafer and the lithography machine multiple times, and perform multiple exposures to form multiple exposure areas.
[0034] Specifically, when each grain of the chip is in the same exposure area, each layer of the structure of each grain in the chip is realized through the same photolithography. Therefore, the process consistency between the grains is higher and the process deviation is smaller. When performing timing analysis on the chip, the effect of timing analysis can be better by approximating each grain as one grain.
[0035] Due to issues such as die yield, in some cases, the die in the same exposure area may not be able to form a chip. Therefore, in another embodiment of the present invention, the die in the chip may also be located in two adjacent exposure areas in the same wafer. Since the exposure areas are adjacent, the photolithography processes are also relatively close, so the process consistency of the die in the chip can also be kept high.
[0036] For example, the comparison effect of the process deviation of each die in the non-planar integrated chip provided by the embodiment of the present invention and the process deviation of each die in the non-planar integrated chip in the prior art can be as follows: Figure 3 As shown. Figure 3 It can be seen that the process deviations of the various grains in the non-planar integrated chip provided by the embodiment of the present invention approximately overlap into an ellipse, while the process deviations of the various grains in the non-planar integrated chip in the prior art vary greatly.
[0037] Corresponding to the aforementioned chip, an embodiment of the present invention further provides a chip manufacturing method, which can effectively reduce the complexity of chip design.
[0038] like Figure 4 As shown, the chip manufacturing method provided by the embodiment of the present invention may include: S31, manufacturing all the crystal grains to be integrated required for the target chip on the same wafer, wherein the number of the crystal grains to be integrated is at least two; The target chip is the chip to be manufactured. The target chip can be obtained by integrating at least two to-be-integrated dies. These to-be-integrated dies can be manufactured on the same wafer.
[0039] The grains to be integrated required by the target chip may be grains of the same type or grains of different types. Here, grains of the same type may refer to grains of the same structure, and grains of different types may refer to grains of different structures. For example, in one example, the target chip may include two grains of the same structure, dieA and dieA, and in another example, the target chip may also include two grains of different structures, dieA and dieB.
[0040] S32, dicing the wafer to obtain corresponding cut crystal grains; After the above-mentioned crystal grains to be integrated are manufactured on the same wafer, in this step, the wafer can be diced and cut to obtain individual crystal grains, namely, cut crystal grains.
[0041] S33, selecting a target crystal grain from each of the cut crystal grains according to the composition information of the target chip; The composition information of the target chip is which grains the target chip is composed of or which grains the target chip includes. In this step, the target grains required to form the target chip can be selected from the cut grains obtained by wafer dicing according to the composition information of the target chip. For example, in one example, the composition information of the target chip can include: the target chip includes one grain dieC and two grains dieD, then one grain dieC and two grains dieD can be selected from each cut grain as the target grains according to the composition information, so as to form the target chip using the target grains.
[0042] S34, integrating the target crystal grains with each other in a non-planar manner to obtain the target chip.
[0043] After selecting the target dies required for the target chip, in this step, the target dies can be integrated with each other in a non-planar manner to obtain the target chip. The dies are integrated with each other in a non-planar manner, for example, the dies can be integrated together in a 2.5D, 3D, or 3.5D manner, which can be achieved by through silicon vias (TSV), adapter plates, hybrid bonding, etc.
[0044] The chip manufacturing method provided by the embodiment of the present invention can make all the grains to be integrated required by the target chip on the same wafer, wherein the number of the grains to be integrated is at least two, the wafer is diced and cut to obtain corresponding cut grains, the target grain is selected from each of the cut grains according to the composition information of the target chip, and each of the target grains is integrated with each other in a non-planar manner to obtain the target chip. In this way, since the grains forming the target chip are all from the same wafer, the grains can maintain good process consistency during the chip processing process. Based on this, when designing the chip, each grain in the chip can be approximately regarded as a grain, and the process deviation of each grain can be approximately regarded as the process deviation within the same grain, so that the method of performing timing analysis on a grain can be used to perform timing analysis on the non-planar integrated target chip without considering the complex situation of the process deviations of different grains superimposed on each other, thereby effectively reducing the complexity of chip design.
[0045] Specifically, there are multiple ways to implement the step S31 of making all the to-be-integrated grains required for the target chip on the same wafer, which is not limited in the embodiments of the present invention. For example, in one embodiment of the present invention, the step S31 of making all the to-be-integrated grains required for the target chip on the same wafer may include: making all the to-be-integrated grains required for the target chip in the same exposure area of the wafer, and the wafer includes at least one exposure area. Figure 2 As shown, in the embodiment of the present invention, the exposure area EP may refer to a small area on the wafer targeted by each exposure operation in the photolithography process of semiconductor processing, and each exposure area EP may include one or more grains, such as die1, die2, die3... For example, in one example, a stepper lithography machine or a scanning lithography machine can expose a small area of 22 milliseconds × 22 mm each time. To complete the lithography on the entire wafer, it is necessary to change the relative position between the wafer and the lithography machine multiple times and perform multiple exposures, thereby forming multiple exposure areas on the wafer. In the embodiment of the present invention, when all the grains to be integrated of the target chip are in the same exposure area, each layer structure of each grain to be integrated in the target chip is realized by the same lithography, so the process consistency between the grains to be integrated is higher and the process deviation is smaller. When the timing analysis of the target chip is performed, the effect of timing analysis by approximating each grain to be integrated as one grain is better.
[0046] In one embodiment of the present invention, making each of the to-be-integrated grains required by the target chip in the same exposure area of the wafer may specifically include: determining the number of each of the to-be-integrated grains distributed in the same exposure area of the wafer according to preset conditions, wherein the preset conditions include: the required number of each of the to-be-integrated grains of the target chip, or the required number of each of the to-be-integrated grains of the target chip and the yield of each of the to-be-integrated grains; making each of the to-be-integrated grains in the same exposure area of the wafer according to the number of each of the to-be-integrated grains distributed in the same exposure area. That is, in order to make each of the to-be-integrated grains required by the target chip in the same exposure area of the wafer, the number of each of the to-be-integrated grains distributed in the same exposure area may be first determined according to the required number of each of the to-be-integrated grains of the target chip. For example, in one example, the to-be-integrated grains required by the target chip are all of the same type and the number is 2, then the number of the to-be-integrated grains distributed in the same exposure area may be determined to be 2. In another example, the target chip requires two grains to be integrated of the same type, but the yield of each grain to be integrated is 50%. Then, it can be determined that the number of grains to be integrated distributed in the same exposure area is four.
[0047] Furthermore, in an embodiment of the present invention, each grain in the target chip can be not only the same kind of grain, but also different kinds of grains. Specifically, in one embodiment of the present invention, each of the grains to be integrated required by the target chip may include at least two grain types, and each grain type may include at least one grain to be integrated. Then, the required number of each of the grains to be integrated by the target chip may specifically include the number of grains to be integrated required by each grain type in the target chip, and the yield of the grains to be integrated may specifically include the yield of the grains to be integrated of each grain type. Based on this, determining the number of each of the grains to be integrated distributed in the same exposure area of the wafer according to preset conditions may specifically include: determining the number of the grains to be integrated under each grain type in the same exposure area of the wafer according to the preset conditions. For example, in one example, the types of grains required for the target chip are grain A and grain B, of which two grains A are required and one grain B is required, the yield of A is 50%, and the yield of B is 100%. It can be determined that the number of grains A in the same exposure area is 2 / 50%=4, and the number of grains B is 1 / 100%=1.
[0048] In some embodiments of the present invention, the area of each grain is relatively small, while the area of the exposure region is relatively large. Therefore, at least two grain groups may be provided in each exposure region, and the structures of the grain groups are the same. Each grain group may include all the grains to be integrated required by the target chip. Based on this, determining the number of the grains to be integrated distributed in the same exposure region of the wafer according to the preset conditions may specifically include: determining the number of the grains to be integrated in each grain group according to the preset conditions to obtain the number of grains in the group; and determining the number of the grains to be integrated distributed in the same exposure region according to the number of grains in the group.
[0049] For example, Figure 5 As shown, the die group G1 includes all the to-be-integrated dies required for the target chip, namely, 3 dieA and 1 dieB. Each exposure area EP may include 2 die groups G1 (wherein, the three dieA and one dieB in the shaded part are one die group G1, and the three dieA and one dieB in the non-shaded part are another die group G1). Each exposure area includes 3×2=6 dieA and 1×2=2 dieB.
[0050] After the above-mentioned grains to be integrated are manufactured on the same wafer, the wafer can be diced and cut in step S32 to obtain discrete grains, i.e., cut grains. In one embodiment of the present invention, before dicing and cutting the wafer to obtain corresponding cut grains, the chip manufacturing method provided by the embodiment of the present invention may also include: testing each grain to be integrated on the wafer, for example, testing each grain to be integrated on the wafer by a probe station; according to the test results, determining the failed grains in each of the grains to be integrated; based on this, dicing and cutting the wafer to obtain the corresponding cut grains may specifically include: dicing and cutting the wafer and removing the failed grains to obtain cut grains. In this way, a part of the failed grains can be eliminated through testing to avoid waste in subsequent steps.
[0051] After obtaining the cut grains, the target grains can be selected from the cut grains according to the composition information of the target chip in step S33 to form the target chip. Specifically, in one embodiment of the present invention, selecting the target grains from the cut grains according to the composition information of the target chip can specifically include: selecting the target grains from the cut grains according to the composition information of the target chip and the positional relationship of the grains to be integrated on the wafer. That is to say, the target grains are not only related to which grains to be integrated constitute the target chip, but also related to the positional relationship between the grains to be integrated on the wafer.
[0052] In one embodiment of the present invention, selecting the target grain from the cut grains according to the composition information of the target chip and the positional relationship between the grains to be integrated on the wafer may specifically include: determining the positional relationship between the grains to be integrated according to the coordinates of the grains to be integrated on the wafer, wherein the positional relationship includes at least one of the following: located in the same exposure area, located in adjacent exposure areas, and located on the same wafer; selecting the target grain from the cut grains according to the composition information of the target chip, the positional relationship between the grains to be integrated, and a preset priority, wherein the preset priority decreases in the following order: the target grains located in the same exposure area, the target grains located in adjacent exposure areas, and the target grains located on the same wafer.
[0053] In this embodiment, when testing each of the grains to be integrated on the wafer, the coordinates of each of the grains to be integrated on the wafer can be known, so that the positional relationship between each of the grains to be integrated can be determined based on the coordinates of each of the grains to be integrated on the wafer. For example, in one example, the coordinates of grain A to be integrated are 001, and the coordinates of grain B to be integrated are 002, then it can be determined that grain A to be integrated is adjacent to grain B to be integrated on the wafer. Optionally, in an embodiment of the present invention, the positional relationship between each of the grains to be integrated may include one or more of the following: located in the same exposure area, located in adjacent exposure areas, and located on the same wafer. Among them, adjacent exposure areas may refer to exposure areas that are adjacent in physical position, for example, exposure area P1 is directly to the left of exposure area P2, exposure area P3 is directly below exposure area P4, etc. Being located on the same wafer may mean that each of the grains to be integrated is located on the same wafer, but is not in the same exposure area, nor in adjacent exposure areas.
[0054] In an embodiment of the present invention, the preset priority is successively decreased in the following order: the target grains located in the same exposure area, the target grains located in adjacent exposure areas, and the target grains located on the same wafer. That is to say, when selecting the target grains, the target grains located in the same exposure area are given priority, followed by the target grains located in adjacent exposure areas, and then the target grains located on the same wafer, because the process consistency of the target grains located in the same exposure area is the highest, the process consistency of the target grains located in adjacent exposure areas is second, and the process consistency of the target grains located on the same wafer is slightly worse than the former two.
[0055] In a specific implementation, in one embodiment of the present invention, selecting the target grain from each of the cut grains according to the composition information of the target chip, the positional relationship between each of the grains to be integrated, and the preset priority may include: searching each of the cut grains for the target grains located in the same exposure area according to the composition information of the target chip; if there are target grains that are not found, then continuing to search each of the cut grains for the target grains located in adjacent exposure areas according to the composition information of the target chip; if there are target grains that are not found, then continuing to search each of the cut grains for the target grains located on the same wafer according to the composition information of the target chip.
[0056] For example, Figure 6As shown, in one embodiment of the present invention, the target chip requires one Die0 and two Die1s. In the exposure area EP1, if Die0(#1) fails, and Die1(#1), Die1(#2), and Die0(#2) are all qualified, then Die1(#1), Die1(#2), and Die0(#2) can be selected as the target grains corresponding to the target chip. In another embodiment of the present invention, the target chip requires one Die0 and two Die1s. If Die0(#3) and Die0(#4) in exposure area EP2 are both failed, and Die1(#3) and Die1(#4) are both qualified, it is difficult to select one Die0 and two Die1s as target grains in the same exposure area EP1. Therefore, it is possible to check whether there is a qualified Die0 in the exposure area EP3 adjacent to the exposure area. For example, if Die0(#5), Die0(#6), Die1(#5), and Die1(#6) in the adjacent exposure area EP3 are all qualified, then Die1(#3), Die1(#4), and Die0(#5) can be selected as the target grains corresponding to one target chip, and Die1(#5), Die1(#6), and Die0(#6) can be selected as the target grains corresponding to another target chip.
[0057] As mentioned above, in some embodiments of the present invention, the area of each grain is relatively small, while the area of the exposure region is relatively large. Therefore, at least two grain groups may be provided in each exposure region, and the structures of the grain groups are the same. Each grain group may include all the grains to be integrated required by the target chip. Based on this, searching for the target grains located in the same exposure region in the cut grains according to the composition information of the target chip may specifically include: searching for the target grains in the cut grains according to the composition information of the target chip in the same exposure region in ascending order of distance from the target grains that have been found. According to the composition information of the target chip, continuing to search for the target grain located in the adjacent exposure area in each of the cut grains may specifically include: according to the composition information of the target chip, searching for the target grain in each of the cut grains in the order of distance from the target grain found in the adjacent exposure area from small to large; according to the composition information of the target chip, continuing to search for the target grain located on the same wafer in each of the cut grains may include: according to the composition information of the target chip, continuing to search for the target grain in each of the cut grains in the order of distance from the target grain found on the same wafer from small to large. That is to say, when there are multiple selectable target grains in the same exposure area, or in adjacent exposure areas, or on the same wafer, the target grain that is closer to the target grain found may be preferentially selected. For example, in one example, the target chip requires a grain die1 and a grain die2. If a grain die1 has been found as the target grain, but grain die2 has not been found as another target grain, then when searching for grain die2, for the case of searching in the same exposure area, the grain die2 closest to grain die1 can be preferentially searched as another target grain. For the case of searching in adjacent exposure areas, the grain die2 closest to grain die1 can also be preferentially searched as another target grain. For the case of searching in the same wafer, the grain die2 closest to grain die1 can also be preferentially searched as another target grain.
[0058] After finding the target grains from each cut grain, each of the target grains can be integrated with each other in a non-planar manner in step S34 to obtain a target chip. Specifically, in one embodiment of the present invention, integrating each of the target grains with each other in a non-planar manner to obtain the target chip may include: dividing each of the target grains into at least two sets according to the composition information of the target chip, and the structures of each of the target grains belonging to the same set are the same; integrating the target grains belonging to different sets with each other in a non-planar manner to obtain the target chip. For example, according to the composition information of the target chip, it can be known that the target chip is non-planarly integrated by 1 grain die0 and 2 grains die1, then the target grains can be divided into 2 sets, where 100 target grains die0 are set 1, and 200 target grains die1 are set 2, then according to the composition information of the target chip, the target grains in set 1 and set 2 can be assembled with each other in a non-planar manner to obtain the target chip.
[0059] Specifically, in one embodiment of the present invention, integrating the target grains belonging to different sets in a non-planar manner to obtain the target chip may include: reconstructing the target grains in at least one of the sets, and obtaining a corresponding reconstructed wafer for each set; based on each of the reconstructed wafers, integrating each of the target grains belonging to different sets in a non-planar manner to obtain the target chip. That is to say, in this embodiment, the target grains in the same set can be formed into a corresponding reconstructed wafer, thereby forming one or more reconstructed wafers, and the target grains belonging to different sets can be integrated with each other in a non-planar manner based on the reconstructed wafer. In a specific implementation, when performing non-planar integration, the grains can be integrated with the reconstructed wafer and then cut, or one reconstructed wafer can be integrated with another reconstructed wafer and then cut, and the embodiments of the present invention do not limit this.
[0060] For example, in one embodiment of the present invention, the process of manufacturing the die to be integrated and integrating the die in a non-planar manner using the reconstructed wafer can be as follows: Figure 7 As shown in the figure, Dummy is a redundant graphic design in the die. Dummy does not have any circuit function, but can be used to enhance the wafer structure strength and maintain process consistency.
[0061] The chip manufacturing method provided by the embodiment of the present invention is described in detail below through a specific embodiment.
[0062] like Figure 8 As shown, the chip manufacturing method provided by the embodiment of the present invention may include: S401, determining the number of each to-be-integrated grain distributed in the same exposure area of the wafer according to preset conditions; The preset conditions may include: the required quantity of each to-be-integrated crystal grain of the target chip, or the required quantity of each to-be-integrated crystal grain of the target chip and the yield of each to-be-integrated crystal grain; S402, according to the number of the crystal grains to be integrated distributed in the same exposure area, manufacturing the crystal grains to be integrated in the same exposure area of the wafer; S403, testing each of the to-be-integrated dies on the wafer; S404, determining the failed grains among the grains to be integrated according to the test results; S405 , dicing and cutting the wafer and removing failed grains to obtain cut grains.
[0063] S406, determining the positional relationship between the crystal grains to be integrated according to the coordinates of the crystal grains to be integrated on the wafer; Optionally, the positional relationship may include at least one of the following: located in the same exposure area, located in adjacent exposure areas, and located on the same wafer; S407, selecting a target crystal grain from each cut crystal grain according to the composition information of the target chip, the positional relationship between each crystal grain to be integrated, and the preset priority; The preset priorities may be reduced in the following order: the target grains located in the same exposure area, the target grains located in adjacent exposure areas, and the target grains located on the same wafer; S408, dividing each target crystal grain into at least two groups according to the composition information of the target chip, and each target crystal grain belonging to the same group has the same structure; S409, performing wafer reconstruction on target dies in at least one set, and obtaining a corresponding reconstructed wafer for each set; S410 , based on each reconstructed wafer, integrating each target grain belonging to different sets with each other in a non-planar manner to obtain a target chip.
[0064] Corresponding to the aforementioned chip, an embodiment of the present invention further provides a timing analysis method for a chip, which can effectively reduce the complexity of chip design.
[0065] like Fig. 9 As shown, the timing analysis method for a chip provided by an embodiment of the present invention may include: S51, obtaining design indication information of a target chip, wherein the design indication information is used to indicate that the target chip is obtained by non-planar integration of at least two crystal grains, and the at least two crystal grains are formed by cutting after processing the same wafer; S52, according to the design instruction information, taking the target chip as a die to be analyzed, and performing timing analysis on the die to be analyzed.
[0066] Here, the die to be analyzed is the die that needs to be analyzed for timing, that is, multiple die in the target chip are equivalent to one die for timing analysis.
[0067] The timing analysis method for a chip provided by an embodiment of the present invention can obtain design indication information of a target chip, wherein the design indication information is used to indicate that the target chip is obtained by non-planar integration of at least two crystal grains, and the at least two crystal grains are formed by cutting after processing the same wafer. According to the design indication information, the target chip is taken as a crystal grain to be analyzed, and timing analysis is performed on the crystal grain to be analyzed. Since the crystal grains forming the target chip are all from the same wafer, good process consistency can be maintained between the crystal grains during the chip processing process. Based on this, when designing a chip, the crystal grains in the chip are approximately regarded as a crystal grain to be analyzed, and the process deviation of each crystal grain can be approximately regarded as the process deviation within the same crystal grain to be analyzed. Therefore, the method of timing analysis of a crystal grain can be used to perform timing analysis on the non-planar integrated target chip without considering the complex situation that the process deviations of different crystal grains are superimposed on each other, thereby effectively reducing the complexity of chip design.
[0068] In one embodiment of the present invention, in addition to indicating that the target chip is obtained by non-planar integration of at least two grains, and the at least two grains are formed by cutting after processing the same wafer, the design indication information can also be used to indicate that the at least two grains are located in the same exposure area of the same wafer or in two exposure areas adjacent to each other in the same wafer.
[0069] Since all the grains of the target chip are in the same exposure area, each layer structure of each grain in the target chip is realized through the same photolithography, so the process consistency between the grains is higher and the process deviation is smaller. When performing timing analysis on the target chip, the effect of timing analysis can be better by approximating each grain as one grain to be analyzed.
[0070] Due to issues such as die yield, in some cases, the die in the same exposure area may not be able to form a chip. Therefore, in another embodiment of the present invention, the die in the chip may also be located in two adjacent exposure areas in the same wafer. Since the exposure areas are adjacent, the photolithography processes are also relatively close, so the process consistency of the die in the chip can also be kept high.
[0071] Corresponding to the aforementioned timing analysis method for a chip, an embodiment of the present invention further provides a timing analysis device for a chip, which can effectively reduce the complexity of chip design.
[0072] like Fig.10As shown, the timing analysis device for a chip provided by an embodiment of the present invention may include: An acquisition unit 61 is used to acquire design indication information of a target chip, wherein the design indication information is used to indicate that the target chip is obtained by non-planar integration of at least two crystal grains, and the at least two crystal grains are formed by cutting after processing the same wafer; The timing analysis unit 62 is used to take the target chip as a target die and perform timing analysis on the target die according to the design instruction information.
[0073] The timing analysis device for a chip provided by an embodiment of the present invention can obtain design indication information of a target chip, wherein the design indication information is used to indicate that the target chip is obtained by non-planar integration of at least two crystal grains, and the at least two crystal grains are formed by cutting after processing the same wafer. According to the design indication information, the target chip is taken as a crystal grain to be analyzed, and timing analysis is performed on the crystal grain to be analyzed. Since the crystal grains forming the target chip are all from the same wafer, good process consistency can be maintained between the crystal grains during the chip processing process. Based on this, when designing a chip, the crystal grains in the chip are approximately regarded as a crystal grain to be analyzed, and the process deviation of each crystal grain can be approximately regarded as the process deviation within the same crystal grain to be analyzed. Therefore, the method of timing analysis of a crystal grain can be used to perform timing analysis on the non-planar integrated target chip without considering the complex situation that the process deviations of different crystal grains are superimposed on each other, thereby effectively reducing the complexity of chip design.
[0074] In one implementation, the design indication information is further used to indicate that the at least two dies are located in the same exposure region of the same wafer or in two exposure regions adjacent to each other in the same wafer.
[0075] Accordingly, an embodiment of the present invention further provides an electronic device that can effectively reduce the complexity of chip design.
[0076] like Fig.11 As shown, the electronic device provided by an embodiment of the present invention may include: a processor 71 and a memory 72, wherein the processor 71 is electrically connected to the memory 72; the memory 72 is used to store executable program codes; the processor 71 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 72, so as to implement any one of the timing analysis methods for chips provided in the aforementioned embodiments.
[0077] The specific execution process of the above steps by the processor 71 and the steps further executed by the processor 71 by running the executable program code can be found in the description of the previous embodiment and will not be repeated here.
[0078] Correspondingly, an embodiment of the present invention also provides a computer-readable storage medium, which stores one or more programs. The one or more programs can be executed by one or more processors to implement any one of the timing analysis methods for chips provided in the aforementioned embodiments, thereby also being able to achieve the corresponding technical effects, which have been described in detail above and will not be repeated here.
[0079] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0080] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.
[0081] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
[0082] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.
[0083] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.
[0084] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims
1. A chip, characterized in that: The chip includes at least two dies, and the at least two dies are integrated with each other in a non-planar manner; The at least two crystal grains are obtained by cutting from the same wafer.
2. The chip according to claim 1, characterized in that: The at least two crystal grains are located in the same exposure area of the same wafer or in two exposure areas adjacent to each other in the same wafer.
3. A method for manufacturing a chip, characterized in that: include: Fabricate all the crystal grains to be integrated required for the target chip on the same wafer, wherein the number of the crystal grains to be integrated is at least two; Slicing the wafer to obtain corresponding cut crystal grains; Selecting a target chip from the cut chips according to the composition information of the target chip; The target crystal grains are integrated with each other in a non-planar manner to obtain the target chip.
4. The method according to claim 3, characterized in that The step of manufacturing all the integrated grains required for the target chip on the same wafer includes: The to-be-integrated grains required for the target chip are fabricated in a same exposure region of the wafer, and the wafer includes at least one exposure region.
5. The method according to claim 4, characterized in that The step of manufacturing the integrated grains required for the target chip in the same exposure area of the wafer includes: Determine the number of each of the to-be-integrated grains distributed in the same exposure area of the wafer according to preset conditions, wherein the preset conditions include: the required number of each of the to-be-integrated grains by the target chip, or the required number of each of the to-be-integrated grains by the target chip and the yield of each of the to-be-integrated grains; According to the number of the crystal grains to be integrated distributed in the same exposure area, the crystal grains to be integrated are manufactured in the same exposure area of the wafer.
6. The method according to claim 5, characterized in that Each of the to-be-integrated grains required for the target chip includes at least two grain types, and each of the grain types includes at least one to-be-integrated grain; The required quantity of each of the to-be-integrated grains of the target chip includes: the quantity of the to-be-integrated grains required by each of the grain types in the target chip; The yield rate of the to-be-integrated grains includes: the yield rate of the to-be-integrated grains of each grain type; The step of determining the number of the to-be-integrated grains distributed in the same exposure area of the wafer according to the preset conditions comprises: The number of the to-be-integrated grains of each grain type in the same exposure area of the wafer is determined according to the preset conditions.
7. The method according to claim 5, characterized in that At least two grain groups are arranged in the exposure area, each of the grain groups has the same structure, and each of the grain groups includes all the grains to be integrated required by the target chip; The step of determining the number of the to-be-integrated grains distributed in the same exposure area of the wafer according to the preset conditions comprises: Determine the number of the to-be-integrated grains in each of the grain groups according to the preset conditions to obtain the number of grains in the group; The number of the to-be-integrated grains distributed in the same exposure region is determined according to the number of grains in the group.
8. The method according to any one of claims 3 to 5, characterized in that The step of selecting a target chip from each of the cut chips according to the composition information of the target chip comprises: The target die is selected from the cut die according to the composition information of the target chip and the positional relationship of the die to be integrated on the wafer.
9. The method according to claim 8, characterized in that The step of selecting the target die from the cut die according to the composition information of the target chip and the positional relationship of the die to be integrated on the wafer comprises: Determining the positional relationship between the crystal grains to be integrated according to the coordinates of the crystal grains to be integrated on the wafer, wherein the positional relationship includes at least one of the following: being located in the same exposure area, being located in adjacent exposure areas, and being located on the same wafer; The target grain is selected from the cut grains according to the composition information of the target chip, the positional relationship between the grains to be integrated, and the preset priority, wherein the preset priority decreases in the following order: the target grains located in the same exposure area, the target grains located in adjacent exposure areas, and the target grains located on the same wafer.
10. The method according to claim 9, characterized in that The step of selecting the target die from the cut die according to the composition information of the target chip, the positional relationship between the die to be integrated, and the preset priority level comprises: According to the composition information of the target chip, searching for each of the target crystal grains located in the same exposure area among the cut crystal grains; If there is the target grain that has not been found, then continue to search for the target grain located in the adjacent exposure area in each of the cut grains according to the composition information of the target chip; If there is the target die that has not been found, then the target die located on the same wafer is continuously searched among the cut die according to the composition information of the target chip.
11. The method according to claim 10, characterized in that At least two grain groups are arranged in the exposure area, each of the grain groups has the same structure, and each of the grain groups includes all the grains to be integrated required by the target chip; The step of searching for each of the target crystal grains located in the same exposure area among the cut crystal grains according to the composition information of the target chip comprises: According to the composition information of the target chip, searching for the target grain in each of the cut grains in the order of distance from the target grain that has been found in the same exposure area from small to large; The step of continuing to search for the target die located in the adjacent exposure region in each of the cut die according to the composition information of the target chip comprises: According to the composition information of the target chip, searching for the target grain in each of the cut grains in the order of distance from the target grain found in the adjacent exposure regions from small to large; The step of continuing to search for the target die located on the same wafer in each of the cut die according to the composition information of the target chip comprises: According to the composition information of the target chip, the target crystal grain is continuously searched in each of the cut crystal grains in the order of distance from the target crystal grain that has been found on the same wafer from small to large.
12. The method according to any one of claims 3 to 5, characterized in that The step of integrating the target grains with each other in a non-planar manner to obtain the target chip comprises: According to the composition information of the target chip, the target grains are divided into at least two groups, and the target grains belonging to the same group have the same structure; The target dies belonging to different sets are integrated with each other in a non-planar manner to obtain the target chip.
13. The method according to claim 12, characterized in that The step of integrating the target grains belonging to different sets with each other in a non-planar manner to obtain the target chip comprises: Reconstructing the target die in at least one of the sets, and obtaining a corresponding reconstructed wafer for each set; Based on each of the reconstructed wafers, each of the target dies belonging to different sets are integrated with each other in a non-planar manner to obtain the target chip.
14. The method according to any one of claims 3 to 5, characterized in that Before dicing the wafer to obtain corresponding cut crystal grains, the method further includes: Testing each of the to-be-integrated dies on the wafer; According to the test results, determining the failed grains among the grains to be integrated; The dicing and cutting of the wafer to obtain corresponding cut grains comprises: The wafer is diced and cut and the failed grains are removed to obtain the cut grains.
15. A timing analysis method for a chip, characterized in that: include: Acquiring design indication information of a target chip, wherein the design indication information is used to indicate that the target chip is obtained by non-planar integration of at least two crystal grains, and the at least two crystal grains are formed by cutting after processing of the same wafer; According to the design instruction information, the target chip is taken as a target crystal grain, and a timing analysis is performed on the target crystal grain.
16. The method according to claim 15, characterized in that The design indication information is further used to indicate that the at least two dies are located in the same exposure region of the same wafer or in two exposure regions adjacent to each other in the same wafer.
17. A timing analysis device for a chip, characterized in that: include: An acquisition unit, used for acquiring design indication information of a target chip, wherein the design indication information is used for indicating that the target chip is obtained by non-planar integration of at least two crystal grains, and the at least two crystal grains are formed by cutting after processing of the same wafer; The timing analysis unit is used to take the target chip as a die to be analyzed and perform timing analysis on the die to be analyzed according to the design instruction information.
18. The device according to claim 17, characterized in that The design indication information is further used to indicate that the at least two dies are located in the same exposure region of the same wafer or in two exposure regions adjacent to each other in the same wafer.
19. An electronic device, characterized in that: The electronic device includes: a processor and a memory, wherein the processor is electrically connected to the memory; the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to implement the timing analysis method for a chip as described in any one of claims 15 to 16.
20. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the timing analysis method for a chip according to any one of claims 15 to 16.