Preparation method of solar cell, solar cell and photovoltaic module

Abstract

The invention discloses a preparation method of a solar cell, the solar cell and a photovoltaic module, and the preparation method comprises the following steps: providing a cell piece, and arranging a transparent conductive layer on a light receiving surface and / or a backlight surface of the cell piece; performing microwave treatment on the transparent conductive layer on the light receiving surface and / or the backlight surface; and preparing an electrode on the surface of the transparent conductive layer. According to the invention, microwave processing is carried out on the transparent conductive layer in the cell, so that the mobility of the transparent conductive layer can be improved, the sheet resistance of the transparent conductive layer can be reduced, the contact resistivity between the transparent conductive layer and the electrode can be reduced, the series resistance of the cell is reduced, the filling factor value is improved, and finally the purpose of improving the cell efficiency is achieved.

Description

Technical Field

[0001] The invention belongs to the technical field of solar cells, and in particular relates to a method for preparing a solar cell, a solar cell and a photovoltaic module. Background Art

[0002] Heterojunction (HJT) cell is a hybrid solar cell made of crystalline silicon wafers and amorphous silicon thin films. It has many advantages such as simple preparation process, low process temperature, high open circuit voltage, high photoelectric conversion efficiency, and low temperature coefficient. It is one of the most widely used high-efficiency crystalline silicon solar energy technologies.

[0003] An important parameter for judging the performance of solar cells is the cell conversion efficiency, and the important parameters that affect cell efficiency include open circuit voltage (Voc), short circuit current (Isc) and fill factor (FF). For heterojunction cells, in order to improve the efficiency of solar cells, the commonly used method is to improve the cell efficiency by increasing Isc and FF, such as texturing on the surface of silicon wafers to trap light and increase Isc to improve the conversion efficiency of the cell, and hydrogen treatment on the surface of silicon wafers to improve the surface passivation performance of silicon wafers and thus improve the FF of the cell.

[0004] The transparent conductive layer (TCO film layer) on the surface of the heterojunction battery not only plays a role in light transmission, but also plays a role in collecting carriers. The performance of the transparent conductive layer (such as mobility, square resistance, contact resistivity, etc.) also has a great influence on the efficiency of the heterojunction battery.

[0005] Therefore, in view of the above technical problems, it is necessary to provide a method for preparing a solar cell, a solar cell and a photovoltaic module. Summary of the invention

[0006] The object of the present invention is to provide a method for preparing a solar cell, a solar cell and a photovoltaic module, so as to improve the performance of a transparent conductive layer on the surface of a cell sheet, thereby improving the efficiency of the cell.

[0007] In order to achieve the above purpose, the technical solution provided by an embodiment of the present invention is as follows: A method for preparing a solar cell, the method comprising the following steps: Providing a cell, wherein a transparent conductive layer is provided on the light-receiving surface and / or the backlight surface of the cell; Performing microwave treatment on the transparent conductive layer on the light-receiving surface and / or the backlight surface; Electrodes are prepared on the surface of the transparent conductive layer.

[0008] In one embodiment, the power of the microwave treatment is 300W to 1000W, and the treatment time is 1s to 120s.

[0009] In one embodiment, the power of the microwave treatment is 300W to 500W, and the treatment time is 1s to 5s; or, The power of microwave treatment is 500W ~ 800W, and the treatment time is 1s ~ 2s.

[0010] In one embodiment, the transparent conductive layer includes an oxide film containing indium or an oxide film not containing indium; and / or, The transparent conductive layer is a single-layer film or a multi-layer composite film; and / or, The thickness of the transparent conductive layer is 50nm to 150nm.

[0011] In one embodiment, the ambient temperature of the microwave treatment is 15° C. to 30° C.

[0012] In one embodiment, the microwave treatment is performed in an air atmosphere, a nitrogen atmosphere, or an inert gas atmosphere.

[0013] In one embodiment, during the process of performing microwave treatment on the transparent conductive layer, the cell is in a stationary state.

[0014] In one embodiment, the transparent conductive layer is deposited by a PVD process, in which the deposition gas pressure is 0.2Pa~0.85Pa, the deposition power is 0.1kW~6kW, the deposition temperature is 100°C~200°C, and the oxygen flow rate during the deposition process accounts for 0.1%~3% of the total gas flow rate.

[0015] In one embodiment, preparing an electrode on the surface of the transparent conductive layer includes: Printing conductive paste on the transparent conductive layer on the surface of the battery cell, and performing low-temperature drying and curing to prepare electrodes; Wherein, the conductive paste is pure silver paste or silver-copper paste, the low-temperature drying temperature is 100°C ~ 200°C, and the curing temperature is 150°C ~ 230°C.

[0016] In one embodiment, the cell is a HJT cell, and the surface subjected to microwave treatment is the light-receiving surface and / or the backlight surface of the HJT cell; or, The cell is an HBC cell, and the surface subjected to microwave treatment is the backlight surface of the HBC cell.

[0017] In one embodiment, the cell comprises a silicon wafer and an intrinsic amorphous silicon layer and a doped microcrystalline silicon layer sequentially stacked on a surface of the silicon wafer, and the transparent conductive layer is stacked on the doped microcrystalline silicon layer.

[0018] In one embodiment, the doping concentration of the doped microcrystalline silicon layer is 1E19 cm -3 ~2E20cm -3 Another embodiment of the present invention provides a technical solution as follows: A solar cell is prepared by the above-mentioned preparation method.

[0019] Another embodiment of the present invention provides a technical solution as follows: A photovoltaic component comprises the above-mentioned solar cell.

[0020] Compared with the prior art, the present invention has the following beneficial effects: The present invention performs microwave treatment on the transparent conductive layer in the battery cell, thereby improving the mobility of the transparent conductive layer and reducing the square resistance of the transparent conductive layer, and also reducing the contact resistivity between the transparent conductive layer and the electrode, thereby reducing the series resistance of the battery cell and improving the fill factor value, and ultimately achieving the purpose of improving the battery efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 It is a schematic diagram of the structure of a heterojunction battery in the prior art; Figure 2 It is a schematic diagram of the process of preparing a solar cell in the present invention; Figure 3 It is a schematic structural diagram of the microwave processing device in the present invention; Figure 4a , 4b They are respectively the representation structure diagrams of the front and back sides of the present invention; Figure 5 It is a schematic diagram of the front structure of the battery cell in the present invention. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the technical solutions in the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0024] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0025] Ginseng Figure 1 The figure shows a schematic diagram of the structure of a heterojunction battery (HJT) in the prior art, wherein the heterojunction battery comprises: A silicon wafer 10, comprising a first surface (i.e., a front surface or a light-receiving surface) and a second surface (i.e., a back surface or a backlight surface) disposed opposite to each other; A first intrinsic layer 21, a first doped layer 31 and a first transparent conductive layer 41 are sequentially stacked on the first surface; A second intrinsic layer 22, a second doped layer 32 and a second transparent conductive layer 42 sequentially stacked on the second surface; A first electrode 51, in contact with the first transparent conductive layer 41; The second electrode 52 contacts the second transparent conductive layer 42 .

[0026] Exemplarily, the silicon wafer 10 is N-type doped; the first intrinsic layer 21 is an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer, and the first doped layer 31 is an N-type doped amorphous silicon layer or a microcrystalline silicon layer; the second intrinsic layer 22 is an intrinsic amorphous silicon layer or an intrinsic microcrystalline silicon layer, and the second doped layer 32 is a P-type doped amorphous silicon layer or a microcrystalline silicon layer; the first transparent conductive layer 41 and the second transparent conductive layer 42 are both TCO (Transparent Conductive Oxides) layers; the first electrode 51 and the second electrode 52 are both gate line electrodes.

[0027] Furthermore, the thickness of the TCO layer is 50nm ~ 150nm, and it can be an oxide conductive film containing indium (In), such as ITO (tin-doped indium oxide), VTTO (vertical target tin oxide), IWO (molybdenum-doped indium oxide), HITO (high-purity tin-doped indium oxide), etc., or it can be an oxide conductive film not containing indium (In); in addition, the TCO layer can be a single-layer film or a multi-layer composite film.

[0028] In the prior art, the preparation process of heterojunction cells usually includes processes such as silicon wafer texturing, CVD (chemical vapor deposition), PVD (physical vapor deposition), printing slurry, low-temperature drying and curing. As described in the background technology, the performance of the transparent conductive layer (such as mobility, square resistance, contact resistivity, etc.) has a great influence on the efficiency of the heterojunction cell.

[0029] In order to improve the performance of the transparent conductive layer on the surface of the battery cell and thus improve the battery efficiency, Figure 2 As shown, the present invention discloses a method for preparing a solar cell, comprising the following steps: S1. Providing a cell, wherein a transparent conductive layer is provided on the light-receiving surface and / or the backlight surface of the cell; S2, performing microwave treatment on the transparent conductive layer on the light-receiving surface and / or the backlight surface; S3. Prepare electrodes on the surface of the transparent conductive layer.

[0030] Taking heterojunction battery (HJT) as an example, its battery structure is similar to Figure 1 The preparation method is basically the same as the existing heterojunction battery, and steps S1 and S3 in the preparation method are basically the same as the preparation process of the existing heterojunction battery.

[0031] The difference is that in this embodiment, the first intrinsic layer 21 on the light-receiving surface is an intrinsic amorphous silicon layer, and the first doped layer 31 is an N-type doped microcrystalline silicon layer; the second intrinsic layer 22 is an intrinsic amorphous silicon layer, and the second doped layer 32 is a P-type doped microcrystalline silicon layer, and the doping concentration of the N-type doped microcrystalline silicon layer and the P-type doped microcrystalline silicon layer is 1E19cm -3 ~2E21cm -3 .

[0032] Using doped microcrystalline silicon instead of doped amorphous silicon in heterojunction cells can increase the doping concentration and light transmittance, help reduce the resistance of the doped layer and increase the current density, improve the carrier transport and contact properties, and reduce light absorption losses, thereby significantly improving the photoelectric conversion efficiency of the cell.

[0033] In step S1, the transparent conductive layers on the light-receiving surface (i.e., front surface) and the backlight surface (i.e., back surface) of the cell are deposited by PVD process. The transparent conductive layer includes an oxide film containing indium or an oxide film not containing indium. It can be a single-layer film or a multi-layer composite film with a thickness of 50nm to 150nm.

[0034] Illustratively, in the PVD process, the deposition gas pressure is 0.2Pa to 0.85Pa, the deposition power is 0.1kW to 6kW, the deposition temperature is 100°C to 200°C, and the oxygen flow rate during the deposition process accounts for 0.1% to 3% of the total gas flow rate.

[0035] Taking microwave treatment of the light-receiving surface of heterojunction solar cells as an example, combined with Figure 3 As shown, the microwave treatment is performed by a microwave treatment device. The microwave treatment device includes a box 210 and a conveying device 220. The box 210 is provided with at least one microwave source 211. The conveying device 220 is provided with a carrier plate 221 for carrying the battery cell 100. Preferably, the microwave source 211 is located above the conveying device 220.

[0036] After completing the PVD process in step S1, the battery cell 100 is placed on a carrier 221 on a conveying device 220, and the carrier 221 and the battery cell thereon are conveyed into a box 210 along a predetermined direction. When conveyed to a predetermined position, the conveyance is stopped to keep the battery cell 100 in a stationary state. In the stationary state, the microwave source 211 is turned on to perform microwave treatment on the transparent conductive layer on the surface of the battery cell.

[0037] Exemplarily, the conveying device 220 is described using a conveyor belt as an example, and the conveying direction is preferably horizontal. In other embodiments, conveying rollers or the like may be used to convey the carrier and the battery cells, and the microwave source 211 is not limited to being disposed above the conveying device 220 .

[0038] In step S3, preparing an electrode on the surface of the transparent conductive layer includes: Conductive paste is printed on the transparent conductive layer on the surface of the cell, and low-temperature drying and curing are performed to prepare electrodes. Preferably, the conductive paste is pure silver paste or silver-copper paste, the low-temperature drying temperature is 100°C to 200°C, and the curing temperature is 150°C to 230°C.

[0039] The preparation process of the heterojunction battery in the present invention includes the steps of silicon wafer texturing, CVD (chemical vapor deposition), PVD (physical vapor deposition), microwave treatment, printing slurry, low-temperature drying and curing.

[0040] Compared with the existing preparation process, by adding a microwave treatment process to the transparent conductive layer before electrode preparation, the mobility of the transparent conductive layer can be improved and the square resistance of the transparent conductive layer can be reduced. In addition, the contact resistivity (Rc) between the transparent conductive layer and the electrode can be reduced, thereby reducing the battery series resistance (Rs) and increasing the fill factor (FF) value, ultimately achieving the purpose of improving the efficiency of the heterojunction battery.

[0041] In addition, the doped microcrystalline silicon layer and the intrinsic amorphous silicon layer on the surface of the silicon wafer will also be processed simultaneously during microwave treatment. Compared with the doped amorphous silicon layer, the doped microcrystalline silicon layer will promote the diffusion of H in the doped microcrystalline silicon layer after microwave treatment, thereby reducing the dangling bonds and defects in the film layer, thereby ensuring that the doped microcrystalline silicon layer has excellent field passivation performance, while ensuring that the battery has a higher performance fill factor (pFF).

[0042] The process parameters in microwave treatment are described in detail below.

[0043] 1. Microwave treatment power and treatment time The power of the microwave treatment in the present invention is 300W ~ 1000W, and the treatment time is 1s ~ 120s.

[0044] The power and processing time in the microwave processing process need to be coordinated. High power matches a shorter processing time, and low power matches a longer processing time. Too high power will cause the battery cell temperature to be too high and damage the passivation layer, resulting in a decrease in battery efficiency. Too low power will not achieve the purpose of improving battery conversion efficiency.

[0045] Exemplarily, the preferred ranges of microwave treatment power and treatment time are: The power of microwave treatment is 300W ~ 500W, and the treatment time is 1s ~ 5s; or, The power of microwave treatment is 500W ~ 800W, and the treatment time is 1s ~ 2s.

[0046] 2. Ambient temperature of microwave treatment The temperature of the microwave treatment can be 15°C to 30°C, preferably, the temperature is room temperature (25°C±5°C).

[0047] 3. Microwave treatment atmosphere The microwave treatment is performed in the box 210 , and the atmosphere in the box 210 can be an air atmosphere, a nitrogen atmosphere, or an inert gas (such as argon, etc.) atmosphere.

[0048] 4. Thickness of TCO layer The transparent conductive layer includes an oxide film containing indium or an oxide film not containing indium, and can be a single-layer film or a multi-layer composite film with a thickness of 50nm to 150nm.

[0049] When the thickness of the TCO layer increases, the parasitic absorption of the film layer increases, which leads to a decrease in the short-circuit current (Isc) of the battery. When the thickness of the TCO layer decreases, the effective use efficiency of light decreases, the transmission efficiency of photoelectrons decreases, and the photoelectric conversion efficiency of the battery cell decreases. Therefore, the thickness of the front and back TCO layers in the present invention needs to be optimized, and the thickness ranges from 50nm to 150nm, preferably from 80nm to 120nm, and optimally 100nm.

[0050] The present invention is further described below in conjunction with specific comparative examples and embodiments.

[0051] In the following comparative examples and embodiments, the electrical performance parameters of the transparent conductive layer are characterized as follows: a) Sheet resistance and mobility of transparent conductive layer The same TCO layer as the heterojunction cell is plated on the glass sheet using PVD equipment and the same process parameters. Then, the glass sheet is processed in the same way as the heterojunction cell and finally cut into the sample size required by the Hall tester (15 mm 15 mm) to perform Hall test to obtain Hall square resistance, mobility and carrier concentration.

[0052] By comparing with the sample that has not been microwave treated, if the square resistance of the microwave treated sample is lower than that of the sample that has not been microwave treated, it is determined that the microwave treatment reduces the square resistance of the TCO layer; if the mobility of the microwave treated sample is higher than that of the sample that has not been microwave treated, it is determined that the microwave treatment improves the mobility of the TCO layer.

[0053] b) Contact resistivity between TCO layer and electrode (Rc) Front contact resistivity test using Figure 4a The characterization structure shown is characterized, and the back contact resistivity test is performed using Figure 4b The characterization structure shown is characterized.

[0054] Specifically, Figure 4a The structure shown in the figure includes a silicon wafer 10, a first intrinsic layer 21, a first doped layer 31, a first transparent conductive layer 41 and a first electrode 51, wherein the silicon wafer 10 is a P-type silicon wafer, and the pyramid velvet structure on its surface is not shown, the first doped layer 31 is an N-type doped microcrystalline silicon layer, and the first electrode 51 is an Ag gate line electrode; Figure 4b The characterizing structure includes a silicon wafer 10, a second intrinsic layer 22, a second doped layer 32, a second transparent conductive layer 42 and a second electrode 52, wherein the silicon wafer 10 is an N-type silicon wafer, and the pyramid velvet structure on its surface is not shown, the second doped layer 32 is a P-type doped microcrystalline silicon layer, and the second electrode 52 is an Ag gate line electrode.

[0055] The cells before and after microwave treatment are cut by laser. Figure 5 The sample is cut into the sample size required for TLM test, and then the contact resistance of the front and back grid electrodes is tested respectively. For example, the size of the cell is 220mm 105mm, the front and back sides include the main grid line 501 and the secondary grid line 502, the spacing between the main grid lines is 8.5mm, the cutting area is the area between two adjacent main grid lines 501, and the sample size is 7 mm 105 mm, cutting can be done by laser process.

[0056] By comparing the contact resistance results of the samples after microwave treatment with those without microwave treatment, if the contact resistance is reduced after microwave treatment, it is determined that microwave treatment helps to reduce the contact resistivity between the TCO layer and the electrode.

[0057] c) Battery efficiency (EFF) and series resistance (Rs) The heterojunction cells prepared by microwave treatment and the cells without microwave treatment are tested by an online Sinton IV tester to obtain the efficiency and series resistance of the cells. If the efficiency of the heterojunction cell treated with microwave is higher than that of the cell without microwave treatment, it is determined that microwave treatment can improve the efficiency of the heterojunction cell. If the series resistance of the heterojunction cell treated with microwave is lower than that of the cell without microwave treatment, it is determined that microwave treatment can reduce the series resistance of the heterojunction cell.

[0058] Comparative Example: This comparative example is a method for preparing a heterojunction battery. The structure of the heterojunction battery is as follows: Figure 1 As shown, the preparation method comprises the following steps: First, the heterojunction cell is prepared using conventional preparation processes (silicon wafer texturing, CVD, PVD and other processes).

[0059] Among them, the transparent conductive layers on the front and back of the heterojunction cell are deposited by PVD process. The first transparent conductive layer on the front is VTTO layer with a thickness of 92nm. The deposition pressure in the PVD process is 0.5Pa, the deposition power is 5kW, the deposition temperature is 160℃, and the oxygen flow rate during the deposition process accounts for 1.5% of the total gas flow rate; the second transparent conductive layer on the back is VTTO layer with a thickness of 110nm. The deposition pressure in the PVD process is 0.4Pa, the deposition power is 6kW, the deposition temperature is 160℃, and the oxygen flow rate during the deposition process accounts for 2% of the total gas flow rate.

[0060] Then, electrodes are prepared on the surface of the transparent conductive layer using conventional processes.

[0061] Specifically, in this comparative example, conductive silver paste is printed on the transparent conductive layer on the surface of the cell, and low-temperature drying and curing are performed to prepare silver grid line electrodes. Exemplarily, the low-temperature drying temperature is 150°C, and the curing temperature is 200°C.

[0062] Example:

[0063] This embodiment is a method for preparing a heterojunction battery. The structure of the heterojunction battery is also as follows. Figure 1 As shown, the preparation method comprises the following steps: First, the heterojunction cell is prepared using conventional preparation processes (silicon wafer texturing, CVD, PVD and other processes).

[0064] Among them, the transparent conductive layers on the front and back of the heterojunction cell are deposited by PVD process. The first transparent conductive layer on the front is VTTO layer with a thickness of 92nm. The deposition pressure in the PVD process is 0.5Pa, the deposition power is 5kW, the deposition temperature is 160℃, and the oxygen flow rate during the deposition process accounts for 1.5% of the total gas flow rate; the second transparent conductive layer on the back is VTTO layer with a thickness of 110nm. The deposition pressure in the PVD process is 0.4Pa, the deposition power is 6kW, the deposition temperature is 160℃, and the oxygen flow rate during the deposition process accounts for 2% of the total gas flow rate.

[0065] Then, the transparent conductive layer on the surface of the cell is subjected to microwave treatment.

[0066] Different from the comparative example, in this embodiment, a microwave treatment process is added to the transparent conductive layer before preparing the electrode. Figure 3 The device is used, the microwave power is 300W ~ 1000W, the processing time is 1s ~ 120s, the ambient temperature is 25°C, and the atmosphere is air atmosphere.

[0067] Finally, electrodes are prepared on the surface of the transparent conductive layer using conventional processes.

[0068] Specifically, in this comparative example, conductive silver paste is printed on the transparent conductive layer on the surface of the cell, and low-temperature drying and curing are performed to prepare silver grid line electrodes. Exemplarily, the low-temperature drying temperature is 150°C, and the curing temperature is 200°C.

[0069] By changing the microwave power and treatment time in the microwave treatment process, the electrical performance parameters of the TCO layer were characterized using the aforementioned characterization method. The characterization results are shown in Table 1.

[0070] Microwave power(W) Processing time(s) Front TCO square resistance (Ω / sq) <![CDATA[Front TCO mobility (cm 2 V - 1 s -1 )]]> <![CDATA[Front TCO carrier concentration (E20cm -3 > <![CDATA[Front TCO / Electrode Contact Resistivity (mΩ·cm -2 )]]> Back TCO square resistance (Ω / sq) <![CDATA[Back TCO Mobility (cm 2 V - 1 s -1 )]]> <![CDATA[Back TCO Carrier Concentration (E20 cm -3 )]]> <![CDATA[Back TCO / Electrode Contact Resistivity (mΩ·cm -2 )]]> Comparative Example - - 49 71.5 1.93 1.01 29 53 3.70 0.46 Example 1 300 1 49 71.5 1.93 0.98 29 53 3.69 0.46 Example 2 500 5 48 73 1.95 0.95 29 54 3.68 0.44 Example 3 800 10 47 75 1.91 0.90 28 56 3.65 0.42 Example 4 1000 20 47 76 1.89 0.93 27 57 3.67 0.43 Example 5 1000 120 46 77 1.90 0.91 27 57 3.66 0.42 Table 1: Electrical performance parameters of TCO layer under different microwave treatment processes As can be seen from Table 1, compared with the cells that have not been microwave treated, at room temperature 25°C, when the microwave treatment power and time are too low (300W, 1s), there is no effect on the sheet resistance of the TCO layer and the contact resistivity between the TCO layer and the electrode. When the microwave treatment power is 800W and the time is 10s, the sheet resistance of the TCO layer on the front side of the cell reaches 47Ω / sq, and the sheet resistance on the back side reaches 28Ω / sq. This is because the high temperature promotes the growth of grains in the TCO layer, thereby promoting the mobility of the front TCO layer from 71.5cm 2 V -1 s -1 Increase to 75cm 2 V -1 s -1, thereby reducing the square resistance of the front TCO layer. At the same time, the contact resistivity between the front and back TCO layer electrodes is also slightly reduced. When the power and time of microwave treatment are too high (1000W, 120s), the square resistance of the front TCO layer is further reduced to 46Ω / sq.

[0071] By changing the microwave power and treatment time in the microwave treatment process, the electrical performance parameters of the heterojunction battery were characterized using the aforementioned characterization method. The characterization results are shown in Table 2.

[0072] Microwave power(W) Processing time(s) Isc(A) Voc(mV) FF(%) EFF(%) Rs(mΩ) pFF(%) Comparative Example - - 8.956 750.1 86.20 26.21 -0.10 86.66 Example 6 300 1 8.958 750.1 86.21 26.22 -0.11 86.68 Example 7 300 5 8.961 750.1 86.27 26.25 -0.16 86.68 Example 8 300 10 8.950 749.6 86.17 26.17 -0.20 86.53 Example 9 500 1 8.957 750.0 86.21 26.22 -0.10 86.67 Example 10 500 3 8.962 750.0 86.26 26.25 -0.16 86.67 Embodiment 11 500 5 8.965 750.0 86.34 26.28 -0.22 86.67 Example 12 500 10 8.947 749.0 86.11 26.12 -0.26 86.40 Embodiment 13 800 1 8.955 750.1 86.21 26.21 -0.11 86.67 Embodiment 14 800 2 8.957 750.0 86.26 26.23 -0.14 86.68 Embodiment 15 800 5 8.947 748.7 84.83 25.72 -0.20 85.60 Example 16 800 10 8.945 748.3 82.98 25.14 -0.35 83.19 Embodiment 17 1000 1 8.954 750.0 86.19 25.20 -0.10 86.66 Embodiment 18 1000 20 8.901 745.0 82.48 24.76 -0.71 82.33 Embodiment 19 1000 120 8.777 743.0 70.64 20.85 -1.10 70.10 Table 2: Electrical performance parameters of heterojunction cells under different microwave treatment processes As can be seen from Table 2, compared with the cells that have not been microwave treated, at room temperature of 25°C, when the microwave treatment power is 300W and 500W, as the treatment time increases (1s-5s), the cell efficiency (EFF) gradually increases, and the maximum efficiency gain is 0.07%, mainly due to the reduction of the series resistance (Rs) and the increase of the short-circuit current (Isc). The reduction of the series resistance (Rs) is due to the reduction of the square resistance of the TCO layer and the reduction of the contact resistivity between the TCO layer and the electrode. When the microwave treatment power is 500W and the treatment time is 10s, the battery performance begins to decline, mainly due to the attenuation of the performance fill factor (pFF). When the power increases to 800W to 1000W, due to the high temperature generated by the high power, the intrinsic amorphous silicon layer on the front and back of the cell will gradually transform into a microcrystalline silicon layer, resulting in a decrease in the passivation performance, thereby reducing the performance fill factor (pFF) of the battery, and finally reducing the battery efficiency (EFF).

[0073] In this embodiment, the front side of the silicon wafer is stacked with an intrinsic amorphous silicon layer, an N-type doped microcrystalline silicon layer and a TCO layer, and the back side of the silicon wafer is stacked with an intrinsic amorphous silicon layer, a P-type doped microcrystalline silicon layer and a TCO layer. By changing the thickness of the TCO layer, the electrical performance parameters of the heterojunction battery are characterized by the aforementioned characterization method. The characterization results are shown in Table 3.

[0074] Front TCO layer thickness (nm) Back TCO layer thickness (nm) Microwave power(W) Processing time(s) Isc(A) Voc(mV) FF(%) EFF(%) Rs(mΩ) pFF(%) Comparative Example 100 100 - - 8.956 750.1 86.20 26.21 -0.10 86.66 Embodiment 20 50 50 500 5 8.970 749.5 86.24 26.25 -0.14 86.60 Embodiment 21 80 80 500 5 8.967 749.7 86.28 26.26 -0.17 86.63 Embodiment 22 100 100 500 5 8.965 750.0 86.34 26.28 -0.22 86.67 Embodiment 23 120 120 500 5 8.955 750.1 86.39 26.27 -0.26 86.68 Embodiment 24 150 150 500 5 8.950 750.0 86.43 26.26 -0.29 86.67 Table 3: Electrical performance parameters of heterojunction cells under microwave treatment process with different TCO layer thickness As can be seen from Table 3, for heterojunction cells with different TCO layer thicknesses, microwave treatment (microwave power of 500W, treatment time of 5s) was used at room temperature of 25°C. It can be seen that with the increase of TCO layer thickness, the efficiency (EFF) of the cell after microwave treatment first increases and then decreases. This is mainly due to the increase in TCO layer thickness, which enhances the parasitic absorption of the film layer, thereby reducing the Isc of the cell. When the thickness of the TCO layer on the front and back is 100nm, the cell performance is optimal.

[0075] In summary, it is very important to select the appropriate power and treatment time in the microwave treatment process, and the thickness of the TCO layer also needs to be controlled and optimized. The optimal microwave treatment power and time in the present invention are: the microwave treatment power is 300W ~ 500W, and the treatment time is 1s ~ 5s; or, the microwave treatment power is 500W ~ 800W, and the treatment time is 1s ~ 2s, and the thickness of the front and back TCO layers is 50nm ~ 150nm, preferably 80nm ~ 120nm, and the optimal is 100nm.

[0076] It should be understood that the above embodiments are described by taking heterojunction batteries as an example, but the present invention is not limited to heterojunction batteries, but can also be applied to back contact heterojunction (HBC) batteries. The transparent conductive layer and the electrode in the HBC battery are formed on the backlight surface. Therefore, the HBC battery only needs to be subjected to microwave treatment on the backlight surface. The specific treatment process is the same as that in the above embodiments and will not be repeated here.

[0077] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0078] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A method for preparing a solar cell, characterized in that: The preparation method comprises the following steps: Providing a cell, wherein a transparent conductive layer is provided on the light-receiving surface and / or the backlight surface of the cell; Performing microwave treatment on the transparent conductive layer on the light-receiving surface and / or the backlight surface; Electrodes are prepared on the surface of the transparent conductive layer.

2. The preparation method according to claim 1, characterized in that: The power of microwave treatment is 300W ~ 1000W, and the treatment time is 1s ~ 120s.

3. The preparation method according to claim 1, characterized in that: The power of microwave treatment is 300W ~ 500W, and the treatment time is 1s ~ 5s; or, The power of microwave treatment is 500W ~ 800W, and the treatment time is 1s ~ 2s.

4. The preparation method according to claim 1, characterized in that: The transparent conductive layer includes an oxide film containing indium or an oxide film not containing indium; and / or, The transparent conductive layer is a single-layer film or a multi-layer composite film; and / or, The thickness of the transparent conductive layer is 50nm to 150nm.

5. The preparation method according to claim 1, characterized in that: The ambient temperature for microwave treatment is 15℃ ~ 30℃.

6. The preparation method according to claim 1, characterized in that: The microwave treatment is performed in an air atmosphere, a nitrogen atmosphere, or an inert gas atmosphere.

7. The preparation method according to claim 1, characterized in that: During the microwave treatment of the transparent conductive layer, the cell is in a stationary state.

8. The preparation method according to claim 1, characterized in that: The transparent conductive layer is deposited by a PVD process, in which the deposition pressure is 0.2Pa to 0.85Pa, the deposition power is 0.1kW to 6kW, the deposition temperature is 100°C to 200°C, and the oxygen flow rate during the deposition process accounts for 0.1% to 3% of the total gas flow rate.

9. The preparation method according to claim 1, characterized in that: Preparing electrodes on the surface of the transparent conductive layer includes: Printing conductive paste on the transparent conductive layer on the surface of the battery cell, and performing low-temperature drying and curing to prepare electrodes; Wherein, the conductive paste is pure silver paste or silver-copper paste, the low-temperature drying temperature is 100°C ~ 200°C, and the curing temperature is 150°C ~ 230°C.

10. The preparation method according to claim 1, characterized in that: The cell is a HJT cell, and the surface subjected to microwave treatment is the light-receiving surface and / or the backlight surface of the HJT cell; or, The cell is an HBC cell, and the surface subjected to microwave treatment is the backlight surface of the HBC cell.

11. The preparation method according to claim 1, characterized in that: The cell comprises a silicon wafer and an intrinsic amorphous silicon layer and a doped microcrystalline silicon layer sequentially stacked on the surface of the silicon wafer, and the transparent conductive layer is stacked on the doped microcrystalline silicon layer.

12. The preparation method according to claim 11, characterized in that: The doping concentration of the doped microcrystalline silicon layer is 1E19 cm -3 ~2E21cm -3 .

13. A solar cell, characterized in that: The solar cell is prepared by the preparation method according to any one of claims 1 to 10.

14. A photovoltaic module, characterized in that: The photovoltaic module comprises the solar cell of claim 13.

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