Solar cell and photovoltaic module

Abstract

The invention provides a solar cell and a photovoltaic module, and belongs to the technical field of semiconductor devices. The solar cell of the present application comprises: a semiconductor substrate comprising a first surface having a plurality of first texture structures, the first texture structures comprising a bottom surface, a side surface and a top surface in a direction away from the first surface, the side surface being located between the bottom surface and the top surface; the tunneling layer is located on the first surface of the semiconductor substrate, and the thickness of the tunneling layer located on the top surface and / or the bottom surface is larger than that of the tunneling layer located on the side surface; and the doped semiconductor layer is located on the surface, far away from the semiconductor substrate, of the tunneling layer.

Description

Technical Field

[0001] The present application relates to the technical field of photovoltaic cells, and in particular, to a solar cell and a photovoltaic module. Background Art

[0002] Different passivation contact schemes are increasingly being used in solar cells to improve cell conversion efficiency. Among them, tunneling passivation contact technology can achieve excellent surface passivation and carrier selective collection. It usually deposits a tunneling layer and a doped semiconductor layer on the surface of the cell. The tunneling layer and the doped semiconductor layer together constitute a tunneling passivation contact structure to achieve a passivation effect.

[0003] In order to improve the light trapping capability of the battery surface, the battery surface usually has an undulating microstructure. However, there is still room for improvement in how to form a tunnel passivation contact structure with good contact on the microstructure. Summary of the invention

[0004] In view of this, in order to at least partially solve at least one of the above-mentioned technical problems, the present application provides a solar cell and a photovoltaic module.

[0005] In order to achieve the above objectives, the technical solution of this application is as follows.

[0006] According to an embodiment of one aspect of the present application, a solar cell is provided, comprising: a semiconductor substrate, comprising a first surface having a plurality of first texture structures, wherein along a direction away from the first surface, the first texture structures comprise a bottom surface, a side surface and a top surface, and the side surface is located between the bottom surface and the top surface; a tunneling layer, located on the first surface of the semiconductor substrate, wherein the thickness of the tunneling layer located on the top surface and / or the bottom surface is greater than the thickness of the tunneling layer located on the side surface; and a doped semiconductor layer, located on the surface of the tunneling layer away from the semiconductor substrate.

[0007] According to another embodiment of the present application, a photovoltaic assembly is provided, comprising: a plurality of the above-mentioned solar cells connected into a solar cell string; and a packaging structure disposed around the periphery of the solar cell string.

[0008] In an embodiment of the present application, a tunneling layer is deposited on a semiconductor substrate, and a doped semiconductor layer is deposited on the tunneling layer. The semiconductor substrate includes a first surface having a plurality of first texture structures, wherein the thickness of the tunneling layer deposited on the top surface and / or the bottom surface of the first texture structure is greater than the thickness of the tunneling layer deposited on the side surface, which makes the interface state density between the tunneling layer and the semiconductor substrate different on the top, bottom and side surfaces. Specifically, on the top surface or the bottom surface, a thicker tunneling layer is provided, which is more conducive to reducing the interface state density between the tunneling layer and the semiconductor substrate, thereby being more conducive to improving the passivation effect, and in combination with the tunneling passivation structure formed by the doped polysilicon layer, the passivation effect of the silicon substrate surface can be further improved; on the side surface, a thinner tunneling layer is provided, which is more conducive to retaining the conductive channel, thereby being more conducive to reducing the contact resistance. By making the thickness of the tunneling layer different on the top, bottom and side surfaces of the first texture structure, the balance and improvement of the passivation and contact performance are taken into account.

[0009] In the embodiments of the present application, the solar cells and photovoltaic modules of the present application, when using the selective passivation contact structure provided by the present application, help to improve the passivation contact effect and the electrical transmission effect, thereby improving the photoelectric conversion efficiency of the solar cells and photovoltaic modules. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0011] Figure 1 A schematic diagram of the structure of a solar cell according to an embodiment of the present application;

[0012] Figure 2 is a side view schematic diagram of a first texture structure according to an embodiment of the present application;

[0013] Figure 3 A transmission electron microscope (TEM) image of a local cross section of a solar cell according to an embodiment of the present application;

[0014] Figure 4 is a TEM image of a cross section of a top surface of a first texture structure of an embodiment of the present application;

[0015] Figure 5 A TEM image of a side surface cross section of a first texture structure according to an embodiment of the present application;

[0016] Figure 6 A schematic side view of a protruding structure of a first texture structure according to an embodiment of the present application;

[0017] Figure 7 A flow chart of a method for a solar cell according to an embodiment of the present application;

[0018] Figure 8 A schematic structural diagram of a solar cell according to another embodiment of the present application;

[0019] Fig. 9 This is a schematic structural diagram of a solar cell according to another embodiment of the present application. DETAILED DESCRIPTION

[0020] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0021] The terms used herein are only for describing specific embodiments and are not intended to limit the present application. The terms "including", "comprising", etc. used herein indicate the presence of features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components. All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0022] The relative position between two components (such as film layers or regions) mentioned in this application, such as "above", "upper" or "above", may refer to the direct contact between the two components, or may refer to the indirect contact between the two components. Similarly, the relative position between two components mentioned in this application, such as "below", "lower" or "below", may refer to the direct contact between the two components, or may refer to the indirect contact between the two components. For example, when one of the components (such as film layers or regions) is referred to as "on another component", it can be directly on the other component, or there may be other components between the two. On the other hand, when a component is referred to as "directly on another component", there is no component between the two. In addition, when one of the components is referred to as "on another component", the two have an up-and-down relationship in the top-view direction, and this component can be above or below the other component, so this up-and-down relationship depends on the orientation of the device.

[0023] For solar cells with tunnel passivation contact structures, in order to improve the surface light trapping ability, a concave-convex structure is usually made on the surface of the semiconductor substrate, and a tunnel passivation contact structure is deposited on the surface of the concave-convex structure. The tunnel passivation contact structure includes a tunnel layer and a doped semiconductor layer, which can block the transmission of minority carriers and selectively allow majority carriers to pass through, effectively reducing the surface recombination of majority carriers and minority carriers. However, the layered structure formed by the tunnel layer and the doped semiconductor layer on the surface of the concave-convex structure is not uniform, which leads to the passivation effect and electrical contact performance still have room for improvement.

[0024] In the process of realizing the technical concept of this application, it was found that by selecting appropriate deposition conditions, tunnel layers of different thicknesses can be deposited on different surfaces of the concave-convex structure. Based on the different carrier transport mechanisms of tunnel layers of different thicknesses, regulating the side surface of the concave-convex structure is more conducive to reducing contact resistance, and the top and bottom surfaces are more conducive to improving the passivation effect, thereby synergistically improving the passivation effect and reducing contact resistance, thereby improving the electrical performance of the battery.

[0025] Specifically, according to an embodiment of one aspect of the present application, a solar cell is provided. Figure 1 Schematic diagram of the structure of a solar cell according to an embodiment of the present application. Figure 2 The side view schematic diagrams of the first texture structure of the embodiment of the present application, wherein (a) is a side view schematic diagram of the first texture structure being a convex structure, (b) is a side view schematic diagram of the first texture structure being a concave structure, and (c) is a side view schematic diagram of the first texture structure being another convex structure. Figure 1 , Figure 2 As shown in (a) to (c) of FIG. 1 , the solar cell provided in the embodiment of the present application includes a semiconductor substrate 101, a tunneling layer 102 and a doped semiconductor layer 103. The semiconductor substrate 101 includes a first surface 101a having a plurality of first texture structures 1011. In a direction away from the first surface 101a, the first texture structure 1011 includes a bottom surface 1011a, a side surface 1011b and a top surface 1011c, and the side surface 1011b is located between the bottom surface 1011a and the top surface 1011c. The tunneling layer 102 is located on the first surface 101a of the semiconductor substrate 101, and the thickness of the tunneling layer 102 located on the top surface 1011c and / or the bottom surface 1011a is greater than the thickness of the tunneling layer 102 located on the side surface 1011b. The doped semiconductor layer 103 is located on the surface of the tunneling layer 102 away from the semiconductor substrate 101.

[0026] According to an embodiment of the present application, a tunneling layer is deposited on a semiconductor substrate, and a doped semiconductor layer is deposited on the tunneling layer. The semiconductor substrate includes a first surface having a plurality of first texture structures, wherein the thickness of the tunneling layer deposited on the top surface or the bottom surface of the first texture structure is greater than the thickness of the tunneling layer deposited on the side surface, which makes the interface state density between the tunneling layer and the semiconductor substrate different on the top, bottom and side surfaces. Specifically, on the top or bottom surface, setting a thicker tunneling layer is more conducive to reducing the interface state density between the tunneling layer and the semiconductor substrate, thereby facilitating improving the passivation effect; on the side surface, setting a thinner tunneling layer is more conducive to retaining a conductive channel, thereby facilitating reducing contact resistance. Thus, by setting the thickness of the tunneling layer on the top, bottom and side surfaces of the first texture structure to be different, the balance and improvement of passivation and contact performance can be taken into account.

[0027] According to the embodiments of this application, please continue to refer to Figure 2 As shown in (a) to (c) in FIG. 1 , along the direction s away from the first surface 101a, the first texture structure 1011 may be a convex structure or a concave structure. When the projection area of ​​the top surface 1011c in the extending direction of the first surface 101a accounts for a larger proportion than the projection area of ​​the bottom surface 1011a in the extending direction of the first surface 101a, it can be indicated that the first texture structure 1011 is a convex structure, such as Figure 2 As shown in (a) and (c) of FIG. 101 ; and the projection area of ​​the top surface 1011c in the extension direction of the first surface 101a is smaller than the projection area of ​​the bottom surface 1011a in the extension direction of the first surface 101a, it can be indicated that the first texture structure 1011 is a groove structure, such as Figure 2 As shown in Figure (b).

[0028] In the above two cases, the "inclination angle" is defined as the angle between the bottom surface 1011a, the side surface 1011b or the top surface 1011c and the extension direction of the first surface 101a, then the bottom surface 1011a or the top surface 1011c has a smaller inclination angle than the side surface 1011b, so that there are top surfaces, bottom surfaces and side surfaces. Further optionally, the top surface 1011c and / or the bottom surface 1011a can be roughly in the shape of a plane parallel to the extension direction of the first surface 101a, for example, it is allowed to have a smaller inclination angle, for example, 0~10°, preferably 0~5°, more preferably 0~2°, and most preferably 0~0.5°, and it is allowed to have micro-nano structures such as grains on it, rather than a smooth surface.

[0029] According to the embodiments of the present application, Figure 2 As shown in FIG. (c), along the direction s away from the first surface 101a, the side surface of at least one first texture structure 1011 may include at least two sub-side surfaces that are non-continuously arranged, and the first texture structure 1011 also includes a transition surface 1011d located between two adjacent sub-side surfaces, so that the first texture structure 1011 presents a laminated tower base structure. The arrangement of the laminated tower base structure is conducive to increasing the light trapping effect.

[0030] Similarly, the transition surface 1011d has a smaller inclination angle than the side surface 1011b, and further optionally, the transition surface 1011d may be substantially in the shape of a plane parallel to the extension direction of the first surface 101a. Figure 2 The first texture structures shown in FIGS. (a) and (c) can be disposed on the first surface individually or in combination, and are randomly distributed on the first surface 101 a .

[0031] According to the embodiment of the present application, the formation of the first texture structure 1011 enables the surface of the semiconductor substrate 101 to have an undulating texture structure, which helps to increase the light trapping effect and improve the photoelectric conversion efficiency of the solar cell.

[0032] Further optionally, the "first texture structure 1011" on the semiconductor substrate 101 can be a microstructure obtained by texturing the first surface of the initial substrate and then polishing it; or it can be a microstructure obtained by directly polishing the first surface of the initial substrate without texturing it.

[0033] According to an embodiment of the present application, the semiconductor substrate 101 may be an N-type or P-type silicon substrate, for example, it may be a semiconductor material selected from monocrystalline silicon, polycrystalline silicon, and microcrystalline silicon, preferably an N-type or P-type monocrystalline silicon substrate. The conversion efficiency of cells based on monocrystalline silicon substrates is higher than that of other types such as polycrystalline silicon cells. An N-type silicon substrate is obtained by introducing donor impurities such as phosphorus (P), arsenic (As), or antimony (Sb) into these semiconductor materials, or a P-type silicon substrate is obtained by introducing acceptor impurities such as boron (B), aluminum (Al), or gallium (Ga) into these semiconductor materials.

[0034] According to an embodiment of the present application, the first surface 101a of the semiconductor substrate 101 can be a light-receiving surface or a backlight surface, preferably a backlight surface. With this configuration, the doped semiconductor layer 103 has smaller optical parasitic absorption when located on the backlight surface than when located on the light-receiving surface.

[0035] According to an embodiment of the present application, the tunneling layer 102 and the doped semiconductor layer 103 cooperate to form a tunneling passivation contact structure, wherein the tunneling layer 102 is used to transmit majority carriers and achieve a passivation effect, and is made of silicon oxide, which can be obtained by plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD). The doped semiconductor layer 103 can be at least one semiconductor material such as a polycrystalline silicon layer or a microcrystalline silicon layer, and its doping type can be the same as or different from the doping type of the semiconductor substrate 101, which can be determined specifically according to the battery type and the semiconductor substrate 101.

[0036] For example, taking a TOPcon cell as an example, when the semiconductor substrate 101 is an N-type silicon substrate, the doped semiconductor layer 103 may be N-type doped or P-type doped, or when the semiconductor substrate 101 is a P-type silicon substrate, the doped semiconductor layer 103 may be N-type doped or P-type doped. The thickness of the doped semiconductor layer 103 is 50-300nm, preferably 80-180nm, for example, 50nm, 80nm, 100nm, 120nm, 150nm, 180nm, 200nm, 250nm, 280nm, 300nm, etc. The appropriate polysilicon thickness can better match the tunneling layer, improve the field passivation performance, and ensure the passivation effect.

[0037] Figure 3 This is a transmission electron microscope (TEM) image of a local cross section of a solar cell according to an embodiment of the present application. Figure 4 is a TEM image of a top surface cross section of the first texture structure of an embodiment of the present application. Figure 5 This is a TEM image of the side surface cross-section of the first texture structure of the embodiment of the present application.

[0038] According to the embodiments of the present application, Figures 3 to 5 As shown, it can be seen that the thickness of the tunneling layer on the top surface 1011c is greater than the thickness of the tunneling layer on the side surface 1011b, and the thickness of the tunneling layer on the bottom surface 1011a can also be set to a thickness similar to that of the tunneling layer on the top surface 1011c. Further optionally, the ratio between the thickness of the tunneling layer 102 on the top surface 1011c and / or the bottom surface 1011a and the thickness of the tunneling layer 102 on the side surface 1011b is greater than 1 and less than or equal to 4, for example, it can be 1.5, 2, 2.5, 3, 3.5, 4, etc. The tunneling layer on the top surface 1011c and / or the bottom surface 1011a needs to be thicker to provide a better passivation effect. A thicker tunneling layer can better isolate and reduce the interface state density, thereby reducing interface recombination and improving the stability and electrical performance of the device. The thickness of the tunneling layer on the side surface 1011b is relatively thin. The thinner tunneling layer has a relatively high interface state density, which provides a conductive channel for carrier transmission, thereby helping to reduce the contact resistance and allowing carriers to be more effectively transmitted in the device. However, a too thin tunneling layer will sacrifice a certain passivation effect. The ratio of the tunneling layer thickness on the top surface and the side surface is an important factor in balancing the passivation effect and the contact resistance. This ratio is conducive to ensuring that the top surface has sufficient tunneling layer thickness to achieve a good passivation effect, while the tunneling layer thickness on the side surface is not too thick to increase the contact resistance. The tunneling layer on the top surface and the side surface has a suitable thickness ratio, which can be conducive to taking into account both the passivation effect and the contact resistance.

[0039] According to an embodiment of the present application, the thickness of the tunneling layer 102 located on the top surface 1011c and / or the bottom surface 1011a may be greater than or equal to 0.5nm, preferably 0.5~2.5nm, for example, it may be 0.5nm, 1nm, 1.5nm, 2nm, 2.5nm, etc.; and / or, the thickness of the tunneling layer 102 located on the side surface 1011b may be greater than or equal to 0.2nm, preferably 0.2~2nm, for example, it may be 0.2nm, 0.5nm, 1nm, 1.5nm, 2nm, etc.

[0040] By setting a suitable tunneling layer thickness, the passivation effect and the contact resistance can be further improved simultaneously. If the tunneling layer thickness is too thin, it will be difficult to form a tunneling layer that can relatively evenly cover the first surface, which is not conducive to the passivation effect. If the tunneling layer thickness is too thick, the contact resistance will be too high, which is not conducive to carrier transmission.

[0041] More specifically, there are two main mechanisms for carrier transport in the tunneling layer: hole transport and tunneling effect. Hole transport mainly occurs when the tunneling layer is thick (usually greater than 2nm). In this case, there may be defects, pinholes or local weak areas in the tunneling layer, which provide direct channels for carriers, allowing carriers to be transported through these holes. However, the efficiency and reliability of hole transport are often affected by the quality and preparation process of the tunneling layer. On the other hand, the tunneling effect mainly occurs when the tunneling layer is thin (usually less than 2nm). The tunneling effect is a quantum mechanical phenomenon. When the thickness of the tunneling layer is thin enough, the carriers have a certain probability to directly pass through the oxide layer barrier, thereby achieving transmission. The efficiency of the tunneling effect is closely related to factors such as the thickness of the tunneling layer, the energy of the carriers, and the barrier height on both sides of the tunneling layer. As the thickness of the tunneling layer decreases, the tunneling effect becomes more significant, and the carrier transport efficiency will also increase accordingly. Therefore, the tunneling effect is not only conducive to carrier transport, but also can retain the conductive channel and form a good resistivity.

[0042] According to an embodiment of the present application, the tunneling layer 102 may preferably be silicon oxide, but is not limited thereto. Other materials suitable for forming a tunneling layer having a thickness characteristic of being thicker on the top surface and thinner on the side surface may also be applicable.

[0043] According to an embodiment of the present application, Figure 6 FIG. 1 is a schematic side view of a convex structure of the first texture structure of an embodiment of the present application. Figure 6As shown, along the direction S away from the first surface 101a, the first texture structure 1011 includes a side surface 1011b and a top surface 1011c. The projection area of ​​at least one of the top surface 1011c and the bottom surface 1011a in the extension direction of the first surface 101a is larger than the projection area of ​​the side surface 1011b in the extension direction of the first surface 101a. The tunneling layer 102 mainly plays a passivation effect. When the inclination angles of the top surface 1011c and the side surface 1011b remain unchanged, the area ratio of the top surface 1011c, the bottom surface 1011a and the side surface 1011b on the first texture structure 1011 is used to control the area ratio of the tunneling layer 102 of different thicknesses on the top surface 1011c, the bottom surface 1011a and the side surface 1011b, so that the passivation effect of the tunneling layer 102 on the top surface 1011c or the bottom surface 1011a is dominant, ensuring the overall passivation effect, and at the same time, the contact performance of the tunneling layer 102 on the side surface 1011b is good, which is beneficial to improve the contact performance of the overall tunneling layer 102, thereby taking into account the balance between contact resistance and passivation effect.

[0044] According to an embodiment of the present application, the lateral dimension W of the top surface 1011c and / or the bottom surface 1011a is 5-80 μm, preferably 10-30 μm, for example, 5 μm, 8 μm, 10 μm, 15 μm, 20 μm, 25 μm, 30 μm, 40 μm, 60 μm, 80 μm, etc.; and / or, the height L between the top surface 1011c and the bottom surface 1011a is 1-10 μm, preferably 1-2 μm, for example, 1 μm, 3 μm, 5 μm, 8 μm, 10 μm, etc. It can be understood that the "lateral dimension" can be a dimension along the direction of the surface, for example, if the top surface 1011c is rectangular, its lateral dimension can be the length of the side, and if the top surface 1011c is circular, its lateral dimension can be the length of the diameter. The appropriate size of the protruding structure helps to meet the aforementioned area requirements while ensuring that the first texture structure 1011 has a good light trapping effect, and at the same time, allows the doped semiconductor layer 103 to be prepared on the first texture structure 1011 in a relatively conformal manner.

[0045] According to an embodiment of the present application, the first texture structure 1011 is a convex structure or a concave structure, for example, Figure 3 The prism shape shown in the figure is not limited to this, and can also be a truncated cone, a prism, etc. Here, "prism shape" means a shape that is roughly a prism, and the same applies to "truncated cone" and "prism". The prism shape can further be, for example, a pyramid base structure with staggered stacking.

[0046] According to the embodiments of the present application, Figure 1As shown, taking the TOPCon cell as an example, the semiconductor substrate 101 also includes a second surface 101b opposite to the first surface 101a, and the second surface has a plurality of second texture structures 1012, and the second texture structures 1012 can be convex structures or groove structures. The formed second texture structure helps to improve the light trapping effect, increase light absorption, and thus improve the photoelectric conversion efficiency.

[0047] According to an embodiment of the present application, further optionally, the second texture structure 1012 may be cylindrical, conical, pyramidal, etc. Similarly, the "conical" here means a substantially conical shape, and the same is true for "cylindrical" and "pyramidal". The pyramidal shape may further be, for example, a staggered stacked positive pyramid structure or an inverted pyramid structure.

[0048] According to an embodiment of the present application, further optionally, the solar cell further includes an emitter 106 and a second passivation anti-reflection layer 107 .

[0049] The emitter 106 is formed in the second surface 101b of the semiconductor substrate 101, and generally has a high doping concentration to form a good ohmic contact, reduce contact resistance, and improve current injection efficiency. The emitter 106 can be N-type doped or P-type doped, and its doping type can be the same as or different from that of the semiconductor substrate. Further optionally, the N-type doping can be achieved by doping the second surface 101b of the semiconductor substrate 101 with a high concentration of donor elements such as phosphorus (P), arsenic (As) or antimony (Sb), or by introducing acceptor elements such as boron (B), aluminum (Al) or gallium (Ga) into the second surface 101b of the semiconductor substrate 101.

[0050] The second passivation anti-reflection layer 107 is located on the surface of the emitter 106, that is, on the second surface. The second passivation anti-reflection layer 107 helps to achieve a good passivation anti-reflection effect, improve the dark saturation current density and hidden open circuit voltage of the solar cell, and the second passivation anti-reflection layer 107 can be, for example, a laminated film of silicon dioxide, silicon nitride, or a combination of the two.

[0051] According to an embodiment of the present application, further optionally, the back side of the solar cell further includes a first passivation anti-reflection layer 104 and an electrode 105. The first passivation anti-reflection layer 104 is formed on the doped semiconductor layer 103, the electrode 105 is located on the first passivation anti-reflection layer 104 and contacts the doped semiconductor layer 103 through the first passivation anti-reflection layer 104, and is located on the second passivation anti-reflection layer 107 and contacts the emitter 106 through the second passivation anti-reflection layer 107.

[0052] Exemplarily, the first passivation anti-reflection layer 104 and the second passivation anti-reflection layer 107 may respectively include an aluminum oxide layer and a silicon nitride layer sequentially disposed in a direction away from the semiconductor substrate 101. Further optionally, the thickness of the aluminum oxide layer may be 3 to 5 nm, for example, 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, etc., and the thickness of the silicon nitride layer may be 80 to 120 nm, for example, 80 nm, 90 nm, 100 nm, 110 nm, 120 nm, etc.

[0053] According to an embodiment of the present application, further, Figure 7 The method flow chart of the solar cell of the present application embodiment is combined with Figure 1 As shown, the method for preparing a solar cell of the present application may include operations S701 to S703:

[0054] In operation S701, a first surface of an initial substrate is wet-polished to form a plurality of first texture structures on the first surface 101a to obtain a semiconductor substrate 101; wherein, along a direction away from the first surface 101a, the first texture structure includes a bottom surface 1011a, a side surface 1011b and a top surface 1011c, and the side surface 1011b is located between the bottom surface 1011a and the top surface 1011c;

[0055] In operation S702, a tunneling layer 102 is deposited on the first surface 101a of the semiconductor substrate 101 by plasma enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD), so that the thickness of the tunneling layer on the top surface 1011c and / or the bottom surface 1011a is greater than the thickness of the tunneling layer 102 on the side surface 1011b;

[0056] In operation S703 , a doped semiconductor layer 103 is formed on a surface of the tunneling layer 102 away from the semiconductor substrate 101 .

[0057] According to an embodiment of the present application, by selecting a suitable deposition method, compared with other methods such as atomic layer deposition (ALD), it is more conducive to forming a tunneling layer 102 with a specific thickness distribution of the present application on the first surface 101a, thereby utilizing the tunneling layer 102 located on the side surface 1011b to improve the contact performance, and utilizing the tunneling layer 102 located on the top surface 1011c and / or the bottom surface 1011a to improve the passivation effect, thereby taking into account the balance between contact resistance and passivation effect.

[0058] According to an embodiment of the present application, in operation S701 , the wet polishing mainly includes two steps of cleaning and alkali polishing.

[0059] The cleaning step may include: using SC-1 cleaning solution in a wet chemical cleaning method (or RCA standard cleaning method) to clean to remove organic residues and some metals; and then washing with deionized water to neutralize the chemicals remaining after cleaning with the SC-1 cleaning solution.

[0060] The alkali polishing step may include: using KOH alkali solution to remove the surface damage layer caused by cutting, and the surface of the initial substrate after cleaning is polished; then using SC-1 cleaning solution to efficiently clean the initial substrate after alkali polishing; then using SC-2 cleaning solution to remove the metal ions remaining after cleaning with SC-1 cleaning solution; and finally cleaning with 5wt% hydrofluoric acid to complete the polishing of the surface of the initial substrate. The polishing thickness of the initial substrate is 5-10μm, and after polishing, a semiconductor substrate with multiple first texture structures is formed.

[0061] According to an embodiment of the present application, in operation S702, taking the tunneling layer as silicon oxide as an example, the conditions for PECVD deposition of the tunneling layer include: power of 1500-2000 W (for example, 1500 W, 1600 W, 1700 W, 1800 W, 1900 W, 2000 W, etc.), pressure of 200-300 Pa (for example, 200 Pa, 220 Pa, 240 Pa, 260 Pa, 280 Pa, 300 Pa, etc.), silane (i.e., SiH4) flow rate of 40-70 sccm (for example, 40 sccm, 50 sccm, 60 sccm, 70 sccm, etc.), carbon dioxide (CO2) flow rate of 300-500 sccm (for example, 300 sccm, 350 sccm, 400 sccm, 450 sccm, 500 sccm, etc.), and carbon dioxide (CO2) flow rate of 150-2000 sccm (for example, 300 sccm, 350 sccm, 400 sccm, 450 sccm, 500 sccm, etc.). sccm, etc.), hydrogen (H2): 1000~2000 sccm (for example, it can be 1000 sccm, 1200 sccm, 1400 sccm, 1600 sccm, 1800 sccm, 2000 sccm, etc.). Selecting the deposition conditions under the above conditions is more conducive to preparing the tunneling layer with a specific thickness distribution in this application.

[0062] According to an embodiment of the present application, in operation S703, taking the doped semiconductor layer as doped polysilicon as an example, a low pressure chemical vapor deposition (LPCVD) method can be used to form an amorphous silicon layer or a polysilicon layer, and further doping is performed through a diffusion process to form a doped polysilicon layer. Since the doped semiconductor layer can be prepared by a conventional process and is not the key to the present application, it will not be described in detail here.

[0063] Further illustratively, in order to prepare Figure 1For the TOPCon cell shown, the preparation method of the present application may also include: wet texturing the second surface of the initial substrate to form a plurality of second texture structures 1012 on the second surface; then preparing an emitter 106 and a second passivation anti-reflection layer 107 on the second surface 101b having the second texture structure 1012; and preparing a first passivation anti-reflection layer 104 on the doped semiconductor layer 103; and preparing electrodes 105 on the first passivation anti-reflection layer 104 and the second passivation anti-reflection layer 107, respectively.

[0064] The passivation contact structure of the present application can be widely applicable to various types of batteries. For example, the solar cell of the present application can be Figure 1 The TOPCon battery shown may also be a back contact battery, such as a TBC (TopCon-Back Contact) battery, an HPBC (Hybrid Passivated BackContact) battery, or a hybrid BC (Back Contact) battery.

[0065] Figure 8 is a schematic diagram of the structure of a solar cell according to another embodiment of the present application, and Figure 1 The difference between the solar cell structures shown is mainly that the first surface 101a is the backlight surface of the solar cell, the first surface 101a includes N regions and P regions that are alternately distributed at intervals, and the tunnel passivation contact structure formed by the tunnel layer 102 and the doped semiconductor layer 103 is located on one of the N region and the P region or on the N region and the P region respectively. At this time, the first surface 101a has a plurality of first texture structures 1011, which can be distributed on the entire surface of the first surface 101a, or distributed on a part of the first surface 101a, for example, can be located in the N region and / or the P region. The first texture structure 1011 includes a bottom surface 1011a, a side surface 1011b and a top surface 1011c, the side surface 1011b is located between the bottom surface 1011a and the top surface 1011c, and the thickness relationship of the tunnel layer on the side surface 1011b, the top surface 1011c, and the bottom surface 1011a is the same as the above, and will not be repeated here.

[0066] For example, Figure 8As shown, in one embodiment, the tunnel passivation contact structure can be located on the N region and the P region respectively. At this time, the tunneling layer 102 can cover the first surface 101a on the front side, or be set as a patterned layer structure, and the doped semiconductor layer 103 can be set as a patterned layer structure. The corresponding back-contact solar cell is a TBC (TopCon-Back Contact, tunneling oxide passivation contact back contact) cell. And the doping type of the doped semiconductor layer 103 located on the N region and the doped semiconductor layer 103 located on the P region is different, that is, the doped semiconductor layer 103 located on the N region is N-type doped, and the doped semiconductor layer 103 located on the P region is P-type doped. At this time, the first texture structure can be located on the N region and the P region, and the thickness distribution law of the tunneling layer can be respectively provided on the N region and the P region.

[0067] According to an embodiment of the present application, it is more preferred that, in the extension direction of the first surface, the sum of the top and bottom surface projection areas of the first texture structure 1011 located in the P region is smaller than the sum of the top and bottom surface projection areas of the first texture structure 1011 located in the N region.

[0068] With such a configuration, when the semiconductor substrate is an N-type substrate, the electron collection efficiency is higher than the hole collection efficiency, that is, the tunneling efficiency of the N region is higher than that of the P region. Therefore, compared with the N region, the proportion of the top and bottom surfaces of the P region is relatively smaller, and the proportion of the side surfaces is relatively larger, so that more conductive channels are retained, which is beneficial to the improvement of the hole collection efficiency, and thus more conducive to the balance of carrier collection.

[0069] Exemplarily, in another embodiment, the tunneling passivation contact structure located on the N region or the P region can be replaced with other passivation contact structures, for example, the tunneling layer 102 and the doped semiconductor layer 103 located on the P region are replaced as a whole with an aluminum back field, thereby forming an aluminum back field passivation structure on the P region, and the corresponding back contact solar cell can be an HPBC (Hybrid Passivated Back Contact, composite passivation back contact) battery, or, for another example, the tunneling layer 102 and the doped semiconductor layer 103 located on the P region are replaced as a whole with intrinsic amorphous silicon and P-type doped amorphous silicon arranged in sequence along the direction away from the second region, thereby forming a heterojunction passivation contact structure on the P region, and the corresponding back contact solar cell can be a hybrid BC (Back Contact) battery.

[0070] For example, for the sake of convenience, hybrid BC is further taken as an example, Fig. 9 This is a schematic diagram of the structure of a solar cell according to another embodiment of the present application. Fig. 9 As shown, the first texture structure may be located on one of the N region and the P region, and the other one may have the second texture structure 1012. Figure 8The main difference of the solar cell structure shown is that, in the direction away from the first surface, the cell further includes an intrinsic semiconductor layer 108 and another doped semiconductor layer 109 located on the N region or P region with the second texture structure 1012, thereby forming a heterojunction passivation contact structure.

[0071] Furthermore, if Fig. 9 As shown, the solar cell further includes: a patterned transparent conductive layer 110 , which is respectively located on the surface of the doped semiconductor layer 103 away from the semiconductor substrate 101 , and on the surface of another doped semiconductor layer 109 away from the semiconductor substrate 101 .

[0072] According to the embodiments of the present application, Figure 8 and Fig. 9 The method for preparing the back contact solar cell is similar to the method described above. Figure 1 The TOPCon cell shown is similar to the one shown in the figure, and the main difference is that the second passivation anti-reflection layer 102 is directly prepared on the second surface of the semiconductor substrate 102 after texturing; the tunneling layer 102 and the doped semiconductor layer 103 are patterned on the first surface of the semiconductor substrate 101 to retain the tunneling layer 102 and the doped semiconductor layer 103 located on the N region or the P region, and the remaining first surface is exposed; and then a doped semiconductor layer with a conductivity type opposite to that of the doped semiconductor layer 103 is made on the exposed first surface, and insulation between the doped semiconductor layer 103 and the semiconductor layer located on the P region is achieved.

[0073] For the hybrid BC battery, one of the N region and the P region can be polished first to produce a patterned tunneling layer 102 and a doped semiconductor layer 103, and then covered with a mask, and then after the second texture structure is formed by milling the P region, an intrinsic semiconductor layer 108 and another doped semiconductor layer 109 are produced.

[0074] According to another embodiment of the present application, a photovoltaic assembly is provided, comprising a plurality of the above-mentioned solar cells and a packaging structure, wherein the plurality of solar cells are connected into a solar cell string, and the packaging structure is disposed around the periphery of the solar cell string.

[0075] According to the embodiments of the present application, the packaging structure may include, for example, a glass panel, an adhesive film and a back panel, wherein the glass panel is located on the front side (or light-receiving side) of the solar cell string, and the back panel is located on the back side (or backlight side) of the solar cell string, both of which play a protective role; the adhesive film is an adhesive film between the solar cell string and the glass panel and the back panel, which plays a role of bonding and fixing, and a transparent material must be used.

[0076] In the embodiments of the present application, the solar cells and photovoltaic modules of the present application, when using the selective passivation contact structure provided by the present application, help to improve the passivation contact effect and the electrical transmission effect, thereby improving the photoelectric conversion efficiency of the solar cells and photovoltaic modules.

[0077] The specific embodiments described above further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the scope of protection of the present application.

Claims

1. A solar cell comprising: A semiconductor substrate, comprising a first surface having a plurality of first texture structures, wherein the first texture structures comprise a bottom surface, a side surface and a top surface in a direction away from the first surface, wherein the side surface is located between the bottom surface and the top surface; a tunneling layer located on the first surface of the semiconductor substrate, wherein the thickness of the tunneling layer located on the top surface and / or the bottom surface is greater than the thickness of the tunneling layer located on the side surface; as well as The doped semiconductor layer is located on the surface of the tunneling layer away from the semiconductor substrate.

2. The solar cell according to claim 1, wherein: A ratio between a thickness of the tunneling layer on the top surface and / or the bottom surface and a thickness of the tunneling layer on the side surface is greater than 1 and less than or equal to 4.

3. The solar cell according to claim 1 or 2, wherein: The thickness of the tunneling layer located on the top surface and / or the bottom surface is greater than or equal to 0.5 nm, preferably 0.5 to 2.5 nm; and / or The thickness of the tunneling layer located on the side surface is greater than or equal to 0.2 nm, preferably 0.2-2 nm.

4. The solar cell according to claim 1, wherein: A projected area of ​​at least one of the top surface and the bottom surface in a direction in which the first surface extends is larger than a projected area of ​​the side surface in the direction in which the first surface extends.

5. The solar cell according to claim 1 or 4, wherein: The projection area of ​​the top surface in the extending direction of the first surface is larger than the projection area of ​​the bottom surface in the extending direction of the first surface; Or a projection area of ​​the top surface in the extending direction of the first surface is smaller than a projection area of ​​the bottom surface in the extending direction of the first surface.

6. The solar cell according to claim 1, wherein: The lateral dimension of the top surface and / or the bottom surface is 5 to 80 μm, preferably 10 to 30 μm; and / or A height from the top surface to the bottom surface is 1-10 μm, preferably 1-2 μm.

7. The solar cell according to claim 1 or 2, wherein: The top surface and / or the bottom surface is / are substantially in a plane parallel to an extending direction of the first surface.

8. The solar cell according to claim 1, wherein: Along a direction away from the first surface, a side surface of at least one of the first texture structures includes at least two sub-side surfaces that are non-continuously arranged, and the first texture structure also includes a transition surface located between two adjacent sub-side surfaces; The thickness of the tunneling layer located on the transition surface is greater than the thickness of the tunneling layer located on the sub-side surfaces at both sides of the transition surface.

9. The solar cell according to claim 1, wherein: The first texture structure is in the shape of a prism, a truncated cone or a prism.

10. The solar cell according to claim 1, wherein: The thickness of the doped semiconductor layer is 50-300 nm, preferably 80-180 nm.

11. The solar cell according to claim 1, wherein: The semiconductor substrate is an N-type substrate, and the first surface includes N regions and P regions that are alternately arranged. In the extension direction of the first surface, the sum of the top surface and bottom surface projection areas of the first texture structure located in the P region is smaller than the sum of the top surface and bottom surface projection areas of the first texture structure located in the N region.

12. A photovoltaic module, comprising: A plurality of solar cells according to any one of claims 1 to 11, connected into a solar cell string; as well as The packaging structure is arranged around the outer periphery of the solar cell string.

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