Silicon wafer textured structure, battery and preparation method

Abstract

The invention relates to a silicon wafer textured structure, a battery and a preparation method. The silicon wafer suede structure comprises a light receiving suede and a shading suede which are formed on a substrate. Wherein the specific surface area of the light receiving suede is larger than that of the shading suede; the specific surface area is the ratio of the surface area of the suede structure to the bottom area of the suede structure. By adopting the structure, the effects of short-circuit current and filling factors can be simultaneously improved, and the photoelectric conversion efficiency of the cell is further improved.

Description

Technical Field

[0001] The present application relates to the field of battery technology, and in particular to a silicon wafer velvet structure, a battery and a preparation method. Background Art

[0002] In the battery field, texturing is the first step in the battery production process. The velvet structure formed by texturing will directly affect the electrical performance of the battery.

[0003] In the related art, when making a velvet structure, the size and morphology of the velvet are usually improved to increase the light-receiving area of ​​the battery and improve the short-circuit current of the battery. However, when the light-receiving area is larger, the contact area between the velvet structure and the slurry will be smaller, resulting in a lower fill factor of the battery, and the problem of low photoelectric conversion efficiency of the battery still exists. Summary of the invention

[0004] Based on this, it is necessary to provide a silicon wafer velvet structure, a battery and a preparation method that can improve the photoelectric conversion efficiency of the battery in response to the above technical problems.

[0005] In a first aspect, the present application provides a silicon wafer velvet structure, the silicon wafer velvet structure comprising: a light-receiving velvet surface and a light-shielding velvet surface formed on a substrate;

[0006] The specific surface area of ​​the light-receiving velvet surface is greater than the specific surface area of ​​the light-shielding velvet surface; the specific surface area is the ratio of the surface area of ​​the velvet structure to the bottom area of ​​the velvet structure.

[0007] In one of the embodiments, metal grid lines are printed on the surface of the light-shielding velvet surface, and the width of the light-shielding velvet surface is greater than the width of the metal grid lines.

[0008] In one of the embodiments, the light-receiving velvet surface and the light-shielding velvet surface are alternately arranged on the substrate.

[0009] In one embodiment, the width of the light-shielding velvet surface is 20-200 microns.

[0010] In one embodiment, the width of the light-receiving velvet surface is 800-1500 microns.

[0011] In one embodiment, both the light-receiving velvet surface and the light-shielding velvet surface include pyramid velvet surfaces.

[0012] In a second aspect, the present application further provides a battery, comprising the silicon wafer velvet structure in any one of the embodiments in the first aspect.

[0013] In a third aspect, the present application also provides a method for preparing a silicon wafer texture structure, the method comprising:

[0014] providing a substrate;

[0015] Performing texturing twice on the substrate to form a light-receiving velvet surface and a light-shielding velvet surface on the substrate;

[0016] Among them, the specific surface area of ​​the light-receiving velvet surface is greater than the specific surface area of ​​the light-shielding velvet surface; the specific surface area is the ratio of the surface area of ​​the velvet structure to the bottom area of ​​the velvet structure.

[0017] In one embodiment, the substrate is textured twice to form a light-receiving velvet surface and a light-shielding velvet surface on the substrate, including:

[0018] performing patterning on the substrate to form a mask on the substrate;

[0019] The substrate is textured once to form an initial light-receiving texture surface in a non-mask area on the substrate;

[0020] The mask on the substrate is removed to form an exposed area, and the substrate is subjected to secondary texturing to form a light-receiving velvet surface in the non-mask area and a light-shielding velvet surface in the exposed area.

[0021] In one of the embodiments, the texturing conditions of the first texturing are different from those of the second texturing; wherein the texturing conditions include at least one of DI ratio, ADD ratio, alkali ratio, texturing temperature and texturing time.

[0022] In one embodiment, the method further comprises:

[0023] The substrate is pre-treated to clean impurities on the surface of the substrate.

[0024] The silicon wafer velvet structure, battery and preparation method, the silicon wafer velvet structure includes: a light-receiving velvet and a light-shielding velvet formed on a substrate. Among them, the specific surface area of ​​the light-receiving velvet is greater than the specific surface area of ​​the light-shielding velvet; the specific surface area is the ratio of the surface area of ​​the velvet structure to the bottom area of ​​the velvet structure. In this structure, by forming a light-receiving velvet and a light-shielding velvet on the substrate respectively, and limiting the specific surface area of ​​the light-receiving velvet to be greater than the specific surface area of ​​the light-shielding velvet, a light-receiving velvet with a larger specific surface area is used to increase the short-circuit current, and a light-shielding velvet with a smaller specific surface area is used to increase the filling factor, so as to achieve the effect of simultaneously increasing the short-circuit current and the filling factor, thereby improving the photoelectric conversion efficiency of the battery. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0026] FIG1 is a schematic structural diagram of a silicon wafer texture structure in one embodiment;

[0027] FIG2 is a schematic diagram of a process for preparing a silicon wafer texture structure in one embodiment;

[0028] FIG3 is a schematic flow diagram of two texturing steps in one embodiment;

[0029] FIG. 4 is a schematic flow chart of a method for preparing a silicon wafer texture structure in another embodiment.

[0030] Description of reference numerals:

[0031] 1: Metal electrode;

[0032] 2: Light-receiving velvet surface;

[0033] 3: Light-blocking suede;

[0034] 4: Substrate. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of the present application; the terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present application; the terms "including" and any variations thereof in the specification and claims of the present application and the above-mentioned figure descriptions are intended to cover non-exclusive inclusions. In the description of the embodiments of the present application, the technical terms "first", "second", "third", "fourth", etc. are only used to distinguish different objects, and cannot be understood as indicating or implying relative importance or implicitly indicating the number, specific order or primary and secondary relationship of the indicated technical features. In the description of the embodiments of the present application, the meaning of "multiple" is more than two, unless otherwise clearly and specifically defined.

[0037] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0038] In the description of the embodiments of the present application, unless otherwise clearly specified and limited, technical terms such as "connection" should be understood in a broad sense, for example, it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present application can be understood according to specific circumstances.

[0039] With the development of science and technology, the performance requirements for batteries are getting higher and higher, such as requiring the short-circuit current of the battery to be as high as possible, the fill factor to be as high as possible, the conversion efficiency to be as high as possible, the service life to be as long as possible, etc.

[0040] In the battery field, texturing is the first step in the battery production process. After pre-cleaning, texturing, alkaline washing, acid washing, drying and other steps, a pyramid-structured velvet surface is obtained. The velvet structure formed by texturing will directly affect the electrical performance of the battery.

[0041] Take monocrystalline silicon solar cells as an example: the texture on the surface of the monocrystalline silicon wafer after texturing has the effect of trapping light. The texture can reduce the reflectivity of the silicon wafer surface from 35% to about 10%, thereby improving the short-circuit current and conversion efficiency of the monocrystalline silicon solar cell.

[0042] However, in the process of manufacturing solar cells, the current velvet making process and the formed structure have defects, making it increasingly difficult to increase the short-circuit current of solar cells. Existing technologies have all been painstakingly researching to obtain a suitable velvet structure, such as the size of the velvet, but still cannot effectively improve the conversion efficiency of the battery.

[0043] After a lot of theoretical and experimental comparisons, the inventors found that the morphology of the silicon wafer velvet structure is an important factor affecting the performance of the battery. Specifically, the smaller the specific surface area of ​​the silicon wafer velvet structure (i.e., a larger tower base and a smaller tower height), the smaller the light-receiving area of ​​the battery; on the contrary, if the specific surface area of ​​the silicon wafer surface velvet is larger (i.e., a smaller tower base and a larger tower height), the light-receiving area of ​​the battery is relatively larger.

[0044] Furthermore, the inventors also found that: when the light-receiving area is larger, although the short-circuit current of the battery is higher, due to the higher specific surface area of ​​the silicon wafer velvet structure, the contact area between the silicon wafer velvet structure and the slurry is smaller, which will lead to poor ohmic contact, which is extremely unfavorable for improving the fill factor.

[0045] In summary, the following conclusions can be drawn: if the surface area of ​​the silicon wafer velvet structure is large, the short-circuit current will increase, but the fill factor will decrease; and if the surface area of ​​the silicon wafer velvet structure is small, the short-circuit current will decrease, but the fill factor will increase. In other words, it is difficult to increase the short-circuit current and the fill factor at the same time in the current velvet solution, which limits the conversion performance of the battery.

[0046] Taking into account the problem that the short-circuit current and the filling factor cannot be improved at the same time, the present application proposes a silicon wafer velvet structure, a battery and a preparation method, by respectively forming a light-receiving velvet and a light-shielding velvet on a substrate, and limiting the specific surface area of ​​the light-receiving velvet to be larger than the specific surface area of ​​the light-shielding velvet. The light-receiving velvet with a larger specific surface area is used to increase the short-circuit current, and the light-shielding velvet with a smaller specific surface area is used to increase the filling factor, thereby achieving the effect of simultaneously and evenly improving the short-circuit current and the filling factor, thereby improving the photoelectric conversion efficiency of the battery.

[0047] It should be noted that the silicon wafer texture structure in the embodiment of the present application can be in a local area of ​​the substrate or in the surface area of ​​the substrate, and the embodiment of the present application is not limited to this.

[0048] It should be pointed out that the silicon wafer velvet structure in the embodiment of the present application can be applicable to different types of solar cells, including but not limited to crystalline silicon solar cells, polycrystalline silicon solar cells, concentrated single crystal silicon, silicon-based heterojunction (HIT) cells, thin-film crystalline silicon and thin-film amorphous silicon cells, selective emitter cells, passivated emitter and back contact cells.

[0049] The silicon wafer texture structure provided by the present application is described below through specific embodiments.

[0050] In an exemplary embodiment, please refer to Figure 1, which is a schematic diagram of a silicon wafer velvet structure provided in the present application, and the silicon wafer velvet structure includes: a light-receiving velvet surface and a light-shielding velvet surface formed on a substrate; wherein the specific surface area of ​​the light-receiving velvet surface is greater than the specific surface area of ​​the light-shielding velvet surface; the specific surface area is the ratio of the surface area of ​​the velvet structure to the bottom area of ​​the velvet structure.

[0051] In the embodiment of the present application, the substrate, as the carrier of the battery cell, is usually composed of a silicon-based material, having high thermal conductivity and good electrical properties. Depending on the substrate material, the battery can be divided into a P-type battery and an N-type battery. Among them, the substrate of the P-type battery includes silicon elements and dopants, forming electron-hole pairs, and acts as an absorption layer for sunlight; the substrate of the N-type battery includes silicon elements and dopants, forming electron-hole pairs, and generating a potential difference under the action of the PN junction.

[0052] In the production process of batteries, no matter what kind of substrate is used, it is necessary to firstly perform texturing on the surface of the substrate to form a velvet surface on the surface of the substrate in order to reduce the reflectivity of the surface and realize the improvement of the short-circuit current of the battery.

[0053] In the embodiment of the present application, a light-exposed area (unprinted area) and a grid line covered area (metallized printed area) are defined on the substrate surface, and different types of velvet are formed in different areas. In addition, a light-exposed velvet is formed in the light-exposed area, and a light-shielding velvet is formed in the grid line covered area.

[0054] Furthermore, in the silicon wafer velvet structure provided in the embodiment of the present application, the specific surface areas of the light-receiving velvet surface and the light-shielding velvet surface are different, and the specific surface area of ​​the light-receiving velvet surface is greater than the specific surface area of ​​the light-shielding velvet surface. Here, the specific surface area is obtained by calculating the ratio of the surface area to the bottom area based on the surface area of ​​the velvet structure and the bottom area of ​​the velvet structure, wherein the bottom area refers to the bottom contact area of ​​the velvet structure on the substrate.

[0055] Then, the specific surface area of ​​the light-receiving velvet surface is greater than the specific surface area of ​​the light-shielding velvet surface, which can be achieved in the following ways: when the height of the light-receiving velvet surface is the same as the height of the light-shielding velvet surface, the contact area of ​​the light-receiving velvet surface on the substrate is smaller than the contact area of ​​the light-shielding velvet surface on the substrate; or when the contact area of ​​the light-receiving velvet surface on the substrate is the same as the contact area of ​​the light-shielding velvet surface on the substrate, the height of the light-receiving velvet surface is higher than the height of the light-shielding velvet surface; or the height of the light-receiving velvet surface is higher than the height of the light-shielding velvet surface, and the contact area of ​​the light-receiving velvet surface on the substrate is smaller than the contact area of ​​the light-shielding velvet surface on the substrate.

[0056] Exemplarily, the width of the light-shielding suede surface is 20-200 microns.

[0057] Exemplarily, the width of the light-receiving suede is 800-1500 microns.

[0058] Next, the specific surface areas of the light-receiving pile surface and the light-shielding pile surface are described in combination with the types of the light-receiving pile surface and the light-shielding pile surface.

[0059] In an exemplary embodiment, the light-receiving velvet surface and the light-shielding velvet surface both include pyramid velvet surfaces.

[0060] Please continue to refer to Figure 1. It can be seen that compared with the tower height and tower base of the light-shielding velvet surface, the tower height of the light-receiving velvet surface is higher and the tower base is smaller. In this way, the light-receiving velvet surface formed by the light-exposed area on the substrate surface can use sunlight to generate photogenerated carriers as much as possible to increase the short-circuit current; for the light-shielding velvet surface formed by the gate line covering area on the substrate surface, since its tower base is larger, the contact area with the gate line is larger, which can achieve better ohmic contact and improve the fill factor.

[0061] It should be noted that the pyramid velvet is a design method for a cell that is a type of monocrystalline silicon solar cell. In practical applications, the light-receiving velvet and the light-shielding velvet can also be other types, such as triangular velvet, pyramid velvet, etc., and the types of the light-receiving velvet and the light-shielding velvet can be the same or different, for example, both the light-receiving velvet and the light-shielding velvet are pyramid velvet, the light-receiving velvet is pyramid velvet, and the light-shielding velvet is pyramid velvet, etc.

[0062] The velvet structure provided in the embodiment of the present application includes: a light-receiving velvet and a light-shielding velvet formed on a substrate; wherein the specific surface area of ​​the light-receiving velvet is greater than the specific surface area of ​​the light-shielding velvet; and the specific surface area is the ratio of the surface area of ​​the velvet structure to the bottom area of ​​the velvet structure. In this structure, by forming the light-receiving velvet and the light-shielding velvet on the substrate respectively, and limiting the specific surface area of ​​the light-receiving velvet to be greater than the specific surface area of ​​the light-shielding velvet, the light-receiving velvet with a larger specific surface area is used to increase the short-circuit current, and the light-shielding velvet with a smaller specific surface area is used to increase the filling factor, thereby achieving the effect of simultaneously increasing the short-circuit current and the filling factor, thereby improving the photoelectric conversion efficiency of the battery.

[0063] From the above embodiments, it can be seen that the light-shielding velvet is formed in the gate line covering area of ​​the substrate, that is, the light-shielding velvet is covered by the metal electrode. Based on this, the formation relationship between the light-shielding velvet and the gate line covering area is further described below through an embodiment.

[0064] In an exemplary embodiment, metal grid lines are printed on the surface of the light-shielding velvet surface, and the width of the light-shielding velvet surface is greater than the width of the metal grid lines.

[0065] In the embodiment of the present application, the surface of the light-shielding velvet is printed with metal grid lines to improve the conductivity and heat dissipation performance of the battery. In addition, the metal grid lines can be made of small-particle high-temperature slurry, such as TOPCon, BC, PERC, etc., to achieve better ohmic contact between the metal electrode in the metal grid lines and the light-shielding velvet.

[0066] In order to further increase the short-circuit current of the battery, the width of the shading velvet on the substrate is slightly wider than the width of the metal grid line, so that more sunlight can act on the substrate surface and generate more photogenerated carriers.

[0067] In an embodiment of the present application, for the light-shielding velvet formed on the substrate, metal grid lines are deployed on the surface of the light-shielding velvet to improve the conductivity of the battery, and the width of the light-shielding velvet is greater than the metal grid lines of the light-shielding velvet to fully and effectively utilize photogenerated carriers and improve the photoelectric conversion efficiency.

[0068] In an exemplary embodiment, the light-receiving velvet surface and the light-shielding velvet surface are alternately arranged on the substrate.

[0069] It can also be seen from the embodiment shown in Figure 1 above that the silicon wafer velvet structure has multiple light-receiving velvet surfaces and multiple light-shielding velvet surfaces. Based on this, in the embodiment of the present application, an alternating arrangement is adopted to determine the light-exposed area of ​​the substrate and the gate line covering area. Correspondingly, the light-receiving velvet surfaces and the light-shielding velvet surfaces are also alternately distributed.

[0070] In actual scenarios, in two adjacent types of velvet structures, the number of light-receiving velvet surfaces and the number of light-shielding velvet surfaces can be the same or different. Usually, the number of light-receiving velvet surfaces is greater than the number of light-shielding velvet surfaces, which can make the total light-receiving area of ​​the battery larger, better utilize photogenerated carriers, and improve the light-trapping effect of the light-receiving velvet surface.

[0071] In the silicon wafer velvet structure provided in the embodiment of the present application, the light-receiving velvet and the light-shielding velvet are alternately arranged on the substrate, so that the light-receiving area and the light-shielding area on the silicon wafer velvet structure are evenly distributed, and the specific surface area of ​​the light-receiving velvet and the specific surface area of ​​the light-shielding velvet can be more accurately controlled. Moreover, such a preparation process is more in line with the process of battery velvet manufacturing process in the conventional field, which improves the applicability of the scene of manufacturing the silicon wafer velvet structure of the present application to a certain extent.

[0072] The above is an explanation of the embodiments related to the silicon wafer texture structure. Based on this, the present application also provides an embodiment of a battery product including the silicon wafer texture structure.

[0073] The following are related embodiments of the battery. Since the battery in the following embodiments includes the silicon wafer velvet structure in the aforementioned embodiments, naturally, the technical effects that can be achieved by the battery also include the technical effects of the aforementioned silicon wafer velvet structure. Therefore, for the sake of brevity and clarity, the following embodiments will not be described one by one, and the implementation process and implementation effects of each embodiment can refer to the description of the aforementioned embodiments.

[0074] In an exemplary embodiment, a battery is provided. The battery includes the silicon wafer textured structure in any of the aforementioned embodiments.

[0075] The battery substrate is provided with light-receiving velvet surfaces and light-shielding velvet surfaces arranged alternately, and the specific surface area of ​​the light-receiving velvet surfaces is larger than that of the light-shielding velvet surfaces, and the width of the light-shielding velvet surfaces is slightly wider than that of the metal grid lines.

[0076] Taking the cell as a monocrystalline silicon solar cell as an example, the light-receiving velvet surface and the light-shielding velvet surface on the cell are both pyramid velvet surfaces, and the tower height of the light-receiving velvet surface is higher than the tower height of the light-shielding velvet surface, and the tower base of the light-receiving velvet surface is smaller than the tower base of the light-shielding velvet surface. In addition, the width of the light-shielding velvet surface can be 20-200 microns, and the width of the light-shielding velvet surface is slightly wider than the width of the metal grid line, for example, the width of the metal grid line is 10-35 microns.

[0077] The surface of the battery substrate in the embodiment of the present application is deployed with a light-receiving velvet with a larger specific surface area and a light-shielding velvet with a smaller specific surface area, so as to increase the short-circuit current through the light-receiving velvet with a larger specific surface area, and increase the filling factor through the light-shielding velvet with a smaller specific surface area, thereby achieving the effect of simultaneously and evenly increasing the short-circuit current and the filling factor, thereby improving the photoelectric conversion efficiency of the battery.

[0078] The above is a description of the silicon wafer texture structure and battery related embodiments. Based on this, the present application also provides an embodiment of a method for preparing the silicon wafer texture structure.

[0079] Next, the relevant embodiments of the method for preparing the silicon wafer texture structure are described.

[0080] Please refer to FIG. 2 , which is a schematic flow chart of a method for preparing a silicon wafer texture structure provided in the present application. As shown in FIG. 2 , the method comprises:

[0081] S201, providing a substrate.

[0082] Different types of substrates are selected according to different battery types, such as N-type monocrystalline silicon, P-type monocrystalline silicon, etc. Considering that the substrate may be uneven or contain foreign matter, affecting the quality of subsequent texturing, the substrate surface can also be processed to provide a flatter and smoother silicon wafer surface for subsequent texturing.

[0083] Exemplarily, the substrate is pre-treated to clean impurities on the surface of the substrate.

[0084] In order to ensure the flatness of the substrate, the substrate surface is processed to remove organic matter and metal impurities attached to the substrate surface, and the substrate surface is polished using physical methods or chemical reagents.

[0085] In the embodiment of the present application, impurities on the surface of the substrate are cleaned to provide a smooth and flat surface for subsequent texturing, thereby ensuring the effectiveness of the texturing process, facilitating precise control of the size and morphology of the silicon wafer texture structure, and thereby improving the quality of the battery including the silicon wafer texture structure.

[0086] S202, performing texturing twice on the substrate to form a light-receiving velvet surface and a light-shielding velvet surface on the substrate.

[0087] Among them, the specific surface area of ​​the light-receiving velvet surface is greater than the specific surface area of ​​the light-shielding velvet surface; the specific surface area is the ratio of the surface area of ​​the velvet structure to the bottom area of ​​the velvet structure.

[0088] The provided substrate is textured twice in different time periods, so that the substrate finally presents a light-receiving velvet surface with a larger specific surface area and a light-shielding velvet surface with a smaller specific surface area.

[0089] Optionally, a first hollow mask is used to cover the surface of the substrate to expose the light receiving area of ​​the substrate, and then the light receiving area is textured once to obtain a light receiving velvet surface; then, the first hollow mask is removed, and a second hollow mask is used to cover the surface of the substrate including the light receiving velvet surface, so that the non-light receiving area is exposed while the light receiving area is covered, and the non-light receiving area is textured a second time to obtain a light-shielding velvet surface; finally, the second hollow mask is removed to obtain a light receiving velvet surface and a light-shielding velvet surface formed on the substrate.

[0090] In addition, in order to meet the condition that the specific surface area of ​​the light-receiving velvet surface is larger than the specific surface area of ​​the light-shielding velvet surface, it can be first determined that the morphologies of the light-receiving velvet surface and the light-shielding velvet surface are both pyramid structures, and then the primary texturing conditions and the secondary texturing conditions are determined in such a way that the tower base of the light-receiving velvet surface is smaller than the tower base of the light-shielding velvet surface, and the tower height of the light-receiving velvet surface is higher than the tower height of the light-shielding velvet surface, so as to form a silicon wafer velvet structure that meets the above conditions on the substrate surface.

[0091] In the embodiment of the present application, the substrate is textured twice to form a light-receiving velvet surface and a light-shielding velvet surface on the substrate. The specific surface area of ​​the light-receiving velvet surface is greater than the specific surface area of ​​the light-shielding velvet surface; the specific surface area is the ratio of the surface area of ​​the velvet structure to the bottom area of ​​the velvet structure. In this method, through two texture processes, a light-receiving velvet surface and a light-shielding velvet surface are formed on the substrate respectively, and a light-receiving velvet surface with a larger specific surface area is used to increase the short-circuit current, and a light-shielding velvet surface with a smaller specific surface area is used to increase the filling factor, so as to achieve the effect of simultaneously increasing the short-circuit current and the filling factor, thereby improving the photoelectric conversion efficiency of the battery.

[0092] As can be seen from the above embodiments, in the process of preparing the light-receiving velvet surface and the light-shielding velvet surface, two texturing processes are required. The following is an embodiment to explain the specific implementation of two texturing processes to form the light-receiving velvet surface and the light-shielding velvet surface.

[0093] In an exemplary embodiment, as shown in FIG3 , texturing is performed twice on the substrate to form a light-receiving velvet surface and a light-shielding velvet surface on the substrate, including:

[0094] S301, performing patterning on the substrate to form a mask on the substrate.

[0095] At a preset scanning speed, a laser with a preset wavelength and laser power is used to pattern the silicon wafer on the surface of the substrate.

[0096] For example, a silicon wafer on the surface of a substrate can be patterned at a scanning speed of 400 mm / s using an ultraviolet laser with a laser power of 3 W and a wavelength of 355 nm, forming a mask at the laser location, that is, the area on the substrate where a light-shielding velvet surface is subsequently formed.

[0097] S302, performing a texturing process on the substrate to form an initial light-receiving texturing surface in a non-mask area on the substrate.

[0098] When a mask is formed on a substrate, texturing the substrate once is equivalent to texturing the non-mask area on the substrate to form an initial light-receiving texture surface in the non-mask area. At this time, the mask area cannot form a texture surface.

[0099] It should be noted that the initial light-receiving velvet surface is not the final light-receiving velvet surface of the substrate in this solution, and the quantitative relationship between the two is that the size of the initial light-receiving velvet surface is smaller than the size of the final light-receiving velvet surface. In other words, the initial light-receiving velvet surface needs to continue to grow during the subsequent secondary velveting to form a light-receiving velvet surface.

[0100] S303, removing the mask on the substrate to form an exposed area, and performing secondary texturing on the substrate to form a light-receiving velvet surface in the non-mask area and a light-shielding velvet surface in the exposed area.

[0101] After the first texturing is completed, there is an unformed initial light-receiving velvet surface on the substrate, and no light-shielding velvet surface is formed. Then, the purpose of the second texturing is to make the initial light-receiving velvet surface continue to grow to form the final light-receiving velvet surface and form a light-shielding velvet surface.

[0102] Based on this, the mask on the substrate is first removed to obtain the bare area where the light-shielding velvet surface is to be formed subsequently, that is, the area corresponding to the mask formed in the above steps, and then, on the basis of keeping the silicon wafer dry, the substrate after the mask is removed is subjected to secondary velvet processing, so that the initial light-receiving velvet surface on the non-mask area continues to grow to form a light-receiving velvet surface, and the exposed area begins to generate velvet to obtain a light-shielding velvet surface.

[0103] In an embodiment of the present application, a substrate is patterned to form a mask on the substrate, and then the substrate including the mask is textured once, and then the mask is removed, and the substrate after the mask is removed is textured for a second time. This is equivalent to making a mask and using the mask area as the area for subsequently forming a light-shielding velvet surface, and using the non-mask area as the area for subsequently forming a light-receiving mask. In this way, the process of preparing the light-receiving velvet surface and the light-shielding velvet surface can accurately control the area to which the light-shielding velvet surface belongs and the area to which the light-receiving velvet surface belongs by controlling the mask area, thereby improving the quality of the velvet structure. At the same time, the secondary texture process provided in the embodiment of the present application has clear logic and is suitable for deployment in various velvet equipment processes, thereby improving the scenario applicability of the preparation solution.

[0104] Next, the texturing conditions of the two texturing processes in the aforementioned embodiment are described.

[0105] In an exemplary embodiment, the texturing conditions of the first texturing are different from those of the second texturing; wherein the texturing conditions include at least one of DI ratio, ADD ratio, alkali ratio, texturing temperature and texturing time.

[0106] In the texturing process, the texturing agent includes three components: DI (Deionized water), ADD (texturing additive) and alkali. The DI ratio refers to the volume ratio of deionized water in the texturing agent, ADD refers to the volume ratio of texturing additive in the texturing agent, and the alkali ratio refers to the volume ratio of alkali in the texturing agent.

[0107] In the embodiment of the present application, the primary texturing is used to form an initial light-receiving velvet surface, and the secondary texturing is used to form a light-shielding velvet surface and control the initial light-receiving velvet surface to grow into a light-receiving velvet surface. When the purposes of different texturing processes are different, the corresponding texturing conditions are also different.

[0108] Optionally, the primary texturing conditions are: DI accounts for 97.5%, ADD accounts for 0.5%, alkali accounts for 2%, texturing temperature is 80°C, and texturing time is 350S; the secondary texturing conditions are: DI accounts for 98%, ADD accounts for 0.5%, alkali accounts for 1.5%, texturing temperature is 80°C, and texturing time is 150S.

[0109] In the embodiment of the present application, different texturing conditions are used in the two texturing processes to accurately control the formation process of the light-shielding velvet surface and the light-receiving velvet surface, thereby ensuring the quality of the light-shielding velvet surface and the light-receiving velvet surface finally formed, and thereby improving the electrical performance of the battery including the velvet surface.

[0110] In a specific embodiment, a method for preparing a silicon wafer texture structure is provided, as shown in FIG4 , comprising:

[0111] S401, pre-processing the silicon wafer.

[0112] Silicon wafer refers to the silicon wafer on the surface of the battery substrate.

[0113] S402, patterning the silicon wafer to form a silicon oxide mask at the laser.

[0114] The silicon wafer was patterned at a scanning speed of 400 mm / s using an ultraviolet laser with a laser power of 3 W and a wavelength of 355 nm, forming a silicon oxide mask at the laser location, which is the area on the substrate where the light-shielding velvet surface will be formed later.

[0115] S403, a primary texturing process is performed to form an initial light-receiving texturing surface.

[0116] A texturing process is performed under the following conditions: DI accounts for 97.5%, ADD accounts for 0.5%, alkali accounts for 2%, the texturing temperature is 80°C, and the texturing time is 350S, so as to form an initial light-receiving texturing surface in the unmasked area.

[0117] S404, secondary texturing, the initial light-receiving texturing surface continues to grow, and the texturing surface in the area corresponding to the mask begins to grow.

[0118] The secondary texturing conditions of DI accounting for 98%, ADD accounting for 0.5%, alkali accounting for 1.5%, temperature 80℃, and texturing time 150S are adopted for secondary texturing. The initial light-receiving suede surface at the unmasked position continues to grow, and the suede surface at the masked position begins to grow to form a fine suede surface.

[0119] S405, obtaining a target velvet structure.

[0120] The target velvet surface structure includes a light-receiving velvet surface formed in a non-mask corresponding area and a light-shielding velvet surface formed in a mask corresponding area.

[0121] In an embodiment of the present application, a patterning process is provided for a substrate, a mask is formed on the substrate, and then a non-mask area is used as an area for subsequently forming a light-receiving mask, and the substrate including the mask is subjected to a first texturing. Then, the mask is removed, and the mask area is used as an area for subsequently forming a light-shielding velvet surface, and a second texturing is performed on the substrate after the mask is removed. In this way, the process of preparing the light-receiving velvet surface and the light-shielding velvet surface can accurately control the area to which the light-shielding velvet surface and the area to which the light-receiving velvet surface belongs by controlling the mask area, thereby improving the quality of the velvet structure. At the same time, the secondary texturing process provided in the embodiment of the present application has clear logic, is suitable for deployment in various velvet equipment processes, and improves the scenario applicability of the preparation solution.

[0122] In order to further illustrate the difference between the preparation method provided in the embodiment of the present application and the traditional one-time texturing method, the embodiment of the present application uses a single variable method to compare the battery obtained by the two-time texturing method (the present application) with the battery obtained by the one-time texturing method (the conventional method) in multiple dimensions. Please refer to Table 1, which is a parameter comparison table between the battery obtained by the two-time texturing method and the battery obtained by the one-time texturing method.

[0123] Table 1

[0124]

[0125] In the above table, Uoc represents the open circuit voltage of the battery, Jsc represents the short circuit current of the battery, FF represents the fill factor of the battery, and Eta represents the efficiency of the battery. It can be seen from the above table that compared with conventional batteries, the battery prepared by the preparation method provided in the embodiment of the present application has a higher short circuit current and a higher fill factor, which improves the efficiency of the battery to a certain extent.

[0126] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0127] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0128] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0129] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A silicon wafer velvet structure, characterized in that: The silicon wafer velvet structure comprises: a light-receiving velvet surface and a light-shielding velvet surface formed on a substrate; The specific surface area of ​​the light-receiving velvet surface is greater than the specific surface area of ​​the light-shielding velvet surface; the specific surface area is the ratio of the surface area of ​​the velvet structure to the bottom area of ​​the velvet structure.

2. The silicon wafer texture structure according to claim 1, characterized in that: The surface of the light-shielding velvet surface is printed with metal grid lines, and the width of the light-shielding velvet surface is greater than the width of the metal grid lines.

3. The silicon wafer texture structure according to claim 1, characterized in that: The light-receiving velvet surface and the light-shielding velvet surface are alternately arranged on the substrate.

4. The silicon wafer texture structure according to claim 1, characterized in that: The width of the light-shielding suede surface is 20-200 microns.

5. The silicon wafer texture structure according to claim 1, characterized in that: The width of the light-receiving velvet surface is 800-1500 microns.

6. The silicon wafer texture structure according to claim 1, characterized in that: The light-receiving velvet surface and the light-shielding velvet surface both include pyramid velvet surfaces.

7. A battery, characterized in that: The battery comprises the silicon wafer textured structure according to any one of claims 1 to 6.

8. A method for preparing a silicon wafer texture structure, characterized in that: The method comprises: providing a substrate; Performing texturing twice on the substrate to form a light-receiving velvet surface and a light-shielding velvet surface on the substrate; Among them, the specific surface area of ​​the light-receiving velvet surface is greater than the specific surface area of ​​the light-shielding velvet surface; the specific surface area is the ratio of the surface area of ​​the velvet structure to the bottom area of ​​the velvet structure.

9. The method according to claim 8, characterized in that The method of performing texturing twice on the substrate to form a light-receiving velvet surface and a light-shielding velvet surface on the substrate comprises: Performing patterning on the substrate to form a mask on the substrate; Performing a texturing process on the substrate to form an initial light-receiving texturing surface in a non-mask region on the substrate; The mask on the substrate is removed to form an exposed area, and the substrate is subjected to secondary texturing to form the light-receiving velvet surface in the non-mask area and the light-shielding velvet surface in the exposed area.

10. The method according to claim 9, characterized in that The texturing conditions of the primary texturing are different from those of the secondary texturing; wherein the texturing conditions include at least one of DI ratio, ADD ratio, alkali ratio, texturing temperature and texturing time.

11. The method according to any one of claims 8 to 10, characterized in that: The method further comprises: The substrate is pre-treated to clean impurities on the surface of the substrate.

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