Display pixel including electroluminescent source

Abstract

A display pixel includes an electroluminescent source. The present disclosure relates to a display pixel (12i, j) for a display screen comprising a light emitting circuit (LEDS) comprising at least a first electroluminescent source (LED), a controllable current source (82) for driving the light emitting circuit with a current pulse (ILED, and a driving circuit (70) for controlling the current source, the driving circuit being configured to receive a digital signal (Data) and to control the current source, and a pulse width modulator for supplying current pulses modulated by pulse width modulation and pulse amplitude modulation based on bits of the digital signal.

Description

[0001] This application claims the benefit of priority to French patent application No. 22 / 06042, filed on June 20, 2022, entitled “Display pixel comprising electroluminescent sources,” which is incorporated herein by reference to the maximum extent permitted by law. Technical Field

[0002] The present disclosure relates to a display pixel including an electroluminescent source (eg, a light emitting diode) and a display screen having such a display pixel. Background Art

[0003] A pixel of an image corresponds to a unit element of an image displayed by a display screen. For the display of a color image, the display screen typically comprises at least three components, also referred to as display sub-pixels, for each pixel of the displayed image, each component emitting light radiation, referred to as an image pixel color component, of essentially a single color (e.g. red, green and blue). The superposition of the image pixel color components emitted by the three display sub-pixels provides the observer with a color sensation corresponding to the pixel of the displayed image. In this case, the assembly formed by the three display sub-pixels for displaying an image pixel is referred to as a display pixel of the display screen. Each display sub-pixel may comprise a light source, in particular a light emitting diode.

[0004] The display pixels may be distributed in an array, with each display pixel being located at the intersection of a row (or line) and a column of the array. Typically, each row of display pixels is selected sequentially, and the display pixels of the selected row are programmed to display the desired image pixels.

[0005] An active array is a screen driver architecture that is able to keep all rows of pixels active for the entire duration of the image, as opposed to a so-called passive array, where each row is active only for a time T = Tframe / M (where Tframe is the display duration of the entire image, and M is the number of rows of the screen). This enables the brightness of the display to be increased. In addition, low voltage or current levels can be sent on the array control lines, which enables larger data streams to be displayed.

[0006] As is known, electroluminescent sources, such as light-emitting diodes, are controlled by pulse width modulation, also known as PWM (for the English abbreviation pulse width modulation). This type of control consists in circulating continuous current pulses of constant intensity in the light-emitting diode, the pulses being repeated periodically, the duty cycle determining the intensity of the light emitted by the light-emitting diode. This control advantageously allows the light-emitting diode to be operated at its optimal operating point, at which the efficiency of the light-emitting diode (equal to the ratio of the optical power emitted by the light-emitting diode to the electrical power consumed by the light-emitting diode) is maximum.

[0007] Color depth, also called bit depth, is the number of bits used to encode the color of each image pixel color component of a single display pixel. It is generally desirable that the color depth be high. However, the implementation of pulse width modulation with high color depth may result in a complex display driver architecture, particularly because the generation of pulse width modulation pulses may require the generation of a large number of clock signals as the color depth increases. Summary of the invention

[0008] An object of an embodiment is to provide a display pixel including an electroluminescent source and a display screen including such a display pixel, which overcome all or part of the disadvantages of existing display pixels including an electroluminescent source and display screens including such a display pixel.

[0009] Another object of an embodiment is to control display pixels with high color depth by pulse width modulation.

[0010] Another object of an embodiment is to reduce the duration of a period for controlling an electroluminescent source.

[0011] One embodiment provides a display pixel for a display screen, the display screen comprising a lighting circuit including at least a first electroluminescent source, a controllable current source for driving the lighting circuit by current pulses, and a drive circuit for controlling the current source, the drive circuit being configured to receive a digital signal comprising a first bit and a second bit, the second bit being different from the first bit, and to control the current source for supplying current pulses modulated by pulse width modulation and modulated by pulse amplitude modulation based on the bits of the digital signal. The drive circuit is configured to command the current source to provide a current that is a sum of consecutive first current pulses having a constant intensity and a first duration that depends on the first bit of the digital signal, and a second current pulse commanded by a second bit of the digital signal and having a constant second duration, the sum of the first durations being less than or equal to the second duration. This advantageously allows for a reduction in the number of clock signals.

[0012] With regard to control using only pulse width modulation, this embodiment advantageously allows reducing the duration of the control period of the electroluminescent source while maintaining the same color depth.

[0013] According to one embodiment, the current source is configured to generate consecutive first current pulses while generating the second current pulses.

[0014] According to one embodiment, the bits of the digital signal are ordered from the most significant bit to the least significant bit, and the strength of the second current pulse depends on the rank of the second bit of the digital signal.

[0015] According to one embodiment, the second bit comprises the most significant bit of the digital signal. This allows the current intensity in the electroluminescent source to be modified only for high values ​​of the digital signal. In particular, when the electroluminescent source comprises a three-dimensional light emitting diode, this allows limiting the wavelength shift of the light emitted by the light emitting diode to high values ​​of the digital signal, which wavelength shift may occur when the current intensity circulating through the light emitting diode is varied.

[0016] According to one embodiment, the digital signal comprises a third bit different from the first bit and the second bit. The driver circuit is configured to command the controllable current source to provide a current as a sum of consecutive first current pulses, second current pulses and third current pulses, the third current pulse being commanded by the third bit of the digital signal and having a second duration.

[0017] According to one embodiment, the current source is configured to generate a third current pulse simultaneously with the second current pulse. According to one embodiment, the strength of the third current pulse depends on the rank of a third bit of the digital signal and is different from the strength of the second current pulse. According to one embodiment, the third bit is the second most significant bit of the digital signal.

[0018] This advantageously allows further reducing the number of clock signals required to perform the pulse amplitude modulation and thereby reducing the duration of the control period of the electroluminescent source.

[0019] According to one embodiment, the digital signal comprises a fourth bit different from the first bit, the second bit and the third bit. The driver circuit is configured to command the controllable current source to provide a current as a sum of consecutive first current pulses, second current pulses, third current pulses and a fourth current pulse, the fourth current pulse being commanded by the fourth bit of the digital signal and having a second duration.

[0020] According to one embodiment, the current source is configured to generate a fourth current pulse simultaneously with the second current pulse. According to one embodiment, the strength of the fourth current pulse depends on the rank of a fourth bit of the digital signal and is different from the strength of the second current pulse and the strength of the third current pulse. According to one embodiment, the fourth bit is the third most significant bit of the digital signal.

[0021] This advantageously allows further reducing the number of clock signals required to perform the pulse amplitude modulation and thereby reducing the duration of the control period of the electroluminescent source.

[0022] According to one embodiment, the drive circuit comprises a first storage circuit for storing said first bit of the digital signal, and the first storage circuit comprises a shift register clocked by a pulse width modulated clock signal. The structure of the drive circuit for the display pixel is advantageously simple and may occupy a reduced silicon area when the drive circuit is manufactured in an integrated manner.

[0023] According to one embodiment, the driver circuit comprises a second storage circuit for storing said second bit of the digital signal, and a logic circuit controlled by the control signal and configured to successively receive the first bit from the shift register clocked by the pulse width modulated clock signal and the second bit from the second storage circuit, and to control the controllable current source as a function of the successively received first and second bits when the control signal is in a given state. This advantageously allows controlling the duration of the display phase.

[0024] According to one embodiment, the lighting circuit comprises a first group of electroluminescent sources having a first number of electroluminescent sources and a second group of electroluminescent sources having a second number of electroluminescent sources. The controllable current source comprises a first controllable current source commanded by a first bit and connected to the first group of electroluminescent sources and a second controllable current source commanded by a second bit and connected to the second group of electroluminescent sources. This allows the current density in each electroluminescent source to be the same.

[0025] According to one embodiment, the controllable current source comprises:

[0026] a first MOS transistor connected to the light emitting circuit and a first switch connected to the first MOS transistor; and

[0027] A second MOS transistor is connected to the light emitting circuit and a second switch is connected to the second MOS transistor.

[0028] The structure of the controllable current source of the display pixel is advantageously simple.

[0029] According to one embodiment, the logic circuit is configured to control the first switch in sequence from each first bit, and to control the second switch based on the second bit.

[0030] According to one embodiment, the driving circuit is configured to control only the first switch based on some first bit, and to control the first switch and the second switch based on another first bit.

[0031] According to one embodiment, a first group of electroluminescent sources is connected to a first MOS transistor and a second group of electroluminescent sources is connected to a second MOS transistor. This allows the current density in each electroluminescent source to be the same.

[0032] According to one embodiment, the lighting circuit includes a third group of electroluminescent sources having a third number of light emitting diodes, and wherein the control source includes a third MOS transistor connected to the third group of electroluminescent sources and a third switch connected to the third MOS transistor, wherein the first number is equal to the second number, and wherein the third number is greater than the second number.

[0033] One embodiment also provides a display screen comprising an array of display pixels as previously defined.

[0034] According to one embodiment, the display screen comprises circuitry configured to modify the supply voltage of the display pixel in dependence on the second bit. This advantageously allows the power consumption of the display to be reduced through easy to use commands. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the following description of specific embodiments given by way of example and not limitation, with reference to the accompanying drawings, in which:

[0036] Figure 1 Examples of display screens are shown partially and schematically;

[0037] Figure 2 Shows Figure 1 An example of a block diagram of a display pixel of a display screen;

[0038] Figure 3 Shown by Figure 2 An example of a timing diagram of a signal for controlling a light emitting diode by pulse width modulation and a current supplied to the light emitting diode for a display pixel;

[0039] Figure 4 Shows the sent to Figure 1 An example of a timing diagram of a signal for two consecutive rows of display pixels of a display screen, the signal being used to control a light emitting diode by pulse width modulation;

[0040] Figure 5 shows a timing diagram of a current supplied to a light emitting diode for displaying a continuous digital color signal according to one embodiment of a method for controlling a light emitting diode;

[0041] Figure 6 shows a timing diagram of a current supplied to a light emitting diode for displaying a continuous digital color signal according to another embodiment of the method for controlling a light emitting diode;

[0042] Figure 7 Shows Figure 1 An embodiment of a block diagram of a display pixel of a display screen;

[0043] Figure 8 Shows Figure 7 A more detailed embodiment of an element of a display pixel;

[0044] Fig. 9 Shows Figure 7 More detailed embodiments of other elements of the display pixel;

[0045] Fig.10 Shows the control Figure 7 A timing diagram of signals during one embodiment of a method of displaying a pixel;

[0046] Fig.11 Shows the control Figure 7 A timing diagram of signals during another embodiment of a method for displaying a pixel;

[0047] Fig.12 Shows the control Figure 7 A timing diagram of signals during another embodiment of a method for displaying a pixel;

[0048] Fig.13 is a block diagram illustrating an embodiment of a method for modifying power to a display screen;

[0049] Fig.14 shows a timing diagram of the display's power supply during video data display;

[0050] Fig.15 is similar to Fig. 9 , and shows Figure 7 Another embodiment of an element of a display pixel;

[0051] Fig.16 yes Fig.15 A top view of a display pixel is shown;

[0052] Fig.17 Another embodiment of a display pixel is shown;

[0053] Fig.18 Shows Fig.17 A timing diagram of signals during operation of a display pixel;

[0054] Fig.19 Another embodiment of a display pixel is shown;

[0055] Fig. 20 Shows Fig.19 A timing diagram of signals during operation of a display pixel;

[0056] Fig.21 Another embodiment of a display pixel is shown;

[0057] Fig. 22 is a very simplified cross-sectional diagram showing an example of a pixel;

[0058] Fig.23 yes Fig. 22 a bottom view of a display pixel of; and

[0059] Fig.24 and Fig.25 They are shown separately Fig. 22 Block diagram of a display pixel. DETAILED DESCRIPTION

[0060] In the various drawings, the same features are represented by the same reference numerals. In particular, common structural and / or functional features in various embodiments may have the same reference numerals and may be provided with the same structure, size, and material properties. For clarity, only the steps and elements useful for understanding the embodiments described herein are shown and described in detail.

[0061] Unless otherwise stated, when referring to two elements connected together, this means a direct connection without any intermediate element except a conductor, and when referring to two elements coupled together, this means that the two elements can be connected, or they can be coupled via one or more other elements. In addition, a signal alternating between a first constant state (e.g., a low state, marked as "0") and a second constant state (e.g., a high state, marked as "1") is referred to as a "binary signal". The high state and low state of different binary signals of the same electronic circuit may be different. In fact, a binary signal may correspond to a voltage or current that may not be completely constant in a high state or a low state. In addition, in the following description, the source and drain of a MOS transistor are referred to as "power terminals" of an insulated gate field effect transistor or a MOS transistor.

[0062] Furthermore, unless otherwise stated, when referring to the voltage on a conductive pad, the difference between the potential at the conductive pad and a reference potential (eg, ground, taken equal to 0 V) ​​is considered.

[0063] Unless otherwise specified, the expressions "about", "approximately", "substantially" and "approximately" mean within 10%, and preferably within 5%. In addition, the expression "substantially constant" means less than 10% change over time relative to a reference value.

[0064] Pulse width modulated driving of an electroluminescent source, such as a light emitting diode, comprises circulating continuous current pulses of constant intensity and varying duration in the electroluminescent source. Pulse amplitude modulated driving of an electroluminescent source, such as a light emitting diode, comprises circulating continuous current pulses of constant duration and varying intensity in the electroluminescent source.

[0065] In the following description, embodiments of display pixels comprising light emitting diodes are disclosed. However, these embodiments can be implemented for display pixels comprising electroluminescent sources other than light emitting diodes, such as organic light emitting diodes, field-induced polymer electroluminescent elements, laser diodes.

[0066] In the following description, embodiments of color display screens comprising color display pixels, each display pixel comprising a light emitting diode adapted to emit radiation of a different color, are disclosed. However, these embodiments are also applicable to monochrome display screens comprising monochrome display pixels, each monochrome display pixel comprising one or more light emitting diodes adapted to emit radiation of a single color.

[0067] Figure 1 An example of a display screen 10 is partially and schematically shown. The display screen 10 includes display pixels 12 arranged, for example, in M ​​rows and N columns. i,j , M is an integer varying from 1 to 8,000, and N is an integer varying from 1 to 16,000, i is an integer varying from 1 to M, and j is an integer varying from 1 to N. For example, in Figure 1 In this example, M and N are equal to 6. Each display pixel has 12 i,j Via electrode 14 i is coupled to a source of a low reference potential Gnd, such as ground, and via electrode 16 j The source is coupled to a high reference potential Vcc. For example, electrode 14 i is shown along Figure 1 The rows are aligned, and the electrodes 16 j is shown along Figure 1 The columns in the display are aligned, and a reverse layout is possible. The supply voltage of the display corresponds to a voltage between a high reference potential Vcc and a low reference potential Gnd. The supply voltage depends in particular on the arrangement of the light-emitting diodes and the technology for manufacturing the light-emitting diodes. For example, the supply voltage can be approximately 4V to 5V.

[0068] For each row, the display pixels 12 in the row i,j is coupled to at least one row electrode 18 i For each column, the display pixels 12 in the column i,j is coupled to at least one column electrode 20 j Display screen 10 includes selection circuit 22 coupled to row electrodes 18 i And suitable for row electrode 18 i Display screen 10 includes data delivery circuit 24, which is coupled to column electrodes 20 j And suitable for the column electrode 20 j The selection circuit 22 and the control circuit 24 are controlled by a circuit 26 which may include, for example, a microprocessor.

[0069] Figure 2 Display pixel 12 of display screen 10 is shown i,j For a color display, the display pixels are 12 i,j The light emitting circuit LED comprises at least three light emitting diodes emitting radiation of different colors, wherein a single light emitting diode LED is Figure 2As shown. Each light emitting diode LED is coupled in series to a controllable current source CS, for example comprising a MOS transistor. In this example, for each light emitting diode LED, the anode of the light emitting diode LED receives a high reference potential Vcc, and the cathode of the light emitting diode LED is coupled to a terminal of the controllable current source CS, for example, and the other terminal of the controllable current source CS receives a low reference potential Gnd.

[0070] Display Pixel 12 i,j A driver circuit 40 for driving a controllable current source CS is also included. The driver circuit 40 may in particular include electronic components such as MOS transistors. The driver circuit 40 includes a storage circuit 48 (color data register) clocked by a clock signal Clk, which is configured to store digital color signals R, G, B based on received digital data Data. The digital color signals R, G, B each include NB bits and represent the color components of the image pixel to be displayed. The driver circuit 40 includes a circuit 50 (LED driver), which is configured to control the controllable current source CS coupled to the light emitting diode LED using the signals I_red, I_green and I_blue obtained from the digital color signals R, G, B and the signal PWM.

[0071] Figure 3 The timing diagram of the signal PWM and the signals I_red_1, I_red_2, I_red_3 and I_red_4 corresponding to the timing diagram of the signal PWM and the signals I_red_1, I_red_2, I_red_3 and I_red_4 corresponding to the timing diagram of the signal PWM Figure 2 Display pixels 12 i,j The signal I_red provided by the circuit 50 is used to display four different color signals R. According to one embodiment, the display pixel 12 i,j The light emitting diodes LED are controlled by pulse width modulation. For this purpose, during the display phase, the signal PWM presents a succession of pulses in the logic state "1", which rates the operation of the circuit 50 for controlling the light emitting diodes LED by pulse width modulation. The number of pulses in the succession of pulses corresponds to the number of bits NB of each digital color signal R, G and B.

[0072] For example, when the current source CS corresponds to a MOS transistor, the transistor is turned on or off at the pulse rate of the signal PWM, starting from the most significant bit, according to the logic value "0" or "1" of each bit of the color signal R, G or B, and the transistor remains turned on or off until the next pulse of the signal PWM. The duration between two consecutive pulses of the signal PWM is divided by two each time, so that the total duration of the light-emitting diode depends on the value of the color signal R, G or B. The consecutive pulses of the signal PWM can be repeated until another image pixel is displayed. In this case, the consecutive pulses of the signal PWM form a display cycle, and the display phase includes more than one display cycle.

[0073] exist Figure 3 , as an example, the number of pulses in the display period of the signal PWM is equal to 7, and only one display period is displayed. The obtained signal I_red_1 is used to display the image pixel color component corresponding to the color signal R equal to "1010101". The obtained signal I_red_2 is used to display the image pixel color component corresponding to the color signal R equal to "0101010". The obtained signal I_red_3 is used to display the image pixel color component corresponding to the color signal R equal to "1111111". The obtained signal I_red_4 is used to display the image pixel color component corresponding to the color signal R equal to "0000000".

[0074] The signal PWM can be generated from a periodic clock signal. The number of clock signals required to generate the signal PWM increases as the number of bits NB of the color signals R, G, and B increases. Generating a large number of clock signals leads to complex circuits. In addition, the image pixels of a new image to be displayed are displayed consecutively from the first row to the last row of the display screen.

[0075] Figure 4 The first line of the display is displayed (signal PWM j ) and the second consecutive line (signal PWM j+1 ) The timing diagram of the signal PWM received by the display pixel. Signal PWM j+1 corresponds to a signal PWM shifted from a duration H equal to Tframe / M j , where Tframe is the duration of the display of the entire image, and M is the number of rows of the display. The offset H of the signal PWM from the first row to the second consecutive row can be obtained by shifting the signal PWM j It is obtained by providing it to the successive latches before providing it to the second row.

[0076] In addition, when each display pixel 12 is controlled by pulse width modulation i,jWhen the light emitting diodes are used, the power consumed by the display screen 10 does not depend on the brightness of the displayed image. It is expected that when the brightness of the displayed image is reduced, the power consumed by the display screen will be reduced.

[0077] According to one embodiment, in order to display the image pixel color component corresponding to the digital color signal, each display pixel of the display screen is configured to drive the lighting circuit by pulse amplitude modulation (PAM) of certain bits of the digital color signal and pulse width modulation (PWM) of other bits of the digital color signal. According to one embodiment, the pulse amplitude modulation is applied to at least the most significant bit (MSB) of the digital color signal, and one or more consecutive bits that may be directly adjacent to the MSB.

[0078] According to one embodiment, for pulse width modulation, for each display phase cycle, a current pulse with a constant intensity and a variable first duration is supplied to the light emitting diode. According to one embodiment, for pulse amplitude modulation, for each display phase cycle, a current pulse with a constant second duration and a variable intensity is supplied to the light emitting diode. The second duration of the pulse of the pulse amplitude modulation is equal to the complete duration Tcycle of the display phase cycle of the pulse width modulation. According to one embodiment, at each time during the display cycle of the pulse width modulation, the current intensity supplied to the light emitting circuit is equal to the sum of the current intensity generated by the pulse amplitude modulation and the voltage intensity generated by the pulse width modulation. According to one embodiment, when all bits of the digital color signal for pulse width modulation are equal to "1", the complete duration Tcycle of the display phase cycle is also equal to the sum of the first duration of the current pulses generated due to the pulse width modulation, plus the duration associated with the low significant bit (LSB).

[0079] According to one embodiment, pulse amplitude modulation is used for the MSB of the digital color signal and the second most significant bit (MSB-1) of the digital color signal, that is, the bit after the MSB, and pulse width modulation is used for the other bits of the digital color signal. According to one embodiment, when only the MSB of the digital color signal is equal to "1", the current intensity supplied to the light emitting circuit is twice the current intensity supplied to the light emitting circuit when only the MSB-1 of the digital color signal is equal to "1". According to one embodiment, when only the MSB-1 of the digital color signal is equal to "1", the current intensity supplied to the light emitting circuit is equal to the current intensity supplied to the light emitting circuit for the pulse width modulated pulse when MSB MSB-1 and MSB-2 are equal to "0".

[0080] According to one embodiment, pulse amplitude modulation is used for the MSB of the digital color signal, the MSB-1 in the digital color signal, and the third most significant bit (MSB-2) of the digital color signal, that is, the bit after MSB-1, and pulse width modulation is used for other bits of the digital color signal. According to one embodiment, when only the MSB of the digital color signal is equal to "1", the current intensity supplied to the light emitting circuit is twice the current intensity supplied to the light emitting circuit when only the MSB-1 of the digital color signal is equal to "1", and is equal to four times the current intensity supplied to the light emitting circuit when only the MSB-2 of the digital color signal is equal to "1". According to one embodiment, when only the MSB-2 of the digital color signal is equal to "1", the current intensity supplied to the light emitting circuit is equal to the current intensity supplied to the light emitting circuit for the pulse width modulated pulse when the MSB, MSB-1 and MSB-2 are equal to "0".

[0081] Figure 5 and Figure 6 Each example of a timing diagram of the current I_LED supplied to the light emitting circuit of a display pixel embodiment is shown to show the image pixel color components encoded on a digital color signal having 10 bits for three different digital color signals. Reference I_MSB represents the portion of the intensity of the current I_LED due to pulse amplitude modulation when the MSB is equal to "1". Reference I_MSB-1 represents the portion of the intensity of the current I_LED due to pulse amplitude modulation when the MSB-1 is equal to "1". Reference I_MSB-2 represents the portion of the intensity of the current I_LED due to pulse amplitude modulation when the MSB-2 is equal to "1". Reference I_PWM represents the portion of the intensity of the current I_LED due to pulse width modulation. For Figure 5 and Figure 6 , the pulse duration of the pulse amplitude modulation is equal to the complete duration of the display phase cycle Tcycle of the pulse width modulation.

[0082] exist Figure 5 , pulse amplitude modulation is used for the MSB, MSB-1 and MSB-2 of the digital color signal, and pulse width modulation is used for the other 7 bits of the digital color signal. The first digital color signal is equal to "1110101010". The second digital color signal is equal to "0010101010". The third digital color signal is equal to "0000101010".

[0083] exist Figure 6, pulse amplitude modulation is used for the MSB and MSB-1 of the digital color signal, and pulse width modulation is used for the other 8 bits of the digital color signal. The first digital color signal is equal to "1101010100". The second digital color signal is equal to "0101010100". The third digital color signal is equal to "0001010100".

[0084] Figure 7 Shows Figure 1 Display pixels 12 i,j A block diagram of an embodiment of the present invention is configured to implement the previously combined Figure 5 and Figure 6 Disclosed is a light emitting diode driver.

[0085] Display Pixel 12 i,j Including previously combined Figure 2 All the disclosed elements, except the driver circuit 40 and the controllable current source CS, are replaced by the drive circuit 70 and the current drive circuit 82, respectively. The drive circuit 70 may in particular include electronic components such as MOS transistors. According to one embodiment, the drive circuit 70 includes two storage circuits 72 and 74, which are configured to store, for each image pixel color component, bits of a digital color signal representing the image pixel color component to be displayed based on the received data Data. The first storage circuit 72 (shift register for lower bits (PWM)) is a shift register in which the number of bits LB of the digital color signal implementing pulse width modulation is stored. The second storage circuit 74 (shift register for upper bits (PAM)) is a shift register in which the number of bits HB of the digital color signal implementing pulse amplitude modulation is stored. According to one embodiment, for each image pixel color component, the digital color signal includes NB bits, wherein the LB bits are stored in the first storage circuit 72 starting from the least significant bit (LSB) and used for pulse width modulation, and the HB bits are stored in the second storage circuit 74 starting from the MSB and used for pulse amplitude modulation.

[0086] The driver circuit 70 further includes a first shift circuit 76 (switch circuit), which receives the continuous bits of the data Data, the write clock signal Clk_wr and the signal PWM, and provides the bits of the data Data and the write clock signal Clk_wr or the signal PWM to the first storage circuit 72. The first shift circuit 76 is controlled by the binary signal Line. The driver circuit 70 further includes a second shift circuit 78 (switch circuit), which receives the write clock signal Clk_wr and the data bits from the first storage circuit 72, and provides the write clock signal Clk_wr and the data bits to the second storage circuit 74. The second shift circuit 78 is controlled by the binary signal Line.

[0087] The driver circuit 70 further comprises a logic circuit 80 (AND gate (HB+1)) which receives the binary signal CPWM from the first storage circuit 72 and the digital signal CPAM having the number of bits HB from the second storage circuit 74. The logic circuit 80 is controlled by the binary signal Ctrl.

[0088] The current driving circuit 82 supplies the current I_LED to the light emitting circuit LEDS. The logic circuit 80 is configured to provide the binary signal CPWM' and the digital signal CPAM' to the current driving circuit 82. Under the control of the signal Ctrl, the binary signal CPWM' may be equal to the binary signal CPWM, and the digital signal CPAM' may be equal to the digital signal CPAM. The current driving circuit 82 may include a digital-to-analog converter (DAC).

[0089] Figure 8 Shows Figure 7 A more detailed embodiment of the driving circuit 70 is shown, for example, when HB is equal to 3.

[0090] The first storage circuit 72 includes a series of D flip-flops FF1 to FF LB D flip-flops FF1 to FF LB The number of flip-flops is equal to LB. LB The Q output terminal of the second storage circuit 74 provides a signal CPWM. The second storage circuit 74 includes a HB continuous trigger, such as Figure 8 The three flip-flops FF shown as an example MSB-2 , FF MSB-1 and FF MSB . Flip-flop FF MSB-2 The Q output terminal provides a binary signal CPAM MSB-2 . Flip-flop FF MSB-1 The Q output terminal provides a binary signal CPAM MSB-1 . Flip-flop FF MSB The Q output terminal provides a binary signal CPAM MSB . Binary signal CPAM MSB-2 、CPAM MSB-1 and CPAM MSB Formed as Figure 7 The digital signal CPAM is shown.

[0091] The first shift circuit 76 includes a first 2:1 multiplexer MUX1 and a second 2:1 multiplexer MUX2, and the second shift circuit 78 includes a third 2:1 multiplexer MUX3 and a fourth 2:1 multiplexer MUX4. Each of the first multiplexer MUX1, the second multiplexer MUX2, the third multiplexer MUX3 and the fourth multiplexer MUX4 is controlled by a signal Line, and includes a first input terminal, a second input terminal and an output terminal, the output terminal being connected to the first input terminal when the signal Line is at a first value (e.g., "0"), and the output terminal being connected to the second input terminal when the signal Line is at a second value (e.g., "1").

[0092] The first input terminal of the first multiplexer MUX1 is connected to the flip-flop FF of the first storage circuit 72. LB The second input terminal of the first multiplexer MUX1 receives the signal Data, and the output terminal of the first multiplexer MUX1 is connected to the D input terminal of the flip-flop FF1 of the first storage circuit 72. The first input terminal of the second multiplexer MUX2 receives the signal PWM. The second input terminal of the second multiplexer MUX2 receives the write clock signal Clk_wr, and the output terminal of the second multiplexer MUX2 is connected to each flip-flop FF1 to FF2 of the first storage circuit 72. LB The clock input terminal.

[0093] The first input terminal of the third multiplexer MUX3 receives the reference potential Gnd. The second input terminal of the third multiplexer MUX3 is connected to the trigger FF of the first storage circuit 72. LB The Q output terminal of the third multiplexer MUX3 is connected to the flip-flop FF of the second storage circuit 74. MSB-2 The first input terminal of the fourth multiplexer MUX4 receives the reference potential Gnd. The second input terminal of the fourth multiplexer MUX4 receives the write clock signal Clk_wr, and the output terminal of the fourth multiplexer MUX4 is connected to each trigger FF of the second storage circuit 74. MSB-2 , FF MSB-1 and FF MSB The clock input terminal.

[0094] The logic circuit 80 includes an AND type HB+1 logic gate AND PWM 、AND MSB-2 、AND MSB-1 AND MSB Each gate AND PWM 、AND MSB-2 、AND MSB-1 AND MSBThe gate AND has a first input terminal receiving a signal Ctrl. PWM The second input terminal is connected to the flip-flop FF of the first storage circuit 72. LB The Q output of the AND gate MSB-2 、AND MSB-1 AND MSB The second input terminals of the two storage circuits 74 are connected to the flip-flop FF MSB-2 , FF MSB-1 and FF MSB The Q output terminal.

[0095] Fig. 9 Shows Figure 7 A more detailed embodiment of the current driving circuit 82, for example, when HB is equal to 3. The lighting circuit LED is displayed by a single light emitting diode LED Fig. 9 However, the lighting circuit LED may include a plurality of light emitting diodes LED connected in parallel.

[0096] The current driving circuit 82 includes HB+1 MOS transistors, for example, N-type, one of which is T PWM For pulse width modulation, and the HB transistor T MSB-2 、T MSB-1 and T MSB For pulse amplitude modulation. Each transistor T PWM 、T MSB-2 、T MSB-1 and T MSB The drain of the transistor T is connected to the cathode of the light emitting diode LED. The anode of the light emitting diode LED receives the high reference potential Vcc. PWM 、T MSB-2 、T MSB-1 and T MSB The gate of transistor T receives the signal Bias. MSB-2 The width of the transistor is equal to PWM The width of transistor T MSB-1 The width of the transistor is equal to MSB-2 The transistor T MSB The width of the transistor is equal to MSB-2 Four times the width.

[0097] The current driving circuit 82 includes HB+1 switches, one of which SW PWM For pulse width modulation, and HB switch SW MSB-2 , SW MSB-1 and SW MSB For pulse amplitude modulation. Each switch SW PWM , SW MSB-2 , SW MSB-1and SW MSB The first terminal of the switch SW receives the low reference potential Gnd. PWM The second terminal is connected to the transistor T PWM Each switch SW MSB-2 , SW MSB-1 and SW MSB The second terminals of the transistors T MSB-2 , T MSB-1 and T MSB The source of switch SW PWM The switch SW is controlled by the binary signal CPWM'. MSB-2 , SW MSB-1 and SW MSB The binary signal CPAM' MSB-2 , CPAM' MSB-1 and CPAM' MSB control.

[0098] Fig.10 Shows the Figure 8 and Fig. 9 Example of a timing diagram of the signals Line, Clk_wr, Ctrl and PWM during operation of a display pixel of the illustrated structure.

[0099] In the write phase WP, the signal Line is set to logic level "1" so as to perform a write operation in the first storage circuit 72 and the second storage circuit 74. More specifically, when the signal Line is at logic level "1", the multiplexer MUX1 provides the signal Data at its output, the multiplexer MUX2 provides the clock signal Clk_wr at its output, and the multiplexer MUX3 provides the clock signal Clk_wr at its output. LB The signal provided at the Q output terminal of the multiplexer MUX4, and the clock signal Clk_wr are provided at the output terminal of the multiplexer MUX4. Successive bits of the data Data are stored in the first storage circuit 72 and the second storage circuit 74 clocked by the clock signal Clk_wr. According to one embodiment, the bits of the data Data are successively provided to the first flip-flop FF1 of the storage circuit 72 from the MSB to the LSB of the digital color signal. The bit is shifted at the rhythm of the clock signal Clk_wr, through the first storage circuit 72, and finally through the second storage circuit 74. Specifically, the MSB of the digital color signal is shifted from the flip-flop FF1 of the first storage circuit 72 to the flip-flop FLL LB , and then from the flip-flop FF MSB-2 Shift to the flip-flop FF of the second storage circuit 74 MSB When the MSB of the digital color signal reaches the flip-flop FF MSB When , the LSB of the digital color signal arrives at the flip-flop FF1.

[0100] In the display phase DP between two consecutive writing phases WP, the signal Line is set to logic level "0". During the display phase DP, the signal Ctrl is set to logic level "1" in at least one display period DC for displaying the image pixel color component via the light emitting diode LED. When the signal Line is at logic level "0", the multiplexer MUX1 provides a flip-flop FF at its output LB The Q output of the multiplexer MUX2 provides the signal PWM at its output, the multiplexer MUX3 provides the low reference potential Gnd at its output, and the multiplexer MUX4 provides the low reference potential Gnd at its output. In addition, since the signal Ctrl is at the logic level "1", each gate AND PWM 、AND MSB-2 、AND MSB-1 AND MSB Provides at its output the bit present at its second input. Thus, the AND gate PWM Provides a flip-flop FF at its output LB bits appear at the output, and each AND gate MSB-2 、AND MSB-1 AND MSB The flip-flops FF1 to FF2 of the first storage circuit 72 provide the MSB-2, MSB-1 and MSB of the color signal data at their output terminals, respectively. LB The signal PWM is clocked, and at each pulse of the signal PWM, the bits of the digital color signal stored in the first storage circuit 71 are shifted from one flip-flop to the next flip-flop so that the bits appearing in the flip-flop FF LB The bits at the output terminal correspond sequentially to the LB bits of the color data signal, and the last bit provided is the LSB in the color data signal.

[0101] Fig.11 Another embodiment is shown in which the signal PWM and the signal Clk_wr are merged into a single binary signal Clk_PWM. According to this variant, the multiplexer MUX2 may not be present.

[0102] exist Fig.10 and Fig.11 In the timing diagram shown, there is only one display period DC during the display phase DP between two consecutive writing phases WP. Alternatively, the display phase DP between two consecutive writing phases WP may comprise more than one display period DC.

[0103] Fig.12 Similar to Fig.10 , and shows Figure 8 and Fig. 9An example of a timing diagram of the signals Line, Clk_wr, Ctrl and PWM during operation of a display pixel of the structure shown. Fig.12 In FIG. 1 , each display phase DP between two consecutive writing phases WP comprises four repetitions of the same display period DC.

[0104] Fig.13 is a block diagram showing an embodiment of a method for modifying the power supply Vcc of the display screen 10. The method comprises the following steps:

[0105] - receiving video data to be displayed by the circuit 26 of the display screen 10 (step 100);

[0106] - Determine the maximum gray level of the image to be displayed (step 102). In order to simplify the calculation of the image gray level, for each image pixel color component of each image pixel, only the bits of the digital color signal used for pulse amplitude modulation are considered;

[0107] - determining the current intensity required for image display based on the maximum gray level of the image (step 104); and

[0108] - Adjust the power supply voltage Vcc (step 106) so that the desired current intensity can be provided to the light emitting diodes of the display pixels when displaying an image.

[0109] For an image with dark tones, the level of the power supply voltage Vcc can be reduced, because in this case, only a low-intensity current is required to display the image. For an image with light tones, the level of the power supply voltage Vcc can be increased, because in this case, a high-intensity current is required to display the image. Therefore, this embodiment allows reducing the power consumed by the display screen.

[0110] Fig.14 An example of the evolution of the power supply Vcc during the display of video data is shown. In this example, the bits used for pulse amplitude modulation are the MSB and MSB-1 of the color data signal. For example, Fig.14 Four consecutive phases P1, P2, P3 and P4 with different maximum gray levels are shown. In phases P1 and P4, the maximum gray level corresponds to the MSB and MSB-1 at the logic state "1". In phase P2, the maximum gray level corresponds to the MSB at the logic state "0" and the MSB-1 at the logic state "1". In phase P3, the maximum gray level corresponds to the MSB and MSB-1 at the logic state "0". Fig.14 As shown, in each phase P1, P2, P3 and P4, the potential Vcc is adjusted to a constant level. The change of the potential Vcc from a constant level to another constant level can be implemented at a given change rate to prevent a sudden change in the displayed image.

[0111] In some cases, the wavelength of radiation emitted by a light emitting diode may vary depending on the intensity of the current passing through the light emitting diode. This may be undesirable.

[0112] Fig.15 is similar to Fig. 9 The figure shows that the display pixel 12 i,j Another embodiment of . Fig.15 The display pixel 12 shown in i,j include Fig. 9 The display shown in the pixel 12 i,j all elements of , except that it comprises a lighting circuit LEDS comprising a plurality of light emitting diodes LED for each image pixel color component, Fig.15 Only the light-emitting diodes LED of one image pixel color component are shown in FIG. This embodiment can be advantageously easily implemented when each light-emitting diode comprises a nano- or micro- three-dimensional element (e.g. a microwire, a nanowire or a nano- or micro- three-dimensional element having a pyramid, cone or truncated cone shape), which is covered by the active area of ​​the light-emitting diode, which is the area where most of the electromagnetic radiation supplied by the light-emitting diode is emitted.

[0113] For each image pixel color component, the light emitting diodes LED of the light emitting circuit LEDS are allocated to the HB+1 group of light emitting diodes. PWM ,LED MSB-2 ,LED MSB-1 and LED MSB For example Fig. 9 HB is equal to 3, and each group of light-emitting diodes LED PWM ,LED MSB-2 ,LED MSB-1 and LED MSB Depend on Fig.15 The electronic symbol of a single light-emitting diode LED. PWM ,LED MSB-2 ,LED MSB-1 and LED MSB The anode of each LED receives a high reference potential Vcc. PWM The cathode of each LED is connected to the transistor T PWM The drain of the LED group MSB-2 The cathode of each LED is connected to the transistor T MSB-2 The drain of the LED group MSB-1 The cathode of each LED is connected to the transistor T MSB-1 The drain of the LED group MSB The cathode of each LED is connected to the transistor T MSBThe drain of each LED PWM ,LED MSB-2 ,LED MSB-1 and LED MSB The number of LEDs in the group is chosen so that, when switched on, MSB-2 The light intensity emitted is equal to that of the LED PWM The light intensity emitted by the LED MSB-1 The light intensity emitted is equal to that of the LED MSB-2 The light intensity emitted is twice that of the LED MSB The light intensity emitted is equal to that of the LED MSB-1 The light intensity emitted is twice as high. Therefore, each LED PWM ,LED MSB-2 ,LED MSB-1 and LED MSB The current density of each light emitting diode is advantageously the same. In the case where the light emitting diodes all have the same structure, the group LED MSB-2 The number of LEDs is equal to the group LED PWM The number of LEDs, group LED MSB-1 The number of LEDs is equal to the group LED MSB-2 The number of LEDs is twice as large, and the LED group MSB The number of LEDs is equal to the group LED MSB-1 Therefore, each LED group PWM ,LED MSB-2 ,LED MSB-1 and LED MSB The current density of each light-emitting diode is advantageously the same.

[0114] Fig.16 yes Fig.15 The display pixel 12 is shown i,j A top view of an embodiment of a light emitting diode of a light emitting circuit LEDS is shown. Each light emitting diode LED is shown by a circle, the letter "R" in the circle represents a light emitting diode emitting red radiation, the letter "G" represents a light emitting diode emitting green radiation, and the letter "B" represents a light emitting diode emitting blue radiation. Fig.16 Middle, group LED MSB Includes four LEDs for each image pixel color component, a group LED MSB-1 Includes two LEDs for each image pixel color component, a group LED MSB-2 Includes one LED for each image pixel color component, and a group LED PWM Includes one light emitting diode for each image pixel color component.

[0115] You may want to reduce the display pixel 12 i,j The storage capacity of digital signals.

[0116] Fig.17 is similar to Fig.15 The figure shows that the display pixel 12 i,j Another embodiment of . Fig.17 The display pixel 12 shown in i,j include Fig.15 The display pixel 12 shown in i,j All components, except for LEDS for lighting circuit, group LED PWM Labeled as LED1, group LED MSB-2 Labeled as LED2, group LED MSB-1 Labeled as LED3, group LED MSB Marked as LED4, transistor T PWM Marked as T1, transistor T MSB-2 Marked as T2, transistor T MSB-1 Marked as T3, transistor T MSB Marked as T1, switch SW PWM Marked as SW1, switch SW MSB-2 Marked as SW2, switch SW MSB-1 Marked as SW3, SW MSB It is marked as SW4 and is controlled by the control circuit 110 except for the gates of the transistors T1 , T2 , T3 , T4 .

[0117] Fig.18 Shows the Fig.17 The display pixel 12 is shown i,j 1 is a timing diagram of the signals Vsync and Clk_wr and the control signal CLED of the light emitting diode of an embodiment of a display screen. In this embodiment, in order to display the color components of a color image pixel, the bits of the digital color signal are sent to each display pixel in successive write phases WP separated by display phases DP. Fig.18 Taking the image pixel display as an example, four writing phases WP and four display phases DP are shown, and during each writing phase WP, a 2-bit digital color signal is stored in the display pixel, and the digital color signal includes 8 bits.

[0118] Each display phase DP is divided into a first sub-phase DP_1 and a second sub-phase DP_2. The total duration of the display phase DP, the duration of the first sub-phase DP_1 and the duration of the second sub-phase DP_2 are the same for all display phases DP. The duration of the first sub-phase DP_1 is equal to a multiple of the duration of the second sub-phase DP_2. In the present example, the duration of the first sub-phase DP_1 is equal to sixteen times the duration of the second sub-phase DP_2. For each display phase DP, different groups of light emitting diodes in the groups LED1, LED2, LED3 and LED4 are switched on or off based on the first storage bit of the digital color signal during the first sub-phase DP_1 and based on the second storage bit of the digital color signal during the second sub-phase DP_2.

[0119] exist Fig.18 , the groups LED1, LED2, LED3 and LED4 of light emitting diodes that can be used during the display phase DP are indicated under the display phase DP. In the present embodiment, the light emitting diodes of the group LED1 are used for the first and second sub-phases DP_1 and DP_2 of all display phases DP. The light emitting diodes of the group LED2 are used for the first and second sub-phases DP_1 and DP_2 of three display phases DP and are systematically switched off in the other display phases DP. The light emitting diodes of the group LED3 are used for the first and second sub-phases DP_1 and DP_2 of two display phases DP and are systematically switched off in the other display phases DP. The light emitting diodes of the group LED4 are used for the first and second sub-phases DP_1 and DP_2 of one of the display phases DP and are systematically switched off in the other display phases DP. Four consecutive display phases correspond to a single display phase, for which the light emitting diodes are controlled by pulse width modulation and pulse amplitude modulation.

[0120] Fig.19 Display pixel 12 i,j Another embodiment of . Fig.19 The display pixel 12 is shown i,j include Figure 8 Pixel 12 shown i,j All elements of the display pixel 12 are absent except that the second storage circuit 74, the second shift circuit 78 and the logic circuit 80 are not present. i,j include Fig.17 The lighting circuit LEDS shown has two groups of light emitting diodes LED1 and LED2. Fig.19In the example in FIG. 1 , the number of flip-flops of the first storage circuit 72 is equal to 4. The flip-flops FF1 to FF4 are clocked by the binary signal Clk_PWM. In addition, the first shift circuit 76 only includes a first multiplexer Mux1. The first input terminal of the first multiplexer MUX1 receives the low reference potential Gnd. The second input terminal of the first multiplexer MUX1 receives the signal Data, and the output terminal of the first multiplexer MUX1 is connected to the D input terminal of the flip-flop FF1 of the first storage circuit 72.

[0121] The drive circuit 70 also includes an additional D flip-flop FF clocked by the binary signal Clk_PWM Cl . Flip-flop FF Cl The D input of the flip-flop FF is connected to C1 The driving circuit 70 further includes an inverter INV and a NOR type logic gate NOR. The input end of the inverter INV is connected to the trigger FF Cl The Q output terminal of the inverter INV provides a binary signal CLED. The QB output terminal of the flip-flop FF4 is connected to the first input terminal of the gate NOR. The output terminal of the inverter INV is connected to the second input terminal of the gate NOR. In this embodiment, the display pixel 12 i,j Only groups of light emitting diodes LED1 and LED2 are included.

[0122] Fig. 20 Shows the Fig.18 The display pixel 12 is shown i,j 1 is a timing diagram of the signals Vsync and Clk_PWM and the signal CLED of an embodiment of a display screen. The binary signal Clk_PWM includes a write clock Clk_wr and a signal PWM. In this embodiment, during the write phase WP, the bits of the digital color signal are sent to the display pixel 12 i,j During the display phase DP following the write phase WP, the signal Clk_PWM comprises first, second, third, fourth and fifth consecutive pulses P1, P2, P3, P4 and P5. The first pulse P1 indicates the start of the display phase DP and the fifth pulse P5 indicates the end of the display phase PP. The storage circuit 72 is clocked by the consecutive pulses P1, P2, P3, P4 to continuously provide the bits stored in the storage circuit 72 at the Q output of the flip-flop FF4.

[0123] The duration between the first pulse P1 and the second pulse P2 is equal to the duration between the second pulse P2 and the third pulse P3. The duration between the third pulse P3 and the fourth pulse P4 is equal to the duration between the fourth pulse P4 and the fifth pulse P5, and is equal to four times the duration between the first pulse P1 and the second pulse P2. The signal CLED provided by the inverter INV alternates between logic states "0" and "1" at each pulse of the signal Clk_PWM, so that CLED is in logic state "0" between the first pulse P1 and the second pulse P2 and between the third pulse P3 and the fourth pulse P4, and the signal CLED is in logic state "1" between the second pulse P2 and the third pulse P3 and between the fourth pulse P4 and the fifth pulse P5.

[0124] exist Fig. 20 , the group LED1 of light emitting diodes can be used during the entire display phase DP, while the group LED2 of light emitting diodes can only be used between the second pulse P2 and the third pulse P3 and between the fourth pulse P4 and the fifth pulse P5. Therefore, between the first pulse P1 and the second pulse P2 and between the third pulse P3 and the fourth pulse P4, only the light emitting diodes of the group LED1 are turned on or off based on the bit provided by the flip-flop FF4, and between the second pulse P2 and the third pulse P3 and between the fourth pulse P4 and the fifth pulse P5, the light emitting diodes of the two groups LED1 and LED2 are turned on or off based on the bit provided by the flip-flop FF4. Therefore, the current density of each light emitting diode of each group LED1 and LED2 is advantageously the same.

[0125] Fig.21 Display pixel 12 i,j Another embodiment of . Fig.21 The display pixel 12 is shown i,j include Fig.18 The display pixel 12 is shown i,j All elements except for one group LED1 which comprises only one light emitting diode for each image pixel color component, the cathodes of the light emitting diodes of the group LED1 being connected to the drain of the transistor T1 and the drain of the transistor T2. Fig.21 The display pixel 12 is shown i,j Operation and Fig.19 The display pixel 12 is shown i,j The operation is the same as

[0126] As described below, in order to limit the i,j The number of conductive pads Gnd, P_Vcc, P_Col, P_Row, data signal Data j Each display pixel 12 i,jDetermine the clock signal and the color signals R, G, B representing the required light intensity of the first, second and third wavelength radiation. As a variant, the data signal Data j can be used only for each display pixel 12 i,j Determine the color signal R, G, B, and the clock signal is generated by each pixel 12 i,j Received on separate conductive pads.

[0127] according to Figure 1 In the embodiment of the display screen 10 shown, for each row, the display pixels 12 in the row i,j is coupled to a single row electrode 18 i For each column, the display pixels 12 in the column i,j is coupled to a single column electrode 20 j Display screen 10 includes selection circuit 22 coupled to row electrodes 18 i And suitable for each row electrode 18 j Delivery selection and timing signals Com i Display screen 10 includes data delivery circuit 24 coupled to column electrodes 20 j And suitable for each column electrode 20 j Data signal j The selection circuit 22 and the control circuit 24 are controlled by a circuit 26 comprising, for example, a microprocessor.

[0128] Fig. 22 Display Pixel 12 i,j A very simplified cross-sectional view of a known example of Fig.23 Display Pixel 12 i,j Bottom view of each display pixel 12 i,jA control circuit 30 is included which is covered with a display circuit 32. The display circuit 32 includes at least one light emitting diode LED, preferably at least three light emitting diodes LED. The display pixel includes a lower surface 34 and an upper surface 35 opposite to the lower surface 34, the surfaces 34 and 35 preferably being planar and parallel. The control circuit 30 also includes conductive pads P_Gnd, P_Vcc, P_Col, P_Row on the lower surface 34. The control circuit 30 may correspond to an integrated circuit including electronic components, in particular insulated gate field effect transistors, also called MOS transistors, or thin film transistors, also called TFTs. Preferably, the display circuit 32 includes only light emitting diodes LED and conductive elements of these light emitting diodes LED, and the control circuit 30 includes all electronic components required to control the light emitting diodes LED of the display circuit 32. As a variant, the display circuit 32 may include other electronic components in addition to the light emitting diodes LED. The light emitting diodes LED may be 2D light emitting diodes, also called planar light emitting diodes, including a stack of planar layers, or 3D light emitting diodes, each including a three-dimensional semiconductor element covered with an active area. In Fig. 22 In FIG. 1 , the light emitting diodes are shown as being connected to a common anode. However, it may be desirable to arrange the light emitting diodes LED according to another configuration. For example, the light emitting diodes may be connected to a common cathode, or may be connected independently of each other.

[0129] According to one embodiment, the display pixel 12 i,j The display pixel 12 includes three display sub-pixels emitting light at first, second and third wavelengths. According to one embodiment, the first wavelength corresponds to blue light and is in the range of 430nm to 490nm. According to one embodiment, the second wavelength corresponds to green light and is in the range of 510nm to 570nm. According to one embodiment, the third wavelength corresponds to red light and is in the range of 600nm to 720nm. As a variant, the display pixel 12 i,j Only one light source emitting light of the first wavelength, the second wavelength, or the third wavelength may be included, or only two light sources emitting light of two of the first wavelength, the second wavelength, and the third wavelength may be included.

[0130] Each conductive pad P_Gnd, P_Vcc, P_Col, P_Row is intended to be connected to Fig. 22 The electrode 14 schematically shown in i , 16 j , 18 i , 20 j The first conductive pad P_Gnd is coupled to the source of the low reference potential Gnd. The second conductive pad P_Vcc is coupled to the source of the high reference potential Vcc. The third conductive pad P_Row is coupled to the row electrode 18. iThe fourth conductive pad P_Col is coupled to the column electrode 20. j And receive data signal Data j .

[0131] Fig.24 Display pixel 12 of display screen 10 is shown i,j Examples of known block diagrams. Fig.24 Above each block is the supply voltage used to power the electronics in that block.

[0132] Display Pixel 12 i,j The drive circuit 70 is comprised of a controllable current source 82. The drive circuit 70 may in particular comprise electronic components such as MOS transistors. It may be desirable to use a reduced supply voltage of less than 4 V, for example about 1 V or 1.8 V, to power the electronic components of the drive circuit 70, the reduced supply voltage corresponding, for example, to a voltage that may be applied between the supply terminals of a MOS transistor. To this end, the display pixel 12 i,j A circuit 42 (Vdd generation) is included for delivering from the supply voltage Vcc a reduced supply voltage Vdd specifically for the power supply of the driver circuit 40. For example, the circuit 42 includes a voltage divider.

[0133] According to one embodiment, in each display pixel 12 i,j The detection and timing signal Com received at the conductive pad P_Row i It is a binary signal that alternates between a low state "0" and a high state "1", the low state corresponding to the low reference potential Gnd, and the high state "1" corresponding to a low voltage less than the reduced power supply voltage Vdd, for example, about 1V. i,j The data signal Data received at the conductive pad P_Col j It is a binary signal that alternates between a low state "0" and a high state "1", the low state corresponding to a low reference potential Gnd, and the high state "1" corresponding to a low voltage less than the reduced power supply voltage Vdd, for example about 1V.

[0134] Display Pixel 12 i,j The circuit 44 (Clk & Data Separation) is coupled to the conductive pad P_Col and receives the data signal Data j , and from the data signal Data j Delivers clock signal Clk and other data. Display pixel 12 i,j The circuit 46 (mode select) comprising the reception signal Clk and data is coupled to the reception selection and timing signal Com iThe conductive pad P_Row is configured to deliver a signal Clk_wr and data or a PWM signal to the driving circuit 70 for controlling a controllable current source 82 associated with each light emitting diode LED.

[0135] As described below, in order to limit the i,j The number of conductive pads Gnd, P_Vcc, P_Col, P_Row, data signal Data j Each display pixel 12 i,j Determine the clock signal and the color signals R, G, B representing the required light intensity of the first, second and third wavelength radiation. As a variant, the data signal Data j can be used only for each display pixel 12 i,j Determine the color signal R, G, B, and the clock signal is generated by each pixel 12 i,j Received on separate conductive pads.

[0136] Fig.25 Indicates display pixel 12 i,j A block diagram of an embodiment of the invention. Fig.25 Display pixels 12 i,j With Fig.24 Display pixels 12 i,j The same structure, except that the circuit 42 for supplying the reduced power supply voltage Vdd is used to supply the reception selection and timing signal Com i And data signal Data j In this embodiment, the reduced power supply voltage Vdd is derived from the selection and timing signal Com i and data signal Data j supply.

[0137] According to one embodiment, for each display pixel 12 i,j , circuit 44 is based on the data signal Data j The pulses of the clock signal Clk and the data Data are determined. For example, the data signal Data j Each pulse of may have a first length or a second length longer than the first length. The signal Clk may correspond to a pulse sequence of the same length, whose rising edge is at a possibly constant offset from the data signal Data. j The rising edge of the pulse coincides with that of j When the pulse of has a first length, the data Data may correspond to a binary signal in state “0”, and when the signal Data j When the pulse has a second length, it can correspond to a binary signal in state "1".i The selected circuit 46 delivers data Data at the rate of the clock signal Clk, the data Data being stored in the circuit 70 in the form of digital color signals R, G, B, the bits of which are provided by the successive values ​​of the signal Data.

[0138] Various embodiments and variations have been described. Those skilled in the art will appreciate that certain features of these embodiments may be combined and that other variations will readily occur to those skilled in the art. In particular, in previously disclosed embodiments, the light emitting diodes have a common anode, that is, the anode of the light emitting diode receives a high reference voltage and the cathode of the light emitting diode is connected to a controllable current source. However, these embodiments are also applicable to display pixels in which the light emitting diodes have a common cathode, that is, the cathode of the light emitting diode receives a low reference voltage and the anode of the light emitting diode is connected to a controllable current source.

[0139] Finally, actual implementation of the embodiments and variations described herein is within the capabilities of those skilled in the art based on the functional description provided above.

Claims

1. A display pixel (12) for a display screen (10) i,j ), the display screen comprises a lighting circuit (LEDS) comprising at least a first electroluminescent source (LED), a controllable current source (82) for driving the lighting circuit by a current pulse (I_LED), and a drive circuit (70) for controlling the current source, the drive circuit being configured to receive a digital signal (Data) comprising a first bit and a second bit, the second bit being different from the first bit, and to control the current source for supplying a current pulse modulated by pulse width modulation and modulated by pulse amplitude modulation based on the bit of the digital signal, wherein The drive circuit (70) is configured to command the current source (82) to provide a current that is a sum of consecutive first current pulses having a constant intensity and a first duration that depends on a first bit of a digital signal and a second current pulse commanded by a second bit of the digital signal and having a constant second duration (Tcycle), the sum of the first durations being less than or equal to the second duration.

2. The display pixel according to claim 1, wherein: The current source (82) is configured to generate the consecutive first current pulses simultaneously with the generation of the second current pulses.

3. The display pixel according to claim 1 or 2, wherein: The bits of the digital signal are ordered from the most significant bit to the least significant bit, and wherein the strength of the second current pulse depends on the rank of the second bit of the digital signal (Data).

4. The display pixel according to claim 6, wherein: The second bit includes the most significant bit of the digital signal (Data).

5. The display pixel according to claim 3 or 4, wherein: The digital signal (Data) includes a third bit different from the first bit and the second bit, and wherein the drive circuit (70) is configured to command the controllable current source (82) to provide a current that is the sum of the consecutive first current pulses, the second current pulses and a third current pulse, the third current pulse being commanded by the third bit of the digital signal (Data) and having the second duration (Tcycle).

6. The display pixel according to claim 5, wherein: The current source (82) is configured to generate the third current pulse simultaneously with the second current pulse.

7. The display pixel according to claim 5 or 6, wherein: The strength of the third current pulse depends on the rank of the third bit of the digital signal and is different from the strength of the second current pulse.

8. The display pixel according to claim 7, wherein: The third bit is the second most significant bit of the digital signal (Data).

9. The display pixel according to any one of claims 5 to 8, wherein: The digital signal (Data) includes a fourth bit different from the first bit, the second bit and the third bit, and wherein the drive circuit (70) is configured to command the controllable current source (82) to provide a current that is the sum of the consecutive first current pulse, the second current pulse, the third current pulse and a fourth current pulse, the fourth current pulse being commanded by the fourth bit of the digital signal (Data) and having the second duration (Tcycle).

10. The display pixel according to claim 6, wherein: The current source (82) is configured to generate the fourth current pulse simultaneously with the second current pulse.

11. The display pixel according to claim 9 or 10, wherein: The intensity of the fourth current pulse depends on the rank of a fourth bit of the digital signal (Data), and is different from the intensity of the second current pulse and the intensity of the third current pulse.

12. The display pixel according to claim 11, wherein: The fourth bit is the third most significant bit of the digital signal (Data).

13. The display pixel according to any one of claims 1 to 12, wherein: The drive circuit (70) includes a first storage circuit (72) for storing the first bit of the digital signal, and wherein the first storage circuit includes a shift register clocked by a pulse width modulated clock signal (PWM).

14. The display pixel according to claim 13, wherein: The drive circuit (70) includes a second storage circuit (72) for storing the second bit of the digital signal, and a logic circuit (80) controlled by a control signal (Ctrl), and the logic circuit is configured to continuously receive the first bit from a shift register (72) clocked by the pulse width modulation clock signal (PWM) and the second bit from the second storage circuit (74), and when the control signal is in a given state, control the controllable current source (82) according to the first bit and the second bit received successively.

15. The display pixel according to any one of claims 1 to 14, wherein: The lighting circuit (LEDS) comprises a first group of electroluminescent sources (LEDS) having a first number of electroluminescent sources PWM ; LED1) and a second group of electroluminescent sources (LED MSB-2 ,LED MSB-1 ,LED MSB ; LED2, LED3, LED4), wherein the controllable current source (82) includes a first bit command and connected to the first group of electroluminescent sources (LED PWM ; LED1) of the first controllable current source (T PWM , SW PWM ; T1), and the second bit command and connected to the second group of electroluminescent sources (LED MSB-2 ,LED MSB-1 ,LED MSB ; LED2, LED3, LED4) of the second controllable current source (T MSB , S.W. MSB , T MSB-1 , S.W. MSB-1 , T MSB-2 , S.W. MSB-2 ; T2, T3, T4).

16. The display pixel according to any one of claims 1 to 15, wherein: The controllable current source (82) comprises: A first MOS transistor (T PWM ; T1) and a first switch (SW PWM ; SW1); and A second MOS transistor (T MSB-2 , T MSB-1 , T MSB ; T2, T3, T4) and a second switch (SW MSB-2 , S.W. MSB-1 , S.W.B. MSB ; SW2, SW3, SW4).

17. The display pixel according to claim 16, wherein: The logic circuit (80) is configured to control the first switch (SW PWM ; SW1), and controls the second switch (SW MSB-2 , SW MSB-1 SWB MSB ).

18. The display pixel according to claim 17, wherein: The driving circuit (70) is configured to control only the first switch (SW1) based on some of the first bits, and to control the first switch and the second switch (SW1) based on other of the first bits.

19. A display pixel according to claims 15 and 16, wherein: The first group of electroluminescent sources (LED PWM ; LED1) is connected to the first MOS transistor (T PWM ; T1), and wherein the second group of electroluminescent sources (LED MSB-2 ,LED MSB-1 ,LED MSB ; LED2, LED3, LED4) are connected to the second MOS transistor (T MSB-2 , T MSB-1 , T MSB ; T2, T3, T4).

20. The display pixel of claim 19, wherein: The lighting circuit (LEDS) comprises a third group of electroluminescent sources (T MSB-2 , T MSB-1 , T MSB ; T2, T3, T4), and wherein the control source (82) comprises a third MOS transistor (T MSB-2 , T MSB-1 , T MSB ; T2, T3, T4) and a third switch (SW MSB-2 , S.W. MSB-1 , S.W.B. MSB ; SW2, SW3, SW4), wherein the first quantity is equal to the second quantity, and wherein the third quantity is greater than the second quantity.

21. A display screen (60) comprising an array of display pixels (12i,j) according to any one of claims 1 to 20.

22. A display screen as claimed in claim 21, comprising a circuit (26) configured to modify a supply voltage (Vcc) of the display pixel in dependence on the second bit.

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