Chip simulation heat source and heat conduction interface material aging test method thereof

Abstract

The invention relates to a chip simulation heat source and a heat conduction interface material aging test method thereof, and the chip simulation heat source comprises a supporting substrate layer which is provided with a plurality of groups of welding points and is provided with metal wires in one-to-one correspondence with the welding points; the metal heating layer is arranged on the surface of the supporting substrate layer, one or more independent heating areas are arranged on the metal heating layer, each heating area is provided with pins in one-to-one correspondence with the metal wires, and the pins are electrically connected with welding points through the metal wires; and the material simulation layer is arranged on the metal heating layer. One or more heating areas are arranged on the heating layer, different heating areas are selected to be electrified according to actual working conditions of different chips, and meanwhile, the power of the electrified heating areas is controlled, so that the heating power of an existing chip during working is simulated, and the precision degree of subsequent testing is ensured.

Description

Technical Field

[0001] The present application relates to the technical field of thermal conductive material aging testing, and in particular to a chip simulation heat source and a thermal conductive interface material aging testing method. Background Art

[0002] Currently, the main heat dissipation method for electronic devices is to install thermal conductive interface materials between metal heat sinks and heat-generating electronic components. The thermal conductive interface materials provide a high-speed heat conduction path, so that the heat of the electronic components is transferred to the metal heat sink with a larger heat dissipation area, and then transferred to the air or liquid heat dissipation medium by natural convection or forced convection.

[0003] Currently, there are many standards and equipment for evaluating the thermal conductivity and thermal resistance of thermal conductive interface materials, such as the steady-state method ASTM D5470 and the dynamic method.

[0004] There is no standard method for thermal interface materials for aging performance evaluation. This is mainly because the aging failure mode of thermal interface materials is not only related to the material itself, but also strongly depends on the application environment, such as the surface material, roughness, flatness, thermal expansion coefficient, and thermal power distribution within the heat source surface of the heat source and the heat sink. There are three main methods commonly used in the industry: The first method is to sandwich the interface material between two metal plates to form a sandwich structure with a limited thickness, test the overall thermal resistance with a thermal resistance meter, and then place it in various environmental chambers for long-term aging before measuring the overall thermal resistance. This method is completely inconsistent with the actual application scenario and it is difficult to reflect the material aging situation in real situations. The second method is to process a metal block with the same plane size as the heat source, bury a resistance wire inside to generate heat, apply or stick the interface material on its surface, install a water-cooled or air-cooled radiator, and add periodic power changes to simulate the power cycle in actual applications. Although this method imitates the power cycle and heat transfer path of the actual chip, it is completely different from the material, surface structure, and thermal power distribution within the surface of the actual chip, so it cannot completely simulate the actual situation.

[0005] The third method is to use interface materials in actual electronic devices for long-term power cycling. Although it simulates the actual situation, due to the expensive equipment and the design limitations of the equipment itself, in order to save costs, it is impossible to conduct accelerated aging experiments under more stringent conditions (such as higher temperature, lower temperature, higher humidity, etc.), and the test evaluation is not very meaningful. Summary of the invention

[0006] The present application provides a chip simulation heat source and a thermal interface material aging test method thereof, which can solve the problems of low accuracy and high cost of existing thermal interface material aging tests.

[0007] The technical solution of the present application is as follows: A chip simulation heat source, comprising: A supporting substrate layer, wherein a plurality of welding points are formed on the supporting substrate layer, and metal wires corresponding to the welding points are arranged on the supporting substrate layer; A metal heating layer, the metal heating layer is arranged on the surface of the support substrate layer, the metal heating layer is provided with one or more independent heating areas, each of the heating areas is provided with a pin corresponding to the metal wire one by one, and the pin is electrically connected to the welding point through the metal wire; The material simulation layer is arranged on the metal heating layer.

[0008] By adopting the above technical solution, by setting one or more heating zones on the heating layer, different heating zones are selected to be energized according to the actual working conditions of different chips, and the power of the energized heating zones is controlled at the same time, so as to simulate the heating power of the existing chip when working, and ensure the accuracy of subsequent tests.

[0009] In one embodiment of the present application, each group of welding points includes four contacts, and each of the contacts is electrically connected to a programmable power supply.

[0010] In one embodiment of the present application, each of the metal wires includes a current input metal wire, a voltage input metal wire, a current output metal wire and a voltage output metal wire, and the current input metal wire, the voltage input metal wire, the current output metal wire and the voltage output metal wire are electrically connected to the four contacts one by one.

[0011] In one embodiment of the present application, the pin includes an input pin and an output pin, the input pin is electrically connected to the current input metal line and the voltage input metal line, and the output pin is electrically connected to the current output metal line and the voltage output metal line.

[0012] By adopting the above technical solution, the current and voltage of each heating zone are accurately measured by using a programmable power supply, thereby improving the accuracy of thermal power calculation of the heating zone.

[0013] In one embodiment of the present application, the supporting substrate layer is a ceramic substrate component or an epoxy substrate component.

[0014] By adopting the above technical solution and providing a supporting substrate layer of ceramic material, the thermal conductivity of the supporting substrate layer can be effectively improved while ensuring the structural strength.

[0015] In one embodiment of the present application, the thickness D1 of the support substrate layer satisfies: 0.1 mm≤D1≤5 mm.

[0016] In one embodiment of the present application, the thickness D2 of the metal heating layer satisfies: 0.05mm≤D2≤0.5mm.

[0017] By adopting the above technical solution and limiting the thickness of the supporting substrate layer and the metal heating layer, the cost of the device is guaranteed while also ensuring its good thermal conductivity. In one embodiment of the present application, the material simulation layer includes one of a silicon wafer, a quartz wafer, a metal wafer and a ceramic wafer.

[0018] In one embodiment of the present application, the thickness D3 of the material simulation layer satisfies: 0.1 mm≤D3≤3 mm.

[0019] By adopting the above technical solution, by using a material simulation layer with good thermal conductivity and controlling the thickness of the device, the temperature drop can be reduced to improve the accuracy of the measurement.

[0020] A second object of the present invention is to provide an aging test method for a thermal interface material of a chip simulating a heat source.

[0021] In order to achieve the above purpose, the technical solution of this application is as follows: A method for testing aging of a thermal interface material using a chip simulating a heat source, using a chip simulating a heat source to perform an aging test of the thermal interface material, comprising the following steps: Step 1: coating the thermal interface material to be tested on the chip simulation heat source, setting a heat sink and pressing it on the thermal interface material to be tested, and embedding a temperature measuring thermocouple in the contact surface between the heat sink and the thermal interface material to be tested; Step 2: Use a programmable power supply to energize the heating zone at a constant power P1, detect the voltage and current flowing through each heating zone, calculate the first initial temperature C1 of each heating zone using the metal resistance temperature coefficient, and simultaneously record the first initial temperature C2 of the temperature measuring thermocouple, and calculate the first temperature difference A1 between the initial temperature C1 of the heating zone and the initial temperature C2 of the temperature measuring thermocouple; Step 3: Use a programmable power supply to energize the heating zone with analog power P2, detect the voltage and current flowing through each heating zone, calculate the test temperature C3 of each heating zone using the metal resistance temperature coefficient, and record the test temperature C4 of the temperature measuring thermocouple at the same time, and calculate the temperature difference S between the initial temperature C3 of the heating zone and the initial temperature C4 of the temperature measuring thermocouple; The simulated power P2 is a dynamic power whose threshold range is not less than the input power of the chip in the actual working condition; Step 4: loop step 3 n times, respectively calculate and record the temperature differences S1, S2, S3, ... Sn between the test temperature of the heating zone and the test temperature of the temperature measuring thermocouple, and judge whether the chip simulation heat source is aged by judging the changes of the temperature differences S1, S2, S3, ... Sn, until the chip simulation heat source after aging treatment is obtained; Step 5: Use a programmable power supply to energize the chip after the aging treatment obtained in step 4 at a constant power P1 to simulate a heat source, and detect the voltage and current flowing through each heating zone, calculate the second temperature C3 of each heating zone using the metal resistance temperature coefficient, and record the second temperature C4 of the temperature measuring thermocouple at the same time, and calculate the second temperature difference A2 between the second temperature C3 of the heating zone and the second temperature C4 of the temperature measuring thermocouple; Step 6: Compare the second temperature difference A2 obtained in step 5 with the first temperature difference A1 obtained in step 3, and determine the aging resistance of the thermal interface material.

[0022] In summary, the present application includes at least one of the following beneficial technical effects: 1. By setting a chip heat source that is consistent with the chip heating power in actual working conditions, the device can simulate the heating condition of the chip in actual working conditions when testing the aging degree of the thermal conductive section, and thus be more accurate when testing the temperature and thermal resistance on both sides of the thermal conductive interface material.

[0023] 2. By setting up multiple sets of welding points and multiple metal wires, the current or voltage of different metal heating layers inside the chip simulated heat source is measured respectively, thereby improving the accuracy of calculating the temperature of the chip simulated heat source.

[0024] 3. Perform power cycle test by simulating the power of the chip in actual working conditions to age the simulated heat source of the chip, and record the temperature difference on both sides of the simulated heat source of the chip before and after aging. By comparing the temperature difference before and after aging, the aging resistance of the thermal interface material can be quantified. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 is a planar cross-sectional view of a chip simulation heat source provided in the present application; Figure 2 It is a schematic plan view of a metal heating layer of a chip simulating heat source provided in this application; Figure 3 It is a planar cross-sectional view of a thermal interface material aging test of a chip simulating a heat source provided in the present application; Figure 4 This is an experimental data diagram of an aging test of a thermal interface material for a chip simulating a heat source provided in Example 1 of the present application; Figure 5This is an experimental data chart of an aging test of a thermal interface material for a chip simulating a heat source provided in Example 2 of the present application.

[0026] Explanation of the accompanying drawings: 1. Support substrate layer; 11. Welding point; 111. Contact; 12. Metal wire; 121. Current input metal wire; 122. Voltage input metal wire; 123. Current output metal wire; 124. Voltage output metal wire; 2. Metal heating layer; 21. Heating area; 211. Input pin; 212. Output pin; 3. Material simulation layer; 4. Thermal interface material to be tested; 5. Radiator. DETAILED DESCRIPTION

[0027] The following is combined with Figure 1-5 A chip simulation heat source and a thermal interface material aging test method provided in the present application are further described in detail.

[0028] See also Figure 1-2 , is a chip simulation heat source provided in an embodiment of the present application, comprising a supporting substrate layer 1, a metal heating layer 2 and a material simulation layer 3: The support substrate layer 1 is provided with a plurality of welding points 11, and the support substrate layer 1 is provided with metal wires 12 corresponding to the welding points 11 one by one; The metal heating layer 2 is arranged on the surface of the support substrate layer 1, and one or more independent heating areas 21 are arranged on the metal heating layer 2, and each heating area 21 is provided with a pin corresponding to the metal wire 12, and the pin is electrically connected to the welding point 11 through the metal wire 12, wherein the metal heating layer 2 and the metal wire 12 can be copper components, platinum components or nickel-chromium components to ensure their thermal conductivity; The material simulation layer 3 is arranged on the metal heating layer 2, and the supporting substrate layer 1, the metal heating layer 2 and the material simulation layer 3 are bonded by using high temperature resistant epoxy insulating glue, high temperature resistant inorganic insulating glue or solder paste welding.

[0029] In this embodiment, a base may be further provided, and screw holes may be provided on the base, and the supporting substrate layer 1 may be fixed to the base by means of bolts to ensure its placement stability.

[0030] Each group of welding points 11 includes four contacts 111 , and each of the contacts 111 is electrically connected to a programmable power source.

[0031] In this embodiment, the welding point 11 can be a through hole opened on the supporting substrate layer 1, and the programmable power supply welds the solder paste or other welding layer at the end of the power line into the through hole so that it is connected to the pin through the metal wire 12.

[0032] Each of the metal wires 12 includes a current input metal wire 121, a voltage input metal wire 122, a current output metal wire 123 and a voltage output metal wire 124, and the current input metal wire 121, the voltage input metal wire 122, the current output metal wire 123 and the voltage output metal wire 124 are electrically connected to the four contacts 111 one by one.

[0033] The pins include an input pin 211 and an output pin 212. The input pin 211 is electrically connected to the current input metal wire 121 and the voltage input metal wire 122. The output pin 212 is electrically connected to the current output metal wire 123 and the voltage output metal wire 124. When the metal heating layer 2 is electrically connected to the programmable power supply, a four-wire electrical connection method is used to connect the current input metal wire 121 and the voltage input metal wire 122 to the input pin 211 of the heating zone 21, and the current output metal wire 123 and the voltage output metal wire 124 to the output pin 212 of the heating zone 21. A complete heating circuit is formed in conjunction with the programmable power supply. The on / off or power of each heating zone 21 is independently controlled to simulate the heating condition of the chip in actual working conditions, thereby improving the accuracy of the device in testing the chip temperature.

[0034] In the embodiment, the technical means of using a programmable power supply to specifically control power output is an existing technical means, so it will not be described again.

[0035] The supporting substrate layer 1 is a ceramic substrate component or an epoxy substrate component.

[0036] In this embodiment, the support substrate layer 1 can be one of a FR4 epoxy composite board, an aluminum oxide board, a boron nitride board and an aluminum nitride board.

[0037] The thickness D1 of the support substrate layer 1 satisfies: 0.1 mm≤D1≤5 mm.

[0038] The thickness D2 of the metal heating layer 2 satisfies: 0.05mm≤D2≤0.5mm.

[0039] The material simulation layer 3 includes one of a silicon wafer, a quartz wafer, a metal wafer and a ceramic wafer, wherein the ceramic wafer can be made of one of aluminum oxide, boron nitride and aluminum nitride.

[0040] The thickness D3 of the material simulation layer 3 satisfies: 0.1 mm≤D3≤3 mm.

[0041] See also Figure 3-5 The second object of the present invention is to provide an aging test method for thermal interface materials of a chip simulating a heat source.

[0042] In order to achieve the above purpose, the technical solution of this application is as follows: A method for testing aging of a thermal interface material using a chip simulating a heat source, using a chip simulating a heat source to perform an aging test of the thermal interface material, comprising the following steps: Step 1: coating the thermal interface material 4 to be tested on the chip simulation heat source, setting a heat sink 5 and pressing it on the thermal interface material 4 to be tested, and embedding a temperature measuring thermocouple in the contact surface between the heat sink 5 and the thermal interface material 4 to be tested, wherein the heat sink 5 can be an air-cooled heat sink 5 or a water-cooled heat sink 5; Step 2: Use a programmable power supply to energize the heating zone 21 at a constant power P1, detect the voltage and current flowing through each heating zone 21, calculate the first initial temperature C1 of each heating zone 21 using the metal resistance temperature coefficient, and simultaneously record the first initial temperature C2 of the temperature measuring thermocouple, and calculate the first temperature difference A1 between the initial temperature C1 of the heating zone 21 and the initial temperature C2 of the temperature measuring thermocouple; Step 3: Use a programmable power supply to energize the heating zone 21 with analog power P2, detect the voltage and current flowing through each heating zone 21, calculate the test temperature C3 of each heating zone 21 using the metal resistance temperature coefficient, and record the test temperature C4 of the temperature measuring thermocouple at the same time, and calculate the temperature difference S between the initial temperature C3 of the heating zone 21 and the initial temperature C4 of the temperature measuring thermocouple; The simulated power P2 is a dynamic power whose threshold range is not less than the input power of the chip in the actual working condition; Step 4: looping step 3 n times, respectively calculating and recording the temperature differences S1, S2, S3, ... Sn between the test temperature of the heating zone 21 and the test temperature of the temperature measuring thermocouple, and judging whether the chip simulation heat source is aged by judging the changes of the temperature differences S1, S2, S3, ... Sn, until the chip simulation heat source after aging treatment is obtained; Step 5: Use a programmable power supply to energize the chip after the aging treatment obtained in step 4 at a constant power P1 to simulate a heat source, and detect the voltage and current flowing through each heating zone 21, calculate the second temperature C3 of each heating zone 21 using the metal resistance temperature coefficient, and record the second temperature C4 of the temperature measuring thermocouple at the same time, and calculate the second temperature difference A2 between the second temperature C3 of the heating zone 21 and the second temperature C4 of the temperature measuring thermocouple; Step 6: Compare the second temperature difference A2 obtained in step 5 with the first temperature difference A1 obtained in step 3, and determine the aging resistance of the thermal interface material.

[0043] In Example 1 of the present application: a 1mm thick FR4 epoxy board is selected as the supporting base board, and a 0.05mm thick nickel-chromium sheet is covered on the FR4 epoxy board as the metal heating layer 2, and the circuit of the heating area 21 is etched on the nickel-chromium sheet, which is divided into 8 heating areas 21, and a 0.8mm thick material simulation layer 3 is selected. The material simulation layer 3 is a silicon wafer with a size of 20mmX10mm, and the three layers are bonded together using a high-temperature resistant inorganic glue to form a chip simulation heat source; A thermal conductive silicone grease is fixedly arranged on the chip simulation heat source as the thermal conductive interface material to be tested 4; An air-cooled heat sink 5 is pressed onto the thermal grease, and a thermocouple is buried between the air-cooled heat sink 5 and the thermal grease; The four heating zones 21 are heated continuously for 30 minutes at a constant power of 1, wherein the constant power of 1 is 5 W. After reaching a steady state, the temperatures of the eight heating zones 21 and the temperature of the thermocouple in the water-cooling radiator 5 are calculated and recorded.

[0044] Then, power cycle is performed on four heating zones 21 at simulated power 1, with a cycle period of 120 seconds, and temperature changes during the process are recorded, wherein the power threshold range of the simulated power is: 0-10W; The other four heating zones 21 are subjected to power cycling with simulated power 2, the cycle period is 60 seconds, and the temperature changes during the process are recorded, wherein the power threshold range of simulated power 2 is: 0-4W; After 72 hours, test the temperature of each heating zone 21 and the thermocouple temperature in the water radiator 5 according to step 4. The specific data are as shown in the attached manual. Figure 4 shown.

[0045] In Example 2 of the present application: a 1mm thick aluminum nitride plate is selected as the supporting base plate, and a 0.2mm thick copper foil is covered on the aluminum nitride plate as the metal heating layer 2, and the circuit of the heating area 21 is etched on the copper foil, which is divided into 4 heating areas 21, and a 0.8mm thick material simulation layer 3 is selected. The material simulation layer 3 is an aluminum nitride sheet with a size of 20mmX20mm. The three layers are bonded together using a high-temperature resistant inorganic glue to form a chip simulation heat source; A thermal conductive silicone grease is fixedly arranged on the chip simulation heat source as the thermal conductive interface material to be tested 4; A water-cooled radiator 5 is pressed onto the thermal grease, and a thermocouple is buried between the water-cooled radiator 5 and the thermal grease; The four heating zones 21 are heated continuously for 30 minutes at a constant power of 2, wherein the constant power of 2 is 50 W. After reaching a steady state, the temperatures of the four heating zones 21 and the temperature of the thermocouple in the water-cooling radiator 5 are calculated and recorded.

[0046] Then, power cycling is performed on the four areas with simulated power three, with a cycle period of 30 seconds, and the temperature changes in the process are recorded, wherein the power threshold range of simulated power three is: 0-50W.

[0047] After 72 hours, test the temperature of each heating zone 21 and the thermocouple temperature in the water radiator 5 according to step 4. The specific data are as shown in the attached manual. Figure 5 shown.

[0048] In summary, by using the present device and the testing method for the thermal interface material 4 to be tested to perform aging tests, the temperature difference of the thermal interface material 4 to be tested under different powers can be accurately tested, and the aging degree of the thermal interface material 4 to be tested can be quantified by judging the values ​​of each temperature difference. After the thermal interface material 4 to be tested is aged, the temperature difference on both sides of the thermal interface material 4 to be tested after aging is compared with the temperature difference on both sides before aging, thereby judging the aging resistance of the thermal cross-sectional material to be tested.

[0049] The above are all preferred embodiments of the present application, and the protection scope of the present application is not limited thereto. Therefore, any equivalent changes made according to the structure, shape, and principle of the present application should be included in the protection scope of the present application.

Claims

1. A chip simulated heat source, characterized in that: include: A supporting substrate layer (1), wherein a plurality of welding points (11) are provided on the supporting substrate layer (1), and metal wires (12) corresponding one to one to the welding points (11) are provided on the supporting substrate layer (1); A metal heating layer (2), the metal heating layer (2) being arranged on the surface of the support substrate layer (1), the metal heating layer (2) being provided with one or more mutually independent heating areas (21), each of the heating areas (21) being provided with a pin corresponding to the metal wire (12) one by one, the pin being electrically connected to the welding point (11) via the metal wire (12); A material simulation layer (3), wherein the material simulation layer (3) is arranged on the metal heating layer (2).

2. A chip simulation heat source according to claim 1, characterized in that: Each group of welding points (11) includes four contacts (111), and each of the contacts (111) is electrically connected to a programmable power source.

3. A chip simulation heat source according to claim 2, characterized in that: Each of the metal wires (12) comprises a current input metal wire (121), a voltage input metal wire (122), a current output metal wire (123) and a voltage output metal wire (124); the current input metal wire (121), the voltage input metal wire (122), the current output metal wire (123) and the voltage output metal wire (124) are electrically connected to the four contacts (111) in a one-to-one correspondence.

4. A chip simulation heat source according to claim 3, characterized in that: The pins include an input pin (211) and an output pin (212); the input pin (211) is electrically connected to a current input metal wire (121) and a voltage input metal wire (122); and the output pin (212) is electrically connected to a current output metal wire (123) and a voltage output metal wire (124).

5. The chip simulation heat source according to claim 1, characterized in that: The supporting substrate layer (1) is a ceramic substrate component or an epoxy substrate component.

6. The chip simulation heat source according to claim 1, characterized in that: The thickness D1 of the supporting substrate layer (1) satisfies: 0.1 mm≤D1≤5 mm.

7. The chip simulation heat source according to claim 1, characterized in that: The thickness D2 of the metal heating layer (2) satisfies: 0.05mm≤D2≤0.5mm.

8. The chip simulation heat source according to claim 1, characterized in that: The material simulation layer (3) comprises one of a silicon wafer, a quartz wafer, a metal wafer and a ceramic wafer.

9. The chip simulation heat source according to claim 1, characterized in that: The thickness D3 of the material simulation layer (3) satisfies: 0.1 mm≤D3≤3 mm.

10. A method for testing aging of thermal interface materials of a chip simulating heat source, characterized in that: Using a chip simulation heat source as described in any one of claims 1 to 9 to perform an aging test on a thermal interface material, The steps include: Step 1: coating a thermal interface material (4) to be tested on a chip simulating a heat source, providing a heat sink (5), and pressing the heat sink (5) onto the thermal interface material (4) to be tested, and embedding a temperature measuring thermocouple in the contact surface between the heat sink (5) and the thermal interface material (4) to be tested; Step 2: using a programmable power supply to energize the heating zone (21) at a constant power P1, detecting the voltage and current flowing through each heating zone (21), calculating the first initial temperature C1 of each heating zone (21) using the metal resistance temperature coefficient, and simultaneously recording the first initial temperature C2 of the temperature measuring thermocouple, and calculating the first temperature difference A1 between the initial temperature C1 of the heating zone (21) and the initial temperature C2 of the temperature measuring thermocouple; Step 3: using a programmable power supply to energize the heating zone (21) with analog power P2, detecting the voltage and current flowing through each heating zone (21), calculating the test temperature C3 of each heating zone (21) using the metal resistance temperature coefficient, and simultaneously recording the test temperature C4 of the temperature measuring thermocouple, and calculating the temperature difference S between the initial temperature C3 of the heating zone (21) and the initial temperature C4 of the temperature measuring thermocouple; The simulated power P2 is a dynamic power whose threshold range is not less than the input power of the chip in the actual working condition; Step 4: looping step 3 n times, respectively calculating and recording the temperature differences S1, S2, S3, ... Sn between the test temperature of the heating zone (21) and the test temperature of the temperature measuring thermocouple, and judging whether the chip simulation heat source is aged by judging the changes of the temperature differences S1, S2, S3, ... Sn, until the chip simulation heat source after aging treatment is obtained; Step 5: using a programmable power supply to energize the chip after the aging treatment obtained in step 4 at a constant power P1 to simulate a heat source, and detecting the voltage and current flowing through each heating zone (21), calculating the second temperature C3 of each heating zone (21) using the metal resistance temperature coefficient, and recording the second temperature C4 of the temperature measuring thermocouple at the same time, and calculating the second temperature difference A2 between the second temperature C3 of the heating zone (21) and the second temperature C4 of the temperature measuring thermocouple; Step 6: Compare the second temperature difference A2 obtained in step 5 with the first temperature difference A1 obtained in step 3, and determine the aging resistance of the thermal interface material.

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