Power-on reset circuit and chip

Abstract

The invention discloses a power-on reset circuit and a chip, the power-on reset circuit comprises a voltage detection module, a comparator and a time delay module, the voltage detection module is set to output a first voltage and a second voltage according to a power supply voltage of a power supply end of the power-on reset circuit, and when the power supply voltage is smaller than a voltage threshold value, the comparator outputs the first voltage and the second voltage. The first voltage is smaller than the second voltage under the condition that the power supply voltage is larger than the voltage threshold value, and the first voltage is larger than the second voltage under the condition that the power supply voltage is larger than the voltage threshold value; the comparator is set to compare the first voltage with the second voltage and output a first signal according to a comparison result; the time delay module is set to carry out time delay processing on the first signal to obtain a reset signal.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and more specifically, to a power-on reset circuit and a chip. Background Art

[0002] The power-on reset (POR) circuit is used to detect the power-on of the chip. When the power-on reset circuit detects that the chip power supply is greater than the set threshold, it generates an internal reset signal. When the digital circuit detects the reset signal, it enables each analog circuit in turn to ensure that the analog circuit is in a normal initial state and that the values ​​of various registers in the digital part are the set initial values.

[0003] The power-on reset circuit architecture used in the chip should satisfy the requirement that when the power supply voltage rises to the threshold voltage at any slope, the power-on reset circuit can correctly generate a reset signal. The power-on reset circuit needs to solve both the fast power-on and slow power-on situations of the chip. Considering the slow power-on situation, a threshold voltage needs to be set. When the comparator detects that the power supply voltage rises to the threshold voltage, the power-on reset circuit outputs the correct reset signal. Considering the fast power-on situation, during the period from when the power supply voltage rises quickly to the threshold voltage (including above the threshold voltage) until the power supply voltage stabilizes, the power-on reset circuit will not generate an erroneous reset signal due to power supply noise, circuit response speed, internal reference voltage establishment speed, etc. Therefore, the power-on reset circuit requires a "delay" to shield these factors that cause the generation of erroneous reset signals.

[0004] Most of the existing power-on reset circuits generate reset signals based on comparison with a reference voltage or a MOS tube threshold voltage. The process, voltage, and temperature seriously affect the working state of the circuit, and it is impossible to simultaneously meet the requirements of fast and slow power-on of the chip. Summary of the invention

[0005] An object of an embodiment of the present invention is to provide a power-on reset circuit and a chip.

[0006] According to a first aspect of the present disclosure, a power-on reset circuit is provided, comprising a voltage detection module, a comparator and a delay module.

[0007] The voltage detection module is configured to output a first voltage and a second voltage according to a power supply voltage at a power supply terminal of the power-on reset circuit, wherein when the power supply voltage is less than a voltage threshold, the first voltage is less than the second voltage, and when the power supply voltage is greater than the voltage threshold, the first voltage is greater than the second voltage;

[0008] The comparator is configured to compare the first voltage and the second voltage, and output a first signal according to the comparison result;

[0009] The delay module is configured to perform delay processing on the first signal to obtain a reset signal.

[0010] Optionally, the voltage detection module includes a first output end, a second output end, a first resistor, a second resistor, a third resistor, a fourth resistor, a first transistor and a second transistor, the first output end is used to output the first voltage, the second output end is used to output the second voltage, the first resistor is connected between the power supply end and the first output end, the second resistor is connected between the power supply end and the second output end, the third resistor is connected between the emitter of the second transistor and the second output end, the fourth resistor is connected between the second output end and the ground end of the power-on reset circuit, the emitter of the first transistor is connected to the first output end, and the collector of the first transistor, the base of the first transistor, the base of the second transistor, and the collector of the second transistor are all connected to the ground end.

[0011] Optionally, the voltage detection module further includes a fifth resistor, wherein the fifth resistor is connected between the first resistor and the power supply end, and between the second resistor and the power supply end.

[0012] Optionally, the resistance value of the first resistor, the resistance value of the second resistor, the resistance value of the third resistor, the resistance value of the fourth resistor, the resistance value of the fifth resistor, and the area ratio of the second transistor to the first transistor are determined according to the voltage threshold.

[0013] Optionally, the first output terminal is connected to the inverting input terminal of the comparator, the second output terminal is connected to the non-inverting input terminal of the comparator, and the output terminal of the comparator is connected to the delay module.

[0014] Optionally, the power-on reset circuit further includes a shaping circuit, and the shaping circuit is configured to perform shaping processing on the reset signal.

[0015] Optionally, the delay circuit includes a MOS resistor, a MOS capacitor and an NMOS tube, the MOS resistor is connected between the drain of the NMOS and the power supply terminal, the MOS capacitor is connected between the drain of the NMOS tube and the ground terminal of the power-on reset circuit, the source of the NMOS tube is connected to the ground terminal, and the gate of the NMOS tube is connected to the comparator.

[0016] Optionally, the power-on reset circuit further includes an inverter, and the inverter is configured to invert the reset signal.

[0017] Optionally, the inverter and the shaping circuit are provided by a Schmitt trigger.

[0018] According to a second aspect of the present disclosure, a chip is provided, comprising the power-on reset circuit as described in the first aspect of the present disclosure.

[0019] Through the embodiments of the present disclosure, the voltage detection module generates a first voltage and a second voltage according to the comparison result between the power supply voltage at the power supply end and the voltage threshold; the comparator then outputs a first signal according to the comparison result between the first voltage and the second voltage; the delay module then performs delay processing on the first signal to obtain a reset signal, and can output a correct reset signal after a delay period after the power supply voltage rises to the voltage threshold. Moreover, the power-on reset circuit can simultaneously meet the requirements of fast power-on and slow power-on of the chip.

[0020] Further features and advantages of the present invention will become apparent from the following detailed description of exemplary embodiments of the present invention with reference to the attached drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0022] Figure 1 is a block diagram of a power-on reset circuit provided according to an embodiment of the present disclosure;

[0023] Figure 2 is a schematic diagram showing that the output of a voltage detection module varies with the power supply voltage according to an embodiment of the present disclosure;

[0024] Figure 3 It is a circuit schematic diagram of a power-on reset circuit provided according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that the relative arrangement of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present invention unless otherwise specifically stated.

[0026] The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

[0027] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered as part of the specification.

[0028] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0029] It should be noted that like reference numerals and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it need not be further discussed in subsequent figures.

[0030] This embodiment provides a power-on reset circuit. Figure 1 As shown, the power-on reset circuit 1000 may include a voltage detection module 1100 , a comparator 1200 and a delay module 1300 .

[0031] The voltage detection module 1100 is configured to output a first voltage and a second voltage according to a power supply voltage VDD of a power supply terminal IN1 of the power-on reset circuit 1000. When the power supply voltage VDD is less than a voltage threshold Vth, the first voltage VN is less than the second voltage VP. When the power supply voltage VDD is greater than the voltage threshold Vth, the first voltage VN is greater than the second voltage VP. The variation of the first voltage VN, the second voltage VP and the power supply voltage VDD can be as follows: Figure 2 shown.

[0032] like Figure 2 As shown, as the power supply voltage VDD increases, the second voltage VP is first greater than the first voltage VN and then less than the first voltage VN. When the power supply voltage VDD is equal to the voltage threshold Vth, the first voltage VN is equal to the second voltage VP.

[0033] The comparator 1200 is configured to compare the first voltage VN and the second voltage VP, and output a first signal according to the comparison result.

[0034] The delay module 1300 is configured to perform delay processing on the first signal to obtain a reset signal.

[0035] In this embodiment, there is no need to set a bandgap reference circuit in the power-on reset circuit, which can reduce the power consumption and area of ​​the power-on reset circuit, and avoid the problem of slow reference voltage establishment of the bandgap reference circuit and resulting in generation of an erroneous reset signal.

[0036] Furthermore, the delay module can prevent the power supply voltage from jittering when the chip is about to be powered on and thus generating an erroneous reset signal.

[0037] Through the embodiments of the present disclosure, the voltage detection module generates a first voltage and a second voltage according to the comparison result between the power supply voltage at the power supply end and the voltage threshold; the comparator then outputs a first signal according to the comparison result between the first voltage and the second voltage; the delay module then performs delay processing on the first signal to obtain a reset signal, and can output a correct reset signal after a delay period after the power supply voltage rises to the voltage threshold. Moreover, the power-on reset circuit can simultaneously meet the requirements of fast power-on and slow power-on of the chip.

[0038] In one embodiment of the present disclosure, the voltage detection module may be designed based on a low voltage bandgap reference principle.

[0039] Specifically, Figure 3 As shown, the voltage detection module 1100 may include a first output terminal out1, a second output terminal out2, a first resistor 1110, a second resistor 1120, a third resistor 1130, a fourth resistor 1140, a first transistor Q1 and a second transistor Q2, the first output terminal out1 is used to output a first voltage VN, the second output terminal out2 is used to output a second voltage VP, the first resistor 1110 is connected between the power supply terminal IN1 and the first output terminal out1, the second resistor 1120 is connected between the power supply terminal IN1 and the second output terminal out2, the third resistor 1130 is connected between the emitter of the second transistor Q2 and the second output terminal out2, the fourth resistor 1140 is connected between the second output terminal out2 and the ground terminal GND of the power-on reset circuit 1000, the emitter of the first transistor Q1 is connected to the first output terminal out1, and the collector of the first transistor Q1, the base of the first transistor Q1, the base of the second transistor W2, and the collector of the second transistor Q2 are all connected to the ground terminal GND.

[0040] In this embodiment, the resistance values ​​of the first resistor 1110 and the second resistor 1120 are equal.

[0041] In one embodiment of the present disclosure, Figure 3 As shown, the voltage detection module 1100 further includes a fifth resistor 1150 , which is connected between the first resistor 1110 and the power supply terminal IN1 , and between the second resistor 1120 and the power supply terminal IN1 .

[0042] Through the voltage detection module of this embodiment, the difference between the first voltage VN and the second voltage VP can be appropriately increased to avoid the comparator from erroneously flipping when the chip is powered on, which causes the power-on reset circuit to output an erroneous reset signal. Moreover, the voltage detection module of this embodiment can cope with the deviation and serious mismatch between the first voltage VN and the second voltage VP caused by extreme processes, voltages, and temperatures.

[0043] In one embodiment of the present disclosure, the resistance of the first resistor 1110, the resistance of the second resistor 1120, the resistance of the third resistor 1130, the resistance of the fourth resistor 1140, the resistance of the fifth resistor 1150, and the area ratio of the second transistor Q2 to the first transistor Q1 are determined according to a voltage threshold.

[0044] Specifically, the relationship between the resistance of the first resistor 1110, the resistance of the second resistor 1120, the resistance of the third resistor 1130, the resistance of the fourth resistor 1140, the resistance of the fifth resistor 1150, the area ratio of the second transistor Q2 to the first transistor Q1, and the voltage threshold can be expressed as:

[0045]

[0046] Among them, Vth represents the voltage threshold, R1 represents the resistance of the first resistor 1110 and the second resistor 1120, R0 represents the resistance of the fifth resistor 1150, R2 represents the resistance of the third resistor 1130, R3 represents the resistance of the fourth resistor 1140, VT represents the turn-on voltage of the bipolar transistor, Vbe0 represents the base-emitter voltage of the first transistor Q1, and N represents the area ratio of the second transistor Q2 to the first transistor Q1.

[0047] It can be known from the low-voltage bandgap reference principle that by reasonably adjusting any one or more of the resistance value of the first resistor 1110, the resistance value of the second resistor 1120, the resistance value of the third resistor 1130, the resistance value of the fourth resistor 1140, the resistance value of the fifth resistor 1150, and the area ratio of the second transistor Q2 to the first transistor Q1, the voltage threshold Vth can be made a value independent of temperature.

[0048] In one embodiment of the present disclosure, Figure 3 As shown, the first output terminal out1 is connected to the inverting input terminal of the comparator 1200 , the second output terminal out2 is connected to the non-inverting input terminal of the comparator 1200 , and the output terminal of the comparator 1200 is connected to the delay module 1300 .

[0049] In this embodiment, when the power supply voltage VDD is less than the voltage threshold Vth, the first voltage VN output by the voltage detection module 1100 is less than the second voltage VP, and the comparator 1200 outputs a high level. When the power supply voltage VDD rises to be greater than the voltage threshold Vth, the first voltage VN output by the voltage detection module 1100 is greater than the second voltage VP, and the comparator 1200 output flips to a low level.

[0050] In one embodiment, the delay module 1300 may output a high level when the comparator 1200 outputs a first signal of a high level, and output a low level after a delay when the comparator 1200 outputs the first signal flipped to a low level, thereby realizing delayed processing of the first signal.

[0051] In one embodiment of the present disclosure, the delay module 1300 may be composed of a resistor and a capacitor. Figure 3As shown, the delay circuit 1300 includes a MOS resistor 1310, a MOS capacitor 1320 and an NMOS tube 1330, the MOS resistor 1310 is connected between the drain of the NMOS tube 1330 and the power supply terminal IN1, the MOS capacitor 1320 is connected between the drain of the NMOS tube 1330 and the ground terminal GND of the power-on reset circuit, the source of the NMOS tube 1330 is connected to the ground terminal GND, and the gate of the NMOS tube 1330 is connected to the comparator 1200.

[0052] In this embodiment, a delay module composed of a MOS resistor and a MOS capacitor is used to reduce the area of ​​the power-on reset circuit.

[0053] In this embodiment, when the power supply voltage VDD is less than the voltage threshold Vth, the first voltage VN output by the voltage detection module 1100 is less than the second voltage VP, the comparator 1200 outputs a high level, the NMOS tube 1330 is turned on, and the delay circuit 1300 outputs the voltage of the ground terminal GND. When the power supply voltage VDD rises to a level greater than the voltage threshold Vth, the first voltage VN output by the voltage detection module 1100 is greater than the second voltage VP, the comparator 1200 output flips to a low level, the NMOS tube 1330 is turned off, the power supply voltage VDD charges the MOS capacitor through the MOS resistor, and after a period of time, the output of the delay circuit 1300 gradually increases to the power supply voltage VDD.

[0054] In some embodiments, since the reset signal is usually at a low level, the power-on reset circuit 1000 further includes an inverter 1400 , and the inverter 1400 is configured to invert the reset signal.

[0055] Through this embodiment, if the power supply voltage VDD fluctuates below the voltage threshold within the delay time, this will cause the first voltage VN output by the voltage detection module 1100 to be less than the second voltage VP, the comparator 1200 outputs a high level, the NMOS tube 1330 is turned on, the delay circuit 1300 outputs a voltage that quickly drops to the ground terminal GND, and the output of the inverter 1400 remains at a high level, ensuring that the power-on reset circuit will not generate an erroneous reset signal due to power supply voltage fluctuations.

[0056] In some embodiments, Figure 3 As shown, the power-on reset circuit 1000 further includes a shaping circuit 1500, and the shaping circuit 1500 is configured to perform shaping processing on the reset signal.

[0057] Through the shaping circuit 1500 of this embodiment, the waveform output by the delay module 1300 can be shaped into a square wave.

[0058] In this embodiment, the output end of the delay module 1300 is connected to the input end of the shaping circuit 1500 , and the output end of the shaping circuit 1500 is connected to the input end of the inverter 1400 .

[0059] In one embodiment of the present disclosure, the inverter 1400 and the shaping circuit 1500 are provided by a Schmitt trigger.

[0060] This embodiment provides a chip, which may include the power-on reset circuit described in the above embodiment.

[0061] The above embodiments mainly focus on describing the differences from other embodiments, but it should be clear to those skilled in the art that the above embodiments can be used alone or in combination with each other as needed.

[0062] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each embodiment focuses on the differences from other embodiments, but it should be clear to those skilled in the art that the above embodiments can be used alone or in combination with each other as needed. In addition, for the device embodiment, since it corresponds to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the description of the corresponding part of the method embodiment. The system embodiment described above is merely illustrative, and the modules described as separate components may or may not be physically separated.

[0063] The present invention may be an apparatus, a method and / or a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for causing a processor to implement various aspects of the present invention.

[0064] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. A computer-readable storage medium may be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples of computer-readable storage media (a non-exhaustive list) include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical compression device, such as a punch card or a raised structure in a groove on which instructions are stored, and any suitable combination of the foregoing. As used herein, a computer-readable storage medium is not to be interpreted as a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., a light pulse through a fiber optic cable), or an electrical signal transmitted through a wire.

[0065] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0066] The computer program instructions for performing the operation of the present invention may be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, including object-oriented programming languages, such as Smalltalk, C++, etc., and conventional procedural programming languages, such as "C" language or similar programming languages. Computer-readable program instructions may be executed entirely on a user's computer, partially on a user's computer, as an independent software package, partially on a user's computer, partially on a remote computer, or entirely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., using an Internet service provider to connect via the Internet). In some embodiments, an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), may be personalized by utilizing the state information of the computer-readable program instructions, and the electronic circuit may execute the computer-readable program instructions, thereby realizing various aspects of the present invention.

[0067] Various aspects of the present invention are described herein with reference to the flow charts and / or block diagrams of the methods, devices (systems) and computer program products according to embodiments of the present invention. It should be understood that each box of the flow chart and / or block diagram and the combination of each box in the flow chart and / or block diagram can be implemented by computer-readable program instructions.

[0068] These computer-readable program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processor of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0069] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0070] The flow charts and block diagrams in the accompanying drawings show the possible architecture, functions and operations of the systems, methods and computer program products according to multiple embodiments of the present invention. In this regard, each box in the flow chart or block diagram can represent a part of a module, a program segment or an instruction, and a part of the module, a program segment or an instruction contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram and / or flow chart, and the combination of the boxes in the block diagram and / or flow chart can be implemented by a dedicated hardware-based system that performs the specified function or action, or can be implemented by a combination of dedicated hardware and computer instructions. It is well known to those skilled in the art that it is equivalent to implement it by hardware, implement it by software, and implement it by combining software and hardware.

[0071] Embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements to the technology in the marketplace, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein. The scope of the present invention is defined by the appended claims.

Claims

1. A power-on reset circuit, characterized in that: Including voltage detection module, comparator and delay module, The voltage detection module is configured to output a first voltage and a second voltage according to a power supply voltage at a power supply terminal of the power-on reset circuit, wherein when the power supply voltage is less than a voltage threshold, the first voltage is less than the second voltage, and when the power supply voltage is greater than the voltage threshold, the first voltage is greater than the second voltage; The comparator is configured to compare the first voltage and the second voltage, and output a first signal according to the comparison result; The delay module is configured to perform delay processing on the first signal to obtain a reset signal.

2. The power-on reset circuit according to claim 1, characterized in that: The voltage detection module includes a first output end, a second output end, a first resistor, a second resistor, a third resistor, a fourth resistor, a first triode and a second triode. The first output end is used to output the first voltage, and the second output end is used to output the second voltage. The first resistor is connected between the power supply end and the first output end, the second resistor is connected between the power supply end and the second output end, the third resistor is connected between the emitter of the second triode and the second output end, the fourth resistor is connected between the second output end and the ground end of the power-on reset circuit, the emitter of the first triode is connected to the first output end, and the collector of the first triode, the base of the first triode, the base of the second triode, and the collector of the second triode are all connected to the ground end.

3. The power-on reset circuit according to claim 2, characterized in that: The voltage detection module further includes a fifth resistor, which is connected between the first resistor and the power supply terminal and between the second resistor and the power supply terminal.

4. The power-on reset circuit according to claim 3, characterized in that: The resistance value of the first resistor, the resistance value of the second resistor, the resistance value of the third resistor, the resistance value of the fourth resistor, the resistance value of the fifth resistor, and the area ratio of the second transistor to the first transistor are determined according to the voltage threshold.

5. The power-on reset circuit according to claim 2, characterized in that: The first output end is connected to the inverting input end of the comparator, the second output end is connected to the non-inverting input end of the comparator, and the output end of the comparator is connected to the delay module.

6. The power-on reset circuit according to claim 1, characterized in that: The power-on reset circuit further includes a shaping circuit, and the shaping circuit is configured to perform shaping processing on the reset signal.

7. The power-on reset circuit according to claim 6, characterized in that: The delay circuit includes a MOS resistor, a MOS capacitor and an NMOS tube, the MOS resistor is connected between the drain of the NMOS and the power supply terminal, the MOS capacitor is connected between the drain of the NMOS tube and the ground terminal of the power-on reset circuit, the source of the NMOS tube is connected to the ground terminal, and the gate of the NMOS tube is connected to the comparator.

8. The power-on reset circuit according to claim 7, characterized in that: The power-on reset circuit further includes an inverter, and the inverter is configured to invert the reset signal.

9. The power-on reset circuit according to claim 8, characterized in that: The inverter and the shaping circuit are provided by a Schmitt trigger.

10. A chip, characterized in that: The method comprises a power-on reset circuit as claimed in any one of claims 1 to 9.

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