Random number generation method and true random number generator

Abstract

The embodiment of the invention provides a random number generation method and a true random number generator, the method is applied to the true random number generator, and the true random number generator comprises an entropy source module, an entropy extraction sampling module and a post-processing module; the method comprises the following steps: generating logic high and low levels by using a first ring oscillator in the entropy source module; respectively inputting the logic high and low levels generated by each order of ring oscillator into a first input end of an exclusive-OR gate of a second ring oscillator in the entropy source module for signal processing to obtain an entropy source signal; sampling the entropy source signal by using the entropy extraction sampling module to obtain an initial random sequence; and eliminating the bias and correlation of the initial random sequence by using the post-processing module to obtain a target random sequence. According to the embodiment of the invention, the randomness of the random number is improved, the structure is simple, excessive resources do not need to be occupied, the frequency of the oscillator does not need to be changed by a programmable delay line, and the universality is high.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular to a random number generation method and a true random number generator. Background Art

[0002] Random number generators are an important part of modern cryptography, communication and security applications. High-quality random numbers are crucial to cryptography, simulation, secure communication and other applications. However, the traditional ring oscillator-based structure has problems such as poor randomness, excessive resource occupation and poor versatility. Therefore, it is necessary to propose a new random number generation structure to overcome the existing shortcomings and provide a reliable, stable and universal true random number generation solution. Summary of the invention

[0003] The embodiments of the present invention provide a random number generation method and a true random number generator, which can solve the problems of poor randomness, excessive resource occupation and poor versatility of the random number generation structure in the related art.

[0004] In order to solve the above problem, an embodiment of the present invention discloses a random number generation method, which is applied to a true random number generator, wherein the true random number generator includes an entropy source module, an entropy extraction sampling module and a post-processing module; the method includes:

[0005] The first ring oscillator in the entropy source module is used to generate logic high and low levels; the first ring oscillator includes at least two-stage ring oscillators, and the output end of each stage ring oscillator is connected to the input end of the current stage;

[0006] The logic high and low levels generated by each order ring oscillator are respectively input to the first input end of the XOR gate of the second ring oscillator in the entropy source module for signal processing to obtain an entropy source signal; the second ring oscillator includes N XOR gates, the second input end of the first XOR gate in the second ring oscillator is connected to the output end of the second ring oscillator, and except for the first XOR gate, the output end of the previous XOR gate is connected to the second input end of the next XOR gate; N is an odd number greater than or equal to 3;

[0007] The entropy source signal is sampled by the entropy extraction sampling module to obtain an initial random sequence;

[0008] The post-processing module is used to eliminate the bias and correlation of the initial random sequence to obtain a target random sequence.

[0009] Optionally, the second ring oscillator further includes M inverters, the M inverters are cascaded in sequence, and M is an odd number greater than or equal to 3;

[0010] The second input terminal of the first XOR gate in the second ring oscillator is connected to the output terminal of the second ring oscillator, comprising:

[0011] The output end of the last inverter in the second ring oscillator is connected to the second input end of the first XOR gate in the second ring oscillator, and the input end of the first inverter in the second ring oscillator is connected to the output end of the second ring oscillator.

[0012] Optionally, in the first ring oscillators, each order of the ring oscillators includes at least two cascaded inverters, and the number of inverters included in each order of the ring oscillator is prime to each other.

[0013] Optionally, the entropy extraction sampling module includes a D-type trigger; and the step of sampling the entropy source signal using the entropy extraction sampling module to obtain an initial random sequence includes:

[0014] Inputting the entropy source signal to the input terminal of the D-type flip-flop, and inputting the sampling clock signal to the clock input terminal of the D-type flip-flop;

[0015] When the rising edge of the sampling clock signal arrives, the D-type flip-flop is used to capture and latch the current state of the entropy source signal, so as to obtain an initial random sequence through continuous sampling; the initial random sequence is a random digital signal containing the randomness of the entropy source signal.

[0016] Optionally, the post-processing module includes a linear feedback shift register; and using the post-processing module to eliminate the bias and correlation of the initial random sequence to obtain a target random sequence includes:

[0017] The linear feedback shifter is used to perform shift and feedback operations on the initial random sequence to obtain a target random sequence.

[0018] On the other hand, an embodiment of the present invention discloses a true random number generator, which includes an entropy source module, an entropy extraction sampling module and a post-processing module connected in series in sequence;

[0019] The entropy source module includes a first ring oscillator and a second ring oscillator;

[0020] The first ring oscillator comprises at least two stages of ring oscillators, and the output end of each stage of the ring oscillator is connected to the input end of the current stage;

[0021] The second ring oscillator comprises N XOR gates, a second input end of a first XOR gate is connected to an output end of the second ring oscillator, and except for the first XOR gate, an output end of a previous XOR gate is connected to a second input end of a subsequent XOR gate; N is an odd number greater than or equal to 3;

[0022] The output end of each order ring oscillator of the first ring oscillator is respectively connected to the first input end of different XOR gates in the second ring oscillator.

[0023] Optionally, the second ring oscillator further includes M inverters, the M inverters are cascaded in sequence, and M is an odd number greater than or equal to 3;

[0024] The output end of the last inverter in the second ring oscillator is connected to the second input end of the first XOR gate in the second ring oscillator, and the input end of the first inverter in the second ring oscillator is connected to the output end of the second ring oscillator.

[0025] Optionally, in the first ring oscillators, each order of the ring oscillators includes at least two cascaded inverters, and the number of inverters included in each order of the ring oscillator is prime to each other.

[0026] Optionally, the entropy extraction sampling module includes a D-type trigger; the input end of the D-type trigger is connected to the output end of the entropy source module, and the output end of the D-type trigger is connected to the input end of the post-processing module.

[0027] Optionally, the post-processing module includes a linear feedback shift register, and an input end of the linear feedback shift register is connected to an output end of the entropy extraction sampling module.

[0028] The embodiments of the present invention include the following advantages:

[0029] The random number generation method provided by the embodiment of the present invention uses a ring oscillator nested structure composed of a first ring oscillator and a second ring oscillator as an entropy source module, and adds the randomness of the logic high and low levels generated by the ring oscillators of each order in the first ring oscillator to the second ring oscillator for superposition through the nested structure, thereby enhancing the randomness of the entropy source signal, which is beneficial to improving the quality of the random numbers output by the true random number generator; then, the entropy source signal is sampled by the entropy extraction sampling module, and the bias and correlation of the initial random sequence obtained by sampling are eliminated by the post-processing module, so that the distribution of the random sequence is more reasonable and the randomness is stronger. Compared with the random number generation method in the prior art, the embodiment of the present invention improves the randomness of random numbers, and has a simple structure, does not need to occupy too many resources, and does not need a programmable delay line to change the frequency of the oscillator, and has strong versatility. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for use in the description of the embodiments of the present invention will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative labor.

[0031] Figure 1 It is a true random number generation structure based on a ring oscillator of the present invention;

[0032] Figure 2 It is another true random number generation structure based on a ring oscillator of the present invention;

[0033] Figure 3 It is a structural schematic diagram of a programmable delay line ring oscillator of the present invention;

[0034] Figure 4 is a flowchart of a random number generation method embodiment of the present invention;

[0035] Figure 5 It is a structural block diagram of a true random number generator of the present invention;

[0036] Figure 6 It is a structural block diagram of an entropy source module of the present invention;

[0037] Figure 7 It is a schematic diagram of signal jitter of an oscillation period of the present invention. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0039] Method Embodiment

[0040] The entropy source structure based on a ring oscillator is a common structure in true random number generators. The ring oscillator uses multiple inverters to form a feedback loop to make the signal oscillate at high speed in the ring. Due to the uncertainty factors such as temperature changes, slight differences between electronic components, and wiring delays in the circuit, the output signal has a certain degree of randomness, so it can be used as an entropy source for random number generators. Then, by converting it into a digital random sequence through a sampling circuit, the randomness in the circuit can be captured and random numbers can be generated. Figure 1 and Figure 2 , respectively show a true random number generation structure based on a ring oscillator.

[0041] like Figure 1 The single ring oscillator shown has a simple structure, and the output of the ring oscillator is based on the noise characteristics of the oscillator circuit structure, but the randomness of the entropy source is single, and the randomness of the output data is poor.

[0042] like Figure 2 The random number generation structure of the multi-ring oscillator shown uses multiple ring oscillators of different orders and uses the phase difference between the orders during oscillation to generate random numbers. Such a structure often uses multiple ring oscillators, which consumes more resources. In addition, the XOR structure of the multi-order ring oscillator uses the phase difference between the ring oscillators and does not consider random factors such as jitter. Therefore, the random number may be repeated periodically, resulting in poor quality.

[0043] Reference Figure 3 , shows a schematic diagram of the structure of a programmable delay line ring oscillator. Figure 3 As shown in the figure, the random number generation structure introduces a programmable delay line in the ring oscillator to change the frequency of the oscillator and continuously introduces new jitter during its oscillation. This scheme effectively reduces the correlation between the ring oscillators, thereby improving the randomness, but due to the bias of the circuit, a von Neumann corrector needs to be introduced for post-processing to eliminate the bias of the output sequence.

[0044] Figure 3 The random number generation structure shown can effectively improve the quality of random numbers. However, due to the large amount of fixed lookup table resources in the FPGA, it occupies too many resources. In addition, when using it, it is necessary to configure the frequency of each port to control the output frequency, so its portability is low and it is not universal.

[0045] The following is an explanation of the random number generation method provided by the embodiment of the present invention.

[0046] Reference Figure 4 , shows a flowchart of a random number generation method embodiment of the present invention, the method is applied to a true random number generator, the true random number generator includes an entropy source module, an entropy extraction sampling module and a post-processing module; the method may specifically include the following steps:

[0047] Step 101, using a first ring oscillator in an entropy source module to generate logic high and low levels;

[0048] Step 102, inputting the logic high and low levels generated by each order ring oscillator to the first input end of the XOR gate of the second ring oscillator in the entropy source module for signal processing to obtain an entropy source signal;

[0049] Step 103: Sample the entropy source signal using an entropy extraction sampling module to obtain an initial random sequence;

[0050] Step 104: Use a post-processing module to eliminate the bias and correlation of the initial random sequence to obtain a target random sequence.

[0051] The random number generation method provided in the embodiment of the present invention is applied to a true random number generator. Figure 5 , shows a structural block diagram of a true random number generator provided by an embodiment of the present invention. Figure 5 As shown, the true random number generator of the present invention includes an entropy source module, an entropy extraction sampling module and a post-processing module.

[0052] Among them, the entropy source module is used to generate the entropy source of random numbers (also called random source); the entropy extraction sampling module is used to extract the entropy source in the entropy source module; the post-processing module is used to reduce or eliminate the bias and correlation of the initial random sequence, so as to make the distribution of the random number sequence more reasonable and more random.

[0053] The entropy source is used to describe the various uncertainties in the clock signal generated by the ring oscillator. The embodiment of the present invention uses a ring oscillator to form an entropy source module to capture the oscillation jitter of the oscillator as an entropy source. As an example, taking the jitter frequency of the clock signal output by the ring oscillator in the entropy source module as 100M, ideally, the duty cycle is 50% and the period is 10ns, that is, the clock signal jumps every 5ns. When the clock signal actually jumps, it is definitely not an ideal situation. Sometimes it jumps a little more than 5ns, and sometimes it jumps a little less. This randomness is unpredictable and is a normal phenomenon in the circuit, but this random phenomenon can be used as an entropy source for a true random number generator. In addition to the output signal jitter, thermal noise and voltage fluctuations in the circuit can be used as entropy sources for a true random number generator.

[0054] The entropy source module in the embodiment of the present invention may include a first ring oscillator and a second ring oscillator. The first ring oscillator includes at least two-stage ring oscillators, and the output end of each stage ring oscillator is connected to the input end of the current stage. The second ring oscillator includes N XOR gates, and the second input end of the first XOR gate in the second ring oscillator is connected to the output end of the second ring oscillator. Except for the first XOR gate, the output end of the previous XOR gate is connected to the second input end of the next XOR gate; N is an odd number greater than or equal to 3.

[0055] like Figure 5 As shown, the output end of each order ring oscillator in the first ring oscillator is respectively connected to the first input end of different XOR gates in the second ring oscillator. The logic high and low levels generated by each order ring oscillator are input to the corresponding XOR gate for logic XOR processing.

[0056] It is understandable that each order ring oscillator in the first ring oscillator of the embodiment of the present invention can be used as a secondary ring oscillator to generate logic high and low levels in the form of free oscillation, thereby forming a certain oscillation frequency.

[0057] The second ring oscillator in the embodiment of the present invention can be used as a main ring oscillator, and is connected to each order of the secondary ring oscillator in the first ring oscillator through an XOR gate, so as to form a nested structure, and perform random superposition on the entropy source generated by the secondary ring oscillator. Specifically, the random source is the jitter of the oscillator. In the embodiment of the present invention, the jitter is first captured by the first ring oscillator, and then the jitter captured by the first ring oscillator is input as a random source to the second ring oscillator by using the nested structure, so as to complete the random superposition, improve the randomness of the entropy source, and help improve the quality of the random number output by the true random number generator.

[0058] The entropy extraction sampling module is used to realize the digital collection process of randomness. Since the entropy source signal is a high-frequency oscillating electrical signal, it is generally not directly usable. The function of this module is mainly to extract the entropy source signal generated by the entropy source module and convert it into a digital signal. Specifically, the entropy source module in the embodiment of the present invention is a high-frequency oscillation circuit. Due to the presence of random factors in the circuit, the generated entropy source signal is observed by an oscilloscope as a high-frequency and irregular waveform. These irregularities can represent the randomness in the circuit. The entropy extraction sampling module is to sample usable digital signals from these high-frequency irregular signals while retaining their random properties.

[0059] As an example, the entropy extraction sampling module in the embodiment of the present invention can use a D-type flip-flop to extract the random entropy source. The D-type flip-flop is a digital logic circuit that can capture and latch the state (0 or 1) of the input signal in each clock cycle.

[0060] Optionally, the entropy extraction sampling module includes a D-type trigger; and the step of sampling the entropy source signal using the entropy extraction sampling module to obtain an initial random sequence includes:

[0061] Step S11, inputting the entropy source signal to the input end of the D-type flip-flop, and inputting the sampling clock signal to the clock input end of the D-type flip-flop;

[0062] Step S12: When the rising edge of the sampling clock signal arrives, the D-type flip-flop is used to capture and latch the current state of the entropy source signal, so as to obtain an initial random sequence through continuous sampling; the initial random sequence is a random digital signal containing the randomness of the entropy source signal.

[0063] In an embodiment of the present invention, the output end of the entropy source module can be connected to the input end (D end) of the D-type flip-flop. When generating a random number, the entropy source signal generated by the entropy source module is input to the D end of the D-type flip-flop, and the sampling clock signal is input to the clock input end of the D-type flip-flop. Whenever the rising edge of the sampling clock signal arrives, the D-type flip-flop will capture and latch the current state of the entropy source signal input at the D end. Through continuous sampling, a random digital signal containing the randomness of the original entropy source signal, that is, an initial random sequence, can be obtained.

[0064] It should be noted that the sampling clock signal input to the D-type flip-flop may be generated by a clock module, and the clock module may include a crystal oscillator and a clock generator.

[0065] In a possible application scenario of the present invention, the true random number generator in the embodiment of the present invention can be burned on an FPGA chip. FPGA is a reconfigurable integrated circuit chip with a wide range of applications. Unlike traditional fixed-function integrated circuits (ASICs), FPGAs can be flexibly reprogrammed and reconfigured according to user needs to adapt to different applications and functions. FPGAs are composed of a large number of programmable logic blocks and programmable interconnect resources. Programmable logic blocks are usually composed of look-up tables (LUTs), registers, and other logic elements, and can perform various logic functions. Programmable interconnect resources are used to connect logic blocks to form a desired circuit structure.

[0066] In an embodiment of the present invention, a hardware description language, such as Verilog language, VHDL or other special languages, can be used to describe the functions of the true random number generator provided in the embodiment of the present invention. The modules implemented on the FPGA include an entropy source module, an entropy extraction sampling module, a post-processing module and a serial port output module, wherein the serial port module implements the function of sending the data generated by the true random number generator to the terminal device. It can be understood that the process of describing the functions of the true random number generator is the process of generating a register transfer level (RTL) circuit, which is used to implement functions equivalent to the above modules. Then, the RTL circuit is simulated, verified and synthesized using appropriate tools to generate a bitstream file that can be configured in the FPGA chip, and the true random number generator in the embodiment of the present invention is burned into the FPGA chip based on the bitstream file.

[0067] The sampling clock signal can be provided by the FPGA chip, and the frequency of the sampling clock signal is lower than the frequency of the oscillator in the entropy source module. By running a true random number generator on the FPGA chip and collecting the output results of the random number generator through the serial port, the target random sequence can be obtained.

[0068] It should be noted that the entropy extraction sampling module in the embodiment of the present invention can also adopt an analog-to-digital converter, a sample-and-hold circuit, etc. Among them, the mode converter is used to convert the analog signal into a digital signal. The sample-and-hold circuit is used to capture and hold the value of the signal at a specific moment. The sample-and-hold circuit can capture the instantaneous state of the entropy source signal, thereby realizing the sampling of the entropy source signal.

[0069] The post-processing module in the embodiment of the present invention is used to eliminate the bias and correlation of each random number in the initial random sequence. Among them, bias refers to the frequency of occurrence of certain values ​​or bits in the random number sequence deviating from the ideal uniform distribution. For example, in an ideal random binary sequence, the probability of occurrence of 0 and 1 should be 50%. If the probability of occurrence of 0 and 1 is not 50%, there is a bias. Correlation refers to the statistical dependence between certain values ​​in the random number sequence and other values. In an ideal random sequence, each value (or bit) should be independent of each other. If there is correlation, it means that some parts of the sequence can predict other parts, which reduces the randomness of the sequence.

[0070] When the power supply voltage in the circuit fluctuates, the frequency of the oscillator will change accordingly. This change will affect the statistical characteristics of the jitter. The fluctuation of the power supply voltage may introduce a certain pattern or bias, which increases or decreases the probability of a specific bit sequence, thus causing the bias and correlation of the random number sequence.

[0071] Temperature changes affect certain properties of semiconductor devices, and these changes can affect the behavior of oscillators or other noise sources. This can cause the statistical properties of the generated random sequences to change, potentially introducing bias and correlation.

[0072] Since there are always power supply voltage fluctuations and temperature changes in the circuit, the initial random sequence obtained by the entropy extraction sampling module is usually not an ideal true random number sequence, and there is still a certain bias and correlation. Therefore, the embodiment of the present invention adopts a post-processing module to further reduce or eliminate the bias and correlation of the initial random sequence, so that the distribution of the random number sequence is more reasonable and the randomness is stronger.

[0073] The random number generation method provided by the embodiment of the present invention uses a ring oscillator nested structure composed of a first ring oscillator and a second ring oscillator as an entropy source module, and adds the randomness of the logic high and low levels generated by the ring oscillators of each order in the first ring oscillator to the second ring oscillator for superposition through the nested structure, thereby enhancing the randomness of the entropy source signal, which is beneficial to improving the quality of the random numbers output by the true random number generator; then, the entropy source signal is sampled by the entropy extraction sampling module, and the bias and correlation of the initial random sequence obtained by sampling are eliminated by the post-processing module, so that the distribution of the random sequence is more reasonable and the randomness is stronger. Compared with the random number generation method in the prior art, the embodiment of the present invention improves the randomness of random numbers, and has a simple structure, does not need to occupy too many resources, and does not need a programmable delay line to change the frequency of the oscillator, and has strong versatility.

[0074] In an optional embodiment of the present invention, the second ring oscillator further includes M inverters, the M inverters are cascaded in sequence, and M is an odd number greater than or equal to 3. The second input end of the first XOR gate in the second ring oscillator is connected to the output end of the second ring oscillator, including: the output end of the last inverter in the second ring oscillator is connected to the second input end of the first XOR gate in the second ring oscillator, and the input end of the first inverter in the second ring oscillator is connected to the output end of the second ring oscillator.

[0075] Reference Figure 6 , shows a structural block diagram of an entropy source module provided by an embodiment of the present invention. Figure 6 As shown, the second ring oscillator in the entropy source module includes M inverters and N XOR gates, wherein M and N are odd numbers greater than or equal to 3. The output end of the last inverter in the second ring oscillator is connected to the second input end of the first XOR gate XOR1, and the input end of the first inverter is connected to the output end of the second ring oscillator, that is, the output end of the last XOR gate XORn, thereby forming a ring oscillator.

[0076] The M inverters in the second ring oscillator can effectively prevent the situation where the XOR gates cannot oscillate when the outputs are the same.

[0077] Optionally, in the first ring oscillators, each order of the ring oscillators includes at least two cascaded inverters, and the number of inverters included in each order of the ring oscillator is prime to each other.

[0078] The first ring oscillator in the embodiment of the present invention comprises a multi-stage ring oscillator. Figure 6 , ring oscillators OSCi, OSCj and OSCk respectively composed of i, j and k inverters are shown, forming secondary ring oscillators of different orders, wherein i, j and k are prime numbers to each other.

[0079] In the secondary ring oscillator, an odd number of inverters in cascade will generate logic high and low levels in the form of free oscillation, thus forming a certain oscillation frequency. Due to various noises in the circuit, the output frequency is unstable, and there is random jitter on the jump edge of the output signal, and the randomness will gradually accumulate as the oscillation time goes by. Figure 7 This is a schematic diagram of signal jitter for one oscillation cycle, such as Figure 7 As shown in Figure 1, due to the presence of jitter, the output signal edge will randomly deviate from the ideal signal edge, and as the oscillation time increases, the output signal will become more and more random. The number of inverters determines the output frequency of the ring oscillator.

[0080] It is understandable that in the first ring oscillator, the output frequency of the secondary ring oscillator is mainly determined by the number of inverters and the delay of each inverter. It takes a certain amount of time for the signal to pass through the inverter. Therefore, the more inverters there are, the lower the output frequency of the secondary ring oscillator.

[0081] In the embodiment of the present invention, since the number of inverters in each order of the secondary ring oscillator of the first ring oscillator is different, the output frequencies of each order of the secondary ring oscillator are also different, thereby generating a phase difference between each order of the secondary ring oscillator. The output signals with different frequencies are connected to the XOR gate of the main ring oscillator, that is, more uncertainty is added to the main ring oscillator, thereby improving the randomness of the entropy source.

[0082] It should be noted that the fewer the number of secondary ring oscillators and the fewer the number of inverters in each ring oscillator, the fewer resources are required for implementation. In an embodiment of the present invention, the number of secondary ring oscillators in the entropy source module and the number of inverters in each secondary ring oscillator can be adjusted according to the resources and random number quality requirements. For example, assuming that the design does not require high random number quality, the number of secondary ring oscillators (that is, the order of the ring oscillators included in the first ring oscillator) can be appropriately reduced, and the number of inverters in each secondary ring oscillator can be reduced at the same time, so as to reduce resource usage as much as possible while meeting the random number quality requirements. If the random number quality requirements are high, the number can be increased to improve the output quality.

[0083] Optionally, the post-processing module includes a linear feedback shift register; and using the post-processing module to eliminate the bias and correlation of the initial random sequence to obtain a target random sequence includes:

[0084] The linear feedback shifter is used to perform shift and feedback operations on the initial random sequence to obtain a target random sequence.

[0085] In the embodiment of the present invention, a linear feedback shift register with a simple structure and less resource consumption can be used as a post-processing module. The linear feedback shift register consists of a register and a feedback polynomial. The register is used to store an initial state, and a new state is generated through each shift and feedback operation. The feedback polynomial is used to determine how to generate the next state from the current state.

[0086] Exemplarily, assuming that the initial random sequence sampled by the entropy extraction sampling module is biased, after the initial random sequence is input into the linear feedback shift register, the linear feedback shift register can disrupt certain patterns in the input initial random sequence through its shift and feedback mechanism, so that the output target random sequence is more evenly distributed.

[0087] Moreover, the linear feedback shift register can break the correlation in the initial random sequence by performing complex linear operations on the initial random sequence. Through the selection of feedback polynomials, the linear feedback shift register can expand and mix the local patterns in the initial random sequence to generate a target random sequence with lower correlation.

[0088] Furthermore, in the embodiment of the present invention, in addition to using a linear feedback shift register as a post-processing module, a post-processing structure such as a de-skew algorithm and a hash function may also be used as a post-processing module to eliminate the bias and correlation of the initial random sequence.

[0089] In summary, the embodiment of the present invention provides a random number generation method, which uses a ring oscillator nested structure composed of a first ring oscillator and a second ring oscillator as an entropy source module, and adds the randomness of the logic high and low levels generated by the ring oscillators of each order in the first ring oscillator to the second ring oscillator for superposition through the nested structure, thereby enhancing the randomness of the entropy source signal, which is beneficial to improving the quality of the random numbers output by the true random number generator; then, the entropy source signal is sampled by the entropy extraction sampling module, and the bias and correlation of the initial random sequence obtained by sampling are eliminated by the post-processing module, so that the distribution of the random sequence is more reasonable and the randomness is stronger.

[0090] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0091] Device Embodiment

[0092] Reference Figure 5, showing a structural block diagram of a true random number generator of the present invention; the true random number generator comprises an entropy source module, an entropy extraction sampling module and a post-processing module connected in series in sequence;

[0093] The entropy source module includes a first ring oscillator and a second ring oscillator;

[0094] The first ring oscillator comprises at least two stages of ring oscillators, and the output end of each stage of the ring oscillator is connected to the input end of the current stage;

[0095] The second ring oscillator comprises N XOR gates, a second input end of a first XOR gate is connected to an output end of the second ring oscillator, and except for the first XOR gate, an output end of a previous XOR gate is connected to a second input end of a subsequent XOR gate; N is an odd number greater than or equal to 3;

[0096] The output end of each order ring oscillator of the first ring oscillator is respectively connected to the first input end of different XOR gates in the second ring oscillator.

[0097] Optionally, the second ring oscillator further includes M inverters, the M inverters are cascaded in sequence, and M is an odd number greater than or equal to 3;

[0098] The output end of the last inverter in the second ring oscillator is connected to the second input end of the first XOR gate in the second ring oscillator, and the input end of the first inverter in the second ring oscillator is connected to the output end of the second ring oscillator.

[0099] Optionally, in the first ring oscillators, each order of the ring oscillators includes at least two cascaded inverters, and the number of inverters included in each order of the ring oscillator is prime to each other.

[0100] Optionally, the entropy extraction sampling module includes a D-type trigger; the input end of the D-type trigger is connected to the output end of the entropy source module, and the output end of the D-type trigger is connected to the input end of the post-processing module.

[0101] Optionally, the post-processing module includes a linear feedback shift register, and an input end of the linear feedback shift register is connected to an output end of the entropy extraction sampling module.

[0102] In summary, the embodiment of the present invention provides a true random number generator, which can use the nested ring oscillator structure composed of the first ring oscillator and the second ring oscillator as an entropy source module, and add the randomness of the logic high and low levels generated by the ring oscillators of each order in the first ring oscillator to the second ring oscillator for superposition through the nested structure, thereby enhancing the randomness of the entropy source signal, which is beneficial to improving the quality of the random numbers output by the true random number generator; then, the entropy source signal is sampled by the entropy extraction sampling module, and the bias and correlation of the initial random sequence obtained by sampling are eliminated by the post-processing module, so that the distribution of the random sequence is more reasonable and the randomness is stronger. Compared with the random number generation structure in the prior art, the true random number generator in the embodiment of the present invention improves the randomness of random numbers, and has a simple structure, does not need to occupy too many resources, and does not need a programmable delay line to change the frequency of the oscillator, and has strong versatility.

[0103] As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0104] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0105] Regarding the true random number generator in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0106] An embodiment of the present invention provides an electronic device, wherein the electronic device is configured with Figure 5 The true random number generator shown is used to implement the step of generating random numbers in the aforementioned method embodiment.

[0107] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0108] It should be understood by those skilled in the art that the embodiments of the present invention can be provided as methods, devices or computer program products. Therefore, the embodiments of the present invention can take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, the embodiments of the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0109] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems) and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0110] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing terminal device to operate in a predictable manner, so that the instructions stored in the computer readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0111] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0112] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0113] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0114] The above is a detailed introduction to a random number generation method and a true random number generator provided by the present invention. Specific examples are used in this article to illustrate the principle and implementation mode of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation mode and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A random number generation method, characterized in that: Applied to a true random number generator, the true random number generator includes an entropy source module, an entropy extraction sampling module and a post-processing module; the method includes: The first ring oscillator in the entropy source module is used to generate logic high and low levels; the first ring oscillator includes at least two-stage ring oscillators, and the output end of each stage ring oscillator is connected to the input end of the current stage; The logic high and low levels generated by each order ring oscillator are respectively input to the first input end of the XOR gate of the second ring oscillator in the entropy source module for signal processing to obtain an entropy source signal; the second ring oscillator includes N XOR gates, the second input end of the first XOR gate in the second ring oscillator is connected to the output end of the second ring oscillator, and except for the first XOR gate, the output end of the previous XOR gate is connected to the second input end of the next XOR gate; N is an odd number greater than or equal to 3; The entropy source signal is sampled by the entropy extraction sampling module to obtain an initial random sequence; The post-processing module is used to eliminate the bias and correlation of the initial random sequence to obtain a target random sequence.

2. The method according to claim 1, characterized in that The second ring oscillator further includes M inverters, the M inverters are cascaded in sequence, and M is an odd number greater than or equal to 3; The second input terminal of the first XOR gate in the second ring oscillator is connected to the output terminal of the second ring oscillator, comprising: The output end of the last inverter in the second ring oscillator is connected to the second input end of the first XOR gate in the second ring oscillator, and the input end of the first inverter in the second ring oscillator is connected to the output end of the second ring oscillator.

3. The method according to claim 1, characterized in that In the first ring oscillator, each order of the ring oscillator includes at least two cascaded inverters, and the number of inverters included in each order of the ring oscillator is prime to each other.

4. The method according to claim 1, characterized in that: The entropy extraction sampling module includes a D-type trigger; the entropy source signal is sampled by the entropy extraction sampling module to obtain an initial random sequence, including: Inputting the entropy source signal to the input terminal of the D-type flip-flop, and inputting the sampling clock signal to the clock input terminal of the D-type flip-flop; When the rising edge of the sampling clock signal arrives, the D-type flip-flop is used to capture and latch the current state of the entropy source signal, so as to obtain an initial random sequence through continuous sampling; the initial random sequence is a random digital signal containing the randomness of the entropy source signal.

5. The method according to claim 1, characterized in that The post-processing module includes a linear feedback shift register; the post-processing module is used to eliminate the bias and correlation of the initial random sequence to obtain a target random sequence, including: The linear feedback shifter is used to perform shift and feedback operations on the initial random sequence to obtain a target random sequence.

6. A true random number generator, characterized in that: The true random number generator comprises an entropy source module, an entropy extraction sampling module and a post-processing module which are connected in series in sequence; The entropy source module includes a first ring oscillator and a second ring oscillator; The first ring oscillator includes at least two stages of ring oscillators, and the output end of each stage of the ring oscillator is connected to the input end of the current stage; The second ring oscillator comprises N XOR gates, a second input end of a first XOR gate is connected to an output end of the second ring oscillator, and except for the first XOR gate, an output end of a previous XOR gate is connected to a second input end of a subsequent XOR gate; N is an odd number greater than or equal to 3; The output end of each order ring oscillator of the first ring oscillator is respectively connected to the first input end of different XOR gates in the second ring oscillator.

7. The random number generator according to claim 6, characterized in that: The second ring oscillator further includes M inverters, the M inverters are cascaded in sequence, and M is an odd number greater than or equal to 3; The output end of the last inverter in the second ring oscillator is connected to the second input end of the first XOR gate in the second ring oscillator, and the input end of the first inverter in the second ring oscillator is connected to the output end of the second ring oscillator.

8. The true random number generator according to claim 6, characterized in that: In the first ring oscillator, each order of the ring oscillator includes at least two cascaded inverters, and the number of inverters included in each order of the ring oscillator is prime to each other.

9. The true random number generator according to claim 6, characterized in that: The entropy extraction sampling module includes a D-type trigger; the input end of the D-type trigger is connected to the output end of the entropy source module, and the output end of the D-type trigger is connected to the input end of the post-processing module.

10. The true random number generator according to claim 6, characterized in that: The post-processing module comprises a linear feedback shift register, and an input end of the linear feedback shift register is connected to an output end of the entropy extraction sampling module.

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