Waveform file conversion method for chip burning

Abstract

The invention discloses a waveform file conversion method for chip burning, and relates to the technical field of chip testing, and the method comprises the following steps: S1, a logic analyzer is used for capturing a waveform in a process of programming a chip by a PC (Personal Computer) end through a downloader (such as jlink), and the waveform is stored as a csv format file; s2, reading the stored csv file, obtaining sampling period information, collecting channel information and state information of each channel in each period; s3, acquiring pin configuration of the ATE machine for the test chip, establishing a corresponding relationship between pins of the ATE machine and the acquisition channel, and modifying the channel in the csv file into the corresponding pin configuration; and S4, deleting time information in each row of information, and converting the pin state into a character string form in a PAT format. According to the method, the waveform file collected by the logic analyzer is directly converted into the vector file used by the ATE machine through the script, so that manpower and time are saved, and the chip test cost is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of chip testing, and in particular to a waveform file conversion method for chip burning. Background Art

[0002] In the field of modern chip testing, especially in the functional testing (FT) process of microcontrollers (MCUs), burning test programs is an important step to ensure the normal operation of the chip. Generally speaking, at a specific stage in the testing process, the ATE (automatic test equipment) machine needs to burn the test program into the chip for subsequent functional verification and performance evaluation.

[0003] At present, making a burning program for ATE machines usually involves complex steps. Design engineers first need to create a test program in a simulation environment and generate the corresponding simulation file. This process not only requires engineers to have deep professional knowledge, but also requires the construction of a suitable development environment to output usable simulation files. After completing the simulation file, engineers need to use special conversion software to convert it into a vector file that can be recognized by the ATE machine. This series of operations usually requires multiple debugging and verification, which is time-consuming and laborious, increasing the overall test cycle and labor costs. Although the existing implementation scheme has solved the problem of program burning in chip testing to a certain extent, it still has significant defects. First of all, the construction of the simulation development environment and the design output of the simulation file require professional technicians, which not only increases the demand for human resources, but also increases the risk of errors. In addition, the conversion process of the dedicated software often requires repeated debugging and modification, which further prolongs the test time. Therefore, the overall process is cumbersome and inefficient, and cannot meet the modern needs of rapid iteration and efficient testing.

[0004] In view of the above shortcomings, the purpose of the present invention is to directly convert the waveform file collected by the logic analyzer into the vector file required by the ATE machine in a scripted manner. This method will greatly simplify the traditional burning process, reduce the dependence on professionals, reduce the complexity of the development and conversion links, and effectively save manpower and time costs. At the same time, the simplified process will also help companies reduce the overall cost of chip testing, improve the efficiency and accuracy of testing, and adapt to the rapidly changing needs of the market. Summary of the invention

[0005] The present invention provides a waveform file conversion method for chip burning to solve the problems raised in the above background technology.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: A waveform file conversion method for chip burning, comprising the following steps: S1: Use a logic analyzer to capture the waveform of the chip being burned into the program by a downloader (such as jlink) on the PC, and save the waveform as a csv file; S2: Read the saved csv file to obtain the sampling cycle information, acquisition channel information, and the status information of each channel in each cycle; S3: Obtain the pin configuration of the ATE machine for the test chip, establish the correspondence between the ATE machine pins and the acquisition channels, and modify the channels in the csv file to the corresponding pin configuration; S4: Delete the time information in each line of information and convert the pin status into a string in PAT format; S5: Add the necessary information for the ATE machine to recognize the PAT file at the beginning and end of the file, and save the file in pat format.

[0007] Preferably, the logic analyzer is an electronic testing tool used to capture the electrical signal waveforms when the chip is burned through a downloader (such as J-Link). These waveforms can reflect the state of data transmission, including the high and low levels of the signal, timing changes and other information.

[0008] Preferably, the downloader (such as J-Link) is a debugging and programming tool, which is used to burn programs to devices such as microcontrollers or FPGAs, and supports multiple programming interfaces (such as JTAG, SWD).

[0009] Preferably, the csv file is a comma-delimited text file format, which is convenient for storing and exchanging data. Each row represents a data record, and columns are separated by commas.

[0010] Preferably, the sampling period refers to the time interval for data sampling, that is, how long it takes to sample the signal state once.

[0011] Preferably, the acquisition channels are different signal input channels used by a logic analyzer for detecting specific signals.

[0012] Preferably, the ATE machine pin configuration refers to the layout and function definition of pins in automatic test equipment, which usually matches the pin arrangement of the chip under test.

[0013] Preferably, the corresponding relationship is that during the data processing, the collected signal channels and the actual pins of the test chip need to be mapped to each other to ensure correctness.

[0014] Preferably, the PAT format refers to a specific file format used to identify and execute test vectors on an ATE machine. The PAT file contains state information of test signals, which is usually represented by a specific string structure.

[0015] Preferably, the file header and tail information refers to the specific header and tail information that the PAT file usually requires in order for the ATE machine to identify the format and content of the file. Such information includes file version, pin configuration, test sequence, etc.

[0016] Due to the adoption of the above technical solution, the present invention has the following technical advances compared with the prior art: 1. Simplify workflow Reduce the complexity of steps: Traditional methods require multiple complex steps, such as setting up the simulation environment, generating simulation files, converting dedicated software, etc. This invention eliminates these cumbersome steps by directly processing the data of the logic analyzer; Reduced human resource requirements: Engineers no longer need to have complex professional skills and can achieve automated processing through scripting methods, thereby reducing dependence on highly skilled personnel.

[0017] 2. Save time and cost Accelerate the test cycle: By simplifying the process and reducing manual intervention, the overall time for burning the test program can be significantly shortened, speeding up the product's time to market; Reduce testing costs: Reduce labor and time costs, allowing companies to conduct chip testing more efficiently within budget, thereby reducing overall testing costs.

[0018] 3. Improve accuracy and reliability Reduce human errors: The automated script processing process can reduce the risk of errors caused by human operations and improve the accuracy of conversion results; Consistency and repeatability: Using the same script and process for conversion can ensure the consistency of each test and improve the reliability of test results.

[0019] 4. Adapt to the needs of rapid iteration Strong flexibility: Facing rapidly changing market demands, enterprises can adjust the testing process more flexibly and quickly adapt to the testing requirements of new products; 5. Support multiple chip types: This method can be extended to different types of microcontrollers and FPGAs, which increases the scope of application of the test.

[0020] 6. Optimize resource allocation and release engineers' energy: Engineers can devote more energy to other more creative work instead of wasting time on tedious file conversion; Improve overall team efficiency: Team members can focus more on design and development, optimize resource allocation, and achieve higher work efficiency.

[0021] 7. Technological innovation Promoting industry progress: The proposal and application of this new method has promoted technological progress in the field of chip testing and promoted the realization of automation and intelligence; Formation of new industry standards: With the promotion and application of this method, new technical standards may be formed, laying the foundation for the development of subsequent related technologies. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic diagram of a technical implementation scheme; Figure 2 It is a schematic diagram of the process of the present invention. DETAILED DESCRIPTION

[0023] The following will be combined with the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] like Figure 1-2 As shown, a method for restoring power after a distribution network fault involving operation risks includes the following steps: S1: Use a logic analyzer (a logic analyzer is used to capture and analyze the waveform of digital signals and can monitor multiple signal channels) to capture the waveform of the chip during the process of burning the program on the PC through a downloader (such as jlink) (a tool used to burn programs to devices such as microcontrollers or FPGAs, supporting multiple programming interfaces (such as JTAG, SWD) and save the waveform as a csv format file; Specifically, connect the logic analyzer: connect the logic analyzer probe to the relevant pins of the target chip to ensure that all signals generated during the burning process can be captured; Configure the logic analyzer: Set the appropriate sampling rate and trigger conditions to ensure accurate data capture. Generally speaking, the sampling rate should be at least 5-10 times the highest frequency of the signal; Start capturing: Start the downloader to burn and start the logic analyzer to capture data at the same time; Save data: After capturing, save the waveform data as a CSV format file for subsequent processing.

[0025] S2: Read the saved csv file (a comma-delimited text file format that facilitates data storage and exchange. Each row represents a data record, and columns are separated by commas), obtain sampling cycle information (the time interval for data sampling, that is, how long it takes to sample the signal state), sampling channel information (the sampling channel is the different signal input channels used by the logic analyzer to monitor specific signals), and the status information of each channel in each cycle; Specifically, read CSV files: Use a CSV library in a programming language (such as Python) or a data analysis library (such as Pandas) to read CSV files; Extract information: Sampling period: Get the sampling period from the header or settings of the CSV file. Acquisition channel: Get the name or number of each channel in CSV. Channel status: Traverse each row and record the status (high / low level) of each channel in each cycle.

[0026] S3: Get the pin configuration of the ATE machine for the test chip (referring to the layout and function definition of the pins in the automatic test equipment, which usually matches the pin arrangement of the chip under test), establish the correspondence between the ATE machine pins and the acquisition channels (the correspondence is that during the data processing process, the acquired signal channels need to be mapped to the actual pins of the test chip to ensure correctness), and modify the channels in the csv file to the corresponding pin configuration; Specifically, obtain the pin configuration: consult the documentation or configuration file of the ATE machine to understand the function of each pin and the corresponding signal; Establish mapping relationship: Create a mapping table to map the logic analyzer channels to the ATE pins one by one; Modify CSV channel information: Update the information of each channel in the CSV file to the corresponding ATE pin according to the mapping relationship.

[0027] S4: Delete the time information in each line of information and convert the pin status into a string in PAT format. PAT format refers to a specific file format used to identify and execute test vectors on ATE machines. PAT files contain the status information of test signals, usually represented by a specific string structure; Specifically, remove the time information: when reading CSV data, ignore the timestamp column and only keep the status information; State conversion: According to the definition, the pin state (such as high level and low level) is converted into PAT format. For example, the high level can be defined as "1" and the low level can be defined as "0"; Generate PAT format string: Combine the status information of each cycle into a string for subsequent use.

[0028] S5: Add necessary information for the ATE machine to identify the PAT file at the head and tail of the file, and save the file in pat format (file head and tail information means that the PAT file usually requires specific header and tail information so that the ATE machine can identify the format and content of the file. This information includes file version, pin configuration, test sequence, etc.); Specifically, add a file header: add the identification information of the ATE machine at the beginning of the PAT file, such as the machine model, test date, etc. Add file tail: add an end mark at the end of the file to ensure the file format is complete; Save as PAT format: Save the processed data as a PAT format file, using the appropriate file extension (pat).

[0029] The above generally describes the present invention in detail, but it is obvious to a person skilled in the art that some modifications or improvements can be made to the present invention. Therefore, modifications or improvements that do not depart from the spirit of the present invention are within the scope of protection of the present invention.

Claims

1. A waveform file conversion method for chip burning, characterized in that: The following steps are involved: S1: Use a logic analyzer to capture the waveform of the chip being burned into the program by a downloader (such as JLink) on the PC, and save the waveform as a csv file; S2: Read the saved csv file to obtain the sampling cycle information, acquisition channel information, and the status information of each channel in each cycle; S3: Obtain the pin configuration of the ATE machine for the test chip, establish the correspondence between the ATE machine pins and the acquisition channels, and modify the channels in the csv file to the corresponding pin configuration; S4: Delete the time information in each line of information and convert the pin status into a string in PAT format; S5: Add the necessary information for the ATE machine to recognize the PAT file at the beginning and end of the file, and save the file in pat format.

2. The waveform file conversion method for chip burning according to claim 1, characterized in that: The logic analyzer is an electronic testing tool used to capture the electrical signal waveforms when the chip is burned through a downloader (such as J-Link). These waveforms can reflect the status of data transmission, including information such as the high and low levels of the signal, timing changes, etc.

3. The waveform file conversion method for chip burning according to claim 1, characterized in that: The downloader (such as J-Link) is a tool debugging and programming tool for burning programs to devices such as microcontrollers or FPGAs, and supports multiple programming interfaces (such as JTAG, SWD).

4. The waveform file conversion method for chip burning according to claim 1, characterized in that: The csv file is a comma-delimited text file format that is convenient for storing and exchanging data. Each row represents a data record, and columns are separated by commas.

5. The waveform file conversion method for chip burning according to claim 1, characterized in that: The sampling period refers to the time interval for data sampling, that is, how long it takes to collect the signal state once.

6. The waveform file conversion method for chip burning according to claim 1, characterized in that: The acquisition channels are different signal input channels used by the logic analyzer and can monitor specific signals.

7. The waveform file conversion method for chip burning according to claim 1, characterized in that: The ATE machine pin configuration refers to the layout and function definition of the pins in the automatic test equipment, which usually matches the pin arrangement of the chip under test.

8. The waveform file conversion method for chip burning according to claim 1, characterized in that: The corresponding relationship is that during the data processing process, the collected signal channels and the actual pins of the test chip need to be mapped to each other to ensure correctness.

9. The waveform file conversion method for chip burning according to claim 1, characterized in that: The PAT format refers to a specific file format used to identify and execute test vectors on an ATE machine. The PAT file contains state information of a test signal, which is usually represented by a specific string structure.

10. The waveform file conversion method for chip burning according to claim 1, characterized in that: The file header and tail information refers to that the PAT file usually requires specific header and tail information so that the ATE machine can identify the format and content of the file. This information includes file version, pin configuration, test sequence, etc.

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