Chip testing method and system
By generating binary files and test cases of FPGA chips, and using the processing end to cure and compare data, the problem of inefficiency of existing chip testing methods is solved, automated testing is realized, and efficiency and accuracy are improved.
Patent Information
- Application Number
- CN202311617564.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-11-28
- Publication Date
- 2025-02-14
AI Technical Summary
The existing chip testing methods are inefficient and rely on manual code function testing. Verification personnel need to provide test files and manually verify the data analysis results.
By generating the binary file corresponding to the RTL code of the FPGA chip, and sending it and the test cases to the processing end. The processing end solidifies the binary file and sends the test cases to the FPGA chip, receives the running data and compares the simulation calculation data, and automatically determines Verification results on the board.
It realizes automation of chip testing, reduces manual participation, and improves testing efficiency and accuracy.
Smart Images
Figure CN119440921A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip technology, and in particular to a chip testing method and system. Background Art
[0002] During the chip development process, testing is required to determine whether the chip's code functions meet the requirements, thereby ensuring the normal use of the chip.
[0003] In related technologies, code functional testing relies on verification personnel. For example, during the chip board verification process, verification personnel are required to provide the files required for testing, manually check the data analysis results, and use data capture tools to capture relevant data online.
[0004] Therefore, the above testing method is relatively inefficient. Summary of the Invention
[0005] The embodiments of the present application provide a chip testing method and system to improve chip testing efficiency.
[0006] In a first aspect, an embodiment of the present application provides a first chip testing method, applied to a test end, the method comprising:
[0007] Generate a binary file corresponding to the resistance transistor logic (RTL) code of the Field-Programmable Gate Array (FPGA) chip;
[0008] Sending the binary file and the test case to a processing end, so that the processing end sends the binary file to the FPGA chip, and after the FPGA chip completes solidifying the binary file, sending the test case to the FPGA chip;
[0009] Receiving operation data sent by the processing end; wherein the operation data is generated after the FPGA chip runs the test case and sent to the processing end;
[0010] The running data and the simulation calculation data corresponding to the test case are compared to determine the board verification result of the FPGA chip.
[0011] In one or more embodiments, before generating a binary file corresponding to the RTL code of the FPGA chip, the method further includes:
[0012] Generate a test top-level file based on the RTL code, and generate code simulation data based on the test top-level file and the test case;
[0013] The code simulation data and the simulation calculation data are compared to determine the code simulation result of the FPGA chip.
[0014] In one or more embodiments, generating a binary file corresponding to the RTL code of the FPGA chip includes:
[0015] If the code simulation result is passed, a binary file corresponding to the RTL code of the FPGA chip is generated.
[0016] In one or more embodiments, further comprising:
[0017] The board verification result is sent to the user end.
[0018] In one or more embodiments, further comprising:
[0019] The test case is generated based on the preset data information and the preset configuration information.
[0020] In one or more embodiments, the simulation calculation data is determined by:
[0021] The test case is simulated and calculated using a preset calculation model to determine the simulation calculation data.
[0022] In a second aspect, an embodiment of the present application provides a second chip testing method, which is applied to a processing end and includes:
[0023] Receive the test cases sent by the test end and the binary file corresponding to the RTL code of the FPGA chip;
[0024] Sending the binary file to the FPGA chip so that the FPGA chip performs a solidification process on the binary file;
[0025] After determining that the FPGA chip is cured, sending the test case to the FPGA chip, and determining the operation data generated after the FPGA chip runs the test case;
[0026] The operation data is sent to the test end, so that the test end compares the operation data with the simulation calculation data corresponding to the test case to determine the board verification result of the FPGA chip.
[0027] In one or more embodiments, before sending the test case to the FPGA chip, the method further includes:
[0028] Send the corresponding register information to the FPGA chip.
[0029] In one or more embodiments, if there are multiple FPGA chips, the processing end transmits data with the target FPGA chip via the Advanced eXtensible Interface (AXI) protocol and transmits data with the non-target FPGA chip via the chip2chip protocol;
[0030] Among them, the target FPGA chip is an FPGA chip coupled to the processing end, or the target FPGA chip is an uncoupled FPGA chip that communicates with the processing end through the AXI protocol through the IO interface; the non-target FPGA chip is other FPGA chips among the multiple FPGA chips except the target FPGA chip.
[0031] In a third aspect, an embodiment of the present application provides a chip testing system, the system comprising: a processing end, an FPGA chip, and a testing end;
[0032] The test end is used to generate a binary file corresponding to the RTL code of the FPGA chip; and send the binary file and the test case to the processing end;
[0033] The processing end is used to send the binary file to the FPGA chip;
[0034] The FPGA chip is used to solidify the binary file;
[0035] The processing end is further configured to send the test case to the FPGA chip after the FPGA chip is solidified;
[0036] The FPGA chip is further configured to run the test case and send the generated running data to the processing end;
[0037] The processing end is further configured to send the operating data to the testing end;
[0038] The test end is further used to compare the running data and the simulation calculation data corresponding to the test case to determine the board verification result of the FPGA chip.
[0039] In one or more embodiments, before generating a binary file corresponding to the RTL code of the FPGA chip, the test end is further used to:
[0040] Generate a test top-level file based on the RTL code, and generate code simulation data based on the test top-level file and the test case;
[0041] The code simulation data and the simulation calculation data are compared to determine the code simulation result of the FPGA chip.
[0042] In one or more embodiments, the test end is specifically used to:
[0043] If the code simulation result is passed, a binary file corresponding to the RTL code of the FPGA chip is generated.
[0044] In one or more embodiments, the test end is further configured to:
[0045] The board verification result is sent to the user end.
[0046] In one or more embodiments, the test end is further configured to:
[0047] The test case is generated based on the preset data information and the preset configuration information.
[0048] In one or more embodiments, the test end is further configured to:
[0049] The test case is simulated and calculated using a preset calculation model to determine the simulation calculation data.
[0050] In one or more embodiments, before sending the test case to the FPGA chip, the processing end is further configured to:
[0051] Send the corresponding register information to the FPGA chip.
[0052] In one or more embodiments, if there are multiple FPGA chips, the processing end performs data transmission with the target FPGA chip via the AXI protocol and performs data transmission with the non-target FPGA chip via the chip2chip protocol;
[0053] Among them, the target FPGA chip is an FPGA chip coupled to the processing end, or the target FPGA chip is an uncoupled FPGA chip that communicates with the processing end through the AXI protocol through the IO interface; the non-target FPGA chip is other FPGA chips among the multiple FPGA chips except the target FPGA chip.
[0054] In a fourth aspect, an embodiment of the present application provides a first chip testing device, which is applied to a test end and includes:
[0055] The data generation module is used to generate the binary file corresponding to the RTL code of the FPGA chip;
[0056] A first sending module is configured to send the binary file and the test case to a processing end, so that the processing end sends the binary file to the FPGA chip, and after the FPGA chip completes solidifying the binary file, sends the test case to the FPGA chip;
[0057] A first receiving module is configured to receive operation data sent by the processing end; wherein the operation data is generated after the FPGA chip runs the test case and sent to the processing end;
[0058] The comparison module is used to compare the operation data and the simulation calculation data corresponding to the test case to determine the board verification result of the FPGA chip.
[0059] In a fifth aspect, an embodiment of the present application provides a second chip testing device, which is applied to a processing end and includes:
[0060] The second receiving module is used to receive the test case sent by the test end and the binary file corresponding to the RTL code of the FPGA chip;
[0061] A second sending module is used to send the binary file to the FPGA chip, so that the FPGA chip solidifies the binary file;
[0062] The second sending module is further configured to send the test case to the FPGA chip after determining that the FPGA chip curing is completed;
[0063] The second receiving module is further configured to determine operation data generated after the FPGA chip runs the test case;
[0064] The second sending module is also used to send the operating data to the test end, so that the test end compares the operating data with the simulation calculation data corresponding to the test case to determine the board verification result of the FPGA chip.
[0065] In a sixth aspect, an embodiment of the present application provides a test end, comprising at least one processor and at least one memory, wherein the memory stores a computer program, and when the program is executed by the processor, the processor executes any chip testing method described in the first aspect above.
[0066] In the seventh aspect, an embodiment of the present application provides a processing end, comprising at least one processor and at least one memory, wherein the memory stores a computer program, and when the program is executed by the processor, the processor executes any chip testing method described in the second aspect above.
[0067] In an eighth aspect, an embodiment of the present application provides a computer-readable storage medium storing a computer program executable by a processor. When the program runs on the processor, the processor executes the chip testing method described in any one of the first or second aspects above.
[0068] The above solution automatically generates the binary file required for board verification through the test end, and sends the binary file and test case to the processing end. The processing end acts as the hub and sends the binary file to the FPGA chip. After the FPGA chip completes solidification of the binary file, the processing end sends the test case to the FPGA chip and obtains the running data generated by the FPGA chip running the test case. The processing end sends the running data to the test end, and the test end automatically compares the running data with the simulation calculation data, thereby automatically determining the board verification result of the FPGA chip. That is, there is no need for manual participation in file writing and data comparison during the board verification process, which improves the testing efficiency of the FPGA chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0069] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.
[0070] Figure 1 This is a diagram of the first chip testing system architecture provided in an embodiment of the present application;
[0071] Figure 2 An interactive flow chart of the first chip testing method provided in an embodiment of the present application;
[0072] Figure 3 An interactive flow chart of the second chip testing method provided in an embodiment of the present application;
[0073] Figure 4 This is a diagram of the second chip testing system architecture provided in an embodiment of the present application;
[0074] Figure 5 This is a diagram of the third chip testing system architecture provided in an embodiment of the present application;
[0075] Figure 6 A schematic diagram of the process of the first chip testing method provided in an embodiment of the present application;
[0076] Figure 7 A schematic diagram of a second chip testing method provided in an embodiment of the present application;
[0077] Figure 8A schematic structural diagram of a first chip testing device provided in an embodiment of the present application;
[0078] Figure 9 A schematic structural diagram of a second chip testing device provided in an embodiment of the present application;
[0079] Figure 10 A schematic diagram of the structure of the test terminal provided in an embodiment of the present application. DETAILED DESCRIPTION
[0080] To make the objectives, technical solutions, and advantages of this application more clear, this application will be further described in detail below with reference to the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.
[0081] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of such features. Throughout this application, unless otherwise specified, "plurality" means two or more.
[0082] In the description of this application, it should be noted that, unless otherwise specified or limited, the term "connection" should be understood in a broad sense. For example, it can mean direct connection, indirect connection through an intermediate medium, or internal communication between two devices. Those skilled in the art will understand the specific meaning of the above terms in this application based on specific circumstances.
[0083] During the chip development process, testing is required to determine whether the chip's code functions meet the requirements, thereby ensuring the normal use of the chip.
[0084] In related technologies, code functional testing relies on verification personnel. For example, during the chip board verification process, verification personnel are required to provide the files required for testing, manually check the data analysis results, and use data capture tools to capture relevant data online.
[0085] Therefore, the above testing method is relatively inefficient.
[0086] In view of this, embodiments of the present application provide a chip testing method and system to improve chip testing efficiency.
[0087] See Figure 1 As shown, the first chip testing system provided by this embodiment includes a processing end, an FPGA chip and a testing end;
[0088] The test end is used to generate a binary file corresponding to the RTL code of the FPGA chip; and send the binary file and the test case to the processing end;
[0089] The processing end is used to send the binary file to the FPGA chip;
[0090] The FPGA chip is used to solidify the binary file;
[0091] The processing end is further configured to send the test case to the FPGA chip after the FPGA chip is solidified;
[0092] The FPGA chip is further configured to run the test case and send the generated running data to the processing end;
[0093] The processing end is further configured to send the operating data to the testing end;
[0094] The test end is further used to compare the running data and the simulation calculation data corresponding to the test case to determine the board verification result of the FPGA chip.
[0095] The above solution automatically generates the binary file required for board verification through the test end, and sends the binary file and test case to the processing end. The processing end acts as the hub and sends the binary file to the FPGA chip. After the FPGA chip completes solidification of the binary file, the processing end sends the test case to the FPGA chip and obtains the running data generated by the FPGA chip running the test case. The processing end sends the running data to the test end, and the test end automatically compares the running data with the simulation calculation data, thereby automatically determining the board verification result of the FPGA chip. That is, there is no need for manual participation in file writing and data comparison during the board verification process, which improves the testing efficiency of the FPGA chip.
[0096] The following will be combined with the accompanying drawings and specific embodiments to explain in detail the technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments.
[0097] Figure 2 The interactive flow chart of the first chip testing method provided in the embodiment of the present application is as follows: Figure 2 As shown, the following steps are included:
[0098] Step S201: The test end generates a binary file corresponding to the RTL code of the FPGA chip.
[0099] See above Figure 1 As shown, the chip test system is provided with a test end and a processing end. The script corresponding to the test end, such as Python (a computer programming language), is written into the test end, and the test end executes the corresponding steps;
[0100] The script corresponding to the processing end is written into the processing end, and the processing end executes the corresponding steps. This embodiment does not specifically limit the processing end, such as an ARM processor (a microprocessor), and the script corresponding to the processing end is written into the Linux system (an operating system) of the ARM processor.
[0101] The testing end can communicate with the processing end through a network, such as a local area network (LAN).
[0102] This embodiment does not impose any specific limitation on the test end, such as a high-performance server.
[0103] In this embodiment, the test end automatically compiles the binary file required for board verification based on the corresponding script, such as generating a binary file (bin) from the RTL code through vivado (a design kit) software.
[0104] Step S202: The test end sends the binary file and the test case to the processing end.
[0105] In this embodiment, the processing end serves as the hub, and the information sent by the test end is sent to the FPGA chip via the processing end;
[0106] Based on this, after compiling the binary file, the test end sends the binary file and test cases to the processing end.
[0107] Step S203: The processing end sends the binary file to the FPGA chip.
[0108] As described above, in this embodiment, the processing end serves as the hub, and the information sent by the test end is sent to the FPGA chip via the processing end;
[0109] Based on this, after receiving the binary file and test case, the processing end needs to send this information to the FPGA chip; because the FPGA chip needs to solidify the binary file before running the test case, the processing end first sends the binary file to the FPGA chip.
[0110] Step S204: The FPGA chip solidifies the binary file.
[0111] In practice, the FPGA chip can only run after solidifying the binary file. Exemplarily, the FPGA chip loads the binary file into a coded flash memory.
[0112] Step S205: After the FPGA chip is solidified, the processing end sends the test case to the FPGA chip.
[0113] As described above, the FPGA chip needs to solidify the binary file before running the test case. Based on this, after determining that the FPGA chip is solidified, the processing end sends the test case to the FPGA chip.
[0114] This embodiment does not specifically limit how the processing end determines that the FPGA chip is solidified. For example, the FPGA chip sends an interrupt signal indicating completion to the processing end, or responds to information through a related communication protocol to inform the processing end that solidification is complete.
[0115] Step S206: The FPGA chip runs the test case to generate running data.
[0116] During implementation, the FPGA chip generates actual running data when it is put on the board by running test cases.
[0117] Step S207: the FPGA chip sends the generated operating data to the processing end, and the processing end sends the operating data to the testing end.
[0118] In this embodiment, in order to determine the board verification result, after knowing the actual running data of the FPGA chip when it is boarded, it is necessary to combine it with the simulation calculation data to determine the board verification result of the FPGA chip;
[0119] Based on this, the FPGA chip sends the running data to the processing end, and the processing end sends the running data to the test end.
[0120] Step S208: The test end compares the running data with the simulation calculation data corresponding to the test case to determine the board verification result of the FPGA chip.
[0121] In this embodiment, the test end automatically compares the running data with the simulation calculation data, thereby automatically determining the board verification result of the FPGA chip.
[0122] Exemplarily, if the operating data is the same as the simulation calculation data, the board verification result is passed; otherwise, the board verification result is determined to be failed.
[0123] The above solution automatically generates the binary file required for board verification through the test end, and sends the binary file and test case to the processing end. The processing end acts as the hub and sends the binary file to the FPGA chip. After the FPGA chip completes solidification of the binary file, the processing end sends the test case to the FPGA chip and obtains the running data generated by the FPGA chip running the test case. The processing end sends the running data to the test end, and the test end automatically compares the running data with the simulation calculation data, thereby automatically determining the board verification result of the FPGA chip. That is, there is no need for manual participation in file writing and data comparison during the board verification process, which improves the testing efficiency of the FPGA chip.
[0124] Figure 3 The interactive flow chart of the second chip testing method provided in the embodiment of the present application is as follows: Figure 3 As shown, the following steps are included:
[0125] Step S301: The test end generates a test top-level file based on the RTL code, and generates code simulation data based on the test top-level file and the test case.
[0126] During chip development, in addition to board verification, code simulation testing is usually required. This can help identify code problems before board deployment and improve testing efficiency.
[0127] If code simulation testing is performed manually, the verification personnel need to write the files required for code simulation testing and manually start the testing process;
[0128] Based on this, in this embodiment, the test end automatically generates a test top-level (testbench) file based on the corresponding script, and uses tools such as vcs (a compiled code simulator) and modelsim (a language simulation software) to generate a test top-level file based on the top-level interface of the module to be tested in the RTL code; based on the test top-level file and the above-mentioned test cases, code simulation data for the RTL code is generated.
[0129] Step S302: The test end compares the code simulation data and the simulation calculation data to determine the code simulation result of the FPGA chip.
[0130] In this embodiment, the test end automatically compares the code simulation data with the simulation calculation data, thereby automatically determining the code simulation result of the FPGA chip.
[0131] Exemplarily, if the code simulation data is the same as the simulation calculation data, the code simulation result is passed; otherwise, the code simulation result is determined to be failed.
[0132] Step S303: If the code simulation result is passed, the test end generates a binary file corresponding to the RTL code of the FPGA chip.
[0133] Step S304: The test end sends the binary file and the test case to the processing end.
[0134] Step S305: The processing end sends the binary file to the FPGA chip.
[0135] Step S306: The FPGA chip solidifies the binary file.
[0136] Step S307: After the FPGA chip is solidified, the processing end sends the test case to the FPGA chip.
[0137] Step S308: The FPGA chip runs the test case to generate running data.
[0138] Step S309: the FPGA chip sends the generated operating data to the processing end, and the processing end sends the operating data to the testing end.
[0139] Step S310: The test end compares the running data and the simulation calculation data corresponding to the test case to determine the board verification result of the FPGA chip.
[0140] The specific implementation of steps S303 to S310 can refer to the above embodiment and will not be repeated here.
[0141] In the above solution, the test end automatically generates a test top-level file based on the RTL code, and then generates code simulation data based on the test top-level file and test cases. The test end automatically compares the code simulation data with the simulation calculation data, thereby automatically determining the code simulation results of the FPGA chip. That is, there is no need for manual participation in file writing and data comparison during the code simulation process, which improves the testing efficiency of the FPGA chip.
[0142] In one or more embodiments, if the code simulation result is not passed, board verification is no longer performed. Instead, a notification is made through a preset notification method so that relevant personnel can modify the RTL code in a timely manner.
[0143] See Figure 4 As shown, the second chip testing system provided by this embodiment, based on the above chip testing system, further includes a user end.
[0144] This embodiment does not impose any specific limitation on the specific implementation of the user terminal, such as a personal computer (PC).
[0145] The user end can communicate with the test end and the processing end through the network, such as issuing the corresponding scripts mentioned above, issuing some instructions, or receiving some test results uploaded by the test end, etc. For example, the user end can communicate with the test end and the processing end through LAN.
[0146] In the above Figure 2 On the basis of the above step S208, the following steps are also included:
[0147] The test end sends the board verification result to the user end.
[0148] By sending the board verification results to the user end, relevant personnel can be informed in time whether the board verification is passed.
[0149] In the above Figure 3 On the basis of the above step S302, the following steps are also included:
[0150] The test end sends the code simulation result to the user end.
[0151] By sending the code simulation results to the user end, relevant personnel can promptly know whether the code simulation has passed.
[0152] In the above Figure 3 On the basis of the above, before step S301, the following steps are also included:
[0153] The user end sends a test start instruction to the test end.
[0154] Exemplarily, relevant personnel trigger a test start instruction through the user terminal, and the test terminal starts subsequent tests based on the test start instruction.
[0155] In one or more embodiments, further comprising:
[0156] The test end generates the test case based on the preset data information and preset configuration information.
[0157] Referring to the above embodiments, test cases are used in the board verification and code simulation processes. Based on this, in this embodiment, the test end automatically generates test cases based on the corresponding script. When generating test cases, it is necessary to refer to the preset data information (data protocol requirements) and preset configuration information (configuration requirements), so as to randomly generate constrained (compliant) test cases.
[0158] In one or more embodiments, the simulation calculation data is determined by:
[0159] The test end performs simulation calculation on the test case through a preset calculation model to determine the simulation calculation data.
[0160] During implementation, a preset calculation model, such as MATLAB (a mathematical software) or an algorithm model built in other languages, is called to generate simulation calculation data through the simulation algorithm of the preset calculation model.
[0161] In one or more embodiments, before sending the test case to the FPGA chip in step S205, the following steps are further performed:
[0162] The processing end sends the corresponding register information to the FPGA chip.
[0163] During implementation, the processing end completes the register configuration of the FPGA chip by sending corresponding register information (register information required for the module under test to work) to the FPGA chip.
[0164] In one or more embodiments, before the above step S206, the following steps are further performed:
[0165] The processing end controls the clock module to reset the module under test of the FPGA chip.
[0166] See Figure 5 As shown, the third chip testing system provided by this embodiment includes multiple FPGA chips;
[0167] The processing end (hereinafter referred to as PS) transmits data with the target FPGA chip (hereinafter referred to as PL) through the AXI protocol, and transmits data with the non-target FPGA chip through the chip2chip protocol;
[0168] Among them, the target FPGA chip is an FPGA chip coupled to the processing end, or the target FPGA chip is an uncoupled FPGA chip that communicates with the processing end through the AXI protocol through the IO interface; the non-target FPGA chip is other FPGA chips among the multiple FPGA chips except the target FPGA chip.
[0169] In implementation, if an FPGA chip is coupled to the processing end, such as a System on Chip (SoC) FPGA, the SoC FPGA integrates an ARM core (processing end) and an FPGA core (FPGA chip), allowing it to run C language (a programming language) code and FPGA code simultaneously. This FPGA chip is the target FPGA chip. The SoC FPGA can directly implement AXI protocol communication between the PS and PL. The AXI protocol is a bus protocol.
[0170] If the FPGA chip is decoupled from the processing end, that is, the processing end is external, additional IO interface circuits are required to implement AXI protocol communication between the PS and PL;
[0171] The processing side uses the chip2chip (inter-chip) protocol to transmit data with the non-target FPGA chip (external FPGA). Due to the limited number of processing side interfaces, the chip2chip interface is usually loaded into the PL. Therefore, it is usually necessary to implement the chip2chip protocol in the PL and communicate with the external FPGA through the interface connected to the PL.
[0172] The following is a specific example, using an external FPGA as an example:
[0173] The PS sends the binary file corresponding to the PL (referred to as bin1) and the binary file corresponding to the external FPGA (referred to as bin2) to the PL through the AXI protocol.
[0174] The PL solidifies bin1 and sends bin2 to the external FPGA through the chip2chip protocol; the external FPGA solidifies bin2.
[0175] Both the PL and the external FPGA can inform the PS of the completion of curing by sending an interrupt signal; or the external FPGA can send a reply indicating the completion of curing to the PS through the PL;
[0176] The PS sends the test case to the PL through the AXI protocol, and the PL sends the test case to the external FPGA through the chip2chip protocol;
[0177] The PL and external FPGA run test cases separately to generate running data;
[0178] The PL and external FPGA write the generated operating data into the target storage module of the PL;
[0179] The PS reads the target storage module through the AXI protocol to obtain the operating data of the PL and the external FPGA.
[0180] The PS sends the PL's operating data and the external FPGA's operating data to the test end via LAN.
[0181] The test end compares the PL's operating data with the corresponding simulation calculation data to determine the PL's board verification result; the test end also compares the external FPGA's operating data with the corresponding simulation calculation data to determine the external FPGA's board verification result.
[0182] The chip testing method performed by the test end in the embodiment of the present application is as follows Figure 6 As shown, the following steps are included:
[0183] Step S601: Generate a binary file corresponding to the RTL code of the FPGA chip;
[0184] Step S602: Sending the binary file and the test case to the processing end, so that the processing end sends the binary file to the FPGA chip, and after the FPGA chip completes solidifying the binary file, sends the test case to the FPGA chip;
[0185] Step S603: receiving operation data sent by the processing end; wherein the operation data is generated after the FPGA chip runs the test case and sent to the processing end;
[0186] Step S604: Compare the running data and the simulation calculation data corresponding to the test case to determine the board verification result of the FPGA chip.
[0187] In one or more embodiments, before generating a binary file corresponding to the RTL code of the FPGA chip, the method further includes:
[0188] Generate a test top-level file based on the RTL code, and generate code simulation data based on the test top-level file and the test case;
[0189] The code simulation data and the simulation calculation data are compared to determine the code simulation result of the FPGA chip.
[0190] In one or more embodiments, generating a binary file corresponding to the RTL code of the FPGA chip includes:
[0191] If the code simulation result is passed, a binary file corresponding to the RTL code of the FPGA chip is generated.
[0192] In one or more embodiments, further comprising:
[0193] The board verification result is sent to the user end.
[0194] In one or more embodiments, further comprising:
[0195] The test case is generated based on the preset data information and the preset configuration information.
[0196] In one or more embodiments, the simulation calculation data is determined by:
[0197] The test case is simulated and calculated using a preset calculation model to determine the simulation calculation data.
[0198] The chip testing method executed by the processing end in the embodiment of the present application is as follows Figure 7As shown, the following steps are included:
[0199] Step S701: Receive the test case sent by the test end and the binary file corresponding to the RTL code of the FPGA chip;
[0200] Step S702: Sending the binary file to the FPGA chip so that the FPGA chip solidifies the binary file;
[0201] Step S703: After determining that the FPGA chip is cured, sending the test case to the FPGA chip, and determining the operation data generated after the FPGA chip runs the test case;
[0202] Step S704: Send the operating data to the test end, so that the test end compares the operating data with the simulation calculation data corresponding to the test case to determine the board verification result of the FPGA chip.
[0203] In one or more embodiments, before sending the test case to the FPGA chip, the method further includes:
[0204] Send the corresponding register information to the FPGA chip.
[0205] In one or more embodiments, if there are multiple FPGA chips, the processing end performs data transmission with the target FPGA chip via the AXI protocol and performs data transmission with the non-target FPGA chip via the chip2chip protocol;
[0206] Among them, the target FPGA chip is an FPGA chip coupled to the processing end, or the target FPGA chip is an uncoupled FPGA chip that communicates with the processing end through the AXI protocol through the IO interface; the non-target FPGA chip is other FPGA chips among the multiple FPGA chips except the target FPGA chip.
[0207] Figures 6 and 7 The specific implementation of the embodiment can refer to the implementation of the above-mentioned interaction method, and the repeated parts will be omitted.
[0208] like Figure 8 As shown, based on Figure 6 The present invention relates to a chip testing method having the same inventive concept as that shown in FIG. 1 , and provides a first chip testing device 800 for use at a test end. The device includes:
[0209] The data generation module 801 is used to generate a binary file corresponding to the RTL code of the FPGA chip;
[0210] A first sending module 802 is configured to send the binary file and the test case to a processing end, so that the processing end sends the binary file to the FPGA chip, and after the FPGA chip solidifies the binary file, sends the test case to the FPGA chip;
[0211] A first receiving module 803 is configured to receive operation data sent by the processing end; wherein the operation data is generated by the FPGA chip after running the test case and sent to the processing end;
[0212] The comparison module 804 is used to compare the operation data and the simulation calculation data corresponding to the test case to determine the board verification result of the FPGA chip.
[0213] In one or more embodiments, the data generation module 801 is further configured to:
[0214] Before generating a binary file corresponding to the RTL code of the FPGA chip, generating a test top-level file based on the RTL code, and generating code simulation data based on the test top-level file and the test case;
[0215] The comparison module 804 is further configured to:
[0216] The code simulation data and the simulation calculation data are compared to determine the code simulation result of the FPGA chip.
[0217] In one or more embodiments, the data generation module 801 is specifically configured to:
[0218] If the code simulation result is passed, a binary file corresponding to the RTL code of the FPGA chip is generated.
[0219] In one or more embodiments, the first sending module 802 is further configured to:
[0220] The board verification result is sent to the user end.
[0221] In one or more embodiments, the data generation module 801 is further configured to:
[0222] The test case is generated based on the preset data information and the preset configuration information.
[0223] In one or more embodiments, the data generation module 801 is further configured to:
[0224] The test case is simulated and calculated using a preset calculation model to determine the simulation calculation data.
[0225] like Figure 9 As shown, based on Figure 7 The present invention relates to a second chip testing device 900, which is applied to a processing end and includes:
[0226] The second receiving module 901 is used to receive the test case sent by the test end and the binary file corresponding to the RTL code of the FPGA chip;
[0227] A second sending module 902 is configured to send the binary file to the FPGA chip so that the FPGA chip solidifies the binary file;
[0228] The second sending module 902 is further configured to send the test case to the FPGA chip after determining that the FPGA chip is cured;
[0229] The second receiving module 901 is further configured to determine the operation data generated after the FPGA chip runs the test case;
[0230] The second sending module 902 is further used to send the operating data to the test end, so that the test end compares the operating data with the simulation calculation data corresponding to the test case to determine the on-board verification result of the FPGA chip.
[0231] In one or more embodiments, the second sending module 902, before sending the test case to the FPGA chip, is further configured to:
[0232] Send the corresponding register information to the FPGA chip.
[0233] In one or more embodiments, if there are multiple FPGA chips, the processing end performs data transmission with the target FPGA chip via the AXI protocol and performs data transmission with the non-target FPGA chip via the chip2chip protocol;
[0234] Among them, the target FPGA chip is an FPGA chip coupled to the processing end, or the target FPGA chip is an uncoupled FPGA chip that communicates with the processing end through the AXI protocol through the IO interface; the non-target FPGA chip is other FPGA chips among the multiple FPGA chips except the target FPGA chip.
[0235] Figures 8 and 9 The specific implementation of the embodiment can refer to the implementation of the above-mentioned interaction method, and the repeated parts will be omitted.
[0236] Based on the same technical concept, the embodiment of the present application also provides a test terminal 1000, such as Figure 10 As shown, it includes at least one processor 1001 and a memory 1002 connected to the at least one processor. The specific connection medium between the processor 1001 and the memory 1002 is not limited in the embodiment of the present application. Figure 10 For example, the processor 1001 and the memory 1002 are connected via bus 1003. Buses can be divided into path buses, data buses, control buses, etc. For ease of representation, Figure 10 Only one thick line is used in the diagram, but this does not mean that there is only one bus or one type of bus.
[0237] Among them, the processor 1001 is the control center of the test end. It can use various interfaces and lines to connect various parts of the test end, and realize data processing by running or executing instructions stored in the memory 1002 and calling data stored in the memory 1002. Optionally, the processor 1001 may include one or more processing units. The processor 1001 may integrate an application processor and a modem processor, wherein the application processor mainly processes the operating system, user interface, and application programs, etc., and the modem processor mainly processes the issuance of instructions. It is understandable that the above-mentioned modem processor may not be integrated into the processor 1001. In some embodiments, the processor 1001 and the memory 1002 can be implemented on the same chip. In some embodiments, they can also be implemented on separate chips.
[0238] The processor 1001 can be a general-purpose processor, such as a central processing unit (CPU), a digital signal processor, an application-specific integrated circuit (ASIC), a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, or a discrete hardware component, and can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. A general-purpose processor can be a microprocessor or any conventional processor, etc. The steps of the method disclosed in the embodiment of the chip testing method can be directly embodied as being executed by a hardware processor, or can be executed by a combination of hardware and software modules in the processor.
[0239] Memory 1002 is a non-volatile computer-readable storage medium that can be used to store non-volatile software programs, non-volatile computer executable programs and modules. Memory 1002 may include at least one type of storage medium, such as a flash memory, a hard disk, a multimedia card, a card-type memory, a random access memory (Random Access Memory, RAM), a static random access memory (Static Random Access Memory, SRAM), a programmable read-only memory (Programmable Read Only Memory, PROM), a read-only memory (Read Only Memory, ROM), an electrically erasable programmable read-only memory (Electrically Erasable Programmable Read-Only Memory, EEPROM), a magnetic memory, a disk, an optical disk, etc. Memory 1002 is any other medium that can be used to carry or store a desired program code in the form of an instruction or data structure and can be accessed by a computer, but is not limited thereto. The memory 1002 in the embodiment of the present application can also be a circuit or any other device that can realize a storage function, for storing program instructions and / or data.
[0240] In the embodiment of the present application, the memory 1002 stores a computer program (that is, a script corresponding to the above-mentioned test terminal). When the program is executed by the processor 1001, the processor 1001 executes:
[0241] Generate binary files corresponding to the RTL code of the FPGA chip;
[0242] Sending the binary file and the test case to a processing end, so that the processing end sends the binary file to the FPGA chip, and after the FPGA chip completes solidifying the binary file, sending the test case to the FPGA chip;
[0243] Receiving operation data sent by the processing end; wherein the operation data is generated after the FPGA chip runs the test case and sent to the processing end;
[0244] The running data and the simulation calculation data corresponding to the test case are compared to determine the board verification result of the FPGA chip.
[0245] In one or more embodiments, before generating a binary file corresponding to the RTL code of the FPGA chip, the processor 1001 further executes:
[0246] Generate a test top-level file based on the RTL code, and generate code simulation data based on the test top-level file and the test case;
[0247] The code simulation data and the simulation calculation data are compared to determine the code simulation result of the FPGA chip.
[0248] In one or more embodiments, the processor 1001 specifically performs:
[0249] If the code simulation result is passed, a binary file corresponding to the RTL code of the FPGA chip is generated.
[0250] In one or more embodiments, the processor 1001 further executes:
[0251] The board verification result is sent to the user end.
[0252] In one or more embodiments, the processor 1001 further executes:
[0253] The test case is generated based on the preset data information and the preset configuration information.
[0254] In one or more embodiments, the processor 1001 further executes:
[0255] The test case is simulated and calculated using a preset calculation model to determine the simulation calculation data.
[0256] Based on the same technical concept, an embodiment of the present application further provides a processing end, comprising at least one processor and at least one memory, wherein the memory stores a computer program (that is, a script corresponding to the above-mentioned processing end). When the program is executed by the processor, the processor executes:
[0257] Receive the test cases sent by the test end and the binary file corresponding to the RTL code of the FPGA chip;
[0258] Sending the binary file to the FPGA chip so that the FPGA chip performs a solidification process on the binary file;
[0259] After determining that the FPGA chip is cured, sending the test case to the FPGA chip, and determining the operation data generated after the FPGA chip runs the test case;
[0260] The operation data is sent to the test end, so that the test end compares the operation data with the simulation calculation data corresponding to the test case to determine the board verification result of the FPGA chip.
[0261] In one or more embodiments, before sending the test case to the FPGA chip, the processor further executes:
[0262] Send the corresponding register information to the FPGA chip.
[0263] In one or more embodiments, if there are multiple FPGA chips, the processing end performs data transmission with the target FPGA chip via the AXI protocol and performs data transmission with the non-target FPGA chip via the chip2chip protocol;
[0264] Among them, the target FPGA chip is an FPGA chip coupled to the processing end, or the target FPGA chip is an uncoupled FPGA chip that communicates with the processing end through the AXI protocol through the IO interface; the non-target FPGA chip is other FPGA chips among the multiple FPGA chips except the target FPGA chip.
[0265] Based on the same technical concept, an embodiment of the present application also provides a computer-readable storage medium, which stores a computer program that can be executed by a processor. When the program runs on the processor, the processor executes the steps of the above-mentioned chip testing method.
[0266] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, systems, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.
[0267] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.
[0268] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.
[0269] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.
[0270] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.
[0271] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.
Claims
1. A chip testing method, characterized in that: Applied to the test end, the method includes: Generate a binary file corresponding to the resistor transistor logic RTL code of the field programmable gate array FPGA chip; Sending the binary file and the test case to the processing end, so that the processing end sends the binary file to the FPGA chip, and after the FPGA chip solidifies the binary file, sends the test case to the FPGA chip; Receiving operation data sent by the processing end; wherein the operation data is generated after the FPGA chip runs the test case and sent to the processing end; The operation data and the simulation calculation data corresponding to the test case are compared to determine the on-board verification result of the FPGA chip.
2. The method according to claim 1, characterized in that Before generating the binary file corresponding to the RTL code of the FPGA chip, it also includes: Generate a test top-level file based on the RTL code, and generate code simulation data based on the test top-level file and the test case; The code simulation data and the simulation calculation data are compared to determine the code simulation result of the FPGA chip.
3. The method according to claim 2, characterized in that Generate binary files corresponding to the RTL code of the FPGA chip, including: If the code simulation result is passed, a binary file corresponding to the RTL code of the FPGA chip is generated.
4. The method according to claim 1, characterized in that Also includes: The board verification result is sent to the user end.
5. The method according to claim 1, characterized in that Also includes: The test case is generated based on the preset data information and the preset configuration information.
6. The method according to any one of claims 1 to 5, characterized in that: The simulation calculation data is determined in the following manner: The test case is simulated and calculated by using a preset calculation model to determine the simulation calculation data.
7. A chip testing method, characterized in that: Applied to the processing end, the method includes: Receive the test cases sent by the test end and the binary files corresponding to the RTL code of the FPGA chip; Sending the binary file to the FPGA chip so that the FPGA chip performs a solidification process on the binary file; After determining that the FPGA chip is solidified, sending the test case to the FPGA chip, and determining the operation data generated after the FPGA chip runs the test case; The operation data is sent to the test end, so that the test end compares the operation data with the simulation calculation data corresponding to the test case to determine the on-board verification result of the FPGA chip.
8. The method according to claim 7, characterized in that Before sending the test case to the FPGA chip, the method further includes: Send the corresponding register information to the FPGA chip.
9. The method according to claim 7, characterized in that If there are multiple FPGA chips, the processing end performs data transmission with the target FPGA chip through the Advanced Extensible Interface AXI protocol, and performs data transmission with the non-target FPGA chip through the chip2chip protocol; Among them, the target FPGA chip is an FPGA chip coupled to the processing end, or the target FPGA chip is an uncoupled FPGA chip that communicates with the processing end through an IO interface using the AXI protocol; the non-target FPGA chip is other FPGA chips among the multiple FPGA chips except the target FPGA chip.
10. An FPGA chip testing system, characterized in that: The system includes: a processing end, an FPGA chip and a testing end; The test end is used to generate a binary file corresponding to the RTL code of the FPGA chip; and send the binary file and the test case to the processing end; The processing end is used to send the binary file to the FPGA chip; The FPGA chip is used to solidify the binary file; The processing end is further used to send the test case to the FPGA chip after the FPGA chip is solidified; The FPGA chip is also used to run the test case and send the generated running data to the processing end; The processing end is further used to send the operation data to the testing end; The test end is also used to compare the operation data and the simulation calculation data corresponding to the test case to determine the on-board verification result of the FPGA chip.