Multi-core DSP single-particle fault detection method based on digital prototype

Abstract

The invention provides a multi-core DSP single-particle fault detection method based on a digital prototype. The method comprises the following steps that 1, a physical prototype is converted into the digital prototype; 2, determining the fault type and packaging the fault type; 3, constructing a fault injector for each fault type; 4, constructing a fault injection framework by using a fault injector; 5, constructing an automatic fault injection architecture based on the fault injection architecture; and step 6, multi-core DSP single-particle fault detection is carried out by using an automatic fault injection architecture. According to the method, the digital prototype is constructed in a software and hardware combination mode for fault detection, the time precision requirement can be met, the cost is effectively reduced, the defects of the domestic multi-core DSP can be exposed in advance, the cost and the period of defect repair are reduced, and finally the stability and the reliability of a spacecraft system are effectively improved.

Description

Technical Field

[0001] The present invention relates to the technical field of fault detection, and in particular to a multi-core DSP single-particle fault detection method based on a digital prototype. Background Art

[0002] DSP (Digital Signal Processor): A digital signal processor is a microprocessor specifically used to implement signal processing algorithms. Multi-core DSP refers to the integration of two or more complete computing engine cores in one processor, and these cores can run program instructions independently. Multi-core DSP uses inter-core communication to achieve high-speed parallel multi-threading and multi-processing, and has faster execution speed and higher execution capability than traditional single-core DSP.

[0003] According to statistics from NASA, about 45% of all failures of various aerospace devices are caused by the single particle effect of high-energy particles, and from 1971 to 1986, 39 synchronous satellites launched had a total of 1,589 failures, of which 1,129 were related to space radiation, and 621 of them were caused by single particle effects. In March 2021, the electronic system of the Crew Dragon spacecraft of the US Space Exploration Technology Company docked with the International Space Station was bombarded by charged particles, sending a false decompression signal and triggering the alarm system of the entire International Space Station. There are currently no relevant statistics in China and the data is sensitive, but it can be inferred that the situation of aerospace device failures caused by single particle failures worldwide is still severe.

[0004] In December 2010, the domestically produced multi-core DSP "Hua Rui No. 1" was released, becoming the first high-end DSP chip in China. The chip integrates four high-performance DSP processor cores, and its processing power, power consumption and other technical indicators have reached the international advanced level. In recent years, with the popularization and application of 5G, Internet of Things, and artificial intelligence, the domestic DSP chip industry has entered a stage of accelerated development. At the same time, the process of domestic DSP chips has been gradually improved, and the communication standards have been gradually standardized. The traditional faults of domestic multi-core DSPs have been greatly reduced, such as capacitor burnout, pin short circuit, data packet loss, etc., but the single-particle faults of domestic multi-core DSPs have not been effectively reduced.

[0005] Single particle failure is a change in the state of electronic devices caused by high-energy protons or heavy ions in cosmic rays. It only causes the "0" or "1" of the electronic device to flip or lock, but it may affect the normal operation of the entire spacecraft system. Usually, single particle failure detection methods can be divided into the following two categories:

[0006] (1) Hardware-based fault detection method: In a laboratory environment, radiation induction, power supply interference, laser implementation, etc. are simulated to detect whether the chip triggers a single-particle fault. The advantage of this method is that it truly restores the single-particle effect, but the disadvantage is that the test cost is high and the fault occurs randomly and cannot be controlled.

[0007] (2) Software-based fault detection method: Insert a fault simulation unit according to the single-particle fault model, and detect whether the chip triggers a single-particle fault by modifying the content of the memory or register. The advantages of this method are low cost and a wide range of faults that can be simulated. The disadvantages are that the fault model cannot completely replace the prototype and the model time accuracy is insufficient.

[0008] Traditional hardware-based single-event fault detection methods such as Figure 1 As shown, in a laboratory environment, radiation induction, power supply interference, laser implementation, etc. are simulated to detect whether the chip triggers a single-particle failure.

[0009] Advantages: True restoration of single particle effects.

[0010] Disadvantages: high testing cost and random and uncontrollable failures.

[0011] Traditional software-based single-event fault detection methods such as Figure 2 As shown, a fault simulation unit is inserted according to a single-particle fault model, and the content of a memory or a register is modified to detect whether the chip triggers a single-particle fault.

[0012] Advantages: low cost and wide range of faults that can be simulated.

[0013] Disadvantages: The fault model cannot completely replace the prototype, and the model's time accuracy is insufficient.

[0014] For domestic multi-core DSP chips, their internal high-speed inter-core communication requires a more efficient fault detection mechanism to shorten the FDTI value (Fault detection time interval, the time interval from the occurrence of a fault to its identification) and the FTTI value (Fault tolerant time interval, the time interval from the occurrence of a fault to the time when a hazardous event may occur). Currently, traditional hardware- and software-based fault detection methods are gradually unable to meet the fault detection requirements of high-performance domestic DSP chips. Therefore, a high-precision and low-cost single-particle fault detection method is urgently needed to avoid greater damage caused by the spread of faults. Summary of the invention

[0015] In view of the problem that traditional hardware- and software-based fault detection methods are gradually unable to meet the fault detection requirements of high-performance domestic DSP chips, the present invention provides a multi-core DSP single-particle fault detection method based on a digital prototype. By constructing a digital prototype in the form of a combination of software and hardware for fault detection, it can not only meet the time accuracy requirements but also effectively reduce the cost. It can expose the defects of domestic multi-core DSP in advance, reduce the cost and cycle of defect repair, and ultimately effectively improve the stability and reliability of the spacecraft system.

[0016] The present invention provides a multi-core DSP single-particle fault detection method based on a digital prototype, comprising the following steps:

[0017] Step 1: Convert physical prototype to digital prototype;

[0018] Step 2: Identify the fault type and encapsulate it;

[0019] Step 3: Construct a fault injector for each fault type;

[0020] Step 4: Use the fault injector to construct a fault injection architecture;

[0021] Step 5: Construct an automated fault injection architecture based on the fault injection architecture;

[0022] Step 6: Use the automated fault injection framework to perform single-event fault detection on multi-core DSPs.

[0023] In some embodiments, in step 1, the conversion of the physical prototype into a digital prototype includes: registers, instruction system, exception system, interrupt system and on-chip peripherals of a digitized multi-core DSP.

[0024] In some embodiments, in step 2, the fault types include simulated single event upset_shared memory fault, simulated single event lock_shared memory fault, simulated single event upset_semaphore fault, simulated single event lock_semaphore fault, simulated single event upset_message queue fault, and simulated single event lock_message queue fault.

[0025] In some embodiments, in step 2, the name, description, triggering time and triggering position of each fault type are defined respectively, and the six fault types are packaged into a fault library.

[0026] In some embodiments, in step 3, constructing a fault injector for each fault type includes:

[0027] Simulate single-event upset_shared memory fault: monitor the status of shared memory and perform single-event "0", "1" flips, changing "0" to "1" and "1" to "0";

[0028] Simulate single-particle lock_shared memory failure: monitor the status of shared memory and perform single-particle "0", "1" lock, "0" is locked to "0", and "1" is locked to "1";

[0029] Simulate single-particle flip_semaphore fault: monitor the semaphore and perform single-particle "0", "1" flip, "0" is changed to "1", "1" is changed to "0";

[0030] Simulate single-particle lock_semaphore fault: monitor the semaphore and perform single-particle "0", "1" lock, "0" is locked to "0", and "1" is locked to "1";

[0031] Simulate single-particle upset_message queue fault: monitor the data in the message queue and perform single-particle "0", "1" flip, "0" is changed to "1", "1" is changed to "0";

[0032] Simulate single-particle lock_message queue failure: monitor the data of the message queue and perform single-particle "0", "1" lock, "0" is locked to "0", and "1" is locked to "1".

[0033] In some embodiments, in step 4, constructing a fault injection architecture using a fault injector includes:

[0034] Power on the multi-core DSP to enable each core to operate normally and initialize inter-core communication;

[0035] The fault injector is used to inject faults into the multi-core DSP to form a multi-core DSP fault injection architecture.

[0036] In some embodiments, in step 5, constructing an automated fault injection architecture based on the fault injection architecture includes:

[0037] Step 5_1: Construct the use case executor;

[0038] Step 5_2: Construct the automation controller;

[0039] Step 5_3: Based on the fault injection architecture, use case executor and automation controller, an automated fault injection architecture is formed.

[0040] In some embodiments, the use case executor is used to schedule the type and timing of each fault injection, determine whether the fault injection is successful, and collect fault injection results.

[0041] In some embodiments, the automation controller is used to control the execution of use cases, implement one-click batch injection of faults, and collect statistics and display the fault injection results.

[0042] In some embodiments, in step 5.3, a data bus is used to connect the fault injection architecture, the use case executor and the automation controller to form an automated fault injection architecture.

[0043] In summary, due to the adoption of the above technical solution, the beneficial effects of the present invention are:

[0044] 1. Reliability - The present invention helps to expose the communication failure of multi-core DSP in the spacecraft in advance, improves the reliability of the spacecraft, and reduces the maintenance cost of the spacecraft.

[0045] 2. Reusability - The present invention encapsulates the single-particle effect fault library and uses the use case executor to schedule the type and timing of each fault injection, thereby maximizing the reusability of existing assets.

[0046] 3. Diversity - The present invention adopts digital prototype technology, which is not limited by hardware when simulating extreme and complex working conditions for fault detection, thereby improving the diversity of fault detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 Schematic diagram of the hardware-based single-particle fault detection method.

[0048] Figure 2 Schematic diagram of the software-based single-particle fault detection method.

[0049] Figure 3 It is a schematic diagram of a multi-core DSP single-particle fault detection method based on a digital prototype in an embodiment of the present invention.

[0050] Figure 4 This is a diagram showing the effect of the fault library in an embodiment of the present invention.

[0051] Figure 5 This is a diagram showing the effect of simulating a shared memory failure in an embodiment of the present invention.

[0052] Figure 6 This is a diagram showing the effect of simulating a signal quantity failure in an embodiment of the present invention.

[0053] Figure 7 This is a diagram showing the effect of simulating a message queue failure in an embodiment of the present invention.

[0054] Figure 8 This is a diagram showing the effect of a multi-core DSP fault injection architecture in an embodiment of the present invention.

[0055] Fig. 9 Schematic diagram of the automated fault injection architecture in an embodiment of the present invention.

[0056] Fig.10 This is a diagram of the verification system architecture in an embodiment of the present invention.

[0057] Fig.11 This is a statistical result diagram of single event effect fault injection in an embodiment of the present invention. DETAILED DESCRIPTION

[0058] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0059] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0060] For domestic multi-core DSP chips, their internal high-speed inter-core communication requires a more efficient fault detection mechanism to shorten the FDTI value (Fault detection time interval, the time interval from the occurrence of a fault to its identification) and the FTTI value (Fault tolerant time interval, the time interval from the occurrence of a fault to the time when a hazardous event may occur). Currently, traditional hardware- and software-based fault detection methods are gradually unable to meet the fault detection requirements of high-performance domestic DSP chips. Therefore, a high-precision and low-cost single-particle fault detection method is urgently needed to avoid greater damage caused by the spread of faults.

[0061] A digital prototype refers to a digital model of a physical prototype. A digital prototype is designed to replicate the form, function, and performance characteristics of a physical prototype. A digital prototype is formed during the product development phase, allowing product designers to intuitively and visually perform design optimization, performance testing, and manufacturing simulation on the product model in a computer in a digital environment. In the present invention, a digital prototype is used to replicate a multi-core DSP chip, presenting the clock, interrupt, register, instruction system, on-chip peripherals, etc. of the multi-core DSP chip in a digital form, so that the digital prototype of the multi-core DSP chip is consistent with the processing logic, performance characteristics, etc. of the multi-core DSP chip itself.

[0062] In view of this, in order to match the requirements of software assurance and testing capabilities in satellite mission systems, the present invention adopts the technology of digital prototypes, combines the advantages of the two traditional detection methods based on hardware and software, and proposes a multi-core DSP single-particle fault detection method based on digital prototypes. The physical prototype is converted into a digital prototype, which can not only restore the single-particle effect more realistically and retain the advantages of the physical prototype, but also reduce the cost of fault detection, expand the range of faults that can be simulated, and retain the advantages of the digital model.

[0063] This embodiment proposes a multi-core DSP single-particle fault detection method based on a digital prototype. It targets the single-particle effect fault injection architecture of the multi-core DSP, builds a means of inter-core communication fault injection including storage unit faults, read-write faults, etc., and uses an automated controller to perform one-click batch injection of faults. Figure 3 As shown, the multi-core DSP single-particle fault detection method based on digital prototype includes the following steps:

[0064] Step 1: Convert physical prototype to digital prototype:

[0065] Registers, instruction system, exception system, interrupt system (synchronous exception, external interrupt), on-chip peripherals (clock, serial port), etc. of digital multi-core DSP.

[0066] Step 2: Identify the fault type and encapsulate it:

[0067] Step 2_1: Identify the fault type: Identify the inter-core communication mode of the multi-core DSP, including three communication modes: shared memory, semaphore, and message queue. Each communication mode includes two fault forms: single particle upset and single particle lock. Therefore, a total of six fault types are simulated, namely: simulated single particle upset_shared memory fault, simulated single particle lock_shared memory fault, simulated single particle upset_semaphore fault, simulated single particle lock_semaphore fault, simulated single particle upset_message queue fault, and simulated single particle lock_message queue fault.

[0068] Step 2_2: Encapsulate the fault library: define the name, description, trigger time and trigger position of each fault type respectively, and encapsulate the six fault types into a fault library, such as Figure 4 shown.

[0069] Step 3: Construct a fault injector for each fault type:

[0070] Simulate single-event upset_shared memory fault: monitor the status of shared memory and perform single-event "0", "1" flips, "0" is changed to "1", "1" is changed to "0", such as Figure 5 shown.

[0071] Simulate single-particle lock_shared memory failure: monitor the status of shared memory and perform single-particle "0", "1" lock, "0" is locked to "0", "1" is locked to "1", such as Figure 5 shown.

[0072] Simulate single-particle flip_semaphore fault: monitor the semaphore and perform single-particle "0", "1" flip, "0" is changed to "1", "1" is changed to "0", such as Figure 6 shown.

[0073] Simulate single-particle lock_semaphore fault: monitor the semaphore and perform single-particle "0", "1" lock, "0" is locked to "0", "1" is locked to "1", such as Figure 6 shown.

[0074] Simulate single-particle upset_message queue fault: monitor the data in the message queue and perform single-particle "0", "1" flips, "0" is changed to "1", "1" is changed to "0", such as Figure 7 shown.

[0075] Simulate single particle lock_message queue failure: monitor the data of the message queue and perform single particle "0", "1" lock, "0" is locked to "0", "1" is locked to "1", such as Figure 7 shown.

[0076] Step 4: Use the fault injector to construct a fault injection architecture:

[0077] Power on the multi-core DSP to make each core run normally and initialize inter-core communication; use the fault injector generated in step 3 to inject faults into the multi-core DSP to form a multi-core DSP fault injection architecture, such as Figure 8 shown.

[0078] Step 5: Construct an automated fault injection architecture based on the fault injection architecture:

[0079] Step 5_1: Construct a use case executor to schedule the type and timing of each fault injection, determine whether the fault injection is successful, and collect the fault injection results.

[0080] Step 5_2: Construct an automated controller to control the execution of use cases, implement one-click batch injection of faults, and count and display the fault injection results.

[0081] Step 5_3: Form an automated fault injection architecture. Use a data bus to connect the fault injection architecture generated in step 4, the use case executor generated in step 5_1, and the automated controller generated in step 5_2 to form an automated fault injection architecture, such as Fig. 9 shown.

[0082] Step 6: Use the automated fault injection framework to perform single-event fault detection on multi-core DSPs.

[0083] In order to verify the effectiveness of the present invention, a verification system was developed. The verification system consists of a PC, a simulator, a Feiteng FT-M6678 processor of the National University of Defense Technology, and some peripheral buses. The Feiteng FT-M6678 processor has 8 DSP cores, each with a main frequency of 1G, a fixed-point computing performance of 32GMAC / s@1GHz, and a floating-point computing performance of 16GFLOPS@1GHz. The verification system architecture is as follows: Fig.10 as shown.

[0084] The single event effect fault injection is performed on the verification system according to the automatic fault injection architecture constructed by the present invention, and the statistical results are as follows: Fig.11 As shown, the use case without single-particle flip and single-particle lock passed, indicating that no fault occurred, and the use case with single-particle flip or single-particle lock failed, indicating that a fault was triggered. This proves the effectiveness of the automatic fault injection architecture for multi-core DSPs of the present invention.

[0085] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A multi-core DSP single-particle fault detection method based on digital prototype, characterized in that: The steps include: Step 1: Convert physical prototype to digital prototype; Step 2: Identify the fault type and encapsulate it; Step 3: Construct a fault injector for each fault type; Step 4: Use the fault injector to construct a fault injection architecture; Step 5: Construct an automated fault injection architecture based on the fault injection architecture; Step 6: Use the automated fault injection framework to perform single-event fault detection on multi-core DSPs.

2. The multi-core DSP single-particle fault detection method based on digital prototype according to claim 1 is characterized in that: In step 1, the physical prototype is converted into a digital prototype including: registers, instruction system, exception system, interrupt system and on-chip peripherals of a digital multi-core DSP.

3. The multi-core DSP single-particle fault detection method based on digital prototype according to claim 1 is characterized in that: In step 2, the fault types include simulated single particle upset_shared memory fault, simulated single particle lock_shared memory fault, simulated single particle upset_semaphore fault, simulated single particle lock_semaphore fault, simulated single particle upset_message queue fault, and simulated single particle lock_message queue fault.

4. The multi-core DSP single-particle fault detection method based on digital prototype according to claim 3 is characterized in that: In step 2, the name, description, triggering time and triggering position of each fault type are defined respectively, and the six fault types are encapsulated into a fault library.

5. The multi-core DSP single-particle fault detection method based on digital prototype according to claim 4 is characterized in that: In step 3, constructing a fault injector for each fault type includes: Simulate single-particle upset_shared memory fault: monitor the status of shared memory and perform single-particle "0" and "1" flips, changing "0" to "1" and "1" to "0"; Simulate single-particle lock_shared memory failure: monitor the status of shared memory and perform single-particle "0" and "1" locks, "0" is locked to "0", and "1" is locked to "1"; Simulate single-particle flip_semaphore fault: monitor the semaphore and perform single-particle "0" and "1" flips, changing "0" to "1" and "1" to "0"; Simulate single-particle lock_semaphore fault: monitor the semaphore and perform single-particle "0" and "1" locks, "0" is locked to "0", and "1" is locked to "1"; Simulate single-particle upset_message queue fault: monitor the data of the message queue and perform single-particle "0" and "1" flips, changing "0" to "1" and "1" to "0"; Simulate single-particle lock_message queue failure: monitor the data of the message queue and perform single-particle "0" and "1" locks, "0" is locked to "0", and "1" is locked to "1".

6. The multi-core DSP single-particle fault detection method based on digital prototype according to claim 1 is characterized in that: In step 4, constructing a fault injection architecture using a fault injector includes: Power on the multi-core DSP to enable each core to operate normally and initialize inter-core communication; The fault injector is used to inject faults into the multi-core DSP to form a multi-core DSP fault injection architecture.

7. The multi-core DSP single-particle fault detection method based on digital prototype according to claim 6 is characterized in that: In step 5, constructing an automated fault injection architecture based on the fault injection architecture includes: Step 5_1: Construct the use case executor; Step 5_2: Construct the automation controller; Step 5_3: Based on the fault injection architecture, use case executor and automation controller, an automated fault injection architecture is formed.

8. The multi-core DSP single-particle fault detection method based on digital prototype according to claim 7 is characterized in that: The use case executor is used to schedule the type and timing of each fault injection, determine whether the fault injection is successful, and collect fault injection results.

9. The multi-core DSP single-particle fault detection method based on digital prototype according to claim 7, characterized in that: The automation controller is used to control the execution of use cases, realize one-click batch injection of faults, and count and display the fault injection results.

10. The multi-core DSP single-particle fault detection method based on digital prototype according to claim 7, characterized in that: In step 5.3, a data bus is used to connect the fault injection architecture, the use case executor, and the automation controller to form an automated fault injection architecture.

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