DMA (Direct Memory Access) communication method based on multi-independent-partition operating system

Abstract

The invention provides a DMA (Direct Memory Access) communication method based on a multi-independent partition operating system, which comprises the following steps: when a partition CoreOS is initialized, applying for a memory space, constructing a shared sending cache region and constructing n annular shared sending cache queues corresponding to n different priority queues respectively; when a partition driver sends a message, a corresponding shared sending cache queue is selected according to the priority of the message, and the number of cache blocks needing to be acquired is determined according to the length of the message; the partition obtaining and sending cache adopts a prefetching mechanism, the partition prefetches cache blocks from a shared sending cache queue, obtains a target number of cache blocks according to the length of a to-be-sent message for privatization, copies the message into the cache blocks, pushes a cache block number to the FPGA, and returns the cache blocks to the tail of the shared sending cache queue after sending to the FPGA is finished. According to the invention, each partition can complete data interaction with the bottom FPGA in a mode of reading or writing in the shared memory, so that the data processing efficiency is improved, and the concurrency performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of data communication technology, and in particular to data communication in a multi-partition field, and is applied to data transmission and communication of multi-independent partition operating systems. Background Art

[0002] Airborne data bus technology is used for interconnection between airborne equipment, subsystems and modules. From the perspective of computer concepts, various avionics equipment is equivalent to microcomputers, and bus communication technology is the channel and link connecting microcomputers, so that avionics equipment forms a network with complete functions. FC (Fibre Channel) is a channel standard proposed by the American Industrial Standards Institute (ANSI) in 1988, which aims to meet the growing demand for high-speed data channels within aerospace vehicles. The FC serial transmission rate can reach 133 megabits baud to 1.0625 gigabits. It is currently the main implementation method of airborne avionics system communication networks, and meets the needs of high-speed airborne communications.

[0003] FC is a standard-based network structure that has the dual advantages of channel and network, allowing the current mainstream channel standards and network protocols to run on the same physical interface. The huge data throughput makes it possible to transmit large amounts of data between different systems on board, and any topology can be established with the same device to meet different connection characteristics, such as point-to-point communication networks, arbitration ring communication networks, switched networks, etc., to achieve high-speed communication between node devices.

[0004] In the communication topology of FC fiber channel, node devices are usually configured with one or more fiber channel ports (FC ports). Node devices can be connected to the host through the PCIE interface, and communicate with the host to send and receive messages, such as sending service messages to the host, receiving the host's configuration information for the node device (FPGA, DDR storage, optical signal processing, etc.), and connecting the host to the FC topology network through the FC port.

[0005] In the increasingly complex application environment of modern airborne equipment, the airborne communication topology network is becoming more and more complex, and the amount of data transmitted in the network is growing exponentially. In order to improve the transmission performance of equipment, multi-core processors are beginning to be used in various types of processors. In this context, how to improve the efficiency of data processing and storage of the overall FC network is a key issue that the current airborne avionics FC network communication system needs to solve. Summary of the invention

[0006] The present invention aims to provide a DMA communication method based on a multi-independent partition operating system, establish a multi-partition shared sending and receiving data buffer, and store data in a shared memory or read data from a shared memory through a DMA method through an FPGA hardware device during data transmission. Each partition completes data interaction with the underlying FPGA hardware device by reading or writing the shared memory, thereby improving data processing efficiency and concurrent performance.

[0007] According to a first aspect of the present invention, a DMA communication method based on a multi-independent partition operating system is proposed, comprising:

[0008] When the partition CoreOS is initialized, memory space is requested and a shared send buffer is constructed for shared access by the upper partition (POS);

[0009] In the shared sending buffer area, n circular shared sending buffer queues are constructed, corresponding to n different priority queues respectively;

[0010] When sending a message, the partition driver selects the corresponding shared sending cache queue according to the message priority, and determines the number of cache blocks to be obtained according to the length of the message; the partition obtains the sending cache using a pre-fetch mechanism, the partition pre-fetches cache blocks from the shared sending cache queue, obtains the target number of cache blocks for privatization according to the length of the message to be sent, and then copies the message to be sent to the obtained cache block, and then pushes the cache block number to the FPGA. After sending to the FPGA, the cache block is returned to the tail of the shared sending cache queue for subsequent recycling;

[0011] Among them, the number of pre-fetched cache blocks in the partition is configured to be pre-set and less than or equal to the maximum number of cache blocks supported by the partition, and a usage threshold is configured. When the number of cache blocks held by the partition is less than the usage threshold, the corresponding number is supplemented from the shared send cache queue.

[0012] As an optional embodiment, when sending data, the partition uses the cache blocks pre-fetched from the shared sending cache queue to store data until the number of pre-fetched cache blocks in the partition decreases to a usage threshold, and then obtains cache blocks from the shared sending cache queue again for replenishment.

[0013] As an optional embodiment, each partition supports parallel sending during concurrent sending, and obtains shared cache resources from the same shared sending cache queue.

[0014] As an optional embodiment, the pre-fetching and returning of the sending buffer are realized through software configuration, for example: indexing the real DMA buffer, finding the DMA buffer address through the index, forming a circular queue by the index, and the FPGA is used to write the index to the tail of the circular queue, and obtain the index from the head of the queue through software configuration. The sending FIFO of the FPGA belongs to the partition shared resource, and each partition is set to obtain the index of the sending DMA buffer from the read position after obtaining the FIFO lock;

[0015] When the partition pushes the index to the FPGA, the FPGA sends the message outward in the order in which it is pushed, and writes the index of the sent DMA buffer to the end of the queue for subsequent recycling.

[0016] As an optional embodiment, when receiving a message, the partition builds a shared receiving buffer area through CoreOS, and uses a shared buffer to realize communication between the underlying FPGA and each partition.

[0017] As an optional embodiment, in the receiving direction, for a data block of a certain priority level received, the FPGA sends the data block of the priority level to the shared receiving cache area of ​​the partition, wherein the header of the data block has a multi-bit partition mapping table. CoreOS sends the index value corresponding to the data block to different partitions in sequence according to the header mapping table of the identified data block. Once the partition receives the index value, it reads the data from the shared receiving cache queue. When all partitions have finished reading the data, CoreOS releases the cache block to the FPGA for subsequent use, thereby completing the data transmission in the receiving direction.

[0018] As an optional embodiment, the partition MAP mapping table is configured by CoreOS inside the FPGA. The FPGA searches the partition mapping table for each received data to determine whether the received data is unicast, multicast or broadcast. The data is then written into the data cache block of the shared receive cache queue configured by CoreOS in the form of DMA. CoreOS notifies each partition to read the data in turn according to the partition MAP mapping at the end of each cache block. When all partitions have completed reading, the data block is released to the FPGA for subsequent use.

[0019] Therefore, through the DMA communication method based on multiple independent partition operating systems proposed by the present invention, in the process of transmitting data, the data is stored in the shared memory by the FPGA hardware device through DMA, or the data is read from the shared memory, and each partition completes the data interaction with the underlying FPGA hardware device by reading or writing the shared memory. By sharing memory and semaphores with the kernel, the call frequency between the partition and the kernel is reduced, so that the partition operation is more efficient. At the same time, each partition is bound to a different processor core and runs a different operating system. The partitions are independent of each other and the transmission does not affect each other.

[0020] In the optional aspect, in order to reduce the switching caused by partition access to the kernel, which leads to performance degradation, the state buffer is shared between multiple partitions and the kernel. When the kernel updates the buffer, each partition will also be updated synchronously. The relevant API for obtaining the state can be completed in the FC partition driver without scheduling to the kernel, which improves the efficiency of partition data processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a principle block diagram of a DMA communication system based on a multi-independent partition operating system according to an embodiment of the present invention.

[0022] Figure 2 It is a schematic diagram of the acquisition and return of cache blocks in the sending process of an embodiment of the present invention.

[0023] Figure 3 It is a schematic diagram of the relationship between the ring queue and the sending buffer according to an embodiment of the present invention.

[0024] Figure 4 It is a schematic diagram of the data processing flow in the sending direction according to an embodiment of the present invention.

[0025] Figure 5 It is a schematic diagram of the receiving direction data processing flow of an embodiment of the present invention. DETAILED DESCRIPTION

[0026] In order to better understand the technical content of the present invention, specific embodiments are given and described as follows in conjunction with the accompanying drawings.

[0027] Various aspects of the present invention are described in this disclosure with reference to the accompanying drawings, in which many illustrative embodiments are shown. The embodiments of the present disclosure are not necessarily intended to include all aspects of the present invention. It should be understood that the various concepts and embodiments introduced above, as well as those described in more detail below, can be implemented in any of many ways, because the concepts and embodiments disclosed by the present invention are not limited to any implementation. In addition, some aspects disclosed by the present invention can be used alone or in any appropriate combination with other aspects disclosed by the present invention.

[0028] Combination Figure 1-4 As shown, the partition is divided from the top layer to the bottom layer: client application layer, FACE layer, and partition driver layer.

[0029] As an intermediate layer, the FACE layer provides the FACE standard API interface to the upper client application layer and encapsulates the API interface provided by the partition driver downward.

[0030] The FC partition driver layer provides a specific functional interface to the application layer and serves as an interface for interactive commands with the kernel.

[0031] The FC partition driver layer exchanges communication data with the kernel through VIO queues and shared partition locks to send and receive application data. It reduces the call frequency between the partition and the kernel by sharing memory and semaphores with the kernel, making the partition run more efficiently.

[0032] The FC partition driver is an interface between the application layer and the FC kernel driver, and is used to implement VIO management (including sending VIO management), network management, health management, partition statistics management, and kernel driver statistics management functions. Among them, network management, health management, partition statistics management, and kernel driver statistics management can be implemented using existing technologies.

[0033] In an embodiment of the present invention, implementation of VIO management for implementing data processing and storage will be described in more detail.

[0034] In order to realize the sharing of sending and receiving data buffers by multiple partitions, the implementation of VIO management mainly includes:

[0035] 1) Zero-copy mechanism for sharing memory with the kernel;

[0036] 2) Use partition locks to jointly manage the send buffer and receive buffer between multiple partitions;

[0037] 3) Use a pre-read mechanism when sending data to reduce access conflicts to the shared access buffer chain and improve concurrency performance.

[0038] As an optional implementation method, in order to reduce the switching caused by partition access to the kernel, resulting in performance degradation, the state buffer is shared between multiple partitions and the kernel. When the kernel updates the buffer, each partition will also be updated synchronously. The relevant API for obtaining the state can be completed in the FC partition driver without scheduling to the kernel.

[0039] Combination Figure 1 , 2 , 3, the DMA communication method based on a multi-independent partition operating system disclosed in the present invention includes the following process:

[0040] When the partition CoreOS is initialized, memory space is requested and a shared send buffer is constructed for shared access by the upper partition (POS);

[0041] In the shared sending buffer area, n circular shared sending buffer queues are constructed, corresponding to n different priority queues respectively;

[0042] When sending a message, the partition driver selects the corresponding shared sending cache queue according to the message priority, and determines the number of cache blocks to be obtained according to the length of the message; the partition obtains the sending cache using a pre-fetch mechanism, the partition pre-fetches cache blocks from the shared sending cache queue, obtains the target number of cache blocks for privatization according to the length of the message to be sent, and then copies the message to be sent to the obtained cache block, and then pushes the cache block number to the FPGA. After sending to the FPGA, the cache block is returned to the tail of the shared sending cache queue for subsequent recycling;

[0043] Among them, the number of pre-fetched cache blocks in the partition is configured to be pre-set and less than or equal to the maximum number of cache blocks supported by the partition, and a usage threshold is configured. When the number of cache blocks held by the partition is less than the usage threshold, the corresponding number is supplemented from the shared send cache queue.

[0044] In particular, when a partition sends data, it uses cache blocks pre-fetched from the shared send cache queue to store the data until the number of pre-fetched cache blocks in the partition decreases to a usage threshold, and then obtains cache blocks from the shared send cache queue again for replenishment.

[0045] Each partition supports parallel sending when sending concurrently, and obtains shared cache resources from the same shared send cache queue. Due to the configurable lock protection of the queue, the cache will not be held by multiple partitions at the same time.

[0046] In an embodiment of the present invention, Figure 2 As shown, the pre-fetching and returning of the sending buffer are realized through software configuration.

[0047] Combination Figure 2 , 3 As shown, the acquisition and return of the send buffer, its specific implementation includes:

[0048] Index the real DMA buffer and find the DMA buffer address through the index. The index forms a circular queue. The FPGA is used to write the index to the end of the circular queue and obtain the index from the head of the queue through software configuration. The FPGA's send FIFO is a partition shared resource. Each partition is set to obtain the index of the sent DMA buffer from the read position after obtaining the FIFO lock.

[0049] When the partition pushes the index to the FPGA, the FPGA sends the message outward in the order in which it is pushed, and writes the index of the sent DMA buffer to the end of the queue for subsequent recycling.

[0050] like Figure 4 As shown, an example process of multiple partitions obtaining cache transmission and FPGA returning cache is more specifically represented.

[0051] Combination Figure 1 , 5 As shown, when a partition receives a message, it builds a shared receiving buffer through CoreOS and uses the shared buffer to realize the communication between the underlying FPGA and each partition.

[0052] In some specific embodiments, in the receiving direction, for a received data block of a certain priority, the FPGA sends the data block of the priority into the shared receiving buffer of the partition, wherein the header of the data block has a multi-bit partition mapping table. CoreOS sends the index value corresponding to the data block to different partitions in sequence according to the header mapping table of the identified data block. Once the partition receives the index value, it reads the data from the shared receiving buffer queue. When all partitions have finished reading the data, CoreOS releases the cache block to the FPGA for subsequent use, thereby completing the data transmission in the receiving direction.

[0053] Inside the FPGA, CoreOS configures the partition MAP mapping table. The FPGA searches the partition mapping table for each received data to determine whether the received data is unicast, multicast, or broadcast. Then, the data is written to the data cache block of the shared receive cache queue configured by CoreOS in the form of DMA. CoreOS notifies each partition to read the data in turn according to the partition MAP mapping at the end of each cache block. When all partitions have completed the reading, the data block is released to the FPGA for subsequent use.

[0054] The following describes the exemplary implementation process of the method of the present invention in more detail with reference to the accompanying drawings.

[0055] 1. Shared cache management function (sending direction)

[0056] In the embodiment of the present invention, in order to save memory resources, message sending will adopt the strategy of all partitions sharing the CoreOS sending cache.

[0057] The bottom layer (CoreOS) applies for memory space during initialization and builds a buffer area for the sending direction, namely the shared sending buffer area, which is used for shared access by the upper partition (POS).

[0058] In the requested memory, n circular sending queues are constructed according to the upper partition (POS) to send the required messages, corresponding to n different priority queues.

[0059] When sending a message, the partition driver will select a sending queue with a corresponding priority level according to the message priority level, and determine the number of cache blocks required based on the length of the message.

[0060] For example, for urgent message sending, since the message length does not exceed 2096 bytes, only one cache block needs to be obtained from the sending queue each time. However, the maximum length of a stream message can reach 16M bytes, and the FC partition driver can obtain the appropriate number of cache blocks from the stream message cache queue according to the actual number of bytes sent.

[0061] 2. Cache block pre-fetching mechanism (sending direction)

[0062] like Figure 2 As shown, the sending direction cache adopts a pre-fetch mechanism. The partition first expects cache blocks from the shared sending cache queue and obtains the target number of cache blocks according to the pre-fetch target.

[0063] When a partition sends data, it uses the pre-fetched cache blocks for caching until the number of cache blocks decreases to a preset usage threshold, at which time it needs to obtain and replenish them from the cache queue again.

[0064] This mechanism can reduce the waiting and delay caused by the lock queue, thereby improving the efficiency of data transmission.

[0065] As an optional example, the number of pre-fetched cache blocks of each partition may be determined according to the actual application scenario, but should be less than or equal to the maximum cache holding number supported by the partition.

[0066] 3. Acquisition and return of shared send cache blocks (sending direction)

[0067] Combination Figure 2 As shown in the figure, it shows the cache block acquisition and return of the partition when sending a message. The basic process of partition sending a message is:

[0068] 1) Get the send buffer from the shared send buffer queue (need to hold the queue lock):

[0069] 2) Copy the message to the cache;

[0070] 3) Push the cache block number to the FPGA;

[0071] 4) After the FPGA finishes sending, it returns the buffer to the end of the shared send buffer queue.

[0072] If the cache pre-fetching conditions are met when sending, the above step 1 is omitted and the sending is completed directly without locking.

[0073] The process of partition sending to other priority queues is similar to the above figure, the difference is that the sending buffer is applied from different queues, such as E queue, U queue, etc.

[0074] Each partition can send messages in parallel and obtain shared cache resources from the same queue. Since the queue is locked, the cache will not be held by multiple partitions at the same time.

[0075] 4. Lock-free return of send buffer (send direction)

[0076] It should be understood that the aforementioned proposed method of obtaining the sending buffer and returning the buffer to the FPGA is implemented through software configuration.

[0077] In the embodiment of the present invention, the cache obtained is actually an index pointing to the real DMA cache, and the DMA cache address can be found through the index. The index forms a circular queue, and the logic (FPGA) is responsible for writing the index to the end of the queue, and the software obtains the index from the head of the queue. The process is as follows Figure 3 As shown, the transmit FIFO is a partition shared resource, and each partition can obtain the transmit DMA index from the read position after acquiring the FIFO lock.

[0078] After the partition pushes the index to the FPGA, the FPGA sends the message outward in the order in which it is pushed, and writes the sent DMA buffer index to the end of the queue. Figure 4 As shown, it shows the situation of multiple partitions obtaining cache transmission and FPGA returning cache.

[0079] 5. Shared cache (receiving direction)

[0080] The receiving direction is similar to the sending direction. A shared receiving buffer is built through CoreOS, and the shared buffer is used to realize the communication between the underlying FPGA and each partition.

[0081] Among them, in the receiving direction, for a data block of a certain priority received, the FPGA sends the data block of the priority to the shared receiving buffer area of ​​the partition, wherein the header of the data block has a multi-bit partition mapping table. CoreOS sends the index value corresponding to the data block to different partitions in sequence according to the header mapping table of the identified data block. Once the partition receives the index value, it reads the data from the shared receiving buffer queue. When all partitions have read the data, CoreOS releases the cache block to the FPGA for subsequent use to complete the data transmission in the receiving direction.

[0082] Inside the FPGA, CoreOS configures the partition MAP mapping table. The FPGA searches the partition mapping table for each received data to determine whether the received data is unicast, multicast, or broadcast. The data is then written into the data cache block of the shared receive cache queue configured by CoreOS in the form of DMA. CoreOS notifies each partition to read the data in turn according to the partition MAP mapping at the end of each cache block. When all partitions have completed reading, the data block is released to the FPGA for subsequent use.

[0083] [Example 1] Sending data

[0084] When both partition 1 and partition 2 need to send priority 2 data, combined Figure 4 Assuming that the free data block indexes in the cache are a to z, and each index corresponds to a cache block, the partition first needs to pre-fetch the index. For the sake of simplicity, the pre-fetch action is not reflected in Figure 4 For reference Figure 2 way to achieve it.

[0085] Partition 1 needs to send content of 4 data blocks, and partition 2 needs to send content of 2 data blocks. At this time, partition 1 obtains four indexes a, b, c, and d from the circular queue and fills the data with priority 2 into the 4 caches corresponding to the 4 indexes.

[0086] Partition 2 obtains the two indexes e and f from the ring queue and fills the data with priority 2 into the two caches corresponding to the two indexes.

[0087] After filling in, the partitions push their respective index numbers to the FPGA device.

[0088] When FPGA initiates a DMA operation based on the index number, after DMP reads the content of the data block, it gives the index number to CoreOS, which then returns it to the ring queue for subsequent use.

[0089] If the pre-fetch action is added, that is, each partition ensures that there are N indexes read in advance from the circular queue within its own partition. When the number of indexes occupied by the sent data is less than or equal to N, the data is directly filled in. After the sending is completed, it is replenished to N from the circular queue again. If the number of indexes occupied by the sent data is greater than N, then the data is directly filled into N cache blocks, and the remaining number is replenished from the circular queue. After the data is sent, the pre-fetch indexes in the partition are replenished to N for use according to the situation.

[0090] [Example 2] Receiving data

[0091] There is a partition MAP mapping table configured by CoreOS inside the FPGA device. The FPGA device searches the mapping table for each data IU (information unit, each IU contains one or more data frames with the same attributes) to obtain whether the IU is unicast, multicast or broadcast.

[0092] The data is written into the data cache block of the shared queue of CoreOS in the form of DMA. CoreOS notifies each partition to read the data in turn according to the partition MAP mapping at the end of each cache block. When all partitions have completed the reading, the data block is released to the FPGA device for subsequent use.

[0093] like Figure 5 Shown is the data flow in the receive direction.

[0094] For example, the ID of U0 is 1, and the destination partition MAP of this IU0 is 0x03, which means it needs to be sent to partition 1 and partition 2 (using binary, 3 is represented by 0011, and each bit starting from the lowest bit is 1, indicating that a partition is selected, eg: 4 is represented by 0100, indicating that partition 3 is selected).

[0095] When IU0 is sent to the shared queue in CoreOS, CoreOS notifies partition 1 and partition 2 to read the data. When the two partitions complete the reading, CoreOS pushes the data block back to the FPGA device for continued use in subsequent data transmission.

[0096] Although the present invention has been disclosed as above with preferred embodiments, it is not intended to limit the present invention. A person with ordinary knowledge in the technical field to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the definition of the claims.

Claims

1. A DMA communication method based on a multi-independent partition operating system, characterized in that: include: When the partition CoreOS is initialized, memory space is requested and a shared send buffer is constructed for shared access by the upper partition (POS); In the shared sending buffer area, n circular shared sending buffer queues are constructed, corresponding to n different priority queues respectively; When sending a message, the partition driver selects the corresponding shared sending cache queue according to the message priority, and determines the number of cache blocks to be obtained according to the length of the message; the partition obtains the sending cache using a pre-fetch mechanism, the partition pre-fetches cache blocks from the shared sending cache queue, obtains the target number of cache blocks for privatization according to the length of the message to be sent, and then copies the message to be sent to the obtained cache block, and then pushes the cache block number to the FPGA. After sending to the FPGA, the cache block is returned to the tail of the shared sending cache queue for subsequent recycling; Among them, the number of pre-fetched cache blocks in the partition is configured to be pre-set and less than or equal to the maximum number of cache blocks supported by the partition, and a usage threshold is configured. When the number of cache blocks held by the partition is less than the usage threshold, the corresponding number is supplemented from the shared send cache queue.

2. The DMA communication method based on a multi-independent partition operating system according to claim 1, characterized in that: When a partition sends data, it uses the cache blocks pre-fetched from the shared send cache queue to store the data until the number of pre-fetched cache blocks in the partition decreases to the usage threshold, and then obtains cache blocks from the shared send cache queue again to replenish the data.

3. The DMA communication method based on a multi-independent partition operating system according to claim 1, characterized in that: Each partition supports parallel sending when sending concurrently, and obtains shared cache resources from the same shared send cache queue.

4. The DMA communication method based on a multi-independent partition operating system according to claim 1, characterized in that: The pre-fetching and returning of the send buffer is realized through software configuration.

5. The DMA communication method based on a multi-independent partition operating system according to claim 1, characterized in that: The acquisition and return of the sending buffer are specifically implemented as follows: Index the real DMA buffer and find the DMA buffer address through the index. The index forms a circular queue. The FPGA is used to write the index to the end of the circular queue and obtain the index from the head of the queue through software configuration. The FPGA's send FIFO is a partition shared resource. Each partition is set to obtain the index of the sent DMA buffer from the read position after obtaining the FIFO lock. When the partition pushes the index to the FPGA, the FPGA sends the message outward in the order in which it is pushed, and writes the index of the sent DMA buffer to the end of the queue for subsequent recycling.

6. The DMA communication method based on multiple independent partition operating systems according to claim 1, characterized in that: When receiving messages, the partition builds a shared receiving buffer through CoreOS and uses the shared buffer to realize the communication between the underlying FPGA and each partition.

7. The DMA communication method based on multiple independent partition operating systems according to claim 6, characterized in that: In the receiving direction, for a data block of a certain priority level received, the FPGA sends the data block of the priority level to the shared receiving buffer of the partition, where the header of the data block has a multi-bit partition mapping table. CoreOS sends the index value corresponding to the data block to different partitions in sequence according to the header mapping table of the identified data block. Once the partition receives the index value, it reads the data from the shared receiving buffer queue. When all partitions have finished reading the data, CoreOS releases the cache block to the FPGA for subsequent use, completing the data transmission in the receiving direction.

8. The DMA communication method based on multiple independent partition operating systems according to claim 6, characterized in that: Inside the FPGA, CoreOS configures the partition MAP mapping table. The FPGA searches the partition mapping table for each received data to determine whether the received data is unicast, multicast, or broadcast. The data is then written into the data cache block of the shared receive cache queue configured by CoreOS in the form of DMA. CoreOS notifies each partition to read the data in turn according to the partition MAP mapping at the end of each cache block. When all partitions have completed reading, the data block is released to the FPGA for subsequent use.

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