Signal identification method and device, electronic equipment and storage medium

Abstract

The invention provides a signal identification method and device, electronic equipment and a storage medium, the method is applied to a first chip, the first chip comprises an accessor, a processor and a first memory block, and the method comprises the steps that the accessor carries first information in a detector to the first memory block through a first channel, and the first information in the detector is sent to the first memory block through a second channel; carrying the second information to the first memory block through the second channel; the first information comprises trigger type data of an input signal detected by the detector, the second information comprises trigger time data of the input signal, and the input signal is a signal sent to the first chip by a second chip; the processor responds to a first request and carries data in the first memory block to a second memory block; and determining the state information of the input signal according to the data in the second memory block.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technology, and in particular to a signal recognition method, device, electronic device, and computer-readable storage medium. Background Art

[0002] Currently, there are application scenarios where two chips frequently interact with each other. For example, chip A needs to interact with chip B and monitor the system status information of chip B.

[0003] In the related art, chip A generally has a monitoring program that uses interrupts to capture input signals from chip B and obtain edge triggers of the input signals, but this will cause a load burden on the processor (CPU, Central Processing Unit) of chip A. Generally, the higher the frequency of the input signal, the greater the chip load. For example, when the input signal exceeds 400KHz, the CPU load rate for most chips has exceeded 50%; when the input signal exceeds 800KHz, the CPU load rate for most chips has reached 100%; this will inevitably affect other programs in chip A to process other tasks, causing significant pressure and delay. Summary of the invention

[0004] The present disclosure provides a signal recognition method, device, electronic device and storage medium to at least solve the above technical problems existing in the prior art.

[0005] In a first aspect, an embodiment of the present disclosure provides a signal recognition method, the method is applied to a first chip, the first chip includes: an access device, a processor, and a first memory block, the method includes:

[0006] The accessor transfers first information in the detector to the first memory block through the first channel, and transfers second information to the first memory block through the second channel; the first information includes trigger type data of the input signal detected by the detector, the second information includes trigger time data of the input signal, and the input signal is a signal sent by the second chip to the first chip;

[0007] In response to a first request, the processor moves the data in the first memory block to a second memory block; and determines the state information of the input signal according to the data in the second memory block.

[0008] In a second aspect, an embodiment of the present disclosure provides a signal recognition device, the device comprising a first chip, the first chip comprising: an access device, a processor, and a first memory block;

[0009] The access device is used to transfer first information in the detector to the first memory block through the first channel, and to transfer second information to the first memory block through the second channel; the first information includes trigger type data of the input signal detected by the detector, the second information includes trigger time data of the input signal, and the input signal is a signal sent by the second chip to the first chip;

[0010] The processor is used to move the data in the first memory block to the second memory block in response to a first request; and determine the state information of the input signal according to the data in the second memory block.

[0011] In a third aspect, an embodiment of the present disclosure provides an electronic device, the electronic device comprising: a first chip and a second chip; the first chip comprises:

[0012] at least one processor; and

[0013] a memory communicatively connected to the at least one processor; wherein,

[0014] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the signal recognition method.

[0015] In a fourth aspect, an embodiment of the present disclosure provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable a computer to execute the signal recognition method.

[0016] The signal recognition method, device, electronic device and storage medium provided by the embodiment of the present disclosure are applied to a first chip, the first chip includes: an accessor, a processor, and a first memory block, and the method includes: the accessor moves the first information in the detector to the first memory block through the first channel, and moves the second information to the first memory block through the second channel; the first information includes the trigger type data of the input signal detected by the detector, the second information includes the trigger time data of the input signal, and the input signal is a signal sent by the second chip to the first chip; the processor moves the data in the first memory block to the second memory block in response to the first request; and determines the state information of the input signal according to the data in the second memory block. In this way, the trigger type and time data of the input signal are obtained by the detector detection, and the processor determines the state information of the input signal according to the stored data, which not only ensures the accurate identification of the signal state, but also avoids affecting the CPU load rate.

[0017] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 A flow chart of a signal recognition method provided by an embodiment of the present disclosure;

[0019] Figure 2 A connection diagram of an electronic device provided by an embodiment of the present disclosure;

[0020] Figure 3 A schematic diagram of the structure of a first chip provided in an embodiment of the present disclosure;

[0021] Figure 4 A flow chart of a signal recognition method provided for an application embodiment of the present disclosure;

[0022] Figure 5 A schematic diagram of connecting a first chip and a second chip provided in an embodiment of the present disclosure;

[0023] Figure 6 A schematic diagram of another connection between a first chip and a second chip provided in an embodiment of the present disclosure;

[0024] Figure 7 A schematic diagram of a structure of a combination of two sets of detectors and a memory block provided in an embodiment of the present disclosure;

[0025] Figure 8 A schematic diagram of the structure of a signal recognition device provided by an embodiment of the present disclosure;

[0026] Fig. 9 A schematic diagram of the structure of an electronic device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] In order to make the purpose, features, and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0028] Before further describing the embodiments of the present disclosure in detail, the related technologies involved in the embodiments of the present disclosure are described.

[0029] In the related art, due to functional requirements, when it is necessary to detect the frequency and duty cycle of the input signal of a certain input / output (IO) port of the chip, the usual practice is that whenever the edge of the IO changes, the CPU core generates an interrupt, and records the interrupt timestamp and trigger mode (the trigger mode is rising edge trigger or falling edge trigger) in the interrupt function to calculate the frequency and duty cycle of the input signal.

[0030] If the chip uses the above interrupt method to identify input signals, it will inevitably cause a significant CPU load burden. For example, the CPU main frequency of the MCU chip is generally within 600MHz, and each time the CPU responds to an interrupt, it will take about 1us; at the same time, the program in the chip is a multi-task processing program that will handle many tasks at the same time. When the frequency of the IO port input is very high, such as when the external input signal exceeds 100KHz square wave, it will bring a significant increase in the CPU load rate of the program in the MCU chip; when the external input signal exceeds 400KHz, it will bring significant pressure and delay to the program in the MCU chip when processing other tasks; when the external input signal exceeds 800KHz, the MCU chip with a main frequency of 600MHZ can basically not handle other tasks. This will inevitably lead to operational problems of the device to which the chip belongs.

[0031] Based on this, an embodiment of the present disclosure provides a signal recognition method, which is applied to a first chip, and the first chip includes: an accessor, a processor, and a first memory block. The method includes: the accessor moves first information in the detector to the first memory block through a first channel, and moves second information to the first memory block through a second channel; the first information includes trigger type data of the input signal detected by the detector, the second information includes trigger time data of the input signal, and the input signal is a signal sent by the second chip to the first chip; the processor moves the data in the first memory block to the second memory block in response to the first request; and determines the status information of the input signal according to the data in the second memory block.

[0032] like Figure 1 As shown, Figure 1 A flow chart of a signal recognition method provided in an embodiment of the present disclosure is provided. The signal recognition method is applied to a first chip. The first chip includes: an access device, a processor, and a first memory block. The method includes:

[0033] Step 101: The access device transfers first information in the detector to the first memory block through the first channel, and transfers second information to the first memory block through the second channel;

[0034] The first information includes trigger type data of the input signal detected by the detector, and the second information includes trigger time data of the input signal, wherein the input signal is a signal sent from the second chip to the first chip;

[0035] Step 102: The processor moves the data in the first memory block to the second memory block in response to the first request;

[0036] Step 103: The processor determines the state information of the input signal according to the data in the second memory block.

[0037] In some embodiments, the first chip further includes: a first interface, through which the first chip receives an input signal sent by the second chip;

[0038] The method further comprises:

[0039] The detector detects edge changes of the input signal received through the first interface, records the trigger type and trigger time of the input signal when the edge changes, and sends a second request to the access device; the second request is used to instruct the access device to move the first information and the second information.

[0040] Here, the first chip has a first interface, and the first chip communicates with the second chip through the first interface. The first interface and the second interface can be any IO ports. For example, the first chip receives an input signal sent by the second chip through the first interface.

[0041] The detector detects the edge change of the input signal received through the first interface, and records the trigger type and trigger time of the input signal when the edge changes, where the trigger type includes: rising edge trigger and falling edge trigger;

[0042] When determining an edge change, the detector can also send a second request to the access device to request the access device to carry the trigger type data (i.e., the first information) of the input signal detected by the detector and the trigger time data (i.e., the second information) of the input signal detected by the detector.

[0043] In some embodiments, the detector is a device for capturing signals. For example, the detector is an event timer etimer, which can detect events (here, signal edge change events) and event occurrence time.

[0044] The detector can detect edge change events to determine the trigger type of the input signal, and the detector includes a signal type (Signal type) detection unit, a first-in first-out (FIFO) register, and a timer (Capture count). The timer can simultaneously detect the trigger time of the edge change.

[0045] The access device is a direct memory access (DMA), which can manage the process of direct memory access and can move data from one place to another without the intervention of the processor.

[0046] Here, DMA is used to transfer the trigger type data and time data of the input signal detected by the detector to the first memory block. In this way, the above functions are realized by the DMA in the first chip, and the processor (such as CPU core) of the first chip does not need to generate an interrupt for the edge change of the IO port, thereby avoiding the impact on the CPU load rate.

[0047] In some embodiments, the first memory block may be divided into a first part and a second part, the first part being used to store trigger type data, and the second part being used to store trigger time data;

[0048] Accordingly, using DMA to transfer the trigger type data and time data of the input signal detected by the detector to the first memory block includes:

[0049] Using DMA to transfer the trigger type data of the input signal detected by the detector to the first part of the first memory block;

[0050] The trigger time data of the input signal detected by the detector is transferred to the second part of the first memory block by using DMA.

[0051] In some embodiments, the processor may move the data in the first memory block to the second memory block in response to the first request.

[0052] Here, in order to prevent DMA from tampering with the data in the first and second parts (such as DMA continuously moving data to the first memory block, or moving too much data, which may cause the latest data to be tampered with), the processor moves the data in the first memory block to the second memory block.

[0053] It should be noted that the operation of the processor moving data from the first memory block to the second memory block will not cause excessive processor load, which is much smaller than the load rate caused by the processor detecting input signals through interruption.

[0054] In some embodiments, the method further comprises at least one of the following:

[0055] The processor determines a first request based on a polling operation;

[0056] The processor receives an operation instruction sent by the third chip, and determines a first request according to the operation instruction.

[0057] Here, the third chip may be the second chip, or may be another chip connected to the first chip.

[0058] In this way, the processor moves the data in the first memory block to the second memory block in response to the first request.

[0059] Here, the signal recognition method can be applied to various scenarios, such as recognition of encoder signals in robot motion control, recognition of collision signals, oil pump control signals, wheel speed signals and other signals in the automotive field, high-precision current acquisition in the power field, flight data measurement in aerospace testing, and processing of sensor signals in smart homes, etc. The types of input signals in different application scenarios may be different, and the types of input signals are not limited here.

[0060] The way in which the processor obtains the first request may also be different in different scenarios. For example, in the automotive field, typical application scenarios include collision signal detection, oil pump control signal detection, wheel speed signal detection, etc. Correspondingly, the input signal may be a collision signal, a control signal, a wheel speed signal, etc.

[0061] In one example, the processor may determine the first request when polling various programs and polling a detection program such as executing a wheel speed signal or an oil pump control signal;

[0062] In another example, the processor may also be triggered by instructions sent by other chips (such as the second chip), such as receiving an operation instruction sent by the second chip, and determining the first request based on the operation instruction. If the operation instruction triggers the execution of a collision detection program, the first request will be determined during the running of the program.

[0063] Of course, the processor can also determine that data transfer operations need to be performed based on other situations, such as timing, polling, and determining that a certain condition is met, and transfer the data in the first memory block to the second memory block. The specific design is based on actual conditions and is not limited.

[0064] In some embodiments, the first chip further includes: a third memory block and a fourth memory block;

[0065] The method further comprises:

[0066] The processor moves the plurality of trigger type data in the second memory block to the third memory block in chronological order;

[0067] The processor moves the plurality of trigger time data in the second memory block to the fourth memory block in chronological order;

[0068] The time sequence of the multiple trigger type data in the second memory block is marked by the register corresponding to the first channel of the accessor; the time sequence of the multiple trigger time data in the second memory block is marked by the register corresponding to the second channel of the accessor;

[0069] Correspondingly, determining the state information of the input signal according to the data in the second memory block includes:

[0070] The state information of the input signal is determined according to the trigger type data in the third memory block and the trigger time data in the fourth memory block.

[0071] Here, the accessor transfers the first information and the second information to the first memory block through two channels, such as the trigger type channel (first channel) is used to transfer the trigger type data, and the timestamp channel (second channel) is used to transfer the trigger time data;

[0072] Correspondingly, the accessor has a register corresponding to the first channel and a register corresponding to the second channel, such as: the shadow_dst_addr register of the timestamp channel and the shadow_dst_addr register of the trigger type channel, where shadow_dst_addr represents the target address of the current accessor operation. The above registers can clearly know the time sequence of the data transmitted by the corresponding channel;

[0073] In this way, the processor can know the time sequence of the data through the shadow_dst_addr register of the trigger type channel and the shadow_dst_addr register of the timestamp channel, and move the first part of the data of the second memory block (such as multiple trigger type data) to the third memory block according to the time sequence, and move the second part of the data of the second memory block (such as multiple trigger time data) to the fourth memory block according to the time sequence.

[0074] In some embodiments, the state of the input signal may include: a period of the input signal, an input frequency of the input signal, a duty cycle of the input signal, and the like.

[0075] In some embodiments, determining the state information of the input signal according to the data in the second memory block includes:

[0076] The period and / or input frequency of the input signal are determined according to the working clock of the detector and a plurality of trigger time data.

[0077] Here, the operating clock of the detector can be known based on the detector used.

[0078] Since the trigger time data in the fourth memory block are sorted in chronological order, the latest timestamp information (recorded as trigger time data 1), the next latest timestamp information (recorded as trigger time data 2), the next latest timestamp information (recorded as trigger time data 3), and so on can be determined.

[0079] Among them, the multiple trigger time data may include: trigger time data 1 and trigger time data 3.

[0080] Here, the working clock determines the accuracy of time measurement, and the high-frequency clock can provide a more accurate time point. When applied, according to the trigger time data 1 and the trigger time data 3, as well as the working clock of the detector, the actual time 1 (based on the time determined by the trigger time data 1) and the time 3 (based on the time determined by the trigger time data 3) can be known.

[0081] Assume that trigger time data 1 and trigger time data 3 are two rising edge time points, and the period of the input signal is: time 1 - time 3. The input frequency of the input signal is: 1 / (time 1 - time 3).

[0082] In some embodiments, determining the state information of the input signal according to the data in the second memory block includes:

[0083] The duty cycle of the input signal is determined according to the working clock of the detector, a plurality of trigger type data and a plurality of trigger time data.

[0084] In some embodiments, determining the duty cycle of the input signal according to the working clock of the detector, a plurality of trigger type data and a plurality of trigger time data comprises:

[0085] Determine the latest trigger type data among the plurality of trigger type data as the target type data;

[0086] determining target time data from the plurality of trigger time data according to the target type data;

[0087] The duty cycle of the input signal is determined according to the working clock of the detector, the target time data and the period of the input signal.

[0088] Here, the target type data is rising edge trigger or falling edge trigger.

[0089] The operating clock of the detector is known based on the detector used.

[0090] Since the trigger type data in the third memory block are sorted in chronological order, the latest trigger type data (recorded as trigger type data 1), the second latest trigger type data (recorded as trigger type data 2), the third latest trigger type data (recorded as trigger type data 3), and so on can be determined therefrom;

[0091] Similarly, since the trigger time data in the fourth memory block is also sorted in chronological order, the latest timestamp information (recorded as trigger time data 1), the second latest timestamp information (recorded as trigger time data 2), the third latest timestamp information (recorded as trigger time data 3), and so on can be determined.

[0092] According to the latest trigger type data, it can be determined whether the trigger type was a rising edge trigger or a falling edge trigger during the last transport (ie, the target type data is determined).

[0093] When applied, based on the trigger time data and the working clock of the detector, the actual time 1 (the time determined based on trigger time data 1), time 2 (the time determined based on trigger time data 2), time 3 (the time determined based on trigger time data 3), etc. can be known.

[0094] Assume that if the trigger type data 1 (i.e. the latest trigger type data) is a rising edge, the high level time (i.e. the target time data) is: time 2 - time 3;

[0095] If the trigger type data 1 is a falling edge, the high level time (i.e. the target time data) is: time 1-time 2;

[0096] In this way, the time of the high level (ie, the target time data) can be determined.

[0097] Alternatively, the high level time beat may be first calculated based on the trigger time data, and then the high level time may be calculated in combination with the working clock.

[0098] Finally, the duty cycle of the input signal is calculated by combining the high level time and the cycle of the input signal, that is, the high level time / cycle length*100%.

[0099] The method provided by the embodiment of the present disclosure realizes the signal state recognition when the second chip inputs the signal to the interface of the first chip, especially when a high-frequency or ultra-high-frequency square wave is input, and can effectively calculate the frequency and duty cycle of the input signal, while minimizing the impact of the interface on the processor load rate.

[0100] In some embodiments, a design of a trigger type, a trigger time, a first memory block, a second memory block, a third memory block, and a fourth memory block is provided as follows:

[0101] The data size of the trigger time is 4 bytes;

[0102] The data size of the trigger type is 4 bytes;

[0103] The size of the first memory block is 32 bytes (can store 4 trigger time data and 4 trigger type data);

[0104] The size of the second memory block is 32 bytes (can store 4 trigger time data and 4 trigger type data);

[0105] The size of the third memory block is 16 bytes (can store 4 trigger type data);

[0106] The size of the fourth memory block is 16 bytes (can store 4 trigger time data).

[0107] The above design is based on 4-byte numbers, but it can also be other numbers, such as 2 bytes, 6 bytes, 8 bytes, etc. The specific design can be based on actual conditions.

[0108] In some embodiments, the first chip may be: MCU (Microcontroller Unit), IC (Integrated Circuit), SOC, FPGA (Field Programmable Gate Array), microprocessor (MPU), communication integrated circuit, sensor chip, etc.;

[0109] The second chip may be: MCU, IC, SOC, FPGA, MPU, communication integrated circuit, sensor chip, etc.

[0110] The SOC may be a multi-core heterogeneous chip. Multi-core heterogeneity refers to a chip architecture design in which multiple processing cores (cores) are integrated and at least two of these cores are different in structure, function or performance. Some tasks may be more suitable for high-performance general-purpose processor cores, while other tasks may require more specialized processor cores to improve efficiency. Multi-core heterogeneity can better balance factors such as performance, power consumption and cost, and provide more flexible and efficient solutions.

[0111] A multi-core heterogeneous chip refers to a chip that integrates two or more processor cores in a single chip. Each processor core can act as an independent processor and independently run the instructions stored in the memory corresponding to the processor core.

[0112] The processor, the detector, the access device, etc. may be IP / IP cores in a SOC, respectively.

[0113] IP, also known as IP core (Intellectual Property Core), refers to the mature design of a circuit module with independent functions in a chip. This circuit module design can be applied to other chip design projects that contain this circuit module, thereby reducing the design workload, shortening the design cycle, and improving the success rate of chip design. IP core can also be understood as an intermediate component of chip design.

[0114] The processor, the detector, the access device, etc. may belong to a multi-purpose domain (MP) in the SOC, or may belong to different multi-purpose domains. The processor, the detector, the access device, etc. may belong to an application domain, or may belong to different application domains. The processor, the detector, the access device, etc. may belong to a safety domain in the SOC, or may belong to different safety domains.

[0115] A hardware domain is a set of hardware that may include hardware resources such as processor cores, interrupt controllers, clock controllers, and memory. The number of processor cores in a hardware set may be one or more. One hardware domain runs one operating system, and different hardware domains may run different operating systems.

[0116] Application domain: refers to one or more hardware domains, which means that the hardware domain has strong computing performance and can support application programs with high computing performance requirements.

[0117] Security domain: is one or more hardware domains, including at least one of the following characteristics: having a high functional safety architecture, running an operating system that meets high functional safety requirements, and processing tasks that require high functional safety.

[0118] The multifunctional domain is one or more hardware domains, which are configured with processor components with certain processing capabilities and specific hardware components that respond to various different requirements, such as a first processor and a second processor, for processing various types of tasks.

[0119] In some embodiments, the method in the embodiments of the present disclosure can be applied to chips in transportation equipment, including but not limited to balance vehicles, cars, buses, subways, trains, and airplanes.

[0120] like Figure 2 In one example provided, a traffic device has a first chip and a second chip, and the first chip and the second chip are respectively responsible for controlling different systems or different functions, and the two need to interact.

[0121] The first chip is an MCU, and the second chip is an IC. The MCU can detect the signal state of a level signal (ie, an input signal) sent by the IC.

[0122] Figure 3 A schematic diagram of the structure of a first chip provided in an embodiment of the present disclosure; Figure 3 As shown, the first chip includes: CPU, DMA, etimer, first memory block, second memory block, third memory block, and fourth memory block. DMA is used to transfer data, CPU is used to transfer data and perform calculations; etimer is used to capture input signals, and etimer includes: signal type detection unit (i.e. Figure 3 Signal type in), FIFO register (ie Figure 3 FIFO in), timer (i.e. Figure 3 Capturecount in .

[0123] DMA has two transmission channels, which are configured as follows:

[0124] The configuration of transmission channel 1 includes:

[0125] Transfer type: DEV2MEM, that is, DMA moves data from registers to the first memory block;

[0126] Transfer mode: continuous, that is, the DMA working mode is continuous. As long as there is a trigger signal, the DMA transfer will be triggered once and will never stop;

[0127] Memory mode: CIRCULAR, that is, the memory address block of the DMA operation is a circular overwrite type,

[0128] Source address increment: No, that is, the timestamp data is the address of a fixed register;

[0129] Target address increment: Yes, that is, the timestamp data is stored in the target address in a circular overwriting manner;

[0130] Source address width: 4, that is, the timestamp data size is 4 bytes;

[0131] Target address width: 4, that is, the timestamp data size is 4 bytes;

[0132] Source address burst length: 1, that is, each DMA trigger only moves 1 timestamp data;

[0133] Target address burst length: 1, that is, each DMA trigger only moves 1 timestamp data;

[0134] Interrupt type: 0, that is, in order to minimize the CPU load rate, DMA does not generate interrupts;

[0135] Trigger mode: hardware;

[0136] Source address: the address of the etimer channel fifo;

[0137] Target address: first memory block, variable name: dma_test_des1;

[0138] Transmission length: (total_array_number*4), where total_array_number indicates the number of timestamp data, such as 4, where 4 indicates that each timestamp is 4 bytes.

[0139] The configuration of transmission channel 2 includes:

[0140] Transfer type: DEV2MEM, that is, DMA moves data from registers to the first memory block;

[0141] Transfer mode: continuous, that is, the DMA working mode is continuous. As long as there is a trigger signal, the DMA transfer will be triggered once and will never stop;

[0142] Memory mode: CIRCULAR, that is, the memory address block of the DMA operation is a circular overwrite type;

[0143] Source address increment: No, that is, the trigger type data is the address of a fixed register;

[0144] Target address increment: Yes, that is, the trigger type data is stored in the target address in a circular overwriting manner;

[0145] Source address width: 4, that is, the trigger type data size is 4 bytes;

[0146] Target address width: 4, that is, the trigger type data size is 4 bytes;

[0147] Source address burst length: 1, that is, each DMA trigger only moves 1 trigger type data;

[0148] Target address burst length: 1, that is, each DMA trigger only moves 1 trigger type data;

[0149] Interrupt type: 0, that is, in order to minimize the CPU load rate, DMA does not generate interrupts;

[0150] Trigger mode: hardware;

[0151] Source address: address of etimer signal status (signal type);

[0152] Target address: first memory block, variable name: dma_test_des2;

[0153] Transmission length: (total_array_number*4), where total_array_number indicates the number of trigger type data, such as 4, and 4 indicates that each trigger type data is 4 bytes.

[0154] In actual application, the electronic device starts the DMA and etimer input capture functions (at this time, the etimer will not generate an interrupt, and the DMA will not generate an interrupt), detects the input signal and inputs the frequency and duty cycle of the signal. Figure 3 The structure shown in the figure, the method of the embodiment of the present disclosure is as follows Figure 4 As shown, specifically including:

[0155] Step 401: The CPU clears the cache in the CPU, so that the CPU reads data from the first memory block;

[0156] It should be noted that due to the working mechanism of the CPU, it will first read its own cache. If there is no data, it will read data from other memory blocks. Therefore, the dma_test_des 1 and dma_test_des2 of the memory block (cache) of the CPU variables are refreshed here to clear them, so that the CPU reads data from the first memory block.

[0157] Of course, the CPU may also be set (such as disabling the cache function) so that it reads data directly from the first memory block when executing the method disclosed herein.

[0158] Step 402, the CPU copies all variables dma_test_des1 and dma_test_des2 (a total of 32 bytes of data) to new_data_array;

[0159] In this way, DMA is prevented from tampering with the data from dma_test_des1 and dma_test_des2 to new_data_array.

[0160] Step 403, the CPU carries out data transfer according to the shadow_dst_addr register of the DMA timestamp channel and the shadow_dst_addr register of the DMA trigger type channel;

[0161] Among them, the shadow_dst_addr register of DMA indicates the target address of the current DMA operation;

[0162] Data handling includes:

[0163] Move the first four data (timestamp data) of the new_data_array variable to time_data_array in chronological order; and,

[0164] Move the last four data (trigger type data) of the new_data_array variable to type_data_array in chronological order.

[0165] Step 403: The CPU calculates the input frequency and / or period of the input signal;

[0166] According to the data of time_data_array[total_array_number-1] and time_data_array[total_array_number-3], as well as the working clock of etimer, the current actual cycle can be known, and then the input frequency of the input signal can be calculated.

[0167] Among them, time_data_array[total_array_number-1] is the latest timestamp information;

[0168] time_data_array[total_array_number-2] is the latest timestamp information;

[0169] time_data_array[total_array_number-3] is the latest timestamp information, and so on.

[0170] Step 404: The CPU calculates the duty cycle of the input signal.

[0171] Based on the value of type_data_array[total_array_number-1], it can be determined whether the last transfer was triggered by a rising edge or a falling edge.

[0172] If type_data_array[total_array_number-1] is a rising edge, the time beat of the high level is:

[0173] time_data_array[total_array_number-2]-time_data_array[total_array_number-3].

[0174] If type_data_array[total_array_number-1] is a falling edge, the high level time beat is:

[0175] time_data_array[total_array_number-1]-time_data_array[total_array_number-2].

[0176] Then, the high level time can be calculated based on the working clock of the etimer. Combined with the period calculated in step 403, the duty cycle of the input signal can be obtained.

[0177] Figure 5 A schematic diagram of a connection between a first chip and a second chip provided in an embodiment of the present disclosure; Figure 5 As shown, the first chip may have a plurality of first interfaces, and each interface may be connected to a second chip respectively.

[0178] Figure 6 A schematic diagram of another connection between a first chip and a second chip provided in an embodiment of the present disclosure; Figure 6 As shown, the first chip may also have multiple first interfaces connected to different interfaces of the same second chip and different interfaces of different second chips.

[0179] The first chip can use the above signal identification method to identify the signal status for input signals from different second chips received through different first interfaces. If multiple input signals need to be identified at the same time, there can be a combination of multiple sets of detectors and memory blocks; each combination of detectors and memory blocks includes: a detector, a first memory block, a second memory block, a third memory block, and a fourth memory block.

[0180] like Figure 7 As shown, an example of a combination of two groups of detectors and memory blocks is provided. If more groups are needed, they can be adaptively increased, which will not be described in detail here.

[0181] Figure 8 A schematic diagram of the structure of a signal recognition device provided by an embodiment of the present disclosure; Figure 8 As shown, the device includes a first chip and a second chip, wherein the first chip includes: an access device, a processor, and a first memory block;

[0182] The access device is used to transfer first information in the detector to the first memory block through the first channel, and to transfer second information to the first memory block through the second channel; the first information includes trigger type data of the input signal detected by the detector, the second information includes trigger time data of the input signal, and the input signal is a signal sent by the second chip to the first chip;

[0183] The processor is used to move the data in the first memory block to the second memory block in response to a first request; and determine the state information of the input signal according to the data in the second memory block.

[0184] In some embodiments, the first chip further includes: a first interface, through which the first chip receives an input signal sent by the second chip;

[0185] The detector is used to detect the edge change of the input signal received through the first interface, record the trigger type and trigger time of the input signal when the edge changes, and send a second request to the access device; the second request is used to instruct the access device to move the first information and the second information.

[0186] In some embodiments, the first chip further includes: a third memory block and a fourth memory block;

[0187] The processor is further configured to transfer the plurality of trigger type data in the second memory block to the third memory block in chronological order;

[0188] Moving the plurality of trigger time data in the second memory block to the fourth memory block in chronological order;

[0189] The time sequence of the multiple trigger type data in the second memory block is marked by the register corresponding to the first channel of the accessor; the time sequence of the multiple trigger time data in the second memory block is marked by the register corresponding to the second channel of the accessor;

[0190] Correspondingly, the processor is used to determine the state information of the input signal according to the trigger type data in the third memory block and the trigger time data in the fourth memory block.

[0191] In some embodiments, the processor is used to determine the period and / or input frequency of the input signal based on the working clock of the detector and multiple trigger time data.

[0192] In some embodiments, the processor is used to determine the duty cycle of the input signal based on the working clock of the detector, multiple trigger type data and multiple trigger time data.

[0193] In some embodiments, the processor is used to determine the latest trigger type data among the plurality of trigger type data as the target type data;

[0194] determining target time data from the plurality of trigger time data according to the target type data;

[0195] The duty cycle of the input signal is determined according to the working clock of the detector, the target time data and the period of the input signal.

[0196] In some embodiments, the processor is further configured to perform at least one of the following:

[0197] Based on the polling operation, determining a first request;

[0198] An operation instruction sent by the third chip is received, and a first request is determined according to the operation instruction.

[0199] The specific working process of the device can refer to the relevant description in the aforementioned method embodiment, which will not be repeated here.

[0200] The embodiment of the present disclosure also provides a component on a traffic device, wherein the component includes a chip, and the chip can execute the above-mentioned signal recognition method.

[0201] In some embodiments, the components may be circuit board-level components, automotive electrical system-level components, or automotive assembly components. As an example, the components may be the engine, chassis, body, and electrical and electronic equipment of the vehicle. The electrical and electronic equipment of the vehicle may include headlights for lighting, management equipment for controlling the engine, and central control equipment for receiving broadcasts, navigation, listening to music, and entertainment.

[0202] The embodiment of the present disclosure also provides a transportation device, the transportation device includes a chip. The chip can execute the above signal recognition method. The first chip can be a multi-core heterogeneous chip, and the transportation device includes but is not limited to a balance car, a car, a bus, a train, etc.

[0203] An embodiment of the present disclosure provides a computer-readable storage medium storing executable instructions, wherein the executable instructions are stored. When the executable instructions are executed by a processor, the processor will be triggered to execute the signal recognition method provided by the embodiment of the present disclosure.

[0204] In some embodiments, the computer-readable storage medium may be a ferroelectric random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disk, or a CD-ROM; it may also be various devices including one or any combination of the above memories.

[0205] In some embodiments, executable instructions may be in the form of a program, software, software module, script or code, written in any form of programming language (including compiled or interpreted languages, or declarative or procedural languages), and may be deployed in any form, including as a stand-alone program or as a module, model, subroutine or other unit suitable for use in a computing environment.

[0206] By way of example, executable instructions may be deployed to be executed on one computing device, or on multiple computing devices located at one site, or on multiple computing devices distributed across multiple sites and interconnected by a communication network.

[0207] An embodiment of the present disclosure provides a computer program product, which includes a computer program / instructions. When the computer program / instructions are executed by a processor, the signal recognition method described in the present disclosure is implemented.

[0208] Fig. 9 A schematic diagram of the structure of an electronic device provided for an embodiment of the present disclosure. Device 900 is intended to represent various forms of digital computers, such as controllers, laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0209] like Fig. 9As shown, the device 900 includes a computing unit 901, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 902 or a computer program loaded from a storage unit 908 into a random access memory (RAM) 903. In the RAM 903, various programs and data required for the operation of the device 900 can also be stored. The computing unit 901, the ROM 902, and the RAM 903 are connected to each other via a bus 904. An input / output (I / O) interface 905 is also connected to the bus 904.

[0210] A number of components in the device 900 are connected to the I / O interface 905, including: an input unit 906, such as a keyboard, a mouse, etc.; an output unit 907, such as various types of displays, speakers, etc.; a storage unit 908, such as a disk, an optical disk, etc.; and a communication unit 909, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 909 allows the device 900 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0211] The computing unit 901 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 901 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 901 performs the various methods and processes described above, such as a signal recognition method. For example, in some embodiments, the signal recognition method may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 908. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 900 via ROM 902 and / or a communication unit 909. When the computer program is loaded into RAM 903 and executed by the computing unit 901, one or more steps of the signal recognition method described above may be performed. Alternatively, in other embodiments, the computing unit 901 may be configured to perform the signal recognition method in any other appropriate manner (e.g., by means of firmware).

[0212] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0213] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0214] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0215] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0216] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0217] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0218] In the above description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0219] Unless otherwise defined, all technical and scientific terms used in this disclosure have the same meaning as those commonly understood by those skilled in the art to which this disclosure belongs. The terms used in this disclosure are only for the purpose of describing the embodiments of this disclosure and are not intended to limit this disclosure.

[0220] It should be understood that in the various embodiments of the present disclosure, the size of the serial number of each implementation process does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present disclosure.

[0221] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0222] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A signal recognition method, characterized in that: The method is applied to a first chip, the first chip includes: an access device, a processor, and a first memory block, and the method includes: The accessor transfers first information in the detector to the first memory block through the first channel, and transfers second information to the first memory block through the second channel; the first information includes trigger type data of the input signal detected by the detector, the second information includes trigger time data of the input signal, and the input signal is a signal sent by the second chip to the first chip; In response to a first request, the processor moves the data in the first memory block to a second memory block; and determines the state information of the input signal according to the data in the second memory block.

2. The method according to claim 1, characterized in that The first chip further includes: a first interface, through which the first chip receives an input signal sent by the second chip; The method further comprises: The detector detects edge changes of the input signal received through the first interface, records the trigger type and trigger time of the input signal when the edge changes, and sends a second request to the access device; the second request is used to instruct the access device to move the first information and the second information.

3. The method according to claim 1, characterized in that The first chip further includes: a third memory block and a fourth memory block; The method further comprises: The processor moves the plurality of trigger type data in the second memory block to the third memory block in chronological order; The processor moves the plurality of trigger time data in the second memory block to the fourth memory block in chronological order; The time sequence of the multiple trigger type data in the second memory block is marked by the register corresponding to the first channel of the accessor; the time sequence of the multiple trigger time data in the second memory block is marked by the register corresponding to the second channel of the accessor; Correspondingly, determining the state information of the input signal according to the data in the second memory block includes: The state information of the input signal is determined according to the trigger type data in the third memory block and the trigger time data in the fourth memory block.

4. The method according to claim 1 or 3, characterized in that: Determining the state information of the input signal according to the data in the second memory block includes: The period and / or input frequency of the input signal are determined according to the working clock of the detector and a plurality of trigger time data.

5. The method according to claim 4, characterized in that Determining the state information of the input signal according to the data in the second memory block includes: The duty cycle of the input signal is determined according to the working clock of the detector, a plurality of trigger type data and a plurality of trigger time data.

6. The method according to claim 5, characterized in that Determining the duty cycle of the input signal according to the working clock of the detector, a plurality of trigger type data and a plurality of trigger time data, comprising: Determine the latest trigger type data among the plurality of trigger type data as the target type data; determining target time data from the plurality of trigger time data according to the target type data; The duty cycle of the input signal is determined according to the working clock of the detector, the target time data and the period of the input signal.

7. The method according to claim 1, characterized in that The method further comprises at least one of the following: The processor determines a first request based on a polling operation; The processor receives an operation instruction sent by the third chip, and determines a first request according to the operation instruction.

8. A signal recognition device, characterized in that: The device comprises a first chip, wherein the first chip comprises: an access device, a processor, and a first memory block; The access device is used to transfer first information in the detector to the first memory block through the first channel, and to transfer second information to the first memory block through the second channel; the first information includes trigger type data of the input signal detected by the detector, the second information includes trigger time data of the input signal, and the input signal is a signal sent by the second chip to the first chip; The processor is used to move the data in the first memory block to the second memory block in response to a first request; and determine the state information of the input signal according to the data in the second memory block.

9. An electronic device, characterized in that: The electronic device comprises: a first chip and a second chip; the first chip comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 7.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that: The computer instructions are used to make a computer execute the method according to any one of claims 1 to 7.

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