Multiprocessor module curing and starting method based on FPGA (Field Programmable Gate Array)
By introducing FPGA into the multiprocessor module, the read and write control of CPU and FLASH is realized, which solves the problem of curing errors and loss of functions during the curing and startup process of traditional multiprocessor modules, and improves the flexibility and reliability of the system.
Patent Information
- Application Number
- CN202411446465.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-16
- Publication Date
- 2025-02-14
AI Technical Summary
Traditional multiprocessor modules have curing errors and loss of function during curing and starting up, and cannot be restored online and need to be recured offline through external devices.
By intervening the FPGA between the CPU and NOR FLASH, the FPGA control is used to realize the read and write operations of the CPU and FLASH, ensuring that the CPU can start normally in abnormal situations, the NOR FLASH data can be read, and no external devices are required. Curing FLASH.
It improves the flexibility of multi-CPU curing and startup and system reliability, avoids the loss of function caused by curing errors in traditional methods, and realizes automatic recovery in abnormal situations.
Smart Images
Figure CN119441126A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of avionics systems, and in particular to a method for curing and starting a multi-processor module based on a field programmable logic device (FPGA). Background Art
[0002] In the field of avionics systems, for front-end data such as radar signals, the back-end data processing unit requires a large amount of computer resources to process massive amounts of data. At this time, one processor often cannot meet the demand, which results in a single module with multiple processors.
[0003] The processor in this module is usually composed of multiple central processing units (CPUs) and FPGAs, and each CPU and FPGA needs to be configured with a separate non-volatile memory NOR FLASH to store the running program.
[0004] 1. Traditional multi-processor module solidification structure
[0005] The hardware structure of the traditional multi-processor module is as follows Figure 1 As shown in the figure, each CPU is connected to NOR FLASH through QSPI interface. At the same time, the power-on signal of CPU is connected to FPGA, and FPGA realizes the power-on control of CPU.
[0006] 2. Traditional multi-processor module curing and startup process
[0007] The traditional multi-processor module startup process is as follows Figure 2 As shown in the figure, after the module is powered on, the FPGA is powered on first, and the program is read from the FLASH and runs. After the FPGA starts normally, the CPU is powered on according to the power-on sequence required by the CPU. After the CPU completes power-on reset and initialization, it reads the program from the NOR FLASH through the QSPI interface and runs it. If the QSPI read instruction fails, the CPU startup fails.
[0008] The QSPI interface of NOR FLASH is only connected to the CPU, and the curing operation is performed by the CPU through QSPI write instructions.
[0009] 3. Traditional multi-processor module curing and startup defects
[0010] The traditional multi-processor module has a fixed curing and startup method, which can only be cured to the corresponding NOR FLASH through the CPU, and the NOR FLASH can only store the running program of the corresponding CPU. If an incorrect program is cured or an erroneous operation is made on the FLASH during program operation, the program in the NOR FLASH will be abnormal, causing the CPU to fail to start normally and lose its function.
[0011] At this time, the function cannot be restored through online operation. It can only be restored offline by connecting the CPU through an external device and re-hardening NORFLASH. Summary of the invention
[0012] The invention aims to provide a multi-processor module curing and startup method based on FPGA, which inserts FPGA between CPU and NOR FLASH. Through the control of FPGA, CPU can read and write NOR FLASH, FPGA can read and write NOR FLASH, and CPU can read and write FPGA, so as to ensure that CPU can start normally when the program in NOR FLASH is abnormal, NOR FLASH data can be read when CPU is abnormal, and NOR FLASH can be cured without external equipment, thereby improving the flexibility of multi-CPU curing and startup and system reliability.
[0013] The object of the present invention is achieved through the following technical solutions:
[0014] A multi-processor module curing and startup method based on FPGA, wherein the multi-processor module includes several CPUs, several FLASHs and an FPGA, characterized in that the CS signal of the CPU QSPI interface is connected to the FPGA, and the CS of the FLASH is given by the FPGA; the three signals MISO, MOSI and SCK in the CPU QSPI interface are connected to both the FLASH and the FPGA; the HOLD and WP in the CPU QSPI interface are only connected to the FLASH; the power-on signal of the CPU is connected to the FPGA;
[0015] According to the above-mentioned multi-processing module, the normal curing and starting mode of the CPU is realized, and when an abnormality occurs, the FPGA cures the FLASH mode and the FPGA starts the CPU mode.
[0016] According to the above characteristics, the normal curing and startup methods of the CPU are:
[0017] After the FPGA is powered on, the CS signal output by the CPU to the FPGA is transparently transmitted to the FLASH. At the same time, the pins connected to the MOSI, MISO, and SCK of the FPGA are configured to a high-impedance state, and then the CPU is powered on according to the power-on timing required by the CPU. After the CPU is powered on, the program in the FLASH is read and run through the QSPI interface. After the CPU program is running, the FLASH is accessed through the QSPI interface for read and write operations to complete the solidification of the CPU running program.
[0018] According to the above characteristics, the FPGA solidification FLASH method is:
[0019] After the FPGA is powered on, the pin connected to MOSI is configured as output, the pin connected to MISO is configured as input, and the pin connected to SCK is configured as output. Finally, the CS signal output to FLASH is pulled low. Then, according to the NOR FLASH instruction required by FLASH, the FPGA implements the read and write operations on FLASH through the SPI interface composed of MOSI / MISO / SCK / CS, and completes the CPU running program solidification.
[0020] At this time, the CPU does not receive the power-on signal, and the HOLD / WP / MISO / MOSI / SCK / CS signals of the QSPI interface are all in high-impedance state.
[0021] According to the above characteristics, the FPGA starts the CPU in the following ways:
[0022] After the FPGA is powered on, the pin connected to the CPU CS is configured as input, the pin connected to MOSI is configured as input, the pin connected to MISO is configured as output, the pin connected to SCK is configured as input, and the pin connected to FLASH CS is configured as high-impedance state; then the FPGA powers on the CPU, and after the CPU completes initialization, it reads data through the QSPI interface; at this time, the FPGA, as an SPI slave device, responds to the SPI bus read operation initiated by the CPU according to the NOR FLASH instruction required by the CPU, and sends the CPU running program to the CPU. The CPU completes the startup after successfully reading the running program from the FPGA.
[0023] The beneficial effects of the present invention are:
[0024] The present invention does not need to add redundant devices to the hardware architecture of the traditional multi-processor module. By connecting some signals of the CPU's QSPI interface to the architecture of the FPGA and different configuration modes of the FPGA, the normal curing and starting method of the CPU, the FPGA curing FLASH method and the FPGA starting CPU method are realized, thereby increasing the diversity of CPU curing and starting, as well as the stability of the system.
[0025] The present invention can be applied to multiple processor modules and has significant application prospects. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 The hardware structure diagram of the traditional multi-processor module.
[0027] Figure 2 The startup flowchart of the traditional multi-processor module.
[0028] Figure 3A schematic diagram of the FPGA-based multi-processor module curing and startup method provided by the present invention. DETAILED DESCRIPTION
[0029] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.
[0030] The embodiment shows a method for curing and starting a multi-processor module based on FPGA, wherein the multi-processor module includes several CPUs, several FLASH and an FPGA, and the structure is as follows: Figure 3 As shown in the figure: Based on the traditional architecture, the CS signal of the CPU QSPI interface is connected to the FPGA, and the CS of the FLASH is given by the FPGA. The three signals MISO, MOSI, and SCK in the CPU QSPI interface are connected to both the FLASH and the FPGA. The HOLD and WP in the CPU QSPI interface are only connected to the FLASH. The power-on signal of the CPU is connected to the FPGA.
[0031] According to the above-mentioned multi-processing module, it is possible to realize the normal curing and starting mode of the CPU and the curing FLASH mode by the FPGA and the starting mode of the CPU by the FPGA when an abnormality occurs.
[0032] 1. Normal CPU curing and startup method
[0033] The normal curing and startup method of the CPU is the same as the curing method of the traditional multi-processor module. The running program is cured into the FLASH by the CPU, and the CPU reads the running program from the FLASH and runs it.
[0034] In this way, after the FPGA is powered on, the CS signal output by the CPU to the FPGA is transparently transmitted to the FLASH, and the pins connected to the MOSI, MISO, and SCK of the FPGA are configured to a high impedance state, and then the CPU is powered on according to the power-on timing required by the CPU. Figure 2 After the CPU program is running, the FLASH is accessed through the QSPI interface for read and write operations, which can complete the solidification of the CPU running program.
[0035] 2. FPGA solidification FLASH method
[0036] FPGA solidification FLASH means solidifying the CPU running program into FLASH through FPGA.
[0037] In this way, after the FPGA is powered on, the pin connected to MOSI is configured as output, the pin connected to MISO is configured as input, the pin connected to SCK is configured as output, and finally the CS signal output to FLASH is pulled low. Then, according to the NOR FLASH instruction required by FLASH, the FPGA implements the read and write operations of FLASH through the SPI interface composed of MOSI / MISO / SCK / CS, and completes the solidification of the CPU running program.
[0038] At this time, the CPU does not receive the power-on signal, and the HOLD / WP / MISO / MOSI / SCK / CS signals of the QSPI interface are all in high-impedance state.
[0039] 3. FPGA starts CPU mode
[0040] The FPGA-starting CPU mode means that the CPU reads and runs the program through the FPGA.
[0041] In this way, after the FPGA is powered on, the pin connected to the CPU CS is configured as input, the pin connected to MOSI is configured as input, the pin connected to MISO is configured as output, the pin connected to SCK is configured as input, and the pin connected to FLASHCS is configured as high impedance. Then the FPGA powers on the CPU, and the CPU follows Figure 2 After the initialization is completed, the data is read through the QSPI interface (the working mode is SPI mode). At this time, the FPGA, as a SPI slave device, responds to the SPI bus read operation initiated by the CPU according to the NOR FLASH instruction required by the CPU, and sends the CPU running program to the CPU. The CPU completes the startup after successfully reading the running program from the FPGA.
[0042] The following is an explanation using a specific use case.
[0043] 1. Use case hardware architecture
[0044] This use case uses the FMQL45T900 launched by Fudan Microelectronics as the FPGA, the Tengrui D2000 launched by Feiteng Information Technology Co., Ltd. as the CPU, and the HCEFLB01GBN of Sevenstar Microelectronics as the CPU's FLASH.
[0045] The multiprocessor module has 1 FPGA, 4 CPUs and 16 FLASHs, of which each CPU is equipped with 4 FLASHs to form a 512MB storage space. The FLASH corresponding to chip select 0 stores the CPU boot program (UBOOT).
[0046] The pin connection relationship between CPU0, FPGA and 4 FLASH chips is shown in Table 1, where pins in the same row are connected together. The connection relationship between CPU1 / CPU2 / CPU3 and FPGA and matching FLASH is omitted.
[0047] Table 1 Use case hardware architecture pin connection table
[0048] CPU0 FPGA FLASH0 FLASH1 FLASH2 FLASH3 QSPI_SCK B16 SCLK SCLK SCLK SCLK QSPI_SO_IO0 B17 SI(IO0) SI(IO0) SI(IO0) SI(IO0) QSPI_SI_IO1 A17 SO(IO1) SO(IO1) SO(IO1) SO(IO1) QSPI_WP_IO2 WP#(IO2) WP#(IO2) WP#(IO2) WP#(IO2) QSPI_HOLD_IO3 IO3 IO3 IO3 IO3 QSPI_CSN0 E5 QSPI_CSN1 E2 QSPI_CSN2 F3 QSPI_CSN3 E6 E3 CS# E2 CS# F3 CS# E6 CS#
[0049] 2. Use case implementation method
[0050] 2.1 Normal CPU curing and startup method
[0051] a) Power on the FPGA.
[0052] b) Configure the FPGA to output the signal input by E5 through E3, and set E2, F3, and E6 to high impedance state.
[0053] c) Configure the FPGA and set the B16, B17, and A17 pins to high impedance.
[0054] d) Configure the FPGA and power on the CPU.
[0055] e) After the CPU is powered on, QSPI_CSN0 is set to low by default, and UBOOT is read from FLASH0 and runs.
[0056] f) While the CPU program is running, FLASH0 can be read and written by setting QSPI_CSN0 to low.
[0057] 2.2FPGA solidification FLASH method
[0058] a) Power on the FPGA.
[0059] b) Configure the FPGA to set B16 as SPI clock output, B17 as SPI MOSI output, and A17 as SPI MISO input.
[0060] c) Configure FPGA, set E3 to output low, and perform SPI communication with FLASH0.
[0061] d) Load the CPU program into the DDR or FLASH of the FPGA via Ethernet or any other method.
[0062] e) FPGA initiates SPI read and write instructions to burn the CPU program into FLASH0.
[0063] 2.3FPGA startup CPU method
[0064] a) Power on the FPGA.
[0065] b) Configure the FPGA to set B16 as SPI clock input, B17 as SPI MOSI input, A17 as SPI MISO output, and E5 as SPI CS input.
[0066] c) Configure the FPGA to set E3 to output high.
[0067] d) Configure the FPGA and power on the CPU.
[0068] e) After the CPU is powered on, QSPI_CSN0 outputs 0 by default and initiates a FLASH read instruction through the SPI mode of the QSPI interface.
[0069] f) After receiving the SPI read FLASH instruction, the FPGA returns the CPU running program stored in DDR or FLASH to the CPU to complete the CPU startup.
[0070] It is understandable that those skilled in the art can make equivalent substitutions or changes based on the technical solution and inventive concept of the present invention, and all these changes or substitutions should fall within the protection scope of the claims attached to the present invention.
Claims
1. A method for curing and starting a multi-processor module based on FPGA, wherein the multi-processor module comprises a plurality of CPUs, a plurality of FLASHs and an FPGA, characterized in that: Connect the CS signal of the CPU QSPI interface to the FPGA, and the CS of the FLASH is given by the FPGA; the three signals MISO, MOSI, and SCK in the CPU QSPI interface are connected to both the FLASH and the FPGA; the HOLD and WP in the CPU QSPI interface are only connected to the FLASH; the power-on signal of the CPU is connected to the FPGA; According to the above-mentioned multi-processing module, the normal curing and starting mode of the CPU is realized, and when an abnormality occurs, the FPGA cures the FLASH mode and the FPGA starts the CPU mode.
2. The method for curing and starting a multi-processor module based on FPGA according to claim 1, characterized in that The normal curing and startup methods of the CPU are: After the FPGA is powered on, the CS signal output by the CPU to the FPGA is transparently transmitted to the FLASH. At the same time, the pins connected to the MOSI, MISO, and SCK of the FPGA are configured to a high-impedance state, and then the CPU is powered on according to the power-on timing required by the CPU. After the CPU is powered on, the program in the FLASH is read and run through the QSPI interface. After the CPU program is running, the FLASH is accessed through the QSPI interface for read and write operations to complete the solidification of the CPU running program.
3. The method for curing and starting a multi-processor module based on FPGA according to claim 1, characterized in that FPGA solidification FLASH method is: After the FPGA is powered on, the pin connected to MOSI is configured as output, the pin connected to MISO is configured as input, and the pin connected to SCK is configured as output. Finally, the CS signal output to FLASH is pulled low. Then, according to the NORFLASH instruction required by FLASH, the FPGA implements the read and write operations of FLASH through the SPI interface composed of MOSI / MISO / SCK / CS, and completes the solidification of the CPU running program. At this time, the CPU does not receive the power-on signal, and the HOLD / WP / MISO / MOSI / SCK / CS signals of the QSPI interface are all in high-impedance state.
4. The method for curing and starting a multi-processor module based on FPGA according to claim 1, characterized in that The FPGA starts the CPU in the following ways: After the FPGA is powered on, the pin connected to the CPU CS is configured as input, the pin connected to MOSI is configured as input, the pin connected to MISO is configured as output, the pin connected to SCK is configured as input, and the pin connected to FLASH CS is configured as high-impedance state; then the FPGA powers on the CPU, and after the CPU completes initialization, it reads data through the QSPI interface; at this time, the FPGA, as an SPI slave device, responds to the SPI bus read operation initiated by the CPU according to the NOR FLASH instruction required by the CPU, and sends the CPU running program to the CPU. The CPU completes the startup after successfully reading the running program from the FPGA.