Asynchronous signal processing method and device based on CPU + FPGA architecture
By segmenting the simulation model in the CPU+FPGA architecture and performing serialization and synchronization processing, the problem that asynchronous signals cannot be effectively synchronized in the power data simulation system is solved, efficient and accurate signal synchronization processing is achieved, and hardware is reduced Resource overhead.
Patent Information
- Application Number
- CN202411486946.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-23
- Publication Date
- 2025-02-14
AI Technical Summary
In the power data simulation system of CPU+FPGA architecture, asynchronous signals cannot be effectively synchronized, resulting in errors in simulation results. The existing synchronization processing methods are expensive and have poor economical benefits.
By segmenting the preset simulation model in the CPU and FPGA, the CPU simulation model serializes the first simulation signal that needs to be passed to the FPGA simulation model. The FPGA simulation model extracts effective data from the second simulation signal and passes the The counter, comparator and register matrix are synchronized to obtain the synchronization signal corresponding to the first simulation signal.
The precise extraction and real-time synchronization processing of the asynchronous signals passed by the CPU to the FPGA is realized, which avoids calculation errors caused by asynchronous signal processing, reduces the overhead of hardware resources, and improves processing efficiency and hardware resource utilization.
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Figure CN119443002A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of data processing technology, and in particular to an asynchronous signal processing method and device based on a CPU+FPGA architecture. Background Art
[0002] Real-time simulation is an effective tool for studying and simulating the characteristics of renewable energy and power electronic equipment, and for power system analysis and fault prevention. In the field of real-time simulation, FPGA (Field Programmable Gate Array) has become an important computing platform for real-time simulation because of its powerful computing power. It can realize more computing tasks in the same time and solve larger-scale power electronic systems. Its simulation step size is less than microseconds to sub-microseconds. However, most control systems in the physical world have a time scale of tens of microseconds. The simulation step size of real-time simulation does not need to be very small, and it is much larger than the simulation step size of FPGA real-time simulation. At the same time, considering the hardware cost and the difficulty of simulation implementation, the CPU (Central Processing Unit) is generally used as the computing platform to meet the requirements. In this context, CPU+FPGA has become the most promising real-time simulation architecture that comprehensively considers the scale and cost of real-time simulation.
[0003] However, in a heterogeneous system such as CPU+FPGA, the CPU uses a large step size for simulation, and the FPGA uses a small step size for simulation. The two different hardware resources need to synchronize data. Due to the different simulation step sizes, the generated data is not synchronized, which may cause errors or even wrong simulation results. Therefore, it is particularly important to synchronize data with large and small steps.
[0004] In the prior art, in a large and small step real-time simulation system of a CPU+FPGA architecture, signals can be processed in parallel on the CPU side by adding hardware resource channels, and then transmitted to the FPGA one by one in parallel by the interface driver. In this way, the simulation data arriving at the FPGA is always kept synchronized, and there is no need to design a synchronization processing method. However, in scenarios where a large amount of simulation data needs to be exchanged between the CPU and the FPGA, this processing method requires a large amount of hardware resource overhead. Although it is simple, it is less economical. Summary of the invention
[0005] The purpose of the embodiments of the present disclosure is to provide an asynchronous signal processing method and device based on a CPU+FPGA architecture, so as to at least solve the technical problems in the prior art that asynchronous signals in the power data simulation system of the CPU+FPGA architecture cannot be effectively processed synchronously, resulting in erroneous simulation results, and the existing synchronous processing methods have large hardware resource overhead and poor economy.
[0006] In order to solve the above technical problems, the embodiments of the present disclosure adopt the following technical solutions:
[0007] In a first aspect, an embodiment of the present disclosure provides an asynchronous signal processing method based on a CPU+FPGA architecture, comprising:
[0008] The preset simulation model is divided into the CPU and the FPGA to obtain a CPU simulation model and an FPGA simulation model;
[0009] The CPU simulation model performs serialization processing on the first simulation signal to be transmitted to the FPGA simulation model to obtain a second simulation signal;
[0010] The FPGA simulation model acquires the second simulation signal, and extracts valid data from the second simulation signal to obtain enable information of the valid data and data information of the first simulation signal;
[0011] Inputting the simulation pulse signal in the CPU simulation model and the enable information of the valid data into the counter of the FPGA simulation model to obtain a counting result;
[0012] Inputting the counting result into the comparator of the FPGA simulation model to obtain an output result of the comparator;
[0013] Inputting the output result of the comparator into the first register of the FPGA simulation model to store a small FPGA simulation step length;
[0014] The data information of the first simulation signal, the enable information of the valid data and the FPGA small simulation step size are input into the register matrix of the FPGA simulation model to obtain a synchronization signal corresponding to the first simulation signal.
[0015] In some embodiments, the simulation pulse signal in the CPU simulation model and the enable information of the valid data are input into the counter of the FPGA simulation model to obtain the counting result, including:
[0016] The format conversion module of the FPGA simulation model converts the simulation pulse signal and the enable information of the valid data into Boolean values respectively;
[0017] Using the Boolean value of the simulation pulse signal as a reset port input signal of the counter, and using the Boolean value of the enable information as an enable port input signal of the counter;
[0018] The counter starts counting from 0, and whenever the Boolean value of the enable information is 1, the counter is incremented by 1; when the Boolean value of the simulated pulse signal is 1, the counter is reset and starts counting from 0 again.
[0019] In some embodiments, inputting the counting result into a comparator of the FPGA simulation model to obtain an output result of the comparator includes:
[0020] The counting result is compared with a preset reference data amount. If the counting result is the reference data amount, the output result of the comparator is determined to be 1; otherwise, the output result of the comparator is 0.
[0021] In some embodiments, the data information of the first simulation signal, the enable information of the valid data, and the FPGA small simulation step size are input into the register matrix of the FPGA simulation model to obtain a synchronization signal corresponding to the first simulation signal, including:
[0022] Inputting the data information into the register matrix and activating the enable port of the first register;
[0023] Using the enable information of the valid data as the enable terminal signal of the input of the register matrix, and using the FPGA small simulation step size as the enable terminal signal of the output of the register matrix;
[0024] The data information is synchronously processed through the register matrix to obtain a synchronization signal corresponding to the first simulation signal.
[0025] In some embodiments, the register matrix comprises 2 rows and N columns of registers, the first row of registers are input registers, the second row of registers are output registers, and each input register in the first row of registers is connected to each output register in the second row of registers in a one-to-one correspondence;
[0026] The enabling information of the valid data is input into each input register in the first row of registers;
[0027] The FPGA small simulation step size is input into each output register in the second row of registers;
[0028] The first input register in the first row of registers is connected to other input registers in the first row of registers respectively.
[0029] In some embodiments, after the CPU simulation model performs serialization processing on the first simulation signal to be transmitted to the FPGA simulation model, the method further includes:
[0030] The CPU simulation model performs data format conversion on the first simulation signal, converting the first simulation signal into unsigned integer data.
[0031] In some embodiments, the unsigned integer data is a 32-bit unsigned integer data, and the second simulation signal is a 33-bit simulation signal;
[0032] The enable information of the valid data is expressed as en={d33
[32] }, and the data information of the first simulation signal is expressed as d32={d33[31:0]}.
[0033] In some embodiments, after the FPGA simulation model extracts valid data from the second simulation signal transmitted by the CPU simulation model, the method further includes:
[0034] The format conversion module of the FPGA simulation model converts the data information into a data type required by the FPGA simulation model.
[0035] In some embodiments, when the output result of the comparator is input into the first register of the FPGA simulation model, the enable port of the first register remains in a closed state.
[0036] In a second aspect, an embodiment of the present disclosure provides an asynchronous signal processing device based on a CPU+FPGA architecture, comprising:
[0037] A splitting module is configured to split the preset simulation model into the CPU and the FPGA to obtain a CPU simulation model and an FPGA simulation model;
[0038] A serialization processing module, configured to use the CPU simulation model to perform serialization processing on the first simulation signal to be transmitted to the FPGA simulation model to obtain a second simulation signal;
[0039] An extraction module is configured to obtain the second simulation signal by using the FPGA simulation model, and extract valid data from the second simulation signal to obtain enable information of the valid data and data information of the first simulation signal;
[0040] A counting module, configured to input the simulation pulse signal in the CPU simulation model and the enable information of the valid data into the counter of the FPGA simulation model to obtain a counting result;
[0041] A comparison module, configured to input the counting result into a comparator of the FPGA simulation model to obtain an output result of the comparator;
[0042] A register module configured to input the output result of the comparator into a first register of the FPGA simulation model and register a small FPGA simulation step size;
[0043] The synchronization processing module is configured to input the data information of the first simulation signal, the enable information of the valid data and the FPGA small simulation step into the register matrix of the FPGA simulation model to obtain a synchronization signal corresponding to the first simulation signal.
[0044] In a third aspect, an embodiment of the present disclosure provides an electronic device, comprising at least a memory and a processor, wherein the memory stores a computer program, and the processor implements the above-mentioned asynchronous signal processing method based on the CPU+FPGA architecture when executing the computer program on the memory.
[0045] In a fourth aspect, an embodiment of the present disclosure provides a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the above-mentioned asynchronous signal processing method based on the CPU+FPGA architecture is implemented.
[0046] An asynchronous signal processing method and device based on a CPU+FPGA architecture provided by an embodiment of the present disclosure comprises the following steps: dividing a preset simulation model into a CPU and an FPGA to obtain a CPU simulation model and an FPGA simulation model; the CPU simulation model serializes a first simulation signal to be transmitted to the FPGA simulation model to obtain a second simulation signal; the FPGA simulation model obtains the second simulation signal, and extracts valid data from the second simulation signal to obtain enable information of the valid data and data information of the first simulation signal; inputs the simulation pulse signal in the CPU simulation model and the enable information of the valid data into a counter of the FPGA simulation model to obtain a counting result; inputs the counting result into a comparator of the FPGA simulation model to obtain an output result of the comparator; and outputs the comparator into a counter. The result is input into the first register of the FPGA simulation model to store a small FPGA simulation step; the data information of the first simulation signal, the enable information of the valid data and the small FPGA simulation step are input into the register matrix of the FPGA simulation model to obtain the synchronization signal corresponding to the first simulation signal, which can accurately extract the simulation data with unknown arrival time transmitted from the CPU to the FPGA, and perform real-time synchronization processing to obtain the required synchronization data. On the one hand, it can avoid the synchronization processing calculation errors caused by the different simulation steps on the CPU and FPGA sides, reduce the calculation errors, and obtain more accurate synchronization data; on the other hand, it can avoid the problem of high hardware cost caused by parallel transmission between the CPU and FPGA, improve the utilization rate and processing efficiency of hardware resources, and realize larger-scale real-time simulation signal processing under the same hardware resources. BRIEF DESCRIPTION OF THE DRAWINGS
[0047] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.
[0048] Figure 1 This is a flowchart of an asynchronous signal processing method based on a CPU+FPGA architecture according to an embodiment of the present disclosure;
[0049] Figure 2 is a schematic diagram of the structure of an asynchronous signal processing system according to an embodiment of the present disclosure;
[0050] Figure 3 is a schematic diagram of the structure of a register matrix according to an embodiment of the present disclosure;
[0051] Figure 4It is a structural schematic diagram of an asynchronous signal processing device based on CPU+FPGA architecture according to an embodiment of the present disclosure. DETAILED DESCRIPTION
[0052] Various aspects and features of the present disclosure are described herein with reference to the drawings.
[0053] It should be understood that various modifications may be made to the embodiments of the present application. Therefore, the above description should not be considered as limiting, but only as an example of an embodiment. Other modifications within the scope and spirit of the present disclosure will occur to those skilled in the art.
[0054] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the general description of the present disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the present disclosure.
[0055] These and other characteristics of the present disclosure will become apparent from the following description of a preferred form of embodiment given as a non-limiting example, with reference to the attached drawings.
[0056] It should also be understood that, although the present disclosure has been described with reference to some specific examples, those skilled in the art will be able to realize many other equivalent forms of the present disclosure that have the features described in the claims and are therefore within the scope of protection defined thereby.
[0057] The above and other aspects, features and advantages of the present disclosure will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.
[0058] Specific embodiments of the present disclosure are described hereinafter with reference to the accompanying drawings; however, it should be understood that the embodiments claimed are merely examples of the present disclosure, which may be implemented in a variety of ways. Well-known and / or repeated functions and structures are not described in detail to avoid obscuring the present disclosure with unnecessary or redundant details. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but merely serve as a basis and representative basis for the claims to teach those skilled in the art to use the present disclosure in a variety of ways with substantially any suitable detailed structure.
[0059] This specification may use the phrases "in one embodiment," "in another embodiment," "in a further embodiment," or "in other embodiments," all of which may refer to one or more of the same or different embodiments according to the present disclosure.
[0060] Embodiment 1
[0061] Figure 1 A flowchart of an asynchronous signal processing method based on a CPU+FPGA architecture according to an embodiment of the present disclosure is shown. Figure 1As shown, an asynchronous signal processing method based on a CPU+FPGA architecture provided by an embodiment of the present disclosure includes:
[0062] S101: Split a preset simulation model into a CPU and an FPGA to obtain a CPU simulation model and an FPGA simulation model.
[0063] The preset simulation model is a real-time simulation model used to simulate and calculate power system data. Figure 2 As shown, the CPU simulation model (CPU model for short) is located in the CPU and is used to simulate and calculate data with a small simulation step size, and the FPGA simulation model (FPGA model for short) is located in the FPGA and is used to simulate and calculate data with a large simulation step size. The CPU simulation model and the FPGA simulation model together constitute an asynchronous signal processing system, which can perform real-time synchronous processing on the simulation signal (or simulation data) transmitted from the CPU to the FPGA. The simulation signal transmitted from the CPU to the FPGA is an asynchronous signal (or asynchronous data), which can be a voltage, current, and other signals in the power system.
[0064] In this step, the simulation model is preprocessed first, and the real-time simulation model is divided into the CPU and FPGA according to the simulation requirements of the power system data. The power system data with smaller simulation step requirements are placed in the FPGA and simulated and calculated using the FPGA simulation model, and the power system data with larger simulation step requirements are placed in the CPU and simulated and calculated using the CPU simulation model.
[0065] S102: The CPU simulation model serializes the first simulation signal to be transmitted to the FPGA simulation model to obtain a second simulation signal.
[0066] like Figure 2 As shown, the CPU simulation model includes a data serialization processing module, which can serialize the first simulation signal that needs to be transmitted from the CPU to the FPGA, convert or merge it into an N-column row vector or a 1×N array to obtain a second simulation signal, and transmit the second simulation signal to the FPGA simulation model.
[0067] Optionally, through step S102, after the CPU simulation model performs serialization processing on the first simulation signal to be transmitted to the FPGA simulation model, the method further includes:
[0068] S201: The CPU simulation model performs data format conversion on the first simulation signal, converting the first simulation signal into unsigned integer data.
[0069] The CPU simulation model in the CPU performs data format conversion on the first simulation signal to be transmitted to the FPGA, and converts all data types of the first simulation signal into unsigned integer data.
[0070] In this embodiment, the converted unsigned integer data is 32-bit unsigned integer data, and the second simulation signal is a 33-bit simulation signal.
[0071] After the CPU simulation model converts all data types of the first simulation signal into 32-bit unsigned integer data, the specific time when the data serially transmitted from the FPGA simulation model to the FPGA simulation model through the driver arrives at the FPGA is unknown (that is, the simulation signal transmitted to the FPGA is a simulation signal with an unknown arrival time). It is only known that the row vector or array is passed to the FPGA within a CPU simulation step, and through the action of the driver, the data arriving at the FPGA simulation model is converted into a 33-bit simulation signal.
[0072] In a specific implementation, the first simulation signal can be converted into other types of data according to actual needs. The format type of the converted first simulation signal is not specifically limited in this disclosure.
[0073] S103: The FPGA simulation model acquires the second simulation signal, and extracts valid data from the second simulation signal to obtain enable information of the valid data and data information of the first simulation signal.
[0074] The FPGA simulation model receives the second simulation signal and extracts valid data therefrom, and can obtain the enable information en of each valid data and the data information d32 of the first simulation signal.
[0075] The enable information of the valid data is expressed as en={d33
[32] }, and the data information of the first simulation signal is expressed as d32={d33[31:0]}.
[0076] Optionally, after the FPGA simulation model extracts valid data from the second simulation signal transmitted by the CPU simulation model through step S103, the method further includes:
[0077] S301: The format conversion module of the FPGA simulation model converts the data information into a data type required by the FPGA simulation model.
[0078] Since the data formats processed by the FPGA simulation model and the CPU simulation model are different, the FPGA simulation model may not be able to directly process the extracted valid data. Therefore, the FPGA simulation model converts the data information d32 of the first simulation signal into the data type required by the FPGA model through the format conversion module therein to obtain data.
[0079] S104: Inputting the simulation pulse signal in the CPU simulation model and the enable information of the valid data into the counter of the FPGA simulation model to obtain a counting result.
[0080] like Figure 2 As shown, the simulation pulse signal of the CPU simulation model and the enable information of the valid data are respectively input into the counter of the FPGA simulation model, and the counter counts the two information of the simulation pulse signal and the enable information of the valid data to obtain the counting result.
[0081] In some embodiments, step S104 specifically includes:
[0082] S1041: The format conversion module of the FPGA simulation model converts the simulation pulse signal and the enable information of the valid data into Boolean values respectively;
[0083] S1042: Using the Boolean value of the simulation pulse signal as a reset port input signal of the counter, and using the Boolean value of the enable information as an enable port input signal of the counter;
[0084] S1043: The counter starts counting from 0, and each time the Boolean value of the enable information is 1, the counter increases by 1; when the Boolean value of the simulation pulse signal is 1, the counter is reset and starts counting from 0 again.
[0085] like Figure 2 As shown, the format conversion module of the FPGA simulation model is used to convert the simulation pulse signal in the CPU simulation model into a Boolean value (0 or 1, False or True). The result of the converted simulation pulse signal is named sync, and sync will refresh the result every CPU simulation step. Similarly, the enable information en of the valid data is converted into a Boolean value 0 or 1 using the above format conversion module and named en_i. Activate the reset port and enable port of the counter, where sync is used as the reset port input signal of the counter and en_i is used as the enable port input signal of the counter. The counter starts counting freely from 0. Whenever en_i is 1, the counter increases by 1. When sync is 1, the counter is reset and starts counting freely from 0 again.
[0086] Boolean value counting is convenient and accurate. In specific implementation, the simulation pulse signal and the enable information en of the valid data can be converted into other types of data according to actual needs. The format type of the converted data is not specifically limited in this disclosure.
[0087] S105: Input the data into the comparator of the FPGA simulation model to obtain an output result of the comparator.
[0088] like Figure 2 As shown, after the counting result is obtained by the counter, it is input into the comparator, and the counting result is compared by the comparator to obtain the output result of the comparator.
[0089] In some embodiments, step S105 specifically includes:
[0090] S1051: Compare the counting result with a preset reference data amount, and if the counting result is the reference data amount, determine that the output result of the comparator is 1; otherwise, the output result of the comparator is 0.
[0091] That is, when the counted amount of the counter is the reference data amount N, it is determined that the count is accurate; otherwise, it is determined that the count is inaccurate and may need to be recounted.
[0092] S106: Input the output result of the comparator into the first register of the FPGA simulation model to store a small FPGA simulation step.
[0093] By inputting the output result of the comparator into the first register, a small FPGA simulation step can be stored, which is recorded as en_o. At the same time, the enable port of the first register is always kept in a closed state.
[0094] S107: Input the data information of the first simulation signal, the enable information of the valid data, and the FPGA small simulation step into the register matrix of the FPGA simulation model to obtain a synchronization signal corresponding to the first simulation signal.
[0095] In some embodiments, step S107 specifically includes:
[0096] S1071: Input the data information into the register matrix, and activate the enable port of the first register;
[0097] S1072: Using the enable information of the valid data as an enable terminal signal of the input of the register matrix, and using the FPGA small simulation step size as an enable terminal signal of the output of the register matrix;
[0098] S1073: Synchronously process the data information through the register matrix to obtain a synchronization signal corresponding to the first simulation signal.
[0099] like Figure 2 As shown, the data obtained after the data information d32 of the first simulation signal is converted is input into the register matrix, the enable port of the first register is activated, and the enable information of the valid data obtained through the above step S103 (the enable information is specifically the Boolean value en_i of the enable information en obtained through step S1042) is used as the enable end signal of the input of the register matrix, and the FPGA small simulation step en_o obtained through the above step 106 is used as the enable end signal of the output of the register matrix, and the signal output by the register matrix is changed from an asynchronous signal to a synchronous signal, and the synchronous signal can be calculated and processed. The signal output by the register matrix is a synchronous signal after the asynchronous signal data is synchronously processed, that is, the synchronous signal of the first simulation signal.
[0100] like Figure 3 As shown, the register matrix includes 2 rows and N columns of registers, wherein the first row of registers are input registers (numbered 1 to N), and the second row of registers are output registers (numbered 1N to NN), and each input register in the first row of registers is connected to each output register in the second row of registers in a one-to-one correspondence, that is, the data end of the first input register (register 1) of the first row is connected to the data port of the first output register (register 1N) of the second row, that is, the data end of the second input register (register 2) of the first row is connected to the data port of the second output register (register 2N) of the second row, ... the data end of the Nth input register (register N) of the first row is connected to the data port of the Nth output register (register NN) of the second row, for transmitting data signals, so as to convert the asynchronous signal data into the corresponding synchronous signal (data1, data2...dataN).
[0101] The enabling information of the valid data is input to each input register in the first row of registers, that is, en_i is used as all the enabling port input signals of the first row of register matrix, and is respectively input to each input register in the first row of registers.
[0102] The FPGA small simulation step size is input to each output register in the second row of registers. That is, en_o is used as all enable port input signals of the second row of register matrix, and is input to each output register in the second row of registers respectively.
[0103] At the same time, the first input register in the first row of registers is connected to the other input registers in the first row of registers respectively. That is, the asynchronous signal date is only input into the data port of the first input register (register 1), and the output port of register 1 is simultaneously connected to register 2, ... register 1N, that is, the output signal of register 1 is used as the data port input signal of register 2, ... register 1N, and so on, forming the input-output relationship of the entire register matrix. Finally, the output port signals data1, data2 ... dataN of the second row of registers are real-time synchronous synchronous data signals. That is, as long as the first input register receives the asynchronous signal date, it will be fine.
[0104] The first input register in the first row of registers can also be connected to the target input register through the intermediate input register, so as to transfer the data of the first input register to the target input register. For example, in this embodiment, the first input register (register 1), the second input register (register 2) ... the first input register (register N) are connected in sequence, and the second input register serves as the intermediate input register between the first input register and the third input register, and transfers the asynchronous signal date to the third input register through the second input register, so that the data transfer is convenient and reliable.
[0105] The asynchronous signal processing method based on CPU+FPGA architecture provided by the embodiment of the present disclosure obtains a CPU simulation model and an FPGA simulation model by dividing a preset simulation model into a CPU and an FPGA; the CPU simulation model performs serial processing on a first simulation signal to be transmitted to the FPGA simulation model to obtain a second simulation signal; the FPGA simulation model obtains the second simulation signal, and extracts valid data from the second simulation signal to obtain enable information of the valid data and data information of the first simulation signal; the simulation pulse signal in the CPU simulation model and the enable information of the valid data are input into the counter of the FPGA simulation model to obtain a counting result; the counting result is input into a comparator of the FPGA simulation model to obtain an output result of the comparator; the output result of the comparator is input into The first register of the FPGA simulation model stores a small FPGA simulation step; the data information of the first simulation signal, the enable information of the valid data and the small FPGA simulation step are input into the register matrix of the FPGA simulation model to obtain a synchronization signal corresponding to the first simulation signal, which can accurately extract the simulation data with unknown arrival time transmitted from the CPU to the FPGA, and perform real-time synchronization processing to obtain the required synchronization data. On the one hand, it can avoid synchronization processing calculation errors caused by different simulation steps on the CPU and FPGA sides, reduce calculation errors, and obtain more accurate synchronization data; on the other hand, it can avoid the problem of high hardware cost caused by parallel transmission between the CPU and FPGA, improve the utilization rate and processing efficiency of hardware resources, and realize larger-scale real-time simulation signal processing with the same hardware resources.
[0106] Embodiment 2
[0107] Figure 4 A schematic diagram of the structure of an asynchronous signal processing device based on a CPU+FPGA architecture according to an embodiment of the present disclosure is shown. Figure 4 As shown, the embodiment of the present disclosure provides an asynchronous signal processing device based on a CPU+FPGA architecture, comprising:
[0108] A segmentation module 10 is configured to segment the preset simulation model into the CPU and the FPGA to obtain a CPU simulation model and an FPGA simulation model;
[0109] The serialization processing module 20 is configured to use the CPU simulation model to perform serialization processing on the first simulation signal to be transmitted to the FPGA simulation model to obtain a second simulation signal;
[0110] An extraction module 30 is configured to obtain the second simulation signal by using the FPGA simulation model, and extract valid data from the second simulation signal to obtain enable information of the valid data and data information of the first simulation signal;
[0111] A counting module 40 is configured to input the simulation pulse signal in the CPU simulation model and the enable information of the valid data into the counter of the FPGA simulation model to obtain a counting result;
[0112] A comparison module 50 is configured to input the counting result into a comparator of the FPGA simulation model to obtain an output result of the comparator;
[0113] A register module 60, configured to input the output result of the comparator into a first register of the FPGA simulation model, and register a small FPGA simulation step size;
[0114] The synchronization processing module 70 is configured to input the data information of the first simulation signal, the enable information of the valid data and the FPGA small simulation step into the register matrix of the FPGA simulation model to obtain a synchronization signal corresponding to the first simulation signal.
[0115] In some embodiments, the counting module 40 is further configured to:
[0116] Inputting the simulation pulse signal in the CPU simulation model and the enable information of the valid data into the counter of the FPGA simulation model to obtain a counting result, including:
[0117] The format conversion module of the FPGA simulation model converts the simulation pulse signal and the enable information of the valid data into Boolean values respectively;
[0118] Using the Boolean value of the simulation pulse signal as a reset port input signal of the counter, and using the Boolean value of the enable information as an enable port input signal of the counter;
[0119] The counter starts counting from 0, and whenever the Boolean value of the enable information is 1, the counter is incremented by 1; when the Boolean value of the simulated pulse signal is 1, the counter is reset and starts counting from 0 again.
[0120] In some embodiments, the comparison module 50 is further configured to:
[0121] The counting result is compared with a preset reference data amount. If the counting result is the reference data amount, the output result of the comparator is determined to be 1; otherwise, the output result of the comparator is 0.
[0122] In some embodiments, the synchronization processing module 70 is further configured to:
[0123] Inputting the data information into the register matrix and activating the enable port of the first register;
[0124] Using the enable information of the valid data as the enable terminal signal of the input of the register matrix, and using the FPGA small simulation step size as the enable terminal signal of the output of the register matrix;
[0125] The data information is synchronously processed through the register matrix to obtain a synchronization signal corresponding to the first simulation signal.
[0126] In some embodiments, the register matrix comprises 2 rows and N columns of registers, the first row of registers are input registers, the second row of registers are output registers, and each input register in the first row of registers is connected to each output register in the second row of registers in a one-to-one correspondence;
[0127] The enabling information of the valid data is input into each input register in the first row of registers;
[0128] The FPGA small simulation step size is input into each output register in the second row of registers;
[0129] The first input register in the first row of registers is connected to other input registers in the first row of registers respectively.
[0130] In some embodiments, the asynchronous signal processing device also includes a first data format conversion module, which is configured to use the CPU simulation model to perform data format conversion on the first simulation signal that needs to be transmitted to the FPGA simulation model after serializing the first simulation signal using the CPU simulation model, and convert the first simulation signal into unsigned integer data.
[0131] In some embodiments, the unsigned integer data is a 32-bit unsigned integer data, and the second simulation signal is a 33-bit simulation signal;
[0132] The enable information of the valid data is expressed as en={d33
[32] }, and the data information of the first simulation signal is expressed as d32={d33[31:0]}.
[0133] In some embodiments, the asynchronous signal processing device also includes a second data format conversion module, which is configured to use the format conversion module of the FPGA simulation model to convert the data information into the data type required by the FPGA simulation model after extracting valid data from the second simulation signal transmitted by the CPU simulation model using the FPGA simulation model.
[0134] In some embodiments, when the output result of the comparator is input into the first register of the FPGA simulation model, the enable port of the first register remains in a closed state.
[0135] The asynchronous signal processing device based on CPU+FPGA architecture provided in the embodiment of the present disclosure corresponds to the asynchronous signal processing method based on CPU+FPGA architecture in the above-mentioned embodiment. Any optional items in the embodiment of the asynchronous signal processing method based on CPU+FPGA architecture are also applicable to the embodiment of the asynchronous signal processing device based on CPU+FPGA architecture, which will not be repeated here.
[0136] Embodiment 3
[0137] An embodiment of the present disclosure also provides an electronic device, comprising at least a memory and a processor, wherein the memory stores a computer program, and the processor implements the above-mentioned asynchronous signal processing method based on the CPU+FPGA architecture when executing the computer program on the memory.
[0138] In some embodiments, the processor executing the computer program may be a processing device including one or more general-purpose processing devices, such as a microprocessor, a central processing unit (CPU), a graphics processing unit (GPU), etc. More specifically, the processor may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor running other instruction sets, or a processor running a combination of instruction sets. The processor may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a system on a chip (SoC), etc.
[0139] The memory may be a read-only memory (ROM), a random access memory (RAM), a phase-change random access memory (PRAM), a static random access memory (SRAM), a dynamic random access memory (DRAM), an electrically erasable programmable read-only memory (EEPROM), other types of random access memory (RAM), a flash disk or other form of flash memory, a cache, a register, a static memory, a compact disk read-only memory (CD-ROM), a digital versatile disk (DVD) or other optical storage, a cassette or other magnetic storage device, or any other possible non-temporary medium used to store information or instructions that can be accessed by a computer device.
[0140] The electronic devices of the embodiments of the present disclosure may include but are not limited to fixed terminal devices such as servers, desktop computers, digital TVs, etc., and mobile terminal devices such as vehicle-mounted devices (such as head-up display devices), handheld devices (such as mobile phones, tablet computers, etc.), wearable devices (such as smart watches, smart bracelets, etc.), etc.
[0141] Embodiment 4
[0142] The embodiment of the present disclosure further provides a computer-readable storage medium, wherein the computer-readable medium stores a computer program, and when the computer program is executed by a processor, the asynchronous signal processing method based on the CPU+FPGA architecture is implemented.
[0143] The computer-readable storage medium of the embodiments of the present disclosure may adopt any combination of one or more computer-readable media. The computer-readable medium may be a computer-readable signal medium or a computer-readable storage medium. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. In the embodiments of the present disclosure, the computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, device or device, for example, the above-mentioned memory.
[0144] The computer programs of the embodiments of the present disclosure may be organized into one or more computer executable components or modules. Any number and combination of such components or modules may be used to implement the various aspects of the present disclosure. For example, the various aspects of the present disclosure are not limited to the specific computer executable instructions or specific components or modules shown in the drawings and described herein. Other embodiments may include different computer executable instructions or components with more or less functions than those shown and described herein.
[0145] The above description is only a preferred embodiment of the present disclosure and an explanation of the technical principles used. Those skilled in the art should understand that the scope of disclosure involved in the present disclosure is not limited to the technical solutions formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the above features are replaced with the technical features with similar functions disclosed in the present disclosure (but not limited to) by each other to form a technical solution.
Claims
1. An asynchronous signal processing method based on CPU+FPGA architecture, characterized in that: include: The preset simulation model is divided into the CPU and the FPGA to obtain a CPU simulation model and an FPGA simulation model; The CPU simulation model performs serialization processing on the first simulation signal to be transmitted to the FPGA simulation model to obtain a second simulation signal; The FPGA simulation model acquires the second simulation signal, and extracts valid data from the second simulation signal to obtain enable information of the valid data and data information of the first simulation signal; Inputting the simulation pulse signal in the CPU simulation model and the enable information of the valid data into the counter of the FPGA simulation model to obtain a counting result; Inputting the counting result into the comparator of the FPGA simulation model to obtain an output result of the comparator; Inputting the output result of the comparator into the first register of the FPGA simulation model to store a small FPGA simulation step length; The data information of the first simulation signal, the enable information of the valid data and the FPGA small simulation step are input into the register matrix of the FPGA simulation model to obtain a synchronization signal corresponding to the first simulation signal.
2. The method according to claim 1, characterized in that Inputting the simulation pulse signal in the CPU simulation model and the enable information of the valid data into the counter of the FPGA simulation model to obtain a counting result, including: The format conversion module of the FPGA simulation model converts the simulation pulse signal and the enable information of the valid data into Boolean values respectively; Using the Boolean value of the simulation pulse signal as a reset port input signal of the counter, and using the Boolean value of the enable information as an enable port input signal of the counter; The counter starts counting from 0, and whenever the Boolean value of the enable information is 1, the counter is incremented by 1; when the Boolean value of the simulated pulse signal is 1, the counter is reset and starts counting from 0 again.
3. The method according to claim 1, characterized in that Inputting the counting result into the comparator of the FPGA simulation model to obtain the output result of the comparator includes: The counting result is compared with a preset reference data amount. If the counting result is the reference data amount, the output result of the comparator is determined to be 1; otherwise, the output result of the comparator is 0.
4. The method according to claim 1, characterized in that: Inputting data information of the first simulation signal, enable information of the valid data, and the FPGA small simulation step into a register matrix of the FPGA simulation model to obtain a synchronization signal corresponding to the first simulation signal, including: Inputting the data information into the register matrix and activating the enable port of the first register; Using the enable information of the valid data as the enable terminal signal of the input of the register matrix, and using the FPGA small simulation step size as the enable terminal signal of the output of the register matrix; The data information is synchronously processed through the register matrix to obtain a synchronization signal corresponding to the first simulation signal.
5. The method according to claim 4, characterized in that The register matrix comprises 2 rows and N columns of registers, the first row of registers are input registers, the second row of registers are output registers, and each input register in the first row of registers is connected to each output register in the second row of registers in a one-to-one correspondence; The enabling information of the valid data is input into each input register in the first row of registers; The FPGA small simulation step size is input into each output register in the second row of registers; The first input register in the first row of registers is connected to other input registers in the first row of registers respectively.
6. The method according to claim 1, characterized in that After the CPU simulation model performs serialization processing on the first simulation signal to be transmitted to the FPGA simulation model, the method further includes: The CPU simulation model performs data format conversion on the first simulation signal, converting the first simulation signal into unsigned integer data.
7. The method according to claim 6, characterized in that The unsigned integer data is 32-bit unsigned integer data, and the second simulation signal is a 33-bit simulation signal; The enable information of the valid data is expressed as en={d33[32]}, and the data information of the first simulation signal is expressed as d32={d33[31:0]}.
8. The method according to claim 1, characterized in that: After the FPGA simulation model extracts valid data from the second simulation signal transmitted by the CPU simulation model, the method further includes: The format conversion module of the FPGA simulation model converts the data information into a data type required by the FPGA simulation model.
9. The method according to claim 1, characterized in that: When the output result of the comparator is input into the first register of the FPGA simulation model, the enable port of the first register remains in a closed state.
10. An asynchronous signal processing device based on CPU+FPGA architecture, characterized in that: include: A splitting module is configured to split the preset simulation model into the CPU and the FPGA to obtain a CPU simulation model and an FPGA simulation model; A serialization processing module, configured to use the CPU simulation model to perform serialization processing on the first simulation signal to be transmitted to the FPGA simulation model to obtain a second simulation signal; An extraction module is configured to obtain the second simulation signal by using the FPGA simulation model, and extract valid data from the second simulation signal to obtain enable information of the valid data and data information of the first simulation signal; A counting module, configured to input the simulation pulse signal in the CPU simulation model and the enable information of the valid data into the counter of the FPGA simulation model to obtain a counting result; A comparison module, configured to input the counting result into a comparator of the FPGA simulation model to obtain an output result of the comparator; A register module, configured to input the output result of the comparator into a first register of the FPGA simulation model, and register a small FPGA simulation step size; The synchronization processing module is configured to input the data information of the first simulation signal, the enable information of the valid data and the FPGA small simulation step into the register matrix of the FPGA simulation model to obtain a synchronization signal corresponding to the first simulation signal.