Chip layout and training method, electronic equipment, storage medium and chip system

Abstract

The invention provides a chip layout and training method, electronic equipment, a storage medium and a chip system, relates to the technical field of chip design, and can improve the generalization of the layout method among different chip netlists. The method comprises the following steps: determining first relative position information; the first relative position information is relative position information between different units in the arranged units in the sample chip; determining a first input of a to-be-trained graph neural network; the first input is obtained based on a first netlist corresponding to the sample chip; obtaining a first output through a graph neural network; executing coding based on the first output to obtain second relative position information; calculating a loss function value according to the first relative position information and the second relative position information; and optimizing trainable parameters in the graph neural network according to the loss function value.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a chip layout and training method, electronic equipment, storage medium and chip system. Background Art

[0002] Chip design and manufacturing can be roughly divided into three stages: front-end design (logic code design), back-end design (wiring process), and wafer production (chip manufacturing, testing and packaging). Among them, chip layout is an important step in the VLSI design process and may significantly affect the iteration cycle of chip design. The chip layout problem can be described as solving the location of the unit given the size and connection relationship of the unit, given constraints and optimization goals.

[0003] The nonlinear programming method is one of the technical means to solve the chip layout problem. In a nonlinear programming scheme, the chip layout problem is expressed as a line length optimization problem under the layout density constraint and is solved. However, this scheme requires independent training on each chip and its generalization needs to be improved. Summary of the invention

[0004] The present application provides a chip layout and training method, electronic device, storage medium and chip system, which can improve the generalization of the chip layout method between different chip netlists.

[0005] In a first aspect, an embodiment of the present application provides a chip layout training method, the method comprising: determining first relative position information; the first relative position information is the relative position information between different units in each unit that has been laid out in a sample chip; determining a first input of a graph neural network to be trained; the first input is obtained based on a first netlist corresponding to the sample chip; obtaining a first output through the graph neural network; based on the first output, performing encoding to obtain second relative position information; calculating a loss function value based on the first relative position information and the second relative position information; and optimizing trainable parameters in the graph neural network based on the loss function value.

[0006] By encoding the relative position relationship between units and using it as the output and training target of the graph neural network model, the graph neural network model can migrate the information of the chip that has been laid out to the chip to be laid out, improving the generalization of the layout method, improving the efficiency of cross-chip reasoning, and solving the problem that large-scale netlist circuit layout knowledge is difficult to migrate. In addition, this scheme is a self-supervised learning scheme, which automatically extracts labels (first relative position information) from the training data during the training process. There is no need to label the training data, and the existing netlist training data set can be used as the training data. There is no need to collect a large amount of sample data, which reduces the workload of data preparation.

[0007] In a feasible implementation, determining the first relative position information includes: obtaining the absolute position information of each unit that has been laid out in the sample chip; and calculating the relative position information between different units based on the absolute position information. The absolute position information can be the position information (e.g., coordinate information) of each unit included in the netlist, which is known and easy to obtain data. Therefore, calculating the relative position information based on the absolute position information can directly use the existing position data without additionally marking the data.

[0008] In a feasible implementation, the absolute position information includes coordinate information; based on the absolute position information, the relative position information between different units is calculated, including: based on the coordinate information corresponding to the j-th unit and the i-th unit, the polar coordinate information of the j-th unit relative to the i-th unit is calculated; i and j are both integers greater than or equal to 1, and i≠j. Polar coordinates can accurately express relative position relationships, which is conducive to accurately locating unit positions.

[0009] In a feasible implementation, encoding is performed based on the first output to obtain the second relative position information, including: determining an independent variable based on the first output, performing an encoding function on the independent variable to obtain the second relative position information; the encoding function is used to map the independent variable to the second relative position information; after calculating the loss function value, the method further includes: optimizing the trainable parameters in the encoding function according to the loss function value. By performing relative position encoding through the encoding function, specific expressions of multiple encoding functions can be set, and trainable parameters can be set, so that the mapping process can also be optimized during the training process, thereby obtaining more accurate relative position information.

[0010] In a second aspect, an embodiment of the present application also provides a chip layout method, which includes: determining a second input of a graph neural network after training; obtaining the second input based on a second netlist corresponding to the chip to be laid out; obtaining a second output through the graph neural network; based on the second output, performing encoding to obtain third relative position information; performing decoding at least based on the third relative position information to obtain the absolute position information of each unit in the chip to be laid out.

[0011] Relative position encoding is used to encode the output features of the graph neural network to obtain the predicted relative position information, and then decoding is performed on this basis to obtain the absolute position information of each unit. Relative position encoding and decoding can enable the graph neural network model to migrate the information of the chip that has been laid out to the chip to be laid out, thereby improving the generalization of the layout method and the efficiency of cross-chip reasoning layout.

[0012] In a feasible implementation, determining the second input of the graph neural network after training includes: obtaining at least a plurality of subgraphs based on the second netlist; in the plurality of subgraphs, nodes represent units or nets; obtaining input features based on the second netlist; the input features include unit features corresponding to each unit in the chip to be laid out; at least determining the graph structure information and input features corresponding to the plurality of subgraphs as the second input. Dividing into multiple subgraphs can alleviate the data processing pressure of the graph neural network and reduce the difficulty of data processing due to the size of the netlist.

[0013] In a feasible implementation, based on the second netlist, at least multiple subgraphs are obtained, including: based on the second netlist, a hypergraph is established; wherein, in the hypergraph, nodes represent units, and hyperedges represent network cables; the hypergraph is divided into N blocks, and N first subgraphs and 1 first global graph corresponding to the N blocks are obtained; wherein, the first subgraph is used to represent the connection relationship between different units in a block through network cables; the first global graph is used to represent the connection relationship between different blocks in the N blocks through network cables; N≥2; the N first subgraphs and 1 first global graph are respectively expanded to obtain corresponding N second subgraphs and 1 second global graph; wherein, in the second subgraph and the second global graph, nodes represent units or network cables, and connecting edges represent pins; at least the graph structure information and input features corresponding to the multiple subgraphs are determined as the second input, including: at least the graph structure information and input features corresponding to the multiple second subgraphs and 1 second global graph are determined as input. First, a hypergraph is established, and an edge in the hypergraph can connect more nodes, which is conducive to quickly sorting out the topological relationship, and the composition efficiency is higher than that of the ordinary graph.

[0014] In a feasible implementation, after obtaining the corresponding N second subgraphs, the method further includes: establishing N unit flow graphs corresponding to the N second subgraphs according to the signal direction information contained in the second netlist; wherein, in the unit flow graph, nodes represent units, and the connecting edges between nodes are directed edges, which are used to represent network cables, and the direction of the directed edges is determined according to the signal direction; at least the graph structure information and input features corresponding to multiple subgraphs are determined as the second input, including: at least the graph structure information and input features corresponding to multiple second subgraphs and 1 second global graph and multiple N unit flow graphs are determined as input. The unit flow graph contains the connection relationship information and signal flow direction information between units. The construction of the unit flow graph can provide important reference information for the encoding and decoding process.

[0015] In a feasible implementation, N unit flow graphs corresponding to N second subgraphs are established according to the signal direction information contained in the netlist, including: in a second subgraph, a unit is regarded as a starting node; a unit connected to the starting node through a network line is searched as a first-order neighboring node corresponding to the starting node; according to the signal direction, a directed edge is generated between the starting node and each first-order neighboring node; a unit connected to the first-order neighboring node through a network line is searched as a second-order neighboring node corresponding to the starting node; according to the signal direction, a directed edge is generated between the first-order neighboring node and the second-order neighboring node; and the next-order neighboring node is continued to be searched until all units in the same second subgraph are visited, thereby obtaining a unit flow graph.

[0016] In a feasible implementation, the input features also include network features corresponding to each network line in the chip to be laid out; the second output includes the output features corresponding to each unit, or the second output also includes the output features corresponding to each network line; the graph neural network is a graph convolutional neural network, and the graph convolutional neural network includes a convolutional layer; the second output is obtained through the graph neural network, including: in the convolutional layer, by executing at least one of the first convolution function, the second convolution function and the third convolution function, the feature transfer between nodes is performed; wherein the first convolution function is used to transfer the network features corresponding to each network line connected to the i-th unit to the i-th unit. The corresponding node obtains the i-th first unit sub-feature; i ≥ 1 and is an integer; the second convolution function is used to transfer the unit features of each unit connected to the t-th network line to the node corresponding to the t-th network line, and obtain the network line feature corresponding to the t-th network line; t ≥ 1 and is an integer; the third convolution function is used to transfer the unit features of each unit connected to the i-th unit to the node corresponding to the i-th unit, and obtain the i-th second unit sub-feature; based on the i-th first unit sub-feature and the i-th second unit sub-feature, obtain the output feature corresponding to the i-th unit; or, based on the network line feature corresponding to the t-th network line, obtain the output feature corresponding to the t-th network line. Through the above operations of the convolution layer, the graph convolutional neural network can fuse the node features with the graph structure information. The features of each node are related to the features of the nodes connected to it, and the output features containing the graph structure information are obtained, which helps to predict more accurate relative position information.

[0017] In a feasible implementation, encoding is performed based on the second output to obtain third relative position information, including: determining an independent variable based on the second output, executing an encoding function on the independent variable, and obtaining the third relative position information; wherein the encoding function is used to map the independent variable to the third relative position information.

[0018] In a feasible implementation, the encoding function includes a first encoding function and a second encoding function; the third relative position information is polar coordinate information; executing the encoding function to obtain the third relative position information includes: determining the first independent variable based on the second output, executing the first encoding function on the first independent variable, and obtaining the polar diameter; determining the second independent variable based on the second output, executing the second encoding function on the second independent variable, and obtaining the deflection angle; the deflection angle represents the relative value of the polar angle corresponding to different units.

[0019] In a feasible implementation, the output includes unit features corresponding to each unit and network features corresponding to each network line; based on the second output, the first independent variable is determined, including: based on the unit features corresponding to the i-th unit and the j-th unit in the second output, and the network features corresponding to the t-th directed edge, the first independent variable is obtained; wherein the t-th directed edge is a directed edge connecting the i-th unit and the j-th unit in the unit flow graph; based on the second output, the second independent variable is determined, including: searching for at least one path corresponding to the j-th unit in the unit flow graph, and selecting one of them as the first path; the path is a directed path formed by at least one directed edge starting from the starting node in the unit flow graph and ending at the node corresponding to the j-th unit; based on the unit features corresponding to each node passed by the first path in the second output and the network features corresponding to at least one directed edge, the second independent variable is obtained; wherein i, j and t are all integers greater than or equal to 1.

[0020] In a feasible implementation, decoding is performed at least according to the third relative position information to obtain the absolute position information of each unit in the chip to be laid out, including: determining a starting node in a subgraph and the absolute position information of the starting node; determining the absolute position information of the first-order neighboring nodes according to the third relative position information of the first-order neighboring nodes corresponding to the starting node and the absolute position information of the starting node; determining the absolute position information of the m+1-order neighboring nodes according to the absolute position information of the m-order neighboring nodes and the third relative position information of the m+1-order neighboring nodes; m≥1 and is an integer.

[0021] In a feasible implementation, decoding is performed at least according to the third relative position information to obtain the absolute position information of each unit in the chip to be laid out, including: for the j-th unit, searching for at least one path with the j-th unit as the end node in the unit flow graph; according to the third relative position information corresponding to the starting node of one of the at least one paths and the third relative position information of each node passed by the path, a feasible solution corresponding to the path is obtained, and at least one path corresponds to at least one feasible solution; based on the at least one feasible solution, the absolute position information of the j-th unit is obtained.

[0022] In a feasible implementation, after obtaining the absolute position information of each unit in the chip to be laid out, the method also includes: using the absolute position information of each unit as an initial solution to calculate the objective function; the objective function uses at least one of line length, density, and anchor point as a constraint; the objective function includes at least one hyperparameter of learning rate, number of iterations, and loss function weight; and gradient updating the absolute position information of each unit.

[0023] After obtaining the absolute position information of each unit through encoding and decoding, the absolute position information can be used as the initial solution for further adaptive fine-tuning. On the one hand, it can avoid the problem of cold start and greatly shorten the time required for optimizing the unit position. On the other hand, fine-tuning can further meet constraints such as no overlap between components and the placement of components cannot exceed the set layout boundaries, thereby optimizing the layout.

[0024] In a third aspect, the technical solution of the present application also provides an electronic device for sending data through a data transmission interface, the electronic device comprising: one or more processors; a memory; at least one application; and one or more computer programs, wherein the one or more computer programs are stored in the memory, and the one or more computer programs include instructions, which, when executed by the electronic device, enable the electronic device to execute a method as described in any one of the first or second aspects above.

[0025] In a fourth aspect, the technical solution of the present application also provides a storage medium, including computer instructions, which, when executed on an electronic device, enables the electronic device to execute a method as described in any one of the first or second aspects above.

[0026] In a fifth aspect, the technical solution of the present application also provides a chip system, comprising: a communication interface for inputting and / or outputting data; a processor for executing a computer executable program so that a device equipped with the chip system executes a method as described in any one of the first or second aspects above. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is an example diagram of the system architecture in the training phase of the method provided in the embodiment of the present application;

[0028] Figure 2 is a flowchart of the method provided by the embodiment of the present application in the training phase;

[0029] Figure 3 This is an example diagram of the system architecture of the method provided in the embodiment of the present application at the application stage;

[0030] Figure 4 It is a method flow chart of the method provided in the embodiment of the present application in the application stage;

[0031] Figure 5 It is a schematic diagram of dividing sub-images during the composition process;

[0032] Figure 6 It is a schematic diagram of data processing of the convolutional layer in the graph convolutional neural network;

[0033] Figure 7 This is an example diagram of the processing flow architecture based on the graph structure during the training phase;

[0034] Figure 8 It is an example diagram of encoding relative position based on absolute position information;

[0035] Fig. 9 It is a schematic diagram of the main flow of the method provided in the embodiment of the present application;

[0036] Fig.10 It is a schematic diagram of chip layout based on hierarchical netlist diagram;

[0037] Fig.11 To establish a unit flow graph and obtain a schematic diagram of unit flow graph edges and unit paths;

[0038] Fig.12 This is an example diagram of the system architecture that uses the unit flow graph as one of the inputs to predict relative positions and perform training;

[0039] Fig.13 This is an example diagram of the system architecture of a graph convolutional neural network;

[0040] Fig.14 This is an example diagram of the data processing architecture of a graph neural network;

[0041] Fig.15 A schematic diagram of encoding based on unit flow graph edges and unit paths;

[0042] Fig.16 A schematic diagram of decoding based on a unit flow graph;

[0043] Fig.17 Schematic diagram for further fine-tuning and optimizing chip layout after inductive layout;

[0044] 18(a)-(c) respectively show the congestion distribution diagrams of the model, D***Place and **Place proposed in the embodiment of the present application on the mgc_fft_2 netlist;

[0045] Figure 18(d) is an example diagram of congestion level;

[0046] 19(a)-(c) respectively show the congestion distribution diagrams of the model, D***Place and **Place proposed in the embodiment of the present application on the mgc_matrix_mult_2 netlist;

[0047] Figure 20(a)-(c) respectively show the congestion distribution diagrams of each method on the mgc_superblue19 netlist;

[0048] Fig.21 Schematic diagram of the hardware structure of the electronic device. DETAILED DESCRIPTION

[0049] In order to make the purpose, technical solution and advantages of the present application clearer, the technical solution of the present application will be clearly and completely described below in combination with the specific embodiments of the present application and the corresponding drawings. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present application.

[0050] The terms used in the implementation section of this application are only used to explain the specific embodiments of this application and are not intended to limit this application.

[0051] Chip design is divided into front-end design and back-end design. Front-end design generally includes specification formulation, RTL (Register Transfer Level) design, simulation verification, logic synthesis (Logic Synthesis), static timing analysis (Static Timing Analysis, STA), formal verification and other stages. Front-end design is the process of determining design requirements to output netlist (generally gate-level netlist circuit); back-end design includes design for testability (Design For Test, DFT), physical implementation, clock tree synthesis (Clock Tree Synthesis, CTS), routing (Place & Route), parasitic parameter extraction, layout physical verification and other stages. The physical layout is handed over to the chip foundry in the GDS II file format, and the actual circuit is made on the silicon wafer, and then packaged and tested to get the chip.

[0052] Among them, the physical implementation stage in the back-end design is the process of converting the logical design into the actual chip layout and connection. Its main task is layout (FloorPlan), which generally determines the placement of various functional circuits such as IP modules, RAM, I / O pins, etc. The layout planning can directly affect the final area of ​​the chip. Considering various functional circuits such as IP modules, RAM, I / O pins, etc. as units, the chip layout problem can be described as given the size and connection relationship of standard cells and macro cells, given constraints (such as no component overlap)) and optimization goals (such as minimizing the total line length), and solving the unit position.

[0053] The chip layout method provided in the embodiment of the present application can be applied to the physical implementation stage or layout planning stage in the chip design application scenario.

[0054] To facilitate understanding of the solutions proposed in the embodiments of the present application, the relevant technologies are briefly described first:

[0055] For chip layout, modern VLSI design needs to be able to quickly generate high-quality layout plans on different chips to accelerate the design iteration cycle. Current technical research directions are mainly focused on developing more efficient global layout algorithms. Some solutions cannot take into account both operational efficiency and generalization at the same time.

[0056] In the related technologies, chip layout methods generally include iterative optimization methods, integer programming methods, nonlinear programming methods, and reinforcement learning methods. Iterative optimization methods can include simulated annealing algorithms, genetic algorithms, Monte Carlo simulation algorithms, etc. The idea is to approach the optimal solution step by step through iteration; the idea of ​​integer programming methods is to limit the variables (all or part) in the planning to integers, and find the best solution that satisfies certain constraints among a finite number of available options; nonlinear programming methods are to solve the optimization problem defined by a set of equations and inequalities (collectively referred to as constraints) composed of a series of unknown real functions, accompanied by an objective function to be maximized or minimized, where some constraints or objective functions are nonlinear. Reinforcement learning methods, for example, use reward functions to guide layout placement by treating the chip layout problem as a finite Markov decision process. The following are several examples of related technologies to illustrate possible problems.

[0057] Related technology 1: It is a nonlinear programming method that uses the GPU (graphics processing unit) acceleration algorithm enabled by the PyTorch framework to digitally calculate the line length and density gradient for modern VLSI (Very Large Scale Integration Circuit) layout, using the weighted indicators such as line length as the objective function to optimize the unit position. This method can improve layout efficiency and save time to a certain extent, but when faced with the reality of diverse chip netlists, there are still the following problems:

[0058] It is necessary to train each chip independently, that is, each chip needs to be trained specifically, and there is no more general layout method to adapt to more chips to be laid out. The generalization needs to be improved, which brings a bottleneck to the chip optimization layout time.

[0059] Secondly, layout has an important impact on subsequent congestion, timing and other indicators, but this method is difficult to effectively optimize timing and congestion indicators during the layout stage.

[0060] Related technology 2: For the first time, reinforcement learning is applied to the chip layout stage. It uses reinforcement learning to generalize the model on different chip netlists. This method is based on the reinforcement learning architecture, takes the netlist and related features, and the location of the placed cells as the state, and defines the reward function as the weighted sum of the total line length and congestion. The total line length is the weighted HPWL (Half-Perimeter Wire Length); each action is defined as the probability distribution of the current macro unit in the current layout.

[0061] During the training process, each training assumes that all macro cells are placed in the current layout in turn. The order of placing macro cells is to arrange the macro cells from large to small according to the area. When the areas of macro cells are the same, the topological order of macro cells in the netlist is introduced, and the topological order is placed in front. The reward generated each time the macro cells are placed in order is 0. When the last macro cell is placed, all standard cell cluster blocks are placed in the center of the layout, and the classic force-directed method is run to obtain the position of each standard cell cluster block, and each cell is placed in the center of the corresponding cluster block. In this way, the layout plan is obtained, HPWL and congestion are calculated, and rewards are obtained. On the chip layout, the position of the macro cell is a continuous value, and the probability distribution of each macro cell placement is the probability of being placed in the center of each grid. Its placement position is the center of the corresponding cell, and finally the probability distribution of the macro cell is discretized.

[0062] Among them, for the generation of the probability density of each macro unit, during the training process, after obtaining the initial macro unit probability distribution, firstly, according to the density constraint, the probability of illegal placement positions is set to zero, and the probability of legal positions is normalized again. The placement position of the macro unit in the current training round is obtained by probability sampling, and the center of the cell with the maximum probability is taken as the placement position during the inference process. However, there is a density constraint in the placement process, that is, the density on each cell must be strictly less than the given maximum density. Therefore, if a macro unit block does not have a legal placement position during the placement process, then the training data is abandoned and retrained from the beginning. The training process adopts the proximal policy optimization (PPO) strategy for training.

[0063] The disadvantage of this reinforcement learning-based solution is that during the reasoning process of layout generation, the number of network reasoning times is equivalent to the number of macro cells, and its time complexity is linearly related to the macro cells and standard cells of the netlist, which consumes a long time and has low layout efficiency.

[0064] Especially for large-scale netlists, the search space is huge, which makes the training time to converge longer. Current integrated circuit netlists are often large-scale netlists with more than one million, which makes this method difficult to apply.

[0065] Related technology three: Obtain the logic diagram executed by the chip to be laid out and the device list corresponding to the chip to be laid out; use a pre-trained layout model to determine the layout diagram of the chip to be laid out based on the logic diagram and the device list. By using a pre-trained layout model to perform chip layout, the layout diagram of the chip to be laid out can be quickly obtained through the logic diagram and the device list. Compared with manual chip layout, the required time can be shortened and the efficiency of chip layout can be improved. Among them, when the layout model is trained, it is necessary to obtain K logic diagram samples and the device list samples corresponding to each logic diagram sample; for each of the logic diagram samples, obtain the operation type of each type of operation sample in the logic diagram sample, the sub-device list sample corresponding to each type of operation sample, and the input or output of each operation sample.

[0066] In this solution, multiple layout samples are used to train the model. The preparation of chip layout data in the early stage is difficult, and the chip layout differences are too large. The model may be underfitting and have poor generalization ability.

[0067] Related technology 4: Analyze the layout and configuration of functional units according to the deep learning method to obtain the best chip layout and routing that meets the set constraints. First, determine the type of functional unit that implements the chip to be designed; set the attribute information corresponding to each functional unit type based on the characteristics of each functional unit type, select the target functional unit corresponding to each functional unit type from the candidate functional units of each functional unit type and add it to the layout of the chip to be designed. Then, based on the set deep learning algorithm, all target functional units are laid out and routed according to the set constraints until the evaluation representation value of the layout and routing according to the constraints is maximized.

[0068] This method reduces the manual workload in the chip design process, especially in the chip layout and routing process, and improves chip design efficiency. However, this method is very slow, and each round of iteration requires the performance, energy consumption, layout density, and area setting of the current design chip to be evaluated and characterized by the wiring results, resulting in low data utilization, long interactive iteration cycles, and weak model migration.

[0069] In summary, the first related technology needs to calculate the layout separately on each chip, which is not generalizable and may not achieve good results in different chips. The second related technology uses reinforcement learning methods to learn layout knowledge and improve generalization between different chips, but its efficiency is low. That is, the layout method with excellent time-efficiency performance cannot achieve generalization, and the reinforcement learning method with generalization is less efficient for large-scale chip netlists because the inference time is linearly related to the number of units to be placed.

[0070] On the one hand, the preparation of training data for related technology three is difficult, and on the other hand, it also has the problem of poor generalization ability; related technology four also has problems such as low efficiency and weak transferability (i.e., poor generalization ability).

[0071] In view of this, an embodiment of the present application proposes a chip layout method, which encodes the relative position relationship between the units and uses it as the training target and prediction target of the graph neural network model, so that the graph neural network model can migrate the information of the chip that has been laid out to the chip to be laid out, which can at least solve the problem of model generalization in chip layout. That is, after the model is trained on a part of the chip netlist, it can directly generate a layout on other unlaid netlists without the need for additional training.

[0072] In the embodiments of the present application, cells include fixed cells and movable cells. Fixed cells are components that are fixed in position and cannot be moved, such as a terminal or a port. Fixed cells generally occupy a larger area or volume than movable cells.

[0073] Removable cells usually include standard cells and macrocell modules. Macrocells mainly include storage cells and various customized IPs, which are the main functional modules of integrated circuits. For example, storage cells can be RAM, ROM, etc. Standard cells are a collection of underlying electronic logic functions, such as AND-OR-NON gates, triggers, latches, etc.

[0074] The position of fixed units such as ports is generally immovable, so the objects of chip layout are mostly movable units. In the process of layout of movable units, the position information of fixed units can be referred to.

[0075] To avoid confusion, the solution provided by the embodiment of the present application is described below in two stages: a training stage and an application stage.

[0076] In the training phase, the present application embodiment provides a chip layout training method. Figure 1 An example of a system architecture for executing a chip layout training method is shown.

[0077] The embodiment of the present application adopts self-supervised learning, at least with graph neural network as the training target. First, sample chips that can be used as training samples are screened out, and the netlists corresponding to the sample chips are used as training data. The sample chips are chips that have completed the layout and all performance indicators meet expectations. For example, the training samples can specifically be the four netlists of mgc_fft_1, mgc_fft_2, mgc_fft_a and mgc_fft_b of the ISPD2015 data set.

[0078] The netlist file (hereinafter referred to as the netlist) is a description of the logical structure of the circuit design. Generally, the netlist consists of cells, pins, ports (Terminal / Port) and networks (Net). The network includes multiple network lines.

[0079] The netlist generally includes LEF (Library Exchange Format) files containing physical library information and DEF (Design Exchange Format) files containing circuit physical information. The DEF file gives information such as the location of the unit, the location of the pins, the direction of the signal and the size of the unit, the connection relationship between the pins and the net wires, and the connection relationship between the pins and the units.

[0080] After the training data is determined, the input of the graph neural network is obtained according to the training data. The input features (initial features) and graph structure information are extracted from the netlist (first netlist) corresponding to the sample chip and input into the graph neural network. The input features include at least unit features and mesh features. For example, in some embodiments, the input features may be unit features and mesh features; in other embodiments, the input features may also include pin features.

[0081] The graph structure information and the unit features, the network features, or the pin features are input into the graph neural network, and the message transmission, fusion and update of the node features are performed through the graph neural network to obtain the output features, and the output features at least include the unit features. For example, in some embodiments, the output features are only unit features, and in other embodiments, the output features include unit features and network features.

[0082] Among them, the graph neural network can adopt one of the graph convolution networks (Graph Convolution Networks, GCN), graph attention networks (Graph Attention Networks), graph autoencoders (Graph Autoencoders), graph generative networks (Graph Generative Networks) and graph spatial-temporal networks (Graph Spatial-temporal Networks), or a combination of two or more of them.

[0083] After obtaining the output, relative position encoding is performed based on the output features to obtain relative position information, which is the predicted value obtained based on the graph neural network.

[0084] The training method of the embodiment of the present application is implemented based on the idea of ​​self-supervised learning, and can complete training on unlabeled data, and requires mining its own supervisory information from the training data.

[0085] The netlist generally records the specific location information of each unit, so the location information of each unit can be obtained from the netlist. In the embodiment of the present application, the location information recorded in the netlist is defined as absolute location information. Generally speaking, the absolute location information is the location information of each unit on the chip relative to the unified coordinate origin.

[0086] In order to solve the problem of difficulty in migration in other training methods, the embodiment of the present application proposes relative position information and relative position encoding. During training, the output features of the graph neural network are mapped to relative position information through relative position encoding, and the value of the loss function is calculated based on the relative position information, and the trainable parameters are updated by gradient. The relative position encoding is a SE (2) (Special Euclidean Group 2, 2-dimensional special Euclidean group) isovariant encoding method, that is, it is insensitive to translation and rotation in two-dimensional space, so as to ensure that the layout learned by the graph neural network model can be generalized between different chip netlists, and self-supervised training is used to enable the graph neural network to learn layout knowledge from the laid out chip netlist.

[0087] Different from the application phase, in the training phase, the relative position information of each unit in the sample chip can be obtained based on its absolute position information.

[0088] For example, based on the absolute position information of the ith unit and the jth unit, the relative position information of the jth unit relative to the ith unit can be calculated. In this way, based on the absolute position information of each unit, the relative position information between different units in the sample chip, that is, the relative position information between different units on the chip that has been laid out, can be obtained.

[0089] To prevent confusion, the relative position information obtained after encoding the features output by the graph neural network is defined as the second relative position information, and the relative position information calculated based on the absolute position information of the sample chip is defined as the first relative position information. The first relative position information can be understood as self-supervisory information extracted from the training sample, that is, the label, without the need for additional annotation.

[0090] Then, based on the first relative position information and the second relative position information, the value of the loss function is calculated, and based on the loss function value (Ltrain), the trainable parameters in the graph neural network are optimized. This process is repeated until the graph neural network converges and the training is completed.

[0091] It should be noted that, in some embodiments, encoding the output features may be performed by mapping the features into relative position information through an encoding function, wherein the encoding function may include trainable parameters, and therefore, the training target may include trainable parameters in the encoding function in addition to the trainable parameters in the graph neural network. Of course, in other embodiments, the encoding function may not include trainable parameters, but only contain hyperparameters, that is, the parameters of non-independent variables are all constants or pre-set without gradient updates.

[0092] Specifically, the chip layout training method provided in the embodiment of the present application may include the following process:

[0093] S201, determine first relative position information.

[0094] The first relative position information is the relative position information between different units in each unit that has been laid out in the sample chip. The first relative position information can be calculated based on the absolute position information of each unit that has been laid out in the sample chip. The absolute position information can be obtained from the netlist.

[0095] For example, the relative position information of the jth unit relative to the i-th unit can be calculated based on the absolute position information (e.g., coordinate information) corresponding to the jth unit and the i-th unit, respectively. Wherein, i and j are both integers greater than or equal to 1, and i≠j. In some embodiments, the relative position information is expressed in the form of polar coordinates, such as the polar coordinate information of the jth unit relative to the i-th unit, including the polar diameter and the deflection angle. In other embodiments, other coordinates can also be used to record the relative position information between units, for example, using a plane rectangular coordinate system or a space rectangular coordinate system, a cylindrical coordinate system, a spherical coordinate system, etc.

[0096] Different from the polar diameter and polar angle in the ordinary polar coordinate system, in the relative position information proposed in the embodiment of the present application, the polar diameter is the modulus of the directed vector between the j-th unit and the ith unit, rather than the polar diameter of the j-th unit relative to the coordinate origin; the deflection angle is the polar angle corresponding to the vector from the ith unit to the j-th unit, relative to the deflection angle of the polar angle corresponding to the vector from the k-th unit to the ith unit.

[0097] S202, determine the first input of the graph neural network to be trained.

[0098] The input data obtained according to the first netlist is defined as the first input. In some embodiments, the input includes input features and graph structure information, wherein the input features include at least unit features, and in some embodiments, the input features may include unit initial features, net line initial features, and pin initial features, and these initial features may be input into the graph neural network in the form of feature vectors or feature matrices.

[0099] For example, the netlist contains information such as the size and position (initial position) of each unit. By using the values ​​of this information as elements in a vector, the initial feature vector of the unit can be obtained; the netlist contains information such as the position, size, number, and spacing of the pins. By using the values ​​of this information as elements in a vector, the initial feature vector of the pins can be obtained. Similarly, based on the network cable related information contained in the netlist, the initial feature vector of the network cable can be obtained.

[0100] There is no restriction on the execution sequence of S202 - S204 and S201 , and S202 - S204 can be executed before S201 .

[0101] S203, obtaining a first output through a graph neural network.

[0102] The first output may specifically be an output feature, where the input feature and graph structure information are input into the graph neural network to be trained, and feature extraction is performed through the graph neural network to obtain the output feature. The output feature includes at least a unit feature, and in some embodiments may also include a mesh feature.

[0103] It should be noted that the word order limitations such as "first" and "second" are only for distinguishing different description objects to prevent confusion, and do not limit the execution sequence or priority of the description objects. "First" and "second" can be objects of the same category or different categories.

[0104] S204: Perform encoding based on the first output to obtain second relative position information.

[0105] In some embodiments, an independent variable can be determined based on the first output, and then an encoding function is performed on the independent variable to obtain the second relative position information. The process of executing the encoding function is equivalent to a mapping process, in which the independent variable is mapped to the second relative position information through the encoding function. The second relative position information is a predicted value obtained based on the graph neural network. The first relative position information is a label.

[0106] S205, calculating a loss function value based on the first relative position information and the second relative position information; and optimizing trainable parameters in the graph neural network based on the loss function value.

[0107] The loss function may be one or more of a cross entropy loss function (Cross Entropy Error Function), a mean squared error loss function (MSE), and Smooth_L1. In other embodiments, it is not excluded that a HingeLoss0-1 loss function, a logarithmic loss function, etc. may be used, and this application specification does not list them one by one.

[0108] The training phase is used to at least train the graph neural network, optimize the trainable parameters, and at least obtain a graph neural network with the expected prediction performance. After the training is completed, the application phase begins, and the trained graph neural network is used to layout the chips to be laid out.

[0109] In the application stage, the embodiment of the present application provides a chip layout method. Figure 3 An example of a system architecture for executing the chip layout method is shown.

[0110] To avoid confusion, the netlist corresponding to the sample chip is defined as the first netlist, and the netlist corresponding to the chip to be laid out in the application phase is defined as the second netlist.

[0111] Extract input features and graph structure information from the second netlist, input them into the graph neural network, obtain output features through the graph neural network, encode the output features in relative position, and obtain relative position information (third relative position information). Different from the training stage, after obtaining the third relative position information, combine the graph structure, and infer the absolute position information of each unit through the relative position information. This inversion process is decoding, and the layout is completed.

[0112] In the application stage, the chip layout method proposed in the embodiment of the present application is combined with Figure 3 and Figure 4 As shown, the following process may be included:

[0113] S401, determine the second input of the graph neural network after training.

[0114] The input data obtained according to the second netlist is the second input. The data format of the input and output of the graph neural network in the training phase and the application phase is consistent. In the application phase, the input of the graph neural network also includes input features and graph structure information. The input features include at least the unit features (initial features) corresponding to each unit in the chip to be laid out. In other embodiments, the input features may include unit initial features, network cable initial features, or also include pin initial features.

[0115] Regarding the graph structure information, in some embodiments, at least multiple subgraphs can be obtained based on the second netlist; then the graph structure information is extracted from the multiple subgraphs, and the graph structure information and input features corresponding to the multiple subgraphs are used as input data (second input) and input into the graph neural network. The graph structure information can specifically be an adjacency matrix. In other embodiments, it can also be other data formats that can digitally express the graph structure information. For example, the graph structure information corresponding to the multiple subgraphs can be one or more of the connection lists, cross-link lists, connection multi-lists, and edge set arrays corresponding to the multiple subgraphs.

[0116] The netlist contains the connection relationship and geometric topology information between units, wires and pins, and the corresponding netlist diagram can be constructed based on the netlist. Inputting a large-scale netlist into the graph neural network at one time requires building a neural network with a huge number of neurons and large-scale computing capabilities. These obstacles reduce the feasibility of the solution implementation.

[0117] In the embodiment of the present application, it is proposed to divide the large-scale netlist graph corresponding to the chip into multiple blocks, and establish a corresponding subgraph for each block, so that multiple subgraphs can be obtained. In this way, each subgraph can be input into the graph neural network one by one and processed separately to reduce the single processing pressure of the graph neural network.

[0118] Specifically, see Figure 5 As shown, in some embodiments, the following method can be used to obtain multiple sub-images:

[0119] Based on the netlist file (second netlist) of the chip to be laid out, a hypergraph is created. In the hypergraph, nodes represent units and hyperedges represent network lines. A hyperedge can connect more than 3 nodes. The hypergraph is divided into N blocks to obtain the corresponding N first subgraphs and 1 first global graph.

[0120] The first subgraph is used to represent the connection relationship between different units in a block through network cables, and the first global graph is used to represent the connection relationship between blocks in N blocks through network cables, that is, the connection relationship within the block is expressed by the first subgraph, and the connection relationship between blocks is expressed by the global graph. N≥2. The first subgraph and the first global graph are still hypergraphs, in which the nodes still represent units and the hyperedges represent network cables.

[0121] Expand N first subgraphs and 1 first global graph respectively to obtain corresponding N second subgraphs and 1 second global graph. The expansion process is the process of expanding the hypergraph into a normal graph. In a normal graph, an edge can only connect two nodes at most. Specifically, clique expansion, star expansion, line expansion (LE), and connected component expansion methods can be used. In the second subgraph and the second global graph obtained after expansion, nodes represent units or network cables, and connecting edges represent pins, such as Fig.11 , which shows an example of a second sub-image.

[0122] In some embodiments, after obtaining multiple second sub-graphs and the second global graph, the graph structure information of the multiple second sub-graphs and the second global graph can be extracted and used together with the input features as the input of the graph neural network.

[0123] It should be noted that constructing a hypergraph is not a necessary process for obtaining multiple subgraphs. In other embodiments, the netlist graph can also be divided directly, that is, there is no need to establish a hypergraph first, but directly construct a large-scale netlist graph based on the netlist, and then divide it to obtain multiple subgraphs.

[0124] Cluster analysis can be used for the division of hypergraphs or netlists. Units with more closely connected relationships are divided into the same block as much as possible, and units with sparse connections are divided into different blocks. The degree of connection can be characterized by the number of net lines between units.

[0125] In some embodiments, after obtaining the corresponding N second subgraphs, a corresponding unit flow graph may also be established:

[0126] According to the signal direction information included in the second netlist, N unit flow graphs corresponding to the N second subgraphs are established.

[0127] In the unit flow graph, a node represents a unit, and the connecting edge between nodes is a directed edge, which is used to represent a network cable. The direction of the directed edge is determined according to the signal direction, and the signal direction information can be obtained in the netlist. Optionally, in some embodiments, the second global graph can also establish a corresponding global flow graph, and in other embodiments, the global flow graph corresponding to the second global graph may not be established.

[0128] Based on the unit flow graph, multiple directed edges (unit flow graph edges) and unit paths can be obtained. Among them, the unit path is a path starting from the starting node and passing through at least one directed edge. For example, the unit path corresponding to the jth unit node is the path starting from the starting node and ending at the jth unit node. Except for the starting node, each node has at least one corresponding path.

[0129] After obtaining multiple unit flow graphs, at least multiple second sub-graphs, one second global graph, and graph structure information corresponding to multiple N unit flow graphs are input into the graph neural network together with input features.

[0130] Exemplarily, the unit flow graph is established according to the second subgraph in the following manner:

[0131] In a second subgraph, a cell is considered as a starting node. The cell considered as a starting node can be a macro cell or other cells. Generally, a cell with a larger area is selected as the starting node. In a block containing a port, the port is generally considered as the starting node. The number of starting nodes in a block can be 1 or more.

[0132] After determining the starting node, next, by searching, directed edge connections are established between other nodes and the starting node in turn to obtain a unit flow graph. When searching, a depth-first search (DFS) or a breadth-first search (BFS) can be used.

[0133] In other embodiments, a hierarchical search method may also be used:

[0134] Search for cells connected to the start node through a network cable as the first-order neighboring nodes corresponding to the start node, and generate directed edges between the start node and each first-order neighboring node according to the signal direction. Then, search for cells connected to the first-order neighboring node through a network cable as the second-order neighboring node corresponding to the start node; generate directed edges between the first-order neighboring node and the second-order neighboring node according to the signal direction; continue to search for the next-order neighboring node until all cells in the same second subgraph are visited, and a cell flow graph is obtained.

[0135] In this way, after the above process, multiple second sub-graphs, a second global graph, multiple unit flow graphs, and the initial features of each unit, the initial features of each network cable, and the initial features of each pin (feature vectors) are obtained. These feature vectors and the adjacency matrices corresponding to the multiple graphs are input into the graph neural network together.

[0136] S402, obtaining a second output through the graph neural network.

[0137] In some embodiments, the graph neural network is a graph convolutional neural network, which includes at least one convolutional layer.

[0138] Through the graph neural network, in the convolution layer, features are transferred between nodes by executing at least one of the first convolution function, the second convolution function and the third convolution function.

[0139] See also Figure 6 As shown, the first convolution function is used to transfer the network line features corresponding to each network line connected to the ith unit to the node corresponding to the ith unit based on the connection relationship information between the nodes and the network lines in the second subgraph (i.e., the graph structure information), to obtain the ith first unit sub-feature, where i ≥ 1 and is an integer.

[0140] The second convolution function is used to transfer the unit features of each unit connected to the tth network line to the node corresponding to the tth network line based on the connection relationship information between the nodes and the network lines in the second subgraph, so as to obtain the network line features corresponding to the tth network line, where t≥1 and is an integer.

[0141] The third convolution function is used to transfer the unit features of each unit connected to the i-th unit to the node corresponding to the i-th unit based on the graph structure information corresponding to the unit flow graph, so as to obtain the i-th second unit sub-feature.

[0142] Based on the i-th first unit sub-feature and the i-th second unit sub-feature, the output feature corresponding to the i-th unit is obtained. For example, the first unit sub-feature and the second unit sub-feature are weighted summed, or the feature obtained by direct summation is used as the output feature corresponding to the i-th unit. In other embodiments, the first unit sub-feature and the second unit sub-feature may be vector-concatenated, and the obtained vector is used as the feature vector output by the i-th unit.

[0143] In some embodiments, the output feature may only include the feature vector corresponding to the unit. In other embodiments, the network cable feature corresponding to the t-th network cable obtained after the above message transmission may also be output as the feature vector corresponding to the t-th network cable.

[0144] It should be noted that, in some embodiments, in the second subgraph, the connecting edges between nodes represent pins. Under the premise that the input features include pin features, when performing message passing in the convolution layer, the pin features of the pins connected to the unit node or the network cable node can be aggregated to the i-th unit node or the t-th network cable node through a convolution function, such as through a first convolution function and / or a second convolution function, so that the output unit features or network cable features contain the pin feature information.

[0145] S403, performing encoding based on the second output to obtain third relative position information.

[0146] The encoding performed on the output of the graph neural network is relative position encoding. Specifically, in some embodiments, the independent variable can be determined based on the second output (output feature), and the encoding function is performed on the independent variable to obtain the third relative position information. The role of the encoding function is to map the output feature to relative position information (third relative position information), and the output feature can be converted into an independent variable. The specific conversion method can be a cascade operation on the output feature vector, etc.

[0147] Specifically, in some embodiments, the encoding function may include a first encoding function and a second encoding function. The relative position encoding process may be based on the second output, determine the first independent variable, execute the first encoding function on the first independent variable, and obtain the polar diameter; based on the second output, determine the second independent variable, execute the second encoding function on the second independent variable, and obtain the deflection angle; the deflection angle represents the relative value of the polar angle corresponding to different units.

[0148] Exemplarily, the output includes unit features corresponding to each unit and network features corresponding to each network line. Based on the second output, the first independent variable can be determined in the following manner: based on the unit features corresponding to the i-th unit and the j-th unit in the second output, and the network features corresponding to the t-th directed edge, the first independent variable is obtained. The t-th directed edge is a directed edge connecting the i-th unit and the j-th unit in the unit flow graph.

[0149] Similarly, based on the second output, the second independent variable can be determined in the following manner:

[0150] At least one path corresponding to the jth unit is searched in the unit flow graph, and one of them is selected as the first path. As mentioned above, a path is a directed path formed by at least one directed edge starting from a start node and ending at a node corresponding to the jth unit in the unit flow graph.

[0151] Based on the unit features corresponding to each node passed by the first path in the second output and the network features corresponding to at least one directed edge, the second independent variable is obtained. For example, the features corresponding to each node and each edge passed by the path are spliced ​​into a feature vector as the second independent variable. Alternatively, the weighted sum of each node feature and each edge feature is taken as the second independent variable. Wherein, i, j and t are all integers greater than or equal to 1.

[0152] After determining the independent variable, the corresponding encoding function is executed to obtain the relative position information. The encoding function may include trainable parameters, which can be optimized through training during the training phase.

[0153] S404, performing decoding at least according to the third relative position information to obtain absolute position information of each unit in the chip to be laid out.

[0154] In some embodiments, layer-by-layer decoding may be performed in the following manner:

[0155] Determine the starting node in a subgraph and the absolute position information of the starting node, determine the absolute position information of the first-order neighboring node according to the third relative position information of the first-order neighboring node corresponding to the starting node and the absolute position information of the starting node; determine the absolute position information of the m+1-order neighboring node according to the absolute position information of the m-order neighboring node and the third relative position information of the m+1-order neighboring node; m≥1 and is an integer.

[0156] For the jth unit, there may be multiple unit paths with the jth unit as the end node, so when searching for at least one path with the jth unit as the end node in the unit flow graph, more than two unit paths may be obtained. The search may be DFS or BFS.

[0157] In this case, based on the position information (absolute position information or relative position information) corresponding to the starting node of each path in at least one path and the relative position information of each other node passed by the path, a feasible solution of the j-th unit relative to the path is obtained, and then multiple unit paths can obtain multiple absolute position information, that is, multiple feasible solutions, and then based on the multiple feasible solutions, the absolute position information of the j-th unit is obtained. For example, multiple feasible solutions are averaged. In other embodiments, one of the multiple unit paths where the j-th unit is the end node can be selected for decoding without the need for averaging. Or a weighted sum is performed on multiple feasible solutions corresponding to multiple paths, and so on. The specific implementation method is not unique.

[0158] Optionally, after obtaining the absolute position information of the unit through decoding, it can also be fine-tuned:

[0159] The absolute position information of each unit is used as the initial solution to calculate the objective function; the objective function uses at least one of line length, density, and anchor point as a constraint; the objective function includes at least one hyperparameter among learning rate, number of iterations, and loss function weight; the absolute position information of each unit is updated by gradient. For example, the gradient descent method is used to iteratively update the position of the unit.

[0160] The embodiment of the present application proposes a transferable self-supervised learning chip layout framework, which encodes the relative position relationship between units and uses it as the output and training target of the model, so that the model can migrate the existing layout information of the chip to the chip to be laid out, saving the resources required for iteration in chip design. Compared with other methods, the model provided by the embodiment of the present application can generate competitive layout solutions on different chips and speed up the iteration speed of chip design.

[0161] To further understand the method provided in the embodiments of the present application, a specific embodiment is listed below. This embodiment is only for illustrative purposes, and other embodiments can be adaptively obtained based on this embodiment:

[0162] Different from the application stage, in the training stage, the absolute position information of each unit laid out in the sample chip needs to be encoded into relative position information. Taking the jth unit, the ith unit and the kth unit as an example, the specific encoding method is as follows:

[0163] The jth unit is connected to the ith unit through a network cable, and the ith unit is connected to the kth unit through a network cable. The signal flows from the kth unit to the ith unit, and from the ith unit to the jth unit. It is assumed that the kth unit is the starting node.

[0164] Then, the relative position information of the jth unit relative to the ith unit can be obtained as follows:

[0165]

[0166] Among them, v i represents the i-th unit, v j represents the jth unit, p i For the i-th unit v i The absolute position, p j For the jth unit v j The absolute position of represents the edge set in the constructed unit flow graph, (v i , v j )express A cell flow graph edge in ; vector The polar coordinates ρ i，j ,θ i，j In the form of i，j For vector The modulus length, θ i，j For vector The polar angle, θ i，j for The angle with the horizontal direction;

[0167]

[0168] Next, calculate the deflection angle Δθ i，j , as shown in formula (3):

[0169] Δθ i，j =θ i，j -θ k，i Formula (3)

[0170] Among them, θ k，i is the polar angle corresponding to the vector pointing from the kth unit to the ith unit,

[0171] where(v k , v i ) = f INCOME (v i )

[0172] f INCOME (v i ) represents the vector from the kth unit to the ith unit, that is, the unit flow graph edge from the kth unit to the ith unit.

[0173] (ρ i，j ,Δθ i，j ) is the relative position information of the j-th unit relative to the ith unit.

[0174] For example, see Figure 8As shown, node 1 is the starting node, and the polar radius of the vector (unit flow graph edge) from node 1 to node 3 is ρ 1,3 =1.00, polar angle θ 1,3 = 0.0π, the polar radius ρ corresponding to the vector (unit flow graph edge) from node 3 to node 4 3,4 =1.12, polar angle θ 3,4 =0.35π, then the relative position information of node 2 relative to node 1 is (ρ 1,3 =1.00, Δθ 1,3 =0.0π); the deflection angle Δθ of node 4 relative to node 3 3,4 =θ 1,3 -θ 3,4 =-0.35π, then the relative position information of node 4 relative to node 3 is (ρ 3,4 =1.12, Δθ 3,4 =-0.35π).

[0175] Where edge represents the vector from one node to another node (unit flow graph edge), ρ represents the polar radius, and Δθ is the deflection angle.

[0176] In this way, the first relative position information corresponding to the other multiple units can be obtained as labels.

[0177] In addition, based on the netlist corresponding to the sample chip, the input data of the graph neural network is determined, and the input data is input into the graph neural network to obtain output features, and then the output features are relatively position encoded and mapped to second relative position information.

[0178] The second relative position information is the predicted value, and the first relative position information is the label. The loss value is calculated through the loss function, and the gradient descent method is used to update the trainable parameters until the graph neural network model converges.

[0179] For example, see Figure 7 As shown, during the training phase, on the one hand, the input features and graph structure information are input into the graph neural network GNN, and the output of the GNN is encoded to obtain the predicted relative position. On the other hand, the actual layout (absolute position) of the sample chip is encoded to obtain the actual relative position, and then the loss function value is calculated based on the actual relative position and the predicted relative position. Figure 7 This is only a schematic diagram, in which the second subgraph can be understood as a part of the input, not the entire input, and the construction of the second subgraph will be elaborated in detail in the application stage. In this embodiment, the loss function is Smooth_L1.

[0180] In other embodiments, the loss function may be a cross entropy loss function (Cross Entropy Error Function) or a mean squared error loss function (MSE), or other loss functions that can be adjusted to be suitable for calculating the relative error between positions. For example, the use of HingeLoss0-1 loss function, logarithmic loss function, etc. is not excluded, and the present application specification does not list them one by one.

[0181] In this embodiment, both the graph neural network and the encoding function contain trainable parameters, and the objects of gradient update include the trainable parameters in the graph neural network and the trainable parameters in the encoding function. In other embodiments, the encoding function may not contain trainable parameters, so the objects of gradient update may only be the trainable parameters in the graph neural network.

[0182] Among them, the process of determining the input based on the netlist and obtaining the output features through the graph neural network will be elaborated in detail in the application stage.

[0183] It should be noted that there is no clear order limitation in the execution sequence of the process of obtaining the first relative position information based on the absolute position information and obtaining the second relative position information through prediction and encoding.

[0184] After the graph neural network, or the encoding function, is trained, it can enter the application stage.

[0185] In the application stage, the second relative position information is predicted based on the trained graph neural network, and decoded according to the second relative position information to obtain the absolute position information of each unit.

[0186] In this embodiment, after the predicted absolute position information is obtained, the position information is fine-tuned. In other embodiments, fine-tuning may not be performed. Fig. 9 As shown, the application stage can be specifically divided into the following three stages: part 1, the composition stage; part 2, the inductive layout generation stage; part 3, the netlist adaptive fine-tuning stage.

[0187] In the composition phase, netlist segmentation is performed and at least a unit flow graph is constructed:

[0188] After the netlist is segmented, a hierarchical netlist diagram is obtained, and a unit flow diagram can be established based on the hierarchical netlist diagram.

[0189] The chip netlist stores the topological information and geometric prior knowledge generated by the chip during the logic synthesis stage. A graph containing graph structure information can be constructed based on the netlist of the chip to be laid out.

[0190] Inductive layout generation phase:

[0191] Based on the netlist, the initial features of the unit, the initial features of the mesh, and the initial features of the pin are generated. In other embodiments, the pin features may not be generated. Then, the initial features of the unit, the initial features of the mesh, and the initial features of the pin are used as input features, and the input features and the graph structure information corresponding to the hierarchical netlist diagram and / or the unit flow diagram are input into the graph neural network, and the output features are encoded to generate the relative positions between the units. Then, according to the unit flow diagram and the relative positions between the units, decoding is performed to obtain the absolute positions of each unit.

[0192] The inductive layout generation stage is the prediction stage, which predicts relative positions through graph neural networks.

[0193] Netlist adaptive fine-tuning stage:

[0194] In the netlist adaptive fine-tuning stage, the absolute position of each unit obtained by inductive layout is used as the initial solution. Based on the netlist information, hyperparameters such as learning rate, number of iterations, and loss function weight are set, the objective function is calculated, the unit position is updated according to the gradient, and the objective function is recalculated. The above process is repeated continuously to obtain the final unit position.

[0195] In this embodiment, the netlist adaptive fine-tuning may include adaptive adjustment of differentiable objective functions and / or density function weights based on wire length, density, and anchor points. For example, by using differentiable objective functions based on wire length, density, and anchor points, the cell position is optimized by using a gradient descent method, and the weight of the density function is adaptively updated during the process of continuously iteratively updating the cell position.

[0196] The following describes in detail how each stage is implemented. In the graphing stage, specifically, in this embodiment, firstly, a hypergraph is established based on the netlist, with units (including fixed units and movable units) as nodes and the net lines between units as edges.

[0197] ordinary Figure 1 An edge can only connect two nodes, while an edge in a hypergraph can connect multiple nodes (greater than or equal to 2 nodes). An edge in a hypergraph is equivalent to a face, and the points connected by the edge are the points contained in the face.

[0198] Compared with building a normal graph based on a netlist, building a hypergraph based on a netlist can reduce the difficulty of graph composition. This is because the logical structure of a large-scale netlist is extremely complex and the number of units is huge. If a normal graph is built, the difficulty coefficient is large, it is time-consuming, and even impossible to implement. Building a hypergraph based on the netlist first allows one edge to connect more nodes, which can reduce the difficulty of graph composition and facilitate the rapid establishment of the graph structure.

[0199] The connection relationship between pins and units and the connection relationship between pins and meshes are recorded in the netlist. In this embodiment, a mapping between pins and units can be established based on the connection relationship between pins and units in the netlist, and the connection relationship between pins and meshes can be mapped to the connection between units and meshes in combination with the connection relationship between pins and meshes.

[0200] Then, the network cables are regarded as hyperedges, and the nodes connected by the hyperedges are the units connected by the network cables, and a hypergraph is established with the units as nodes and the network cables as hyperedges.

[0201] In order to quantitatively express the complex properties of the netlist, the hypergraph (netlist graph) form is defined as follows:

[0202]

[0203] in Represents a unit, where They represent terminal / port and movable cells respectively. Represents a network cable, a hyperedge that is not connected to a unit in the hypergraph, and a pin Indicates the interaction between the unit and the network cable. They are and The corresponding feature matrix is, Stored port The horizontal and vertical position information may be, for example, horizontal and vertical coordinate information.

[0204] Next, a partitioning procedure is performed on the hypergraph to divide the hypergraph into N blocks.

[0205] In this embodiment, during the execution of dividing the hypergraph into N blocks, different macro units cannot be divided into the same block at the same time, that is, the number of macro units in each block after division is less than or equal to 1. Specifically, in this embodiment, different macro units are divided into different blocks, and with the macro unit as the center, standard units that have more connections with the macro unit are divided into the same block as much as possible. Fixed units (such as ports) can be divided into a block alone, or divided into the same block with similar macro units.

[0206] The partitioning procedure can be implemented by a clustering algorithm, such as a K-means clustering algorithm, a K-Medoids algorithm, a CLARANS algorithm, etc., or a derivative or improved algorithm based on the above algorithms. When clustering, the macro cells and ports can be first divided into different blocks, and then for the standard cells, whether they are connected to the same macro cell is used as a clustering feature, and the standard cells to be divided are grouped according to the similarity of their own features. The standard cells connected to the same macro cell are divided into one group. The more connection edges there are with the macro cell, the more priority they are divided into the group. Multiple clusters can be obtained, and one cluster corresponds to one block.

[0207] It should be noted that there are various specific implementations of dividing into N blocks according to different division rules. For example, in some other embodiments, the division can also be performed according to the number of units, and the maximum and minimum values ​​of the number of units in each block can be set.

[0208] Alternatively, in some other embodiments, the macrocells and ports may be first divided into different blocks, and the ports and macrocells may be divided into the same block or into different blocks. Then, for the standard cells, the macrocells or ports may be used as the center point of the cluster, and the standard cells may be clustered according to the Euclidean distance between the standard cells and the macrocells or ports, and the cells that are closer in distance may be divided into the same block. There are many specific implementation methods, which are not listed one by one in this application specification.

[0209] When the division is completed, multiple blocks are obtained, and each unit belongs to a unique block B. i , for each block B i , build a hypergraph (First sub-image). The node is block B i The contained units, the hyperedge is only connected to block B i Network cable of the inner unit.

[0210] Secondly, treat each block as a node and build a hypergraph (First Global Graph), Hypergraph The nodes in the hypergraph are the blocks after division. The edges in are the wires connecting the units in different blocks. In this way, we get N+1 hypergraphs, including N first subgraphs and 1 first global graph. in, It is used to indicate the connection relationship between blocks and does not contain the logical structure information within the block.

[0211] Then, the N+1 hypergraphs are expanded respectively, and for each hypergraph, a corresponding common graph is established. In this embodiment, the star expansion method is used for the hypergraph. In other embodiments, one or more of other expansion methods can be used.

[0212] After the hypergraph is expanded, N+1 ordinary graphs are obtained, among which N first subgraphs are expanded to obtain N second subgraphs, and the first global graph is expanded to obtain the second global graph. The second subgraph and the second global graph are both ordinary graphs, including two types of nodes, units and wires. The edges in the graph are the connections between wires and units, that is, the edges represent pins, and the nodes represent units or wires. It should be noted that the subgraph obtained after the division (the first subgraph or the second subgraph) is defined as a hierarchical netlist graph in the embodiment of the present application, and the hierarchical netlist graph can be the first subgraph or the second subgraph.

[0213] For example, see Fig.10 As shown, the netlist diagram (hypergraph) Partition the set, where nodes 3 and 4 are divided into the same block B1, and nodes 5 and 6 are divided into the same block B2, to obtain a hypergraph and Hypergraph It should be noted that Fig.10 This is only a schematic diagram, the netlist diagram Hypergraph and Hypergraph In the diagram, each edge only connects two nodes. In the actual netlist diagram, each edge connects more than two nodes, not limited to two nodes.

[0214] from Fig.10 It can be seen that after being divided into multiple blocks, hierarchical layout can be performed, that is, first determine the layout between blocks, and then reconstruct the layout within each block into the corresponding block to obtain a complete netlist layout.

[0215] The netlist (hypergraph) and the subgraphs after division established above are undirected graphs, which only retain the topological connection relationship of the chip. In chip design, the signal flow (i.e., signal direction) is also one of the important factors that determine the layout. Next, according to the N subgraphs, the corresponding N unit flow graphs are established. The unit flow graph is a directed graph that carries the signal flow information.

[0216] Exemplarily, the unit flow chart process is established as follows Fig.11 As shown, in this embodiment, for each common graph (second subgraph) in the hierarchical netlist graph, a corresponding unit flow graph is established. In other embodiments, the unit flow graph can be established according to the first subgraph, that is, the first subgraph is not expanded, but directly based on the first subgraph, based on the topological relationship expressed by it, a corresponding unit flow graph is established.

[0217] In this embodiment, the specific method of establishing the unit flow graph is:

[0218] In each common graph (second subgraph), the starting point is first determined. The number of starting nodes may be one or more than two.

[0219] The principle of determining the starting point may be to regard the macrocell as the starting node, and if there is no macrocell, the cell with the largest area is used as the starting node. For example, if there is no macrocell, the port may be used as the starting point. If there is neither a macrocell nor a port, the cell with the largest area among the standard cells is used as the starting point. In other embodiments, any cell may be selected as the starting point, or the cell with the largest area may be directly selected as the starting point.

[0220] Alternatively, two units can be selected as starting nodes. For example, when a subgraph contains more than two ports, both ports are used as starting nodes; or when a subgraph includes a macro unit and at least one port, both the macro unit and one port are used as starting nodes.

[0221] Put the node as the starting point into the queue, search for the unit connected to the same network line as the starting point, and establish an edge connection between the starting point and the unit according to the signal flow direction. Put the unvisited units into the queue one by one until all units have been visited, and the construction of a unit flow graph is completed.

[0222] More generally, when building a unit flow graph, an ordered traversal can be used, that is, when traversing, first traverse the first-order neighboring nodes of the starting node, establish directed edges between the starting node and the first-order neighboring nodes, then traverse the second-order neighboring nodes, establish directed edges between the first-order neighboring nodes and the second-order neighboring nodes, and so on, until all units in the same subgraph are visited and the construction of the unit flow graph is completed.

[0223] For example, Fig.11 As shown, in the first subgraph, nodes 0 and 1 are ports, nodes 2-6 represent movable units, and the connecting edges between nodes are network cables. In the second subgraph, nodes 0-6 represent units, nodes af represent network cables, and the connecting edges between units and network cables represent pins.

[0224] On the basis of the second subgraph, a unit flow graph is established. Among the nodes 0-6 representing the unit, node 0 and node 1 are selected as the starting nodes. It can be known from the first subgraph that both node 0 and node 1 are ports.

[0225] Then, traverse other unit nodes connected to node 0 through the same network line. From the second subgraph, the connection through the same network line is represented as being connected to the same network line node. For example, node 0 and node 2 are both connected to network line node a, that is, node 0 is connected to node 2 through a network line a, then node 2 is the first-order neighbor node of node 0, and node 3 and node 0 are connected to network line node b at the same time, then node 3 is also the first-order neighbor node of node 0.

[0226] A directed edge is established between node 0 and node 2, and a directed edge is established between node 0 and node 3.

[0227] Next, among the first-order neighbor nodes, there is no other node connected to the same network node as node 2, so the traversal continues to the first-order neighbor node 3. Node 3 and node 4 are connected to the network node d together, so node 4 is the second-order neighbor node of the starting node 0. A directed edge is established between the first-order neighbor node 3 and the second-order neighbor node 4. And so on. Through traversal, it can be determined that node 5 is the second-order neighbor node of the starting node.

[0228] Taking node 1 as the starting node, both node 1 and node 5 are connected to network cable node c. Node 5 is the first-order neighbor node of starting node 1, and there is no other first-order neighbor node. A directed edge is established between node 1 and node 5. Continue traversing and find that both node 6 and node 5 are connected to network cable node f, that is, node 5 is connected to node 1 through a network cable c, and node 6 is connected to node 5 through a network cable f. Then node 6 is the second-order neighbor node of starting node 1, and a directed edge is established between node 6 and node 5.

[0229] In this way, based on the unit flow graph, multiple directed edges are obtained, and the directed edges are defined as unit flow graph edges f INCOME .

[0230] In this embodiment, for each unit flow graph, continue to construct the unit path f path A unit path refers to a connection path in a unit flow graph that starts from the start node and passes through at least one unit flow graph edge. Fig.11 As shown in , based on the unit flow graph shown therein, multiple unit paths of 0→2, 0→3, 0→3→4, 1→5, 0→3→5, 1→5→6 are obtained.

[0231] More generally, as shown in the following formula (5), where v i represents the unit, t represents the path length, (v0, v1, ..., v t ) P Indicates a path.

[0232] (v0, v1, ...v t )P=f PATH ((v t-1 , v t )),

[0233] where f INCOME (v i )=(v i-1 , v i ), i∈{1, 2, …, t-1} Formula (5)

[0234] It should be noted that the patterning process also needs to be executed in the training phase. Unlike the application phase, the patterning is performed based on the netlist corresponding to the sample chip in the training phase. In some embodiments, when encoding, it is necessary to encode the absolute position into a relative position with the help of the directed edges in the unit flow graph. For example, see Fig.12 As shown, in a specific embodiment, in the training stage, the input includes graph structure information and input features, the graph structure information includes a netlist graph and a unit flow graph, and the netlist graph can be N hierarchical netlist graphs (second subgraphs) and 1 second global graph. The input features are the features of each node, and for the netlist graph, they include the initial features of the net line and the initial features of the unit; for the unit flow graph, they only include the initial features of the unit.

[0235] Next, we will explain part 2 of the application phase: the inductive layout generation phase.

[0236] The inductive layout generation stage can be further divided into three sub-stages: graph neural network feature generation (output feature), relative position encoding, and relative position decoding.

[0237] See also Fig.13 , Fig.13 The hierarchical architecture of the graph neural network and the data processing flow at each level are shown.

[0238] In the composition stage, multiple hierarchical netlist graphs (second subgraphs) and unit flow graphs corresponding to each hierarchical netlist graph are obtained based on the netlist. In this embodiment, the input of the graph neural network includes input features and graph structure information, wherein the input features include unit initial features, network cable initial features and pin initial features, and the graph structure information includes graph structure information of N second subgraphs, 1 second global graph and N unit flow graphs.

[0239] Among them, the graph structure information can be input into the graph neural network in the form of an adjacency matrix, and the initial features of the unit, the initial features of the network cable, and the initial features of the pin can be input into the graph neural network in the form of a feature vector or a feature matrix. For example, the netlist contains information such as the size and position (initial position) of each unit. By taking the values ​​of this information as elements in the vector, the initial feature vector of the unit can be obtained; the netlist contains information such as the position, size, quantity, and spacing of the pins. By taking the values ​​of this information as elements in the vector, the initial feature vector of the pins can be obtained. Similarly, based on the network cable related information contained in the netlist, the initial feature vector of the network cable can be obtained.

[0240] In the adjacency matrix corresponding to the second subgraph, the row elements and column elements can represent cells, pins, or pins and cables respectively. If a cell or cable is connected to a pin, the element value of the corresponding row-column intersection is 1, otherwise it is 0. In the corresponding adjacency matrix in the cell flow graph, the row and column elements both represent cell nodes. If cells are connected, the element value of the corresponding row-column intersection is 1, otherwise it is 0.

[0241] Specifically, in this embodiment, a graph convolutional network based on a unit flow graph and a hierarchical netlist graph is designed, that is, the graph neural network is a graph convolutional neural network.

[0242] Exemplarily, in this embodiment, the graph convolutional neural network may include a multilayer perceptron (MLP), a convolutional layer and an attention mechanism layer (Attention layer); wherein the MLP includes at least one fully connected layer, the convolutional layer includes at least one convolutional layer; the attention layer includes at least one attention mechanism layer and at least one hidden layer.

[0243] See also Fig.13 As shown in x+6, in the convolution layer, three convolution functions are used and To transmit the message M, and perform feature fusion and update in the hidden layer, finally obtaining the output features of each unit and the output features of the network. The convolution function is Fig.14 The message passing functions shown in .

[0244] like Fig.13 As shown, for example, after performing the following calculations on the MLP fully connected layer, we can obtain

[0245]

[0246] in, denote the initial feature vectors of the unit v and the network line u respectively; MLP denotes the operation performed by the fully connected layer. Optionally, in this embodiment, the initial features of the pins may not participate in the fully connected operation. The H output by the MLP P That is, the initial eigenvector of the pin.

[0247] In the convolutional layers, message passing is performed from unit to unit, from unit to wire, and from wire to unit.

[0248] Specifically, based on the graph structure information of the unit flow graph, the message passing from unit to unit (V→V) is performed. In the application scenario of the present application, the message is the feature, and the transmission of the message is the transmission of the feature. In the unit flow graph, only one type of node is included: the unit node. In this embodiment, as shown in the figure, the message passing of the first-order neighborhood can be performed, that is, the features of the first-order neighborhood nodes of each unit node are transferred to the unit node. The specific transmission can be the execution of the corresponding convolution function, mapping the features of multiple first-order neighborhood nodes to the features of the unit node. Here, the process of mapping the features of multiple nodes to one node can be understood as the process of feature aggregation.

[0249] In other embodiments, message passing of multiple order neighborhoods may be performed, for example, message passing of second order neighborhoods may be performed: for each cell node, first determine its first order neighborhood nodes and second order neighborhood nodes, first pass the features of the second order neighborhood nodes to the first order neighborhood nodes, and then pass the features of the first order neighborhood nodes to the cell node, that is, the number of convolutional layers is 2, and 2 layers of message passing are performed. Wherein, cell represents a cell node, and edge represents a connecting edge (network cable).

[0250] Based on the graph structure information of the hierarchical netlist, message passing from net to cell (U→V) and from cell to net (V→U) is performed. Cell represents a cell node, net represents a net node, and edge represents a connection edge (pin).

[0251] The computational expressions involved in the message passing process performed through the convolutional layer are as follows:

[0252]

[0253] in, They represent the unit set and the network cable set respectively; It is the adjacency matrix corresponding to the hierarchical netlist graph, which represents the connection between cells and net lines. Represents the adjacency matrix corresponding to the unit flow graph, indicating the connection between units The feature representation of the lth hidden layer of the unit and the network line; l is the number of convolutional layers of the model; Indicates that the lth layer passes through the edge The message obtained after message passing.

[0254] For example, for Consider a single network cable u and fuse its adjacent unit set and the pin information that connects them, and finally The form can be shown as follows:

[0255]

[0256] in, is the eigenvector of cell v, is the eigenvector of the pin connecting v and u, Represents the connection edge between the unit and the network line Represent the set of units and the set of network cables respectively. is a learnable parameter matrix, i.e., trainable parameters. ⊙ represents the Hadamard product operation. The unit features containing the pin information are already in collect.

[0257] For example, The form is as follows:

[0258]

[0259] in is the eigenvector of the network cable u, is the feature vector of the pins connecting v and u, where v and u represent the unit and the network line respectively. Represents the connection edge between the unit and the network line Represent the set of units and the set of network cables respectively. is a learnable parameter matrix, i.e., a trainable parameter; ⊙ represents the Hadamard product operation, and η and shift are hyperparameters.

[0260] In the unit flow diagram Only the feature vectors of cells are used to perceive the topological information in the cell flow graph. As shown below:

[0261]

[0262] in, is the eigenvector of cell v, Represents the connection edge between units represents the set of all units, v represents the unit, is a learnable parameter matrix, i.e., trainable parameters.

[0263] In this embodiment, an attention mechanism layer is set after the convolution layer, and the output of the convolution layer is fused and updated based on the attention mechanism. In other embodiments, the attention mechanism may not be set after the convolution layer, but at least one hidden layer is set to achieve message fusion and update. The attention mechanism is not a necessary component of the graph neural network. After the convolution layer, there can be any neural network layer that can perform the following operations:

[0264]

[0265] f update is an update function. Exemplarily, in this embodiment, the update function is:

[0266] f update (H, M) = H + Tanh (M) Formula (12)

[0267] Tanh represents the hyperbolic tangent function, and its expression is

[0268] In other embodiments, other update functions may be selected and are not limited to the hyperbolic tangent function. For example, it is not excluded that in other embodiments, hyperbolic sine, hyperbolic cosine, hyperbolic cotangent, hyperbolic secant, hyperbolic cosecant, etc. may be used as update functions.

[0269] In this way, after the above-mentioned graph neural network generates feature sub-stages, output features can be obtained. In this embodiment, the output features include feature vectors corresponding to unit nodes and feature vectors corresponding to network nodes. In other embodiments, only unit features can be output, that is, the output features only include feature vectors corresponding to unit nodes, but not feature vectors corresponding to network nodes.

[0270] Next, relative position encoding is performed based on the output features. Exemplarily, the specific process of relative position encoding is as follows:

[0271] After obtaining the feature representations of the unit and the mesh, they are converted into the relative distance ρ and the deflection angle Δθ between the units through relative position coding. Optionally, in this embodiment, relative position coding is the process of mapping the output features into relative position information through a coding function.

[0272] See also Fig.15 As shown, in this embodiment, the relative position encoding process needs to refer to the unit flow graph, specifically, the unit flow graph edge and unit path. Optionally, the first independent variable can be obtained based on the unit flow graph edge (directed edge) and its related node features and network line features; the second independent variable can be obtained based on the unit path and its related node features and network line features.

[0273] For example, the relative position information of the jth unit relative to the ith unit is encoded as follows:

[0274] First, combine the unit flow graph edges to get the first independent variable; combine the unit paths to get the second independent variable:

[0275]

[0276] in, Represent the output features of the i, j, k-th unit and the t, s-th network line respectively; Represents the connection operation between vectors; Represents the unit set and the network cable set respectively. is the first independent variable, representing the unit flow graph The edge (v i , v j )The characteristic representation of its relative distance ρ; is the second independent variable, which is represented in the unit flow diagram The edge (v i , v j ) The characteristic representation of its deflection angle Δθ;

[0277] v k Representation unit v i The predecessor node in the unit flow graph, that is, the kth unit is connected to the i-th unit through a directed edge; f NET Indicates the network cable between two units, for example u s =f NET ((v k , v i )), indicating that the kth unit and the ith unit are connected via the sth network cable; u t =f NET ((v i , v j )), indicating that the i-th unit and the j-th unit are connected through the t-th network cable.

[0278] Represents the feature vector (output feature) corresponding to the i-th unit, Represents the feature vector (output feature) corresponding to the tth network line, Represents the feature vector (output feature) corresponding to the jth unit. In the unit flow graph, there is a directed edge (unit flow graph edge) from the i-th unit to the j-th unit.

[0279] After the output features are obtained through the graph neural network, the corresponding first independent variables are obtained in sequence by traversing the unit flow graph edges. For example, for the unit flow graph edge pointing from the i-th unit to the j-th unit, the first independent variable is obtained based on the output features of the i-th unit, the output features of the j-th unit, and the output features of the t-th network line.

[0280] It can be seen from the above calculation formula (8) that in this embodiment, the output feature of the ith unit, the output feature of the jth unit, and the output feature of the tth network line can be subjected to a vector connection operation, and the connected vector is the first independent variable. In other embodiments, the output feature of the ith unit, the output feature of the jth unit, and the output feature of the tth network line can be subjected to other operations to obtain the first independent variable, for example, weighted summation, connection after normalization, etc., and is not limited to performing vector connection.

[0281] The second argument is obtained based on the cell path. Fig.15 , the unit path starts at the kth unit, passes through the sth network line, the ith unit, the tth network line in turn to reach the jth unit, and obtains the second independent variable according to the eigenvector corresponding to the kth unit, the eigenvector corresponding to the sth network line, the eigenvector corresponding to the ith unit, and the eigenvector corresponding to the jth unit. For example, the eigenvectors corresponding to the nodes and the network lines on the path can be connected. In other embodiments, the eigenvectors corresponding to the nodes and the network lines on the path can be weighted summed or normalized before being connected, etc., and are not limited to performing vector connection operations.

[0282] After obtaining the first independent variable (polar diameter feature) and the second independent variable (deflection angle feature), the first independent variable and the second independent variable are mapped to the polar diameter and the deflection angle respectively through the encoding function:

[0283]

[0284]

[0285] ρ i，j , Δθ i，j Represents the polar diameter (relative distance between units) and the deflection angle, is the first encoding function, which is used to convert the first independent variable Mapped to the polar diameter in relative position information; is the second encoding function, which is used to convert the second independent variable Mapped to the deflection angle in relative position information.

[0286] a ρ , a θ , b ρ , b θ is the learnable parameter vector, b ρ , b θ is a learnable parameter scalar. α, β are hyperparameters.

[0287] After the above steps, the mapping from output features to relative position information can be achieved.

[0288] After the relative position information is obtained, the third sub-stage, i.e., relative position decoding, is entered. It should be noted that in other embodiments, after the relative position information is obtained, the decoding operation may not be performed, but the decoding operation may be performed by other service providers, or a decoding solution may be provided and the user may decode the information by himself. The decoding operation is not a necessary step of the method.

[0289] Specifically, in this embodiment, after the relative position code is obtained, it is decoded to obtain the absolute position of the unit.

[0290] For a cell path (v0, v1, ..., v t-1 , v t ) P , with the unit flow graph edge (v t-1 , v t ) Calculate the unit position vector

[0291]

[0292] Where ρ0 is the polar radius of the first node relative to the starting node, ρ0 is the modulus of p0, and p0 is the vector of the first node relative to the starting node, and its relative coordinates are (x0, y0). Then θ0 is the angle between p0 and the positive direction of the x-axis, θ t-1，t is the vector between units t-1 and t The angle with the horizontal direction, For two units v t-1 , v t The vector formed by connecting the lines.

[0293] During decoding, N unit flow graphs may be decoded one by one, taking the unit flow graph as a unit.

[0294] For a unit flow graph, a layer-by-layer decoding method can be used: first determine the starting node and the absolute position information of the starting node, and then determine the absolute position information of the first-order neighboring nodes according to the relative position information of the first-order neighboring nodes corresponding to the starting node and the absolute position information of the starting node. Next, according to the relative position information of the second-order neighboring nodes relative to the first-order neighboring nodes and the absolute position information of the first-order neighboring nodes, the absolute position information of the second-order neighborhood can be obtained. Similarly, according to the absolute position information of the m-th order neighboring nodes and the relative position information of the m+1-th order neighboring nodes, the absolute position information of the m+1-th order neighboring nodes can be determined; m≥1 and is an integer.

[0295] For example, see Fig.16As shown, for example, in a unit flow graph, node 1 is the starting node, and the node connected to the starting node through a directed edge (unit flow graph edge) is the first-order neighbor node of the starting node. Then, in the graph, nodes 2 and 3 are the first-order neighbor nodes of the starting node. According to the absolute position of node 1, the relative position information of node 2 relative to node 1, and the relative position information of node 3 relative to node 1, the absolute position information of node 2 and node 3 can be obtained. According to the signal flow direction, the downstream node connected to the first-order neighbor node through a directed edge is the second-order neighbor node of the starting node. In the graph, node 4 is the second-order neighbor node of node 1. Then, on the premise of obtaining the absolute position information of the first-order neighbor nodes 2 and 3, according to the relative position information of node 4 relative to node 3, the absolute position information of the second-order neighbor node 4 can be obtained. For more complex unit flow graphs, this method can be used for layer-by-layer decoding. In this way, when decoding the deflection angle based on the unit path, when the last node on the path needs to be decoded, the predecessor nodes (upstream nodes) on the path have been decoded.

[0296] It should be noted that, since each unit node may be a terminal node (end node) of multiple unit paths, during decoding, the same unit node may obtain different absolute positions according to different unit paths.

[0297] Optionally, in this embodiment, the average value of multiple absolute positions obtained based on multiple paths can be taken to obtain v t Final position p t .

[0298]

[0299] Among them, p t；(t-1，t) To use the path (v0, v1, ..., v t ) P The decoded unit v t The absolute position of For two units v t-1 , v t The vector formed by the connecting line, p t For unit v t The final position, mean means the average value, Represents the connecting edges between cells Represents a collection of cells.

[0300] In other embodiments, during decoding, one path may be selected from multiple paths for decoding, such as the shortest path. The longer the path, the greater the error may be, so selecting the shortest path can reduce the error to a certain extent. Alternatively, one absolute position information is selected from the multiple absolute position information obtained as the decoding result. In addition, in other embodiments, multiple absolute position information obtained based on multiple paths may be weighted summed, and the implementation method is not unique.

[0301] It should be noted that, during the encoding stage, it is also possible to encounter a situation where the same node corresponds to multiple paths. During encoding, one path can be selected from the multiple paths for encoding, for example, any one or the shortest path can be selected for encoding. In other embodiments, during encoding, the encoding results of multiple paths can also be averaged, or weighted summed, the sum of each weight is 1, etc., which are not listed one by one in this application specification.

[0302] In this way, after the inductive layout generation stage, the absolute position information of each unit is obtained. In some embodiments, the absolute position information obtained in the inductive layout generation stage can be directly used as the chip layout result. In this embodiment, after the absolute position information is obtained by decoding, the chip layout is further optimized by fine-tuning, such as Fig.17 As shown, after the relative position is encoded and decoded to obtain the layout, the layout position is further fine-tuned to obtain an optimized layout as a layout result.

[0303] In the related art, each chip is trained separately, which is not generalizable and may not achieve good results in different chips, which also leads to bottlenecks in speed optimization. The embodiment of the present application adopts an inductive layout generation algorithm, which mainly includes variant encoding methods such as SE (2) to ensure that the layout learned by the model can be generalized between different chip netlists. Self-supervised training is used to enable the graph neural network to learn layout knowledge from the laid out chip netlist, and the positions of each unit are obtained based on the unit flow graph and the relative position decoding between units, which improves the generalization of the layout method for different chips and does not require separate training for each chip.

[0304] In addition, a variety of layout samples are used to train the model, and the early chip layout data preparation is difficult. In the solution provided in the embodiment of the present application, the inductive layout generation algorithm is based on the existing information of the chip netlist (the connection relationship between pins and wires, the mapping relationship between pins and units, pin positions, signal directions, unit sizes, and unit types), constructs unit, wire, and pin features, and inputs them into the graph neural network with the hierarchical netlist diagram and the unit flow diagram, and encodes based on the output to obtain the relative position between units, and finally decodes the relative position to obtain the absolute position. This method uses relative position encoding and graph neural networks to significantly improve the efficiency of cross-chip training and reasoning. In addition, this method reduces the difficulty of preparing chip layout data by learning layout knowledge on the laid out netlist and reasoning on the unlaid chip netlist.

[0305] The netlist is adaptively fine-tuned, using the positions of each unit obtained by inductive layout as the initial solution. In the adaptive fine-tuning stage, the objective function needs to be determined first, and then based on the netlist information, hyperparameters such as learning rate, number of iterations, and loss function weights are set, the objective function is calculated, the unit position is updated according to the gradient, and the objective function is recalculated. The above process is repeated continuously to obtain the final unit position.

[0306] When using graph neural networks to generate chip layout, sometimes the graph neural network model cannot fully meet the constraints of chip layout, such as no overlap between components and the placement of components cannot exceed the set layout boundaries. Further performing netlist adaptive fine-tuning based on inductive layout can solve this problem.

[0307] In addition, since the output of the graph neural network is a geometric layout based only on the topological structure of the netlist, even similar topological structures on different netlists may have large geometric layout differences due to reasons such as chip layout. This difference cannot be perceived by the graph neural network only through the topological structure, so further fine-tuning is required to improve the quality of the layout and its usability in the subsequent design process.

[0308] Exemplarily, the fine-tuning phase process is as follows:

[0309] Three objectives are set for optimization: wire length, density, and anchor point. The wire length can be half-perimeter wire length (HPWL).

[0310] The line length takes the weighted average line length as the line length function, and the formula is shown in the following formula (11), where x v ,y v Represents the horizontal and vertical coordinates of unit v, and γ is a hyperparameter.

[0311]

[0312] The density function is the same as that in the self-supervised training stage. The unit is regarded as a charged body to solve the electric potential energy and the electric field strength in the x and y directions.

[0313] The calculation formula is shown in formula 12 and formula 13, where N(v) is the cell density function, v represents the cell, x and y are the spatial coordinates, ρ(x, y) and ψ(x, y) represent the spatial single point density function and potential distribution function, is a vector orthogonal to the boundary, is the spatial electric field intensity distribution function, Indicates the chip layout boundary.

[0314]

[0315]

[0316] The above electrostatic field can be solved using a method similar to the fast Fourier transform, with a time complexity of O(Nlog N×M log M). The time complexity of the final algorithm is

[0317] The role of the anchor function is to prevent the final fine-tuned layout from being too different from the output layout of the graph neural network during the fine-tuning process, thereby destroying the output layout of the graph neural network and slowing down the convergence speed. Therefore, the anchor function is used to limit the unit from drifting too much during the optimization process.

[0318] The anchor point function is shown in formula (14):

[0319]

[0320] in is the cell position before fine-tuning, (X, Y) is the chip layout area, x v ,y v represents the horizontal and vertical coordinates of unit v. The negative slope of LeakyReLU is fixed to 0.01. In the fine-tuning stage, the final chip layout is directly optimized. The loss function of the final fine-tuning stage is shown in the following formula (15), where λ D ,λ A is the weight coefficient.

[0321]

[0322] The parameter γ in the weighted average line length is adjusted once every multiple rounds during the training process. For example, it is adjusted once every 5 rounds. The adjustment formula is shown in the following formula (16):

[0323]

[0324] where γinit It is necessary to set an initial value. For example, in this embodiment, the initial value γ init It is set to 40960. In other embodiments, it can be set to other values, which are not listed one by one.

[0325] The congestion value overflow of the layout is calculated as shown in the following formula (17).

[0326] overflow=ΣN(v)-target density *Area(v) Formula (24)

[0327] Where N(v) is the cell density function, target density is a hyperparameter, and Area(v) is the area of ​​cell v.

[0328] When the congestion value of the layout is large, it means that the cells are arranged too closely, and the value of γ is increased in turn, which is actually equivalent to decreasing The weight is equivalent to spreading out the layout units.

[0329] λ D It can be adjusted in each training round, and its initial value is calculated as follows:

[0330]

[0331]

[0332]

[0333] After each round D The update formula is as follows:

[0334]

[0335]

[0336] ΔHPWL=HPWL new -HPWL old Formula (26)

[0337] Among them, the initial value density init is an adjustable hyperparameter, To calculate the weighted average function and density function of the layout and perform back propagation, the gradient at each unit position of the layout, epochs is the current training round, HPWL new is the HPWL of the current round, HPWL old is the HPWL of the previous round, and UPCOF is an adjustable hyperparameter.

[0338] It should be noted that the optimization in the fine-tuning phase is directly applied to the movable unit position P M , rather than the trainable parameters in the graph neural network. In the fine-tuning phase, the time complexity is where t f is the number of rounds of fine-tuning that need to be performed on each netlist.

[0339] Adaptive fine-tuning can further optimize the layout position based on the chip layout result obtained by inductive generation, but some embodiments may not perform fine-tuning.

[0340] Some models in the related art have poor training and reasoning time on large-scale netlists and low efficiency, partly because the traditional method of directly optimizing the unit position has the problem of cold start and requires a long time to train. In the embodiment of the present application, the netlist adaptive fine-tuning realizes the adaptive fine-tuning based on the unit positions obtained by the inductive layout as the initial solution, avoiding the problem of cold start, greatly shortening the time required to optimize the unit position, and improving efficiency; and the netlist adaptive fine-tuning realizes the further optimization of the results generated by the inductive layout.

[0341] After testing, the solution proposed in the embodiment of the present application can achieve the following technical effects:

[0342] See the following tables, where “Our” is the solution proposed in this application, D***Place is a solution in the related art, and **Place is another solution in the related art.

[0343] Tables 1-4 below show the results of the model proposed in the embodiment of the present application on the ISPD2015[1] and ISPD2019[2] datasets, and the D***Place[3] method and the **PlAce[4] method. The model proposed in the embodiment of the present application is trained on the four netlists mgc_fft_1, mgc_fft_2, mgc_fft_a and mgc_fft_b of ISPD2015, while the other netlist designs are directly inferred to obtain the layout results.

[0344] Table 1 is a comparison of the HPWL results of the methods D***Place and **Place in the related art and the method proposed in the embodiment of the present application based on the netlists of the ISPD2015 data set (the smaller the value, the better):

[0345] Table 1

[0346]

[0347] Table 2 is a comparison of the running time of the methods in the related art and the method proposed in the embodiment of the present application based on the netlists of the ISPD2015 data set (the smaller the value, the better):

[0348] Table 2

[0349]

[0350] Table 3 is a comparison of the HPWL results of the methods in the related art and the methods proposed in the embodiments of the present application on each netlist based on the ISPD2019 data set (the smaller the value, the better):

[0351] Table 3

[0352]

[0353]

[0354] Table 4 is a comparison of the running time of the method in the related art and the method proposed in the embodiment of the present application based on each netlist of the ISPD2019 data set (the smaller the value, the better):

[0355] Table 4

[0356]

[0357] From Tables 1 and 2, it can be found that on the training set netlist (mgc_fft_1, mgc_fft_2, mgc_fft_a and mgc_fft_b), the model proposed in this application can achieve 13% and 46% improvement compared with D***Place and **PlAce on HPWL. At the same time, in terms of running speed, the model proposed in this application has achieved an average improvement of 595% and 1929% compared with D***Place and **PlAce. This shows that the model proposed in this application can learn layout knowledge from the training set and quickly generate high-quality chip layout.

[0358] In the test set of other chip netlists, the model proposed in this application achieved 5% and 79% improvement in HPWL compared with D***Place and **PlAce methods. At the same time, in terms of running speed, the model proposed in this application can achieve 53% and 4974% improvement compared with D***Place and **PlAce. This shows that the layout knowledge learned by this application is generalizable.

[0359] It can be seen from Tables 3 and 4 that, compared with D***Place and **PlAce, the model proposed in this application has achieved an improvement of 1% and 23% in HPWL, and an improvement of 138% and 857% in running speed, respectively.

[0360] From the perspective of the chip design process, it is not enough to just achieve excellent HPWL. In order to further compare the layout quality, the OpenROAD flow wiring tool is used to perform global wiring according to the models in the relevant technology and the layout schemes generated by the methods proposed in the embodiments of the present application. The wire length and congestion are evaluated based on the results of global wiring. The wire length determines the cost of etching in the subsequent chip manufacturing process, and the part of the chip that is too congested may be at risk of burning, making the design unusable. Moreover, the wire length and congestion calculated by the wiring scheme obtained by the global layout are more accurate than the HPWL and density of the global layout, and the results of the global wiring calculation are more accurate in estimating the results in the final scheme.

[0361] Table 5 shows the results after routing of some netlists. Table 5 is a comparison of rWL and Overflow of D***Place and the method proposed in the embodiment of the present application based on some netlists of ISPD2015 (the smaller the value, the better):

[0362] Table 5

[0363]

[0364] It can be found from Table 5 that even after global routing, the model method proposed in the embodiment of the present application achieves a 7% improvement in line length compared to D***Place. At the same time, it can be found from Table 5 that compared to D***Place, the method proposed in the present application shows a significant and excellent routing optimization effect.

[0365] Refer to Figures 18(a)-(d), 19(a)-(c), and 20(a)-(c), which show the visualization of congestion after routing on netlists of different architectures. The darker the grayscale in the figure, the more severe the congestion. Among them, Figures 18(a)-(c) respectively show the congestion distribution diagrams of the model, D***Place and **Place proposed in the embodiment of the present application on the mgc_fft_2 netlist. Figure 18(d) is an example diagram of the degree of congestion. Figures 19(a)-(c) respectively show the congestion distribution diagrams of the model, D***Place and **Place proposed in the embodiment of the present application on the mgc_matrix_mult_2 netlist; Figures 20(a)-(c) respectively show the congestion distribution diagrams of each method on the mgc_superblue19 netlist.

[0366] It can be seen from Figures 18-20 that, compared with D***Place and **Place on the netlists of three different architectures, the method proposed in the embodiment of the present application can obtain a chip layout with a lower degree of congestion. This shows that the model proposed in the embodiment of the present application can be generalized on different heterogeneous netlists and achieve better layout quality.

[0367] In summary, in the related art, each chip is trained separately, which is not generalizable, which makes the chip layout have bottlenecks in speed optimization. This application provides a complete and portable global layout generation framework (inductive layout generation and netlist adaptive fine-tuning) by learning layout knowledge from the laid out netlist and performing reasoning on the unlaid chip netlist, generating a usable global layout solution in a relatively short time, and providing a good estimate for the subsequent calculation of congestion, line length and timing. Through this framework, a global layout solution for a usable high-quality chip netlist can be quickly generated, which greatly improves the layout efficiency, and realizes the portability of the layout method through inductive layout generation based on relative position encoding and decoding.

[0368] Optionally, netlist adaptive fine-tuning achieves further optimization of the results of inductive layout generation. Related methods directly optimize cell positions and have the problem of cold start, which requires a long time to train. In this application, by using the results of inductive layout generation as the initial solution, the problem of cold start is avoided and the time required to optimize cell positions is greatly shortened.

[0369] In general, the portable chip layout scheme proposed in this application can provide higher quality layout results in a short time compared to traditional technologies. It can achieve portable layout through inductive layout generation, and optimize the inductive layout generation results in a short time with the help of netlist adaptive fine-tuning, and further improve the layout quality. While improving generalization, it also ensures the timeliness of chip layout to a certain extent.

[0370] An embodiment of the present application also provides an electronic device, which includes: one or more processors; a memory; at least one application; and one or more computer programs, wherein the one or more computer programs are stored in the memory, and the one or more computer programs include instructions, which, when executed by the electronic device, enable the electronic device to execute a method as described in any of the above embodiments.

[0371] Specifically, the electronic device may be a server or server cluster that provides chip layout services. Referring to FIG18 , the hardware structure of the electronic device may include: a processor, a memory, and a chipset.

[0372] Processor, the core that handles all computing tasks and requests, including at least the CPU.

[0373] Storage: includes memory and hard disk. The larger the capacity, the more requests and files can be processed simultaneously.

[0374] Chipset: includes northbridge chip and southbridge chip, which connect various I / O devices. Northbridge chip connects CPU, memory and PCI bus, while southbridge chip connects hard disk, network and other I / O devices.

[0375] I / O bus: connects various I / O devices, such as network card, graphics card, sound card, USB, etc. The larger the I / O bus bandwidth of the server, the more requests it can handle.

[0376] I / O devices: including network card, graphics card, sound card, USB, etc. The network card is the main device connecting the server to the external network, and its speed and performance directly affect the response speed and transmission speed of the server.

[0377] Power supply: Provides stable power to the server to ensure normal operation of the server.

[0378] Chassis (not shown in Figure 18): The outer shell of the server hardware that protects the hardware from dust, vibration and temperature.

[0379] Exemplarily, the processor may include one or more processing units, for example, the processor includes a neural-network processing unit (NPU), and may also include an application processor (AP), a modem processor, a graphics processor (GPU), an image signal processor (ISP), a controller, a digital signal processor (DSP), a baseband processor, etc. Among them, different processing units may be independent devices or integrated into one or more processors. The controller may generate an operation control signal according to the instruction opcode and the timing signal to complete the control of fetching and executing instructions.

[0380] The memory can be used to store computer executable program codes, which include instructions. The internal memory may include a program storage area and a data storage area. Among them, the program storage area may store an operating system, at least one application required for a function, etc. The data storage area may store data (such as input data, output data) created during the use of the electronic device, etc. In addition, the internal memory may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, a universal flash storage (UFS), etc. The processor executes various functional applications and data processing of the electronic device by running instructions stored in the internal memory and / or instructions stored in a memory provided in the processor.

[0381] Alternatively, the electronic device may also be a terminal device with certain computing capabilities, such as a mobile phone, a personal computer (PC) (such as a laptop), a tablet computer (Tablet Personal Computer, Tablet PC), a wearable electronic device, etc. The terminal device may include a processor, an external memory interface, an internal memory, a universal serial bus (USB) interface, a charging management module, a power management module, a battery, etc.

[0382] It is to be understood that the structure illustrated in the embodiment of the present invention is only an example and does not constitute a limitation on the electronic device. The electronic device in the embodiment of the present application may include more or fewer components than shown in the figure, or combine certain components, or split certain components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0383] An embodiment of the present application further provides a storage medium, including computer instructions, which, when executed on an electronic device, enables the electronic device to execute a method as described in any of the above embodiments.

[0384] An embodiment of the present application also provides a chip system, including a communication interface for inputting and / or outputting data; and a processor for executing a computer executable program so that a device equipped with the chip system executes a method as described in any of the above embodiments.

[0385] It should be noted that the solution provided in the embodiments of the present application includes any one or more of chip layout and training methods, electronic devices, storage media and chip systems, or may also be other forms of software products, hardware products or virtual service products obtained based on the technical concept of the method described in the specification of this application.

[0386] In the description of the device in the embodiment of the present application, various modules for implementing the method flow functions are constructed in the device. The division of modules is merely a division of logical functions. When implementing the embodiment of the present application, the functions of each module can be implemented in the same or multiple software and / or hardware.

[0387] Specifically, each functional module can be fully or partially integrated into one physical entity during actual implementation, or can be physically separated. And these modules can all be implemented in the form of software calling through processing elements; or all can be implemented in the form of hardware; or some modules can be implemented in the form of software calling through processing elements, and some modules can be implemented in the form of hardware. For example, the detection module can be a separately established processing element, or it can be integrated in a chip of an electronic device. The implementation of other modules is similar. In addition, these modules can be fully or partially integrated together, or they can be implemented independently. In the implementation process, each step of the above method or each of the above modules can be completed by an integrated logic circuit of hardware in the processor element or instructions in the form of software.

[0388] For example, the above modules may be one or more integrated circuits configured to implement the above methods, such as one or more application specific integrated circuits (ASIC), or one or more digital signal processors (DSP), or one or more field programmable gate arrays (FPGA), etc. For another example, these modules may be integrated together and implemented in the form of a system-on-a-chip (SOC).

[0389] Specifically, in one embodiment of the present application, the above-mentioned one or more computer programs are stored in the above-mentioned memory, and the above-mentioned one or more computer programs include instructions. When the above-mentioned instructions are executed by the above-mentioned device, the above-mentioned device executes the method steps described in the embodiment of the present application.

[0390] Specifically, in one embodiment of the present application, the processor of the electronic device may be a SOC device on a chip, which may include a central processing unit (CPU) and may further include other types of processors, such as a graphics processing unit (GPU). Specifically, in one embodiment of the present application, the processor of the electronic device may be a PWM control chip.

[0391] Specifically, in an embodiment of the present application, the processor involved may include, for example, a CPU, a DSP, a microcontroller or a digital signal processor, and may also include a GPU, an embedded neural network processor (Neural-network Process Units, NPU) and an image signal processor (Image Signal Processing, ISP). The processor may also include necessary hardware accelerators or logic processing hardware circuits, such as ASICs, or one or more integrated circuits for controlling the execution of the program of the technical solution of the present application. In addition, the processor may have the function of operating one or more software programs, and the software programs may be stored in a storage medium.

[0392] Specifically, in one embodiment of the present application, the memory of the electronic device may be a read-only memory (ROM), other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital versatile discs, Blu-ray discs, etc.), a magnetic disk storage medium or other magnetic storage devices, or may be any computer-readable medium that can be used to carry or store desired program codes in the form of instructions or data structures and can be accessed by a computer.

[0393] Specifically, in an embodiment of the present application, the processor and the memory can be combined into a processing device, more commonly, they are independent components, and the processor is used to execute the program code stored in the memory to implement the method described in the embodiment of the present application. In specific implementation, the memory can also be integrated into the processor, or independent of the processor.

[0394] Furthermore, the devices, apparatuses, and modules described in the embodiments of the present application may be implemented by computer chips or entities, or by products having certain functions.

[0395] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, devices, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code.

[0396] In the several embodiments provided in the present application, if any function is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application.

[0397] The embodiments described in this application are described with reference to the flowcharts and / or block diagrams of the methods, devices (apparatus), and computer program products according to the embodiments of the application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0398] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0399] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0400] It should also be noted that in the embodiments of the present application, "at least one" refers to one or more, and "more than one" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent the existence of A alone, the existence of A and B at the same time, and the existence of B alone. Among them, A and B can be singular or plural. The character " / " generally indicates that the previous and subsequent associated objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b and c can be represented by: a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, c can be single or multiple.

[0401] In the embodiments of the present application, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the presence of other identical elements in the process, method, commodity or device including the element.

[0402] The present application may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0403] Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0404] Those skilled in the art will appreciate that the various units and algorithm steps described in the embodiments of the present application can be implemented by a combination of electronic hardware, computer software, and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0405] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices, apparatuses and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0406] The above is only a specific implementation of the present application. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. The protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A chip layout training method, characterized in that: The method comprises: Determine first relative position information; the first relative position information is relative position information between different units in each unit that has been laid out in the sample chip; Determine a first input of a graph neural network to be trained; the first input is obtained based on a first netlist corresponding to the sample chip; Obtaining a first output through the graph neural network; Based on the first output, perform encoding to obtain second relative position information; Calculate a loss function value based on the first relative position information and the second relative position information; and optimize trainable parameters in the graph neural network based on the loss function value.

2. The method according to claim 1, characterized in that Determining first relative position information includes: Obtaining absolute position information of each laid out unit in the sample chip; The relative position information between different units is calculated based on the absolute position information.

3. The method according to claim 2, characterized in that The absolute position information includes coordinate information; Calculating relative position information between different units according to the absolute position information includes: According to the coordinate information corresponding to the j-th unit and the i-th unit respectively, the polar coordinate information of the j-th unit relative to the i-th unit is calculated; both i and j are integers greater than or equal to 1, and i≠j.

4. The method according to claim 1, characterized in that Based on the first output, encoding is performed to obtain second relative position information, including: Determine an independent variable based on the first output, and execute an encoding function on the independent variable to obtain second relative position information; the encoding function is used to map the independent variable to the second relative position information; After calculating the loss function value, the method further includes: According to the loss function value, the trainable parameters in the encoding function are optimized.

5. A chip layout method, characterized in that: The method comprises: Determine a second input of the graph neural network after training; the second input is obtained based on a second netlist corresponding to the chip to be laid out; Obtaining a second output through the graph neural network; Based on the second output, performing encoding to obtain third relative position information; Decoding is performed at least according to the third relative position information to obtain absolute position information of each unit in the chip to be laid out.

6. The method according to claim 5, characterized in that Determine the second input of the graph neural network after training, including: Based on the second netlist, at least a plurality of subgraphs are obtained; in the plurality of subgraphs, nodes represent units or netlines; Based on the second netlist, an input feature is obtained; the input feature includes a cell feature corresponding to each cell in the chip to be laid out; At least the graph structure information corresponding to the multiple sub-graphs and the input features are determined as the second input.

7. The method according to claim 6, characterized in that Based on the second netlist, at least a plurality of subgraphs are obtained, including: Based on the second netlist, a hypergraph is established; wherein, in the hypergraph, nodes represent units and hyperedges represent network lines; Divide the hypergraph into N blocks, and obtain N first subgraphs and 1 first global graph corresponding to the N blocks; wherein the first subgraph is used to represent the connection relationship between different units in a block through network connection; the first global graph is used to represent the connection relationship between different blocks in the N blocks through network connection; N≥2; Expand the N first subgraphs and the 1 first global graph respectively to obtain corresponding N second subgraphs and 1 second global graph; wherein in the second subgraphs and the second global graph, nodes represent units or network cables, and connecting edges represent pins; Determining at least the graph structure information corresponding to the plurality of sub-graphs and the input features as the second input includes: At least the graph structure information corresponding to the plurality of second subgraphs and the one second global graph and the input features are determined as the input.

8. The method according to claim 7, characterized in that After obtaining the corresponding N second sub-images, the method further includes: According to the signal direction information contained in the second netlist, N unit flow graphs corresponding to the N second subgraphs are established; wherein, in the unit flow graphs, nodes represent units, and the connecting edges between nodes are directed edges, which are used to represent network cables, and the directions of the directed edges are determined according to the signal directions; Determining at least the graph structure information corresponding to the plurality of sub-graphs and the input features as the second input includes: At least the graph structure information corresponding to the plurality of second subgraphs, the one second global graph, and the plurality of N unit flow graphs, and the input features are determined as the input.

9. The method according to claim 8, characterized in that According to the signal direction information included in the netlist, N unit flow graphs corresponding to the N second subgraphs are established, including: In a second subgraph, a unit is considered as the starting node; Searching for a unit connected to the starting node via a network cable as a first-order neighboring node corresponding to the starting node; Generate directed edges between the starting node and each first-order neighboring node according to the signal direction; Searching for a unit connected to the first-order neighboring node via a network cable as a second-order neighboring node corresponding to the starting node; Generate a directed edge between the first-order neighboring node and the second-order neighboring node according to the signal direction; Continue searching for the next-order neighboring nodes until all cells in the same second subgraph are visited, and obtain a cell flow graph.

10. The method according to any one of claims 6 to 9, characterized in that The input features also include network features corresponding to each network in the chip to be laid out; the second output includes output features corresponding to each unit, or the second output also includes output features corresponding to each network; The graph neural network is a graph convolutional neural network, and the graph convolutional neural network includes a convolutional layer; Through the graph neural network, a second output is obtained, including: In the convolution layer, feature transfer between nodes is performed by executing at least one of a first convolution function, a second convolution function, and a third convolution function; The first convolution function is used to transfer the network cable features corresponding to each network cable connected to the i-th unit to the node corresponding to the i-th unit to obtain the i-th first unit sub-feature; i≥1 and is an integer; The second convolution function is used to transfer the unit features of each unit connected to the t-th network line to the node corresponding to the t-th network line to obtain the network line features corresponding to the t-th network line; t≥1 and is an integer; The third convolution function is used to transfer the unit features of each unit connected to the i-th unit to the node corresponding to the i-th unit to obtain the i-th second unit sub-feature; Based on the i-th first unit sub-feature and the i-th second unit sub-feature, an output feature corresponding to the i-th unit is obtained; or, based on the network cable feature corresponding to the t-th network cable, an output feature corresponding to the t-th network cable is obtained.

11. The method according to any one of claims 8 to 10, characterized in that: Based on the second output, encoding is performed to obtain third relative position information, including: An independent variable is determined based on the second output, and an encoding function is executed on the independent variable to obtain third relative position information; wherein the encoding function is used to map the independent variable to the third relative position information.

12. The method according to claim 11, characterized in that The encoding function includes a first encoding function and a second encoding function; the third relative position information is polar coordinate information; Execute the encoding function to obtain the third relative position information, including: Based on the second output, determining a first independent variable, performing a first encoding function on the first independent variable to obtain a polar radius; Based on the second output, a second independent variable is determined, and a second encoding function is performed on the second independent variable to obtain a deflection angle; the deflection angle represents the relative value of the polar angles corresponding to different units.

13. The method according to claim 12, characterized in that The output includes unit features corresponding to each unit and network line features corresponding to each network line; Based on the second output, determining a first independent variable comprises: Based on the unit features corresponding to the i-th unit and the j-th unit in the second output, and the network line features corresponding to the t-th directed edge, a first independent variable is obtained; wherein the t-th directed edge is a directed edge connecting the i-th unit and the j-th unit in the unit flow graph; Based on the second output, determining a second independent variable includes: Searching for at least one path corresponding to the j-th unit in the unit flow graph, and selecting one of the paths as a first path; the path is a directed path formed by at least one directed edge starting from a start node in the unit flow graph and ending at a node corresponding to the j-th unit; Based on the unit features corresponding to each node passed by the first path in the second output and the network features corresponding to at least one directed edge, a second independent variable is obtained; wherein i, j and t are all integers greater than or equal to 1.

14. The method according to any one of claims 6 to 13, characterized in that: Performing decoding at least according to the third relative position information to obtain the absolute position information of each unit in the chip to be laid out includes: Determine a starting node in a subgraph and absolute position information of the starting node; Determine the absolute position information of the first-order neighboring node according to the third relative position information of the first-order neighboring node corresponding to the starting node and the absolute position information of the starting node; The absolute position information of the m+1 order neighbor node is determined according to the absolute position information of the m-order neighbor node and the third relative position information of the m+1 order neighbor node; m≥1 and is an integer.

15. The method according to claim 13, characterized in that Performing decoding at least according to the third relative position information to obtain the absolute position information of each unit in the chip to be laid out includes: For the j-th unit, searching the unit flow graph for at least one path with the j-th unit as an end node; Obtaining a feasible solution corresponding to a path according to the third relative position information corresponding to a starting node of the at least one path and the third relative position information of each node passed by the path, wherein the at least one path corresponds to at least one feasible solution; Based on the at least one feasible solution, the absolute position information of the j-th unit is obtained.

16. The method according to any one of claims 5 to 15, characterized in that After obtaining the absolute position information of each unit in the chip to be laid out, the method further includes: The absolute position information of each unit is used as an initial solution to calculate an objective function; the objective function uses at least one of line length, density, and anchor point as a constraint condition; the objective function includes at least one hyperparameter of a learning rate, a number of iterations, and a loss function weight; The gradient updates the absolute position information of each unit.

17. An electronic device, characterized in that: The electronic device comprises: One or more processors; a memory; at least one application; and one or more computer programs, wherein the one or more computer programs are stored in the memory, and the one or more computer programs include instructions that, when executed by the electronic device, cause the electronic device to perform a method as described in any one of claims 1-16.

18. A storage medium, characterized in that: The method comprises computer instructions, which, when executed on an electronic device, cause the electronic device to execute the method as claimed in any one of claims 1 to 16.

19. A chip system, characterized in that: include: A communication interface for inputting and / or outputting data; A processor, configured to execute a computer executable program so that a device equipped with the chip system executes a method as described in any one of claims 1 to 16.

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