Method and device for determining non-layout wiring area in integrated circuit layout, electronic equipment and storage medium
By dividing the non-layout wiring areas of the integrated circuit layout according to the placement direction of the design port, the problem of data length too long or generating too many data rows in the prior art is solved, and more efficient expression and calculation cost are achieved.
Patent Information
- Application Number
- CN202411591702.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-08
- Publication Date
- 2025-02-14
AI Technical Summary
When existing EDA tools describe non-layout wiring areas in integrated circuit layouts, they can easily lead to excessive data length or generate excessive data rows, increasing calculation costs.
By determining the reference position for regional division of the current layer according to the placement direction of each design port in the current layer of the integrated circuit layout, and dividing it into multiple sub-regions along the preset direction, the non-layout wiring area is determined.
This method reduces the amount of data expressed in the position of the non-layout routing area, avoids the problem of excessive data length or generation of too many data rows, and improves the availability of library exchange files.
Smart Images
Figure CN119443033A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of integrated circuit design, and in particular to a method, device, electronic device and storage medium for determining a non-layout and wiring area in an integrated circuit layout. Background Art
[0002] Electronic Design Automation (EDA) software is widely used in the functional design, synthesis, verification, and simulation of chips. Designers can design using hardware description languages on the software platform of EDA tools, and then use computers to complete logic compilation, optimization, wiring, and simulation to complete the functional design, synthesis, verification, and physical design of ultra-large-scale integrated circuit chips. LEF (Library Exchange File) is a file that abstractly describes the layout design of integrated circuits. It can be used to exchange design information between EDA tools. For example, LEF files record a variety of layout information, including cell size, port (PIN) location, layer (LAYER) information, etc. This information can be used for P&R (Place and route).
[0003] The OBS (Obstruction, a non-layout and routing area in a specified cell) in LEF specifies some areas in which routing tools cannot route wires. Current EDA tools provide two ways to express OBS: COVER and DETAIL. When there are many ports inside a cell, using COVER to express OBS will result in polygons (POLYGON) with very long data lengths, which may generate data rows that exceed the length limit and make the LEF file unusable; when the cell size is relatively large, using DETAIL to express OBS will generate a lot of rectangles (RECT), which will generate too many data rows and will add additional computing costs in the P&R stage. Summary of the invention
[0004] In view of this, the present application provides a method, device, electronic device and storage medium for determining a non-layout and routing area in an integrated circuit layout, so as to generate a library exchange file that is easy to read and use.
[0005] In a first aspect, an embodiment of the present invention provides a method for determining a non-layout and routing area in an integrated circuit layout, comprising: determining a reference position for dividing the current layer into regions according to the placement directions of the design ports in the current layer of the integrated circuit layout, wherein the placement directions of the design ports are along the same preset direction; at the reference position, along the preset direction, dividing the current layer into multiple sub-regions; for a sub-region, if the sub-region contains a design port, determining the region outside the design port contained in the sub-region as a non-layout and routing region; if the sub-region does not contain a design port, determining the sub-region as a non-layout and routing region.
[0006] In a specific implementation scheme, the method of determining a reference position for dividing the current layer into regions according to the placement directions of the design ports in the current layer of the integrated circuit layout includes: obtaining first axis projection endpoints of the design ports on the first coordinate axis of a preset coordinate system, wherein the direction of the first coordinate axis is perpendicular to the preset direction; and determining a reference position for dividing the current layer into regions according to the first axis projection endpoints of the design ports.
[0007] In a specific implementation scheme, the current layer is divided into multiple sub-areas along the preset direction according to the reference position, and also includes: completely dividing each design port into one of the sub-areas; the reference position for dividing the current layer into regions according to the first-axis projection endpoints of each design port is determined, including: if there are design ports with overlapping projections among the design ports, the reference position for dividing the current layer into regions is determined according to the first-axis projection endpoint with the largest coordinate value and the first-axis projection endpoint with the smallest coordinate value among the design ports with overlapping projections, wherein each design port among the design ports with overlapping projections at least partially overlaps with the projection of another design port on the first coordinate axis.
[0008] In a specific implementation scheme, before determining the non-layout and routing area, the method also includes: obtaining the second axis projection endpoints of the design ports on the second coordinate axis of the preset coordinate system, wherein the second coordinate axis is perpendicular to the first coordinate axis; for a sub-area, if the sub-area contains a design port, then the area outside the design port contained in the sub-area is determined as a non-layout and routing area, including: for a sub-area, according to the second axis projection endpoint of the design port contained in the sub-area, or according to the first axis projection endpoint and the second axis projection endpoint of the design port contained in the sub-area, determining the re-partition reference position of the sub-area; according to the re-partition reference position, dividing the sub-area into multiple re-sub-areas; and treating the re-sub-area that does not contain a design port as a non-layout and routing area.
[0009] In a specific implementation scheme, the reference position for dividing the current layer into regions is determined based on the placement direction of each design port in the current layer of the integrated circuit layout, including: in the vertical direction of the placement direction of each design port, according to a preset size, determining the reference position for dividing the current layer into regions.
[0010] In a specific implementation, after determining the non-layout and routing area, the method further includes expressing the position of the non-layout and routing area in the current layer in a preset manner.
[0011] In a specific implementation, expressing the position of the non-layout routing area in the current layer in a preset manner also includes: selecting two or more non-layout routing areas that can be connected to form a single area from the non-layout routing areas of the multiple sub-areas as an integrated area, wherein the number of vertices of the integrated area is less than the sum of the number of vertices of each non-layout routing area in the integrated area, and the number of vertices of the integrated area is less than a preset threshold; expressing the position of the integrated area in the current layer in a preset manner.
[0012] In a second aspect, an embodiment of the present invention further provides a device for determining a non-layout and routing area in an integrated circuit layout, the device for determining a non-layout and routing area in the integrated circuit layout comprising: a reference position determining unit, for determining a reference position for dividing the current layer into regions according to the placement directions of the design ports in the current layer of the integrated circuit layout, wherein the placement directions of the design ports are along the same preset direction; a sub-region dividing unit, for dividing the current layer into a plurality of sub-regions at the reference position along the preset direction; a non-layout and routing area judging unit, for determining, for a sub-region, if the sub-region contains a design port, the region outside the design port contained in the sub-region as a non-layout and routing region; if the sub-region does not contain a design port, determining the sub-region as a non-layout and routing region.
[0013] In a specific implementation scheme, the reference position determination unit includes: a projection endpoint acquisition module, used to obtain the first axis projection endpoints of each design port on the first coordinate axis of a preset coordinate system, wherein the direction of the first coordinate axis is perpendicular to the preset direction; a current layer reference position determination module, used to determine the reference position for regional division of the current layer according to the first axis projection endpoints of each design port.
[0014] In a specific implementation scheme, the sub-region division unit is also used to: completely divide each design port into one of the sub-regions; the current layer reference position determination module is used to: if there are design ports with overlapping projections among the design ports, then determine the reference position for region division of the current layer based on the first axis projection endpoint with the largest coordinate value and the first axis projection endpoint with the smallest coordinate value in the design ports with overlapping projections, wherein each design port in the design ports with overlapping projections at least partially overlaps with the projection of another design port on the first coordinate axis.
[0015] In a specific implementation scheme, the projection endpoint acquisition module is also used to obtain the second axis projection endpoints of each design port on the second coordinate axis of the preset coordinate system before determining the non-layout and routing area, wherein the second coordinate axis is perpendicular to the first coordinate axis; the non-layout and routing area judgment unit includes: a sub-region reference position determination module, used to determine the sub-region reference position for a sub-region according to the second axis projection endpoints of the design port contained in the sub-region, or according to the first axis projection endpoints and the second axis projection endpoints of the design port contained in the sub-region; a sub-region division module, used to divide the sub-region into multiple sub-regions according to the sub-region reference position; a non-layout and routing area determination module, used to treat the sub-region that does not contain the design port as a non-layout and routing area.
[0016] In a specific implementation manner, the reference position determination unit further includes a preset size division module for determining a reference position for dividing the current layer into regions according to a preset size in a direction perpendicular to the placement direction of each design port.
[0017] In a specific implementation manner, it further includes a position generating unit, which is used to express the position of the non-layout and routing area in the current layer in a preset manner after determining the non-layout and routing area.
[0018] In a specific implementation scheme, the position generation unit includes: an integration area selection module, which is used to select two or more non-layout and routing areas that can be connected to form a single area from the non-layout and routing areas of the multiple sub-areas as an integration area, wherein the number of vertices of the integration area is less than the sum of the number of vertices of each non-layout and routing area in the integration area, and the number of vertices of the integration area is less than a preset threshold; an integration area generation module, which is used to express the position of the integration area in the current layer in a preset manner.
[0019] In a third aspect, an embodiment of the present invention further provides an electronic device, comprising: a processor and a memory, wherein the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, and is used to execute any method for determining a non-layout and wiring area in an integrated circuit layout provided by an embodiment of the present invention.
[0020] In a fourth aspect, an embodiment of the present invention further provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement any method for determining a non-layout and routing area in an integrated circuit layout provided by an embodiment of the present invention.
[0021] The embodiments of the present invention provide a method, device, electronic device and storage medium for determining a non-layout and routing area in an integrated circuit layout, which determines a reference position for dividing the current layer into regions according to the placement direction of each design port in the current layer of the integrated circuit layout, wherein the placement direction of each design port is along the same preset direction; then, at the reference position, along the preset direction, the current layer is divided into multiple sub-regions; for a sub-region, if the sub-region contains a design port, the region outside the design port contained in the sub-region is determined as a non-layout and routing region; if the sub-region does not contain a design port, the sub-region is determined as a non-layout and routing region. The method facilitates the generation of a library exchange file that is easy to read and use. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.
[0023] Figure 1 An example of using polygons to represent non-layout and routing areas provided in an embodiment of the present application; Figure 2 An example of using a rectangle to represent a non-layout and routing area provided in an embodiment of the present application; Figure 3 A flow chart of a method for determining a non-layout and wiring area in an integrated circuit layout provided in an embodiment of the present application; Figure 4 A schematic diagram of the current layer and design ports in an integrated circuit layout provided in an embodiment of the present application; Figure 5A schematic diagram of dividing an integrated circuit layout into regions according to reference positions provided in an embodiment of the present application; Figure 6 A schematic diagram of multiple sub-regions obtained by dividing a current layer into regions in an integrated circuit layout provided in an embodiment of the present application; Figure 7 A flowchart for re-dividing sub-regions of a current layer in an integrated circuit layout provided in an embodiment of the present application; Figure 8 A step diagram of a method for determining a non-layout and wiring area in an integrated circuit layout provided in an embodiment of the present application; Fig. 9 A schematic diagram of the structure of a device for determining a non-layout and wiring area in an integrated circuit layout provided by an embodiment of the present application; Fig.10 A schematic diagram of the structure of a non-layout and wiring area judgment unit in an integrated circuit layout provided by an embodiment of the present application; Fig.11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0024] The embodiments of the present invention are described in detail below with reference to the accompanying drawings.
[0025] It should be clear that the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.
[0026] Current EDA tools provide two ways to describe non-layout area OBS: COVER and DETAIL. COVER describes the non-layout area as a polygon, and describes the coordinates of each vertex of the polygon in a line of data. DETAIL describes the non-layout area as a rectangle, and describes the coordinates of each vertex of each rectangle in a line of data. When there are many ports inside a cell, using COVER to describe the non-layout area will result in a polygon with very long data length, for example Figure 1 The polygonal area 10 shown in the figure may generate data lines exceeding the length limit, which may cause the LEF file to be unusable. When the cell size is relatively large, the DETAIL method of describing the non-layout area will generate a lot of rectangles, such as Figure 2 The rectangular area 20 shown in the figure will generate too many data rows, which will increase the additional computing cost in the layout and routing stage. To solve the above problems, firstly, Figure 3As shown, an embodiment of the present invention provides a method for determining a non-layout and routing area in an integrated circuit layout, and the method may include: S11. Determine a reference position for dividing the current layer into regions according to the placement directions of the design ports in the current layer of the integrated circuit layout, wherein the placement directions of the design ports are along the same preset direction.
[0027] An integrated circuit layout can contain multiple layers, each of which can be used to describe information such as unit size and port location. The placement direction of each design port in the same layer of the integrated circuit layout is consistent, for example Figure 4~Figure 6 As shown in the current layer 300, if each design port of the current layer is designed as a horizontal port, the placement direction of each design port can be arranged along the same preset direction, that is, horizontally; if each design port of the current layer is designed as a vertical port, the placement direction of each design port can be arranged along the same preset direction, that is, vertically. Therefore, in this embodiment, according to the placement direction of each design port in the current layer of the integrated circuit layout, the reference position for regional division of the current layer is determined, so that the existing placement direction information of each design port can be used to perform more targeted regional division of the current layer. For example, based on the known placement direction of each design port, it is convenient to establish a unified position reference coordinate system for each design port, so as to determine the relative position of each design port, and based on the reference coordinate system, determine the reference position for regional division of the current layer.
[0028] S12. At the reference position, along a preset direction, divide the current layer into a plurality of sub-areas.
[0029] like Figure 5 As shown, after determining the reference position for dividing the current layer into regions, this embodiment further utilizes the existing placement direction information of each design port, that is, along a preset direction consistent with the placement direction of each design port, the current layer is divided into multiple sub-regions, and each design port may have a different shape or size. In addition, a certain design port may be completely located in one of the sub-regions, and a certain design port may also be partially located in one of the sub-regions.
[0030] S13. For a sub-region, if the sub-region includes a design port, the region outside the design port included in the sub-region is determined as a non-layout and routing region; if the sub-region does not include a design port, the sub-region is determined as a non-layout and routing region.
[0031] After the current layer is divided into multiple sub-regions, a sub-region may contain ports, for example, a sub-region completely contains a design port or a sub-region only contains a partial part of a design; a sub-region may not contain ports, for example, a sub-region does not contain any complete design port, nor does it contain any partial part of a port. Therefore, for a sub-region containing a design port, such as Figure 6 The sub-region 30a shown in FIG. 1 is a region other than the design port contained in the sub-region, and is determined as a non-layout and routing region; and for the sub-region not containing the design port, such as Figure 6 As shown in the sub-region 30b, the entire area of the sub-region is determined as a non-layout and routing area, thereby determining the non-layout and routing area in the current layer.
[0032] The embodiment of the present invention provides a method for determining a non-layout and routing area in an integrated circuit layout, which determines a reference position for dividing the current layer into regions according to the placement direction of each design port in the current layer of the integrated circuit layout, wherein the placement direction of each design port is along the same preset direction; then, at the reference position, along the preset direction, the current layer is divided into multiple sub-regions; for a sub-region, if the sub-region contains a design port, the region outside the design port contained in the sub-region is determined as a non-layout and routing region; if the sub-region does not contain a design port, the sub-region is determined as a non-layout and routing region. The method facilitates the generation of a library exchange file that is easy to read and use.
[0033] As before, based on the known placement direction of each design port, it is convenient to establish a unified position reference coordinate system for each design port to determine the relative position of each design port or the reference position for regional division of the current layer. Therefore, optionally, in one embodiment of the present invention, the reference position for regional division of the current layer is determined according to the placement direction of each design port in the current layer of the integrated circuit layout, including: obtaining the first axis projection endpoint of each design port on the first coordinate axis of the preset coordinate system, wherein the direction of the first coordinate axis is perpendicular to the preset direction; determining the reference position for regional division of the current layer according to the first axis projection endpoint of each design port.
[0034] The preset coordinate system can be determined according to the current layer information, wherein the direction of the first coordinate axis of the preset coordinate system is perpendicular to the preset direction, that is, the direction of the first coordinate axis is perpendicular to the placement direction of each design port. Based on the first axis projection endpoints of each design port on the first coordinate axis of the preset coordinate system, the projection boundary of each design port on the first coordinate axis can be determined. In this way, when the current layer is divided into regions along the projection direction to the first coordinate axis, that is, the preset direction, the reference position can be determined according to the first axis projection endpoints of each design port, and then the current layer is divided into regions along the preset direction at each reference position. In this way, the current layer can be divided into multiple sub-regions. A certain design port can be completely located in one of the sub-regions. For example, the projection of a certain design port on the first coordinate axis does not overlap with the projection of other design ports on the first coordinate axis. Then, the sub-region divided by taking the first axis projection endpoint of the design port as the reference position completely includes the design port. A certain design port can also be partially located in one of the sub-regions. For example, the projections of two or more design ports on the first coordinate axis may partially overlap. Then, in the sub-regions divided by taking the first axis projection endpoints of the two or more design ports as the reference position, a certain sub-region may include a local part of a certain design port.
[0035] Specifically, when determining the reference position, if the first axis projection endpoint of a certain design port on the first coordinate axis does not overlap with the first axis projection endpoints of other design ports on the first coordinate axis, then the reference position for regional division of the current layer is determined based on the first axis projection endpoint of the design port; if the projections of two or more design ports on the first coordinate axis have overlapping first axis projection endpoints, then the reference position for regional division of the current layer is determined based on the overlapping first axis projection endpoints of the two or more design ports and the non-overlapping first axis projection endpoints of the two or more design ports, for example, the first axis projection endpoint of the design port PIN1 on the first coordinate axis is the reference position for regional division of the current layer. The projection area is [y1, y2], and the coordinates of the two corresponding first-axis projection endpoints on the first coordinate axis are y1 and y2 respectively; the projection area of the design port PIN2 on the first coordinate axis is [y2, y3], and the coordinates of the two corresponding first-axis projection endpoints on the first coordinate axis are y2 and y3 respectively, that is, the design port PIN1 and the design port PIN2 have overlapping first-axis projection endpoints y2 on the first coordinate axis, so the overlapping first-axis projection endpoints y2 of the design port PIN1 and the design port PIN2, as well as the non-overlapping first-axis projection endpoints y1 and y3, can be used to determine the corresponding area division reference position. After the current layer is divided into multiple sub-areas, one or more rectangular non-layout and routing areas can be determined from the sub-areas according to the size or coordinate information of the design port contained in the sub-area.
[0036] As described above, due to the diverse design positions of each design port in the current layer, for example, there may be more than two design ports whose projections on the first coordinate axis partially overlap. To reduce the number of sub-regions divided, optionally, in an embodiment of the present invention, according to the reference position, along the preset direction, the current layer is divided into multiple sub-regions, further including: completely dividing each design port into one of the sub-regions; determining the reference position for dividing the current layer according to the first-axis projection endpoints of each design port, including: if there are design ports with overlapping projections among the design ports, then according to the first-axis projection endpoint with the largest coordinate value and the first-axis projection endpoint with the smallest coordinate value among the design ports with overlapping projections, determine the reference position for dividing the current layer, where each of the design ports with overlapping projections has at least partial overlap with the projection of another design port on the first coordinate axis.
[0037] Determine the reference position for dividing the current layer according to the first-axis projection endpoint with the largest coordinate value and the first-axis projection endpoint with the smallest coordinate value among the design ports with overlapping projections, which is convenient for dividing the design ports with overlapping projections into the same sub-region, ensuring the integrity and unity of each sub-region obtained by dividing the current layer. In this embodiment, each of the design ports with overlapping projections has at least partial overlap with the projection of another design port on the first coordinate axis. Specifically, it may be partial overlap of the projection line segments, and in some embodiments, it may also be overlap of the projection endpoints. For example, two adjacent design ports with overlapping projection endpoints on the first coordinate axis can be divided into one sub-region according to the above method. For example, the projection area of design port PIN1 on the first coordinate axis is [y1, y2], and the coordinates of the corresponding two first-axis projection endpoints on the first coordinate axis are y1 and y2 respectively; the projection area of design port PIN2 on the first coordinate axis is [y3, y4], and the coordinates of the corresponding two first-axis projection endpoints on the first coordinate axis are y3 and y4 respectively, where y1 < y3 < y2 < y4, that is, design port PIN1 and design port PIN2 are design ports with overlapping projections, having an overlapping projection area [y3, y2]. Therefore, the reference position for corresponding region division can be determined according to the first-axis projection endpoint with the largest coordinate value among the design ports with overlapping projections, that is, y4, and the first-axis projection endpoint with the smallest coordinate value, that is, y1. Then, one or more than two rectangles or polygons of non-layout routing regions can be determined from this sub-region according to the size or coordinate information of the design ports included in this sub-region, which is beneficial to reducing the number of sub-regions and the data volume of the position representation of the non-layout routing regions in the sub-regions, and is convenient for generating a library exchange file that is easy to read and use.
[0038] After the current layer is divided into multiple sub-regions, the non-layout and routing region needs to be determined based on more sufficient shape and position information of the design ports in the sub-regions. Therefore, it is optional, such as Figure 7 As shown, in one embodiment of the present invention, before determining the non-layout and routing area, the method further includes: obtaining the second axis projection endpoints of each design port on the second coordinate axis of the preset coordinate system, wherein the second coordinate axis is perpendicular to the first coordinate axis; for a sub-area, if the sub-area includes a design port, determining the area outside the design port included in the sub-area as the non-layout and routing area, including: S21, for a sub-region, according to the second axis projection endpoint of the design port included in the sub-region, or according to the first axis projection endpoint and the second axis projection endpoint of the design port included in the sub-region, determine a re-partitioning reference position of the sub-region; S22, dividing the sub-region into a plurality of sub-regions according to the sub-region reference position; S23, treating the sub-area not including the designed port as a non-layout and routing area.
[0039] After determining the second axis projection endpoints of each design port on the second coordinate axis of the preset coordinate system, the projection boundary of each design port on the second coordinate axis can be obtained. In this way, for a certain sub-region, when the sub-region is subdivided along the projection direction to the second coordinate axis, that is, the vertical direction of the preset direction, the sub-region reference position can be determined according to the second axis projection endpoints of the design port contained in the sub-region. For example, the second axis projection endpoints of the design port contained in the sub-region can be used as the sub-region reference position, and the sub-region is subdivided along the vertical direction of the preset direction to obtain multiple sub-regions. If the sub-region contains multiple design ports, multiple sub-regions can be obtained based on this method. Among the multiple sub-regions, there are both regions containing design ports and regions not containing design ports. Then, the sub-region not containing design ports is selected as the non-layout and routing region.
[0040] In some embodiments, as described above, each design port is completely divided into one of the sub-areas. If each design port has a design port with overlapping projections on the first coordinate axis, the non-layout and routing area in the sub-area obtained by dividing according to the first-axis projection endpoint with the largest coordinate value and the first-axis projection endpoint with the smallest coordinate value in the design port with overlapping projections may be an irregular polygon. In this case, the re-partition reference position of the sub-area can be determined according to the first-axis projection endpoint and the second-axis projection endpoint of the design port contained in the sub-area. Based on the re-partition reference position, the sub-area can be further divided vertically along a preset direction, or the sub-area can be further divided along a preset direction, so as to further divide the polygonal sub-area into multiple rectangles, or polygons with no more than a set number of sides, thereby helping to further reduce the amount of data describing the position of the non-layout and routing area and facilitate the generation of a library exchange file that is easy to read and use.
[0041] In some application scenarios, for example, each design port may have a regular shape or relative position. In order to further facilitate the description of the position of the non-layout and wiring area in the integrated circuit layout and improve the design efficiency, optionally, in one embodiment of the present invention, according to the placement direction of each design port in the current layer of the integrated circuit layout, the reference position for dividing the current layer is determined, including: in the vertical direction of the placement direction of each design port, according to the preset size, the reference position for dividing the current layer is determined. It can be understood that determining the reference position for dividing the current layer according to the preset size can further utilize the existing design information, thereby improving the design efficiency, and is conducive to further reducing the amount of data for describing the position of the non-layout and wiring area in the sub-area.
[0042] Optionally, in one embodiment of the present invention, after determining the non-layout and routing area, the method further includes expressing the position of the non-layout and routing area in the current layer in a preset manner. For example, if the non-layout and routing area in the sub-region is a rectangle, the positions of the vertices of the non-layout and routing area of the rectangle in the current layer can be expressed in the RECT manner in LEF, and if the non-layout and routing area in the sub-region is a polygon, the positions of the vertices of the non-layout and routing area of the polygon in the current layer can be expressed in the POLYGON manner in LEF, thereby obtaining a LEF file that can be used for design by different EDA tools. This embodiment can significantly reduce the amount of data used to describe the position of the non-layout and routing area in the sub-area. For example, for a unit with a size of 50.022um×180.936um, there are 830 non-power design ports in a certain layer. For the non-layout and routing area of this layer, if the COVER method is used, a polygon with a data length of up to 41,184 characters is required to describe it. If the DETAIL method is used, 319,417 rectangles are required to describe it and the maximum data length of the rectangle is 52 characters. However, if the method of this embodiment is used, only 1,660 rectangles are required to describe it and the maximum description length of the rectangle is 52 characters. It can be seen that the description method of this embodiment avoids the shortcomings of the COVER method and DETAIL, can reduce the number of rectangles or polygons used to describe the non-layout and routing area, and ensure that the maximum data length of the rectangles or polygons does not exceed the limit, thereby facilitating the generation of easy-to-read and easy-to-use library exchange files.
[0043] After determining the non-layout and routing areas in each sub-region, in order to further reduce the amount of data describing the position of the non-layout and routing areas in the sub-region and improve the availability of the description file of the non-layout and routing areas, optionally, in one embodiment of the present invention, the position of the non-layout and routing areas in the current layer is described in a preset manner, and also includes: selecting two or more non-layout and routing areas that can be adjacent to form a single area from the non-layout and routing areas of multiple sub-regions as an integrated area, wherein the number of vertices in the integrated area is less than the sum of the number of vertices of each non-layout and routing area in the integrated area, and the number of vertices in the integrated area is less than a preset threshold; describing the position of the integrated area in the current layer in a preset manner.
[0044] It can be understood that using two or more non-layout wiring areas that can be connected to form a single area as an integrated area is beneficial to further reduce the amount of data used to describe the position of the non-layout wiring area in the sub-area. For example, if the position of each non-layout wiring area in the integrated area in the current layer is described separately, the vertex coordinates of each non-layout wiring area need to be described. The number of vertices of the integrated area obtained according to the method of this embodiment is less than the sum of the number of vertices of each non-layout wiring area in the integrated area. This allows the description of the position of the integrated area in the current layer to have a smaller amount of data. In addition, since the number of vertices in the integrated area is less than the preset threshold, this can prevent the integrated area from forming a polygon with too many sides, thereby avoiding the generation of lines exceeding the limit length, which makes the LEF file unusable. For example, for a rectangular non-layout wiring area A, there is a rectangular non-layout wiring area B adjacent to its upper part, and the left and right sides of the non-layout wiring area A and the non-layout wiring area B are aligned respectively, that is, the lengths of the non-layout wiring area A and the non-layout wiring area B are the same. If the non-layout wiring area A and the non-layout wiring area B are described separately, data description must be performed for the four vertices of the non-layout wiring area A and the four vertices of the non-layout wiring area B, a total of eight vertices. However, according to the above method of this embodiment, the integrated area obtained by integrating the non-layout wiring area A and the non-layout wiring area B has only four vertices, and the data description of the integrated area can significantly reduce the amount of data; and if the non-layout wiring area A and the non-layout wiring area B are only aligned on the left side or only on the right side, the integrated area obtained by integrating the non-layout wiring area A and the non-layout wiring area B has six vertices, and the data description of the integrated area can still reduce the amount of data. It can be seen that this embodiment can further optimize the amount of data for the position description of the non-layout wiring area and improve the availability of the library exchange file of the non-layout wiring area.
[0045] In summary, if Figure 8 As shown, the embodiment of the present application provides specific steps of a method for determining a non-layout and wiring area in an integrated circuit layout: For the current layer in the integrated circuit layout, each design port in the current layer, such as the placement direction of each design port, can be determined in step S301; then, the placement direction of each design port is determined according to step S302. If the placement direction is horizontal, that is, along the x-axis of the preset coordinate system, the y-coordinate value of each design port is obtained in step S303, and the region is divided at the y-coordinate value of each design port in step S304 to obtain multiple sub-regions. If the placement direction is vertical, that is, along the y-axis of the preset coordinate system, the x-coordinate value of each design port is obtained in step S305, and the region is divided at the x-coordinate value of each design port in step S306 to obtain multiple sub-regions; then, the non-layout and routing area of each sub-region is determined in step S307. For example, according to the above method of this embodiment, multiple sub-regions can be further divided into sub-regions to determine the non-layout and routing area, or the non-layout and routing areas of multiple sub-regions can be further integrated to optimize the amount of data describing the position of the non-layout and routing area and generate a library exchange file that is easy to read and use.
[0046] In a second aspect, an embodiment of the present invention further provides a device for determining a non-layout and routing area in an integrated circuit layout, so as to facilitate the generation of a library exchange file that is easy to read and use.
[0047] like Fig. 9 As shown, the device for determining the non-layout and wiring area in the integrated circuit layout provided by the embodiment of the present application may include: A reference position determination unit 41 is used to determine a reference position for dividing the current layer into regions according to the placement directions of the design ports in the current layer of the integrated circuit layout, wherein the placement directions of the design ports are along the same preset direction; A sub-region dividing unit 42 is used to divide the current layer into a plurality of sub-regions along a preset direction at a reference position; The non-layout and routing area judgment unit 43 is used for determining, for a sub-area, if the sub-area contains a design port, the area outside the design port contained in the sub-area as a non-layout and routing area; if the sub-area does not contain a design port, determining the sub-area as a non-layout and routing area.
[0048] Optionally, the reference position determination unit 41 includes: a projection endpoint acquisition module, used to obtain the first axis projection endpoint of each design port on the first coordinate axis of a preset coordinate system, wherein the direction of the first coordinate axis is perpendicular to the preset direction; a current layer reference position determination module, used to determine the reference position for regional division of the current layer according to the first axis projection endpoint of each design port.
[0049] Optionally, the sub-region division unit 42 is further used to: completely divide each design port into one of the sub-regions; the current layer reference position determination module is used to: if there are design ports with overlapping projections among the design ports, then determine the reference position for region division of the current layer based on the first-axis projection endpoint with the largest coordinate value and the first-axis projection endpoint with the smallest coordinate value among the design ports with overlapping projections, wherein each design port among the design ports with overlapping projections at least partially overlaps with the projection of another design port on the first coordinate axis.
[0050] Optionally, the projection endpoint acquisition module is further used to, before determining the non-layout and routing area, acquire the second axis projection endpoints of each design port on the second coordinate axis of the preset coordinate system, wherein the second coordinate axis is perpendicular to the first coordinate axis; Fig.10 As shown, the non-layout and routing area determination unit 43 includes: A re-partition reference position determination module 431 is used to determine, for a sub-region, a re-partition reference position of the sub-region according to a second axis projection endpoint of a design port included in the sub-region, or according to a first axis projection endpoint and a second axis projection endpoint of a design port included in the sub-region; A sub-region division module 432 is used to divide the sub-region into a plurality of sub-regions according to the sub-region reference position; The non-layout and routing area determination module 433 is used to divide the sub-area that does not contain the design port into non-layout and routing areas.
[0051] Optionally, the reference position determination unit 41 further includes a preset size division module, which is used to determine the reference position for dividing the current layer into regions according to a preset size in a direction perpendicular to the placement direction of each design port.
[0052] Optionally, the device for determining a non-layout and wiring area in an integrated circuit layout further includes a position generating unit for expressing the position of the non-layout and wiring area in the current layer in a preset manner after determining the non-layout and wiring area.
[0053] Optionally, the position generation unit includes: an integration area selection module, used to select two or more non-layout and routing areas that can be connected to form a single area from the non-layout and routing areas of multiple sub-areas as an integration area, wherein the number of vertices in the integration area is less than the sum of the number of vertices of each non-layout and routing area in the integration area, and the number of vertices in the integration area is less than a preset threshold; an integration area generation module, used to express the position of the integration area in the current layer according to a preset method.
[0054] In a third aspect, an embodiment of the present invention further provides an electronic device. Fig.11As shown, the electronic device includes: a processor 52 and a memory 53, wherein the memory 53 is used to store executable program codes; the processor 52 runs a program corresponding to the executable program code by reading the executable program code stored in the memory 53, and is used to execute any method for determining a non-layout wiring area in an integrated circuit layout provided by an embodiment of the present invention.
[0055] like Fig.11 As shown, the electronic device provided in the embodiment of the present application specifically includes: a shell 51, a processor 52, a memory 53, a circuit board 54 and a power supply circuit 55, wherein the circuit board 54 is arranged inside the space enclosed by the shell 51, and the processor 52 and the memory 53 are arranged on the circuit board 54; the power supply circuit 55 is used to supply power to various circuits or devices of the above-mentioned electronic device; the memory 53 is used to store executable program codes; the processor 52 runs the program corresponding to the executable program code by reading the executable program code stored in the memory 53, so as to execute any method for determining the non-layout wiring area in the integrated circuit layout provided in the embodiment of the present invention.
[0056] The specific execution process of the above steps by the processor 52 and the steps further executed by the processor 52 by running the executable program code can be found in the description of the previous embodiment, which will not be repeated here.
[0057] The above electronic devices exist in many forms, including but not limited to: (1) Mobile communication devices: These devices are characterized by their mobile communication functions and their main purpose is to provide voice and data communications. These terminals include: smart phones (such as iPhone), multimedia phones, feature phones, and low-end phones.
[0058] (2) Ultra-mobile personal computer devices: These devices fall into the category of personal computers, have computing and processing capabilities, and generally also have mobile Internet access features. These terminals include: PDA, MID and UMPC devices, such as iPad.
[0059] (3) Portable entertainment devices: These devices can display and play multimedia content. They include audio and video players (such as iPods), handheld game consoles, e-books, smart toys, and portable car navigation devices.
[0060] (4) Server: A device that provides computing services. The server consists of a processor, hard disk, memory, system bus, etc. The server is similar to a general-purpose computer architecture, but because it needs to provide highly reliable services, it has higher requirements in terms of processing power, stability, reliability, security, scalability, and manageability.
[0061] (5) Other electronic devices with data interaction functions.
[0062] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein the computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement any method for determining a non-layout and routing area in an integrated circuit layout provided in an embodiment of the present invention, thereby also being able to achieve the corresponding technical effects, which have been described in detail above and will not be repeated here.
[0063] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0064] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referenced to each other, and each embodiment focuses on the differences from other embodiments.
[0065] In particular, for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.
[0066] For the convenience of description, the above device is described by dividing the functions into various units / modules. Of course, when implementing the present invention, the functions of each unit / module can be implemented in the same or multiple software and / or hardware.
[0067] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the processes of the embodiments of the above-mentioned methods. The storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.
[0068] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims
1. A method for determining a non-layout and routing area in an integrated circuit layout, characterized in that: include: Determining a reference position for dividing the current layer into regions according to the placement directions of the design ports in the current layer of the integrated circuit layout, wherein the placement directions of the design ports are along the same preset direction; At the reference position, along the preset direction, the current layer is divided into a plurality of sub-areas; For a sub-region, if the sub-region includes a design port, the region outside the design port included in the sub-region is determined as a non-layout and routing region; if the sub-region does not include a design port, the sub-region is determined as a non-layout and routing region.
2. The method for determining a non-layout and routing area in an integrated circuit layout according to claim 1, wherein: The step of determining a reference position for dividing the current layer into regions according to the placement directions of the design ports in the current layer of the integrated circuit layout includes: Obtaining first axis projection endpoints of each of the design ports on a first coordinate axis of a preset coordinate system, wherein the direction of the first coordinate axis is perpendicular to the preset direction; A reference position for dividing the current layer into regions is determined according to the first axis projection endpoints of the design ports.
3. The method for determining a non-layout and routing area in an integrated circuit layout according to claim 2, wherein: The step of dividing the current layer into a plurality of sub-regions along the preset direction according to the reference position further includes: completely dividing each design port into one of the sub-regions; The step of determining a reference position for dividing the current layer into regions according to the first axis projection endpoints of each design port includes: If there is a design port with overlapping projections among the design ports, a reference position for dividing the current layer into regions is determined based on the first-axis projection endpoint with the largest coordinate value and the first-axis projection endpoint with the smallest coordinate value among the design ports with overlapping projections, wherein each design port among the design ports with overlapping projections at least partially overlaps with the projection of another design port on the first coordinate axis.
4. The method for determining a non-layout and routing area in an integrated circuit layout according to claim 2, wherein: Before determining the non-layout and routing area, the method further includes: obtaining second axis projection endpoints of each design port on a second coordinate axis of the preset coordinate system, wherein the second coordinate axis is perpendicular to the first coordinate axis; For a sub-region, if the sub-region includes a design port, determining the region outside the design port included in the sub-region as a non-layout and routing region includes: For a sub-region, determining a re-partitioning reference position of the sub-region according to a second axis projection endpoint of a design port included in the sub-region, or according to a first axis projection endpoint and a second axis projection endpoint of a design port included in the sub-region; Dividing the sub-region into a plurality of sub-regions according to the sub-region reference position; The subdivided area that does not contain the design port is regarded as a non-placement and routing area.
5. The method for determining a non-layout and routing area in an integrated circuit layout according to claim 1, wherein: The step of determining a reference position for dividing the current layer into regions according to the placement directions of the design ports in the current layer of the integrated circuit layout includes: In a direction perpendicular to the placement direction of the designed ports, a reference position for dividing the current layer into regions is determined according to a preset size.
6. The method for determining a non-layout and routing area in an integrated circuit layout according to claim 1, wherein: After determining the non-layout and routing area, the method further includes expressing the position of the non-layout and routing area in the current layer in a preset manner.
7. The method for determining a non-layout and routing area in an integrated circuit layout according to claim 1, wherein: The step of expressing the position of the non-layout and routing area in the current layer in a preset manner further includes: From the non-layout and routing areas of the multiple sub-areas, select two or more non-layout and routing areas that can be connected to form a single area as an integrated area, wherein the number of vertices of the integrated area is less than the sum of the number of vertices of each non-layout and routing area in the integrated area, and the number of vertices of the integrated area is less than a preset threshold; The position of the integrated area in the current layer is expressed in a preset manner.
8. A device for determining a non-layout and routing area in an integrated circuit layout, characterized in that: include: A reference position determination unit, configured to determine a reference position for dividing the current layer into regions according to the placement directions of the design ports in the current layer of the integrated circuit layout, wherein the placement directions of the design ports are along the same preset direction; A sub-region division unit, configured to divide the current layer into a plurality of sub-regions along the preset direction at the reference position; The non-layout and routing area judgment unit is used for determining, for a sub-area, if the sub-area contains a design port, the area outside the design port contained in the sub-area as a non-layout and routing area; if the sub-area does not contain a design port, the sub-area is determined as a non-layout and routing area.
9. The device for determining a non-layout and routing area in an integrated circuit layout according to claim 8, characterized in that: The reference position determining unit comprises: A projection endpoint acquisition module, used to acquire first axis projection endpoints of each design port on a first coordinate axis of a preset coordinate system, wherein the direction of the first coordinate axis is perpendicular to the preset direction; The current layer reference position determination module is used to determine the reference position for dividing the current layer into regions according to the first axis projection endpoints of the design ports.
10. The device for determining a non-layout and routing area in an integrated circuit layout according to claim 9, characterized in that: The sub-region division unit is also used to: completely divide each design port into one of the sub-regions; the current layer reference position determination module is used to: if there are design ports with overlapping projections among the design ports, then determine the reference position for region division of the current layer based on the first axis projection endpoint with the largest coordinate value and the first axis projection endpoint with the smallest coordinate value among the design ports with overlapping projections, wherein each design port among the design ports with overlapping projections at least partially overlaps with the projection of another design port on the first coordinate axis.
11. The device for determining a non-layout and routing area in an integrated circuit layout according to claim 9, wherein: The projection endpoint acquisition module is further used to, before determining the non-layout and routing area, acquire the second axis projection endpoints of each design port on the second coordinate axis of the preset coordinate system, wherein the second coordinate axis is perpendicular to the first coordinate axis; The non-layout and routing area determination unit comprises: A re-partition reference position determination module is used to determine, for a sub-region, a re-partition reference position of the sub-region according to a second axis projection endpoint of a design port included in the sub-region, or according to a first axis projection endpoint and a second axis projection endpoint of a design port included in the sub-region; A sub-region division module, used for dividing the sub-region into a plurality of sub-regions according to the sub-region reference position; The non-layout and routing area determination module is used to divide the sub-area that does not contain the design port into non-layout and routing areas.
12. The device for determining a non-layout and routing area in an integrated circuit layout according to claim 8, wherein: The reference position determination unit further includes a preset size division module, which is used to determine the reference position for dividing the current layer into regions according to a preset size in a direction perpendicular to the placement direction of each design port.
13. The device for determining a non-layout and routing area in an integrated circuit layout according to claim 8, wherein: It also includes a position generating unit, which is used to express the position of the non-layout and wiring area in the current layer in a preset manner after determining the non-layout and wiring area.
14. The device for determining a non-layout and routing area in an integrated circuit layout according to claim 13, wherein: The position generating unit comprises: an integration region selection module, configured to select, from the non-layout and routing regions of the plurality of sub-regions, two or more non-layout and routing regions that can be connected to form a single region as an integration region, wherein the number of vertices of the integration region is less than the sum of the number of vertices of each non-layout and routing region in the integration region, and the number of vertices of the integration region is less than a preset threshold; The integration region generating module is used to express the position of the integration region in the current layer in a preset manner.
15. An electronic device, characterized in that: The electronic device comprises: a processor and a memory, wherein the memory is used to store executable program code; the processor runs a program corresponding to the executable program code by reading the executable program code stored in the memory, so as to execute the method for determining a non-layout and wiring area in an integrated circuit layout as described in any one of claims 1 to 7.
16. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores one or more programs, and the one or more programs can be executed by one or more processors to implement the method for determining a non-layout and routing area in an integrated circuit layout as described in any one of claims 1-7.