Memory device with computing function and operating method thereof

Abstract

The invention discloses a memory device with a computing function and an operating method thereof. The memory device with a computing function includes: a first cell array including first memory cells connected to word lines; a second cell array including second memory cells connected to the word lines; a first bit line sense amplifier sensing a first voltage of a first bit line connected to the first memory cell; a second bit line sense amplifier sensing a second voltage of a second bit line connected to the second memory cell; a first column selection circuit that outputs a first output signal among the first voltages based on the first column calculation selection signal; a second column selection circuit outputting a second output signal among the second voltages based on a second column calculation selection signal different from the first column calculation selection signal; and a column calculation control circuit that generates a first column calculation selection signal and a second column calculation selection signal.

Description

[0001] This application claims the priority of Korean Patent Application No. 10-2023-0101019 filed on August 2, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] Devices, apparatuses, and methods consistent with the present disclosure relate to semiconductor memories, and more particularly, to memory devices having computing functions and methods of operating the same. Background Art

[0003] Semiconductor memories may be classified as volatile memories (such as, for example, static random access memory (SRAM) or dynamic random access memory (DRAM)) that lose data stored therein when power is disconnected, or nonvolatile memories (such as, for example, flash memory, phase change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM)) that retain data stored therein even when power is disconnected.

[0004] Because DRAM has a fast response speed and operation speed, DRAM is widely used as the main memory of the system. Under the control of the host, the DRAM of the prior art stores data therein or outputs the data stored therein. Nowadays, DRAM devices including internal processors are being developed, and the internal processor performs a part of the computing operation of the host (e.g., CPU) as internal processing. Internal processing can reduce the burden of the computing operation of the host, and therefore, the overall performance of the system can be improved. However, internal processing requires a separate processor or a separate arithmetic logic unit. Summary of the invention

[0005] One aspect provides a memory device and an operating method thereof that provide computing functions while improving performance and reducing cost.

[0006] According to an aspect of one or more embodiments, a memory device with a computing function is provided, the memory device comprising: a first cell array comprising first memory cells connected to a plurality of word lines; a second cell array comprising second memory cells connected to the plurality of word lines; a first bit line sense amplifier configured to sense a first voltage of a first bit line connected to the first memory cell and output the first voltage; a second bit line sense amplifier configured to sense a second voltage of a second bit line connected to the second memory cell and output the second voltage; a first column selection circuit configured to output a first output signal among the first voltages output by the first bit line sense amplifier based on a first column computing selection signal; a second column selection circuit configured to output a second output signal among the second voltages output by the second bit line sense amplifier based on a second column computing selection signal different from the first column computing selection signal; and a column computing control circuit configured to generate a first column computing selection signal and a second column computing selection signal.

[0007] According to another aspect of one or more embodiments, a method for operating a memory device with a computing function is provided, the method comprising: loading an input operand; setting a plurality of column registers based on the input operand; performing a first internal read operation on a memory cell of the memory device regarding a first word line based on a plurality of first column computing select signals respectively generated from the plurality of column registers; updating the plurality of column registers and an output register based on a result of the first internal read operation; and performing a second internal read operation on a memory cell of the memory device regarding the first word line based on a plurality of second column computing select signals respectively generated from the plurality of column registers that have been updated.

[0008] According to another aspect of one or more embodiments, a memory device with a computing function is provided, the memory device comprising: a first cell array, configured to store a first computing output pattern; a first bit line sense amplifier, configured to sense a first voltage of a first bit line connected to the first cell array, and output the first voltage; a first column selection circuit, configured to output a first output signal among the first voltages output by the first bit line sense amplifier based on a first column computing selection signal; and a first column computing control circuit, configured to generate a first column computing selection signal based on an input operand, wherein the first column computing control circuit updates the first column computing selection signal when an internal read operation on the first computing output pattern is repeatedly performed.

[0009] According to another aspect of one or more embodiments, there is provided an operating method of a controller, the controller being configured to control a memory device having a computing function, the operating method comprising: sending a load command to the memory device, the load command instructing the memory device to load an input operand into the memory device; sending a set command to the memory device, the set command instructing the memory device to set a column computing control circuit of the memory device based on the input operand; sending an execute command to the memory device, the execute command instructing the memory device to perform a computing operation on the input operand so that an internal read operation is repeatedly performed in the memory device; and sending a store command to the memory device, the store command instructing the memory device to store a result of the computing operation in the memory device.

[0010] According to another aspect of one or more embodiments, a memory device having a computing function is provided, the memory device comprising: a first memory bank comprising a plurality of first memory cells; and a second memory bank comprising a plurality of second memory cells. The first memory bank comprises: a first column selection circuit configured to output a first output signal among the outputs of the plurality of first memory cells based on a first column computing selection signal; and a first column computing control circuit configured to generate the first column computing selection signal based on an input operand. The second memory bank comprises: a second column selection circuit configured to output a second output signal among the outputs of the plurality of second memory cells based on a second column computing selection signal; and a second column computing control circuit configured to generate a second column computing selection signal based on an input operand. When an internal read operation is performed for the plurality of first memory cells and the plurality of second memory cells, the first column selection circuit updates the first column computing selection signal based on the first output signal, and the second column selection circuit updates the second column computing selection signal based on the second output signal and information fed forward from the first column computing control circuit.

[0011] According to another aspect of one or more embodiments, a memory device having a computing function is provided, the memory device comprising: a cell array including memory cells connected to a plurality of word lines; and a plurality of column registers configured according to input operands; and an output register. The memory device is configured to: perform a first internal read operation on memory cells on a first word line among the plurality of word lines based on a plurality of first column computing select signals respectively generated from the plurality of column registers, update the plurality of column registers and the output register based on a result of the first internal read operation, and perform a second internal read operation on memory cells on the first word line based on a plurality of second column computing select signals respectively generated from the plurality of column registers that have been updated BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects will become clear by describing in detail embodiments of the above and other aspects with reference to the accompanying drawings, in which:

[0013] Figure 1 is a block diagram showing a memory device according to an embodiment;

[0014] Figure 2A and Figure 2B is a diagram for describing a read operation of a memory device according to an embodiment;

[0015] FIG. 3A to FIG. 3C is a diagram for describing a bit serial calculation based on a lookup table according to an embodiment;

[0016] Figure 4A and Figure 4B It is used to describe the embodiment according to Figure 1 A diagram of a computing operation of a memory device;

[0017] Figure 5 It is used to describe the embodiment according to Figure 1 A flowchart of a computing operation of a memory device;

[0018] FIG. 6A to FIG. 6E is used to describe the embodiment according to Figure 5 an illustration of a flowchart of a computing operation of a memory device;

[0019] Figure 7 It is used to describe the embodiment according to Figure 1 A diagram of an example of a computing output mode of a memory device;

[0020] Fig. 8A and Figure 8B It is used to describe the embodiment according to Figure 1 A diagram of a computing operation of a memory device;

[0021] Fig. 9 is a block diagram showing a memory device according to an embodiment;

[0022] Fig.10 and Fig.11 It is used to describe the embodiment according to Fig. 9 A diagram of a computing operation of a cluster unit of a memory device;

[0023] Fig. 12A and Fig. 12B is a block diagram showing a memory device according to an embodiment;

[0024] Fig.13 is a block diagram illustrating a memory system according to an embodiment;

[0025] Fig.14 According to the embodiment shown Fig.13 A flowchart of the operation of the memory system;

[0026] Fig.15 It is used for describing in detail according to the embodiment Fig.14 A flowchart of operation S1100 of the flowchart;

[0027] Fig.16 It is used to describe the embodiment according to Fig.13 A diagram of storage capacity of a memory device of a memory system;

[0028] Fig.17 It is used to describe the embodiment according to Fig.16 A diagram of a lookup table of a memory device;

[0029] Fig.18A and Fig.18B The details of the embodiment are shown in Fig.14 ; FIG. 1 is a diagram of operation S1200 of a flowchart of FIG.

[0030] Fig.19 According to the embodiment shown Fig.14 A flowchart of operation S1300 of the flowchart;

[0031] Fig. 20A , Fig. 20B and Fig. 20C According to the embodiment shown Fig.14 A flowchart of operation S1400 of the flowchart;

[0032] Fig.21 According to the embodiment shown Fig.13 A block diagram of a memory controller of a host of a memory system;

[0033] Fig. 22 is a diagram showing a memory module according to an embodiment;

[0034] Fig.23 is a block diagram illustrating a memory system according to an embodiment;

[0035] Fig.24 is a block diagram illustrating a memory system according to an embodiment; and

[0036] Fig.25 is a diagram illustrating an example of a data center to which a memory device according to an embodiment is applied. DETAILED DESCRIPTION

[0037] Hereinafter, various embodiments will be described in detail so that those having ordinary skill in the art can easily implement the various embodiments.

[0038] Figure 1is a block diagram showing a memory device according to an embodiment. Figure 1 , the memory device 100 may include a memory cell array 110, a command and address (CA) buffer 120, an address decoder 130, a command decoder 140, a control logic circuit 150, an input / output (I / O) circuit and column decoder 160, and a column calculation control circuit 170.

[0039] The memory cell array 110 may include a plurality of memory cells. The plurality of memory cells may be connected to word lines and bit lines. In one embodiment, each of the plurality of memory cells may be a dynamic random access memory (DRAM) cell including an access transistor and a storage capacitor. However, the embodiment is not limited thereto. In one embodiment, the memory cell array 110 may include various components (e.g., a word line driver, a bit line sense amplifier, and / or a column selection circuit) for controlling a plurality of memory cells, word lines, or bit lines. The construction of the memory cell array 110 will be described in more detail below with reference to the accompanying drawings.

[0040] The CA buffer 120 may receive a command / address signal CA from an external device (eg, a memory controller). The CA buffer 120 may be configured to buffer the received signal. In one embodiment, the signal buffered by the CA buffer 120 may include a command CMD and an address ADDR.

[0041] The address decoder 130 may receive the address ADDR from the CA buffer 120 and may decode the received address ADDR. Based on the address decoding result, the address decoder 130 may provide a row address to the memory cell array 110 (or, in some embodiments, a row driver), and may provide a column address to the input / output circuit and the column decoder 160.

[0042] The command decoder 140 may receive the command CMD from the CA buffer 120 and may decode the received command CMD. The command decoder 140 may provide the command decoding result to the control logic circuit 150.

[0043] The control logic circuit 150 may control the overall operation of the memory device 100 based on the command decoding result from the command decoder 140. Figure 1 An embodiment is shown where the control logic circuit 150 is connected to the command decoder 140 and the I / O circuit and column decoder 160 , but in some embodiments, the control logic circuit 150 may also be connected to other components of the memory device 100 .

[0044] The input / output (I / O) circuit and column decoder 160 may be connected to the memory cell array 110 through the bit lines. The input / output circuit and column decoder 160 may control the bit lines based on the column address from the address decoder 130. The input / output circuit and column decoder 160 may receive data "DATA" from an external device (e.g., a memory controller) through a data signal DQ and a data strobe signal DQS, and may store the received data "DATA" in the memory cell array 110. In one embodiment, the input / output circuit and column decoder 160 may receive data "DATA" from the memory cell array 110, and may provide the received data "DATA" to an external device (e.g., a memory controller) through the data signal DQ and the data strobe signal DQS.

[0045] As described above, under the control of an external device (eg, a memory controller), the memory device 100 may store data “DATA” or may output the stored data “DATA”.

[0046] In one embodiment, the memory device 100 may provide a computing function. For example, the memory device 100 may perform various computing operations under the control of an external device (e.g., a memory controller), and the memory device 100 may store the results of the computing operations in the memory device 100 or may provide the results of the computing operations to the external device (or memory controller). In detail, the memory cell array 110 of the memory device 100 may be configured to store a computing output pattern LUT_SET, which will be described in more detail below.

[0047] When the memory device 100 performs a calculation operation, the memory cell storing the calculation output pattern LUT_SET may be activated. In this case, the column calculation control circuit 170 may control the column selection circuit of the memory cell array 110 based on the input operand. A specific value may be selected and output from the calculation output pattern LUT_SET by the operation of the column calculation control circuit 170, and a combination of the selected specific values ​​may correspond to the calculation result of the input operand. In one embodiment, the column calculation control circuit 170 may support a bit serial calculation function based on a lookup table. The structure and operation of the memory device 100 according to various embodiments will be described in detail with reference to the accompanying drawings.

[0048] Figure 2A and Figure 2B is a diagram for describing a read operation of a memory device according to an embodiment. Figure 2A and Figure 2B A read operation of the memory device 100 is described. In this case, the read operation of the memory device 100 may refer to a read operation on user data "DATA" (ie, a normal read operation).

[0049] Reference Figure 1 , Figure 2A and Figure 2B In some embodiments, the input / output (I / O) circuit and column decoder 160 may include a column address decoder 161 and a read buffer 162. The column address decoder 161 may receive a column address and may generate a column select signal CSL based on the received column address. In one embodiment, the column address may be received from the address decoder 130.

[0050] The read buffer 162 may receive the read data DATA_READ output from the input / output sense amplifier IOSA and may transmit the received read data DATA_READ to an external device (eg, a memory controller).

[0051] The memory cell array 110 may include a cell array CAR, a bit line sense amplifier BLSA, a column selection circuit CSC, and an input / output sense amplifier IOSA.

[0052] The cell array CAR may include a plurality of memory cells, and the plurality of memory cells may be connected to a plurality of word lines WL0 to WLn. The plurality of memory cells may store data "DATA". In a read operation of the memory device 100, a word line selected from the plurality of word lines WL0 to WLn may be activated. The data stored in the memory cells connected to the selected word lines may be output through a plurality of bit lines BL.

[0053] The bit line sense amplifier BLSA may be connected to a plurality of memory cells of the cell array CAR through a plurality of bit lines BL. The bit line sense amplifier BLSA may be configured to sense voltage changes of the plurality of bit lines BL and output the sensed voltage changes.

[0054] In response to the column selection signal CSL, the column selection circuit CSC may select some of the voltage changes output from the bit line sense amplifier BLSA to be output through the local input / output line LIO. The local input / output line LIO may be connected to the global input / output line GIO.

[0055] The input / output sense amplifier IOSA may be configured to sense a change of the global input / output line GIO and output the sensed change as read data DATA_READ.

[0056] In one embodiment, Figure 2A The structure of the memory cell array 110 shown in FIG. 1 may correspond to one lane. One lane may refer to a component associated with read data output based on one column selection signal CSL.

[0057] In one embodiment, the memory device 100 may include a plurality of memory banks, and each of the plurality of memory banks may include a plurality of channels. Figure 2B A memory bank of the memory cell array 110 is shown by way of example. Figure 2B As shown in , one bank of the memory cell array 110 may include four channels. In detail, one bank of the memory cell array 110 may include a plurality of cell arrays CAR[0] to CAR[3]. The plurality of cell arrays CAR[0] to CAR[3] may be connected to a plurality of bit line sense amplifiers BLSA[0] to BLSA[3], respectively. The plurality of bit line sense amplifiers BLSA[0] to BLSA[3] may be connected to a plurality of column selection circuits CSC[0] to CSC[3], respectively. The plurality of column selection circuits CSC[0] to CSC[3] may output a plurality of output signals OUT0 to OUT3, respectively, in response to a column selection signal CSL.

[0058] The plurality of input / output sense amplifiers IOSA[0] to IOSA[3] may be configured to amplify a plurality of output signals OUT0 to OUT3 output from a plurality of column selection circuits CSC[0] to CSC[3] through a plurality of global input / output lines GIO1 to GIO3 and output the amplified signals.

[0059] Signals output from the plurality of input / output sense amplifiers IOSA[0] to IOSA[3] may be provided to the read buffer 162, and the read buffer 162 may output the received signals as read data to an external device.

[0060] In one embodiment, in a read operation of the memory device 100, a column selection signal CSL may be generated based on a column address, and the same column selection signal CSL may be provided to each of the plurality of column selection circuits CSC[0] to CSC[3]. In this case, the plurality of column selection circuits CSC[0] to CSC[3] may respectively select a bit line BL corresponding to the same column selection signal CSL, or may output data corresponding to the column selection signal CSL.

[0061] FIG. 3A to FIG. 3C is a diagram for describing a bit serial calculation based on a lookup table according to an embodiment. FIG. 3A to FIG. 3C Describes the lookup table-based bit-serial computation corresponding to a 4-bit multiplication operation.

[0062] Reference FIG. 3A to FIG. 3C, for a 4-bit multiplication operation, the four lookup tables LUT0 to LUT3 may be connected in series. Each of the four lookup tables LUT0 to LUT3 may receive four inputs IN[0] to IN[3], and may output two outputs OUT[0] and OUT[1] corresponding to the four inputs IN[0] to IN[3]. In one embodiment, in each of the four lookup tables LUT0 to LUT3, the number of inputs and the number of outputs are provided as an example for a 4-bit multiplication operation, and the embodiment is not limited thereto.

[0063] In each of the four lookup tables LUT0 to LUT3, the 0th output OUT[0] can be fed forward to the second input IN[2] of the next lookup table by delay "D" (hereinafter referred to as "feedforward operation FF"), and the first output OUT[1] can be fed back to the third input IN[3] of the current lookup table by delay "D" (hereinafter referred to as "feedback operation FB"). For example, the 0th output OUT[0] of the 0th lookup table LUT0 is provided to the second input IN[2] of the first lookup table LUT1 by delay "D". The first output OUT[1] of the 0th lookup table LUT0 is provided to the third input IN[3] of the 0th lookup table LUT0 by delay "D". The operations of the first lookup table LUT1 and the second lookup table LUT2 are similar to those of the 0th lookup table LUT0, and therefore, additional descriptions will be omitted to avoid redundancy and for brevity. The 0th output OUT[0] of the third lookup table LUT3 can be accumulated as the final output "y" by delay "D".

[0064] For a 4-bit multiplication operation, bits a3, a2, a1, and a0 of the bit string corresponding to the first operand may be sequentially provided to be input to the 0th input IN[0] of the four lookup tables LUT0 to LUT3, respectively. For a 4-bit multiplication operation, bits b3, b2, b1, and b0 of the bit string corresponding to the second operand may be sequentially provided to be input to the first input IN[1] of the four lookup tables LUT0 to LUT3, respectively.

[0065] A 4-bit multiplication operation can be performed by a structure of four lookup tables LUT0 to LUT3 connected as described above. In this case, the four lookup tables LUT0 to LUT3 can be connected as described above. Figure 3B is shown in .

[0066] For example, Figure 3BAs shown in , when the 0th input IN[0] to the third input IN[3] of the 0th lookup table LUT0 is {0000b}, the 0th output OUT[0] and the first output OUT[1] of the 0th lookup table LUT0 can be {10b}. When the 0th input IN[0] to the third input IN[3] of the 0th lookup table LUT0 is {0001b}, the 0th output OUT[0] and the first output OUT[1] of the 0th lookup table LUT0 can be {01b}. The outputs corresponding to the remaining combinations are shown in Figure 3B , and therefore, additional description will be omitted to avoid redundancy and for brevity.

[0067] When the 0th input IN[0] to the 3rd input IN[3] of each of the first lookup table LUT1, the second lookup table LUT2, and the third lookup table LUT3 is {0000b}, the 0th output OUT[0] and the first output OUT[1] of each of the first lookup table LUT1, the second lookup table LUT2, and the third lookup table LUT3 may be {00b}. When the 0th input IN[0] to the 3rd input IN[3] of each of the first lookup table LUT1, the second lookup table LUT2, and the third lookup table LUT3 is {0001b}, the 0th output OUT[0] and the first output OUT[1] of each of the first lookup table LUT1, the second lookup table LUT2, and the third lookup table LUT3 may be {10b}. The outputs corresponding to the remaining combinations are as follows Figure 3B , and therefore, additional description will be omitted to avoid redundancy and for brevity.

[0068] Can be referenced Figure 3A and Figure 3B The structure described here is used to perform a 4-bit multiplication operation. Figure 3C As shown in , it is assumed that a 4-bit multiplication operation is performed on "5×7". In this case, the first operand "A" can be 5 and can be represented by {0101b}. The second operand "B" can be 7 and can be represented by {0111b}. In this case, a0=0, a1=1, a2=0, a3=1, b0=0, b1=1, b2=1 and b3=1.

[0069] In the 0th cycle #0, the value of the bit a3 of the first operand "A" (i.e., 1) is provided to each of the 0th input IN[0] of the 0th lookup table LUT0 to the third lookup table LUT3. The bit value of the second operand "B" (i.e., 0, 1, 1, 1) is provided to the first input IN[1] of the 0th lookup table LUT0 to the third lookup table LUT3, respectively. The third input IN[3] of the 0th lookup table LUT0 is set to "1", and the remaining inputs of the 0th lookup table LUT0 are set to "0".

[0070] In this case, {1001b} is input to the 0th input IN[0] to the third input IN[3] of the 0th lookup table LUT0, and {1100b} is input to the 0th input IN[0] to the third input IN[3] of each of the first lookup table LUT1, the second lookup table LUT2, and the third lookup table LUT3. In response to the values ​​provided to the 0th input IN[0] to the third input IN[3], the 0th lookup table LUT0 may output {01b} as the 0th output OUT[0] and the first output OUT[1], and each of the first lookup table LUT1, the second lookup table LUT2, and the third lookup table LUT3 may output {10b} as the 0th output OUT[0] and the first output OUT[1].

[0071] In the first cycle #1, the value of the bit a2 of the first operand "A" (i.e., 0) is input to each of the 0th input IN[0] of the 0th lookup table LUT0 to the third lookup table LUT3. The 0th output OUT[0] of the 0th lookup table LUT0 may be fed forward to the second input IN[2] of the first lookup table LUT1, and the first output OUT[1] of the 0th lookup table LUT0 may be fed back to the third input IN[3] of the 0th lookup table LUT0. The 0th output OUT[0] of the first lookup table LUT1 may be fed forward to the second input IN[2] of the second lookup table LUT2, and the first output OUT[1] of the first lookup table LUT1 may be fed back to the third input IN[3] of the first lookup table LUT1. The 0th output OUT[0] of the second lookup table LUT2 may be fed forward to the second input IN[2] of the third lookup table LUT3, and the first output OUT[1] of the second lookup table LUT2 may be fed back to the third input IN[3] of the second lookup table LUT2. The 0th output OUT[0] of the third lookup table LUT3 may be accumulated as an output value, and the first output OUT[1] of the third lookup table LUT3 may be fed back to the third input IN[3] of the third lookup table LUT3.

[0072] In this case, {0001b} is input to the 0th input IN[0] to the third input IN[3] of the 0th lookup table LUT0; {0100b} is input to the 0th input IN[0] to the third input IN[3] of the first lookup table LUT1; {0110b} is input to the 0th input IN[0] to the third input IN[3] of the second lookup table LUT2; and {0110b} is input to the 0th input IN[0] to the third input IN[3] of the third lookup table LUT3. In response to the values ​​provided to the 0th input IN[0] to the third input IN[3], the 0th lookup table LUT0 may output {01b} as the 0th output OUT[0] and the first output OUT[1], the first lookup table LUT1 may output {00b} as the 0th output OUT[0] and the first output OUT[1], the second lookup table LUT2 may output {10b} as the 0th output OUT[0] and the first output OUT[1], and the third lookup table LUT3 may output {10b} as the 0th output OUT[0] and the first output OUT[1].

[0073] When the above operation is repeatedly performed a given number of times, the calculation result can be obtained by accumulating the 0th output OUT[0] of the third lookup table LUT3. Figure 3C As shown in , when the calculation using the 0th lookup table LUT0 to the third lookup table LUT3 is repeatedly performed 7 times (i.e., performed from the 0th cycle #0 to the sixth cycle #6), the accumulated value of the 0th output OUT[0] of the third lookup table LUT3 may be {0100011b}. The accumulated value {0100011b} may indicate the result value of the multiplication operation of "5×7" (i.e., 35).

[0074] FIG. 3A to FIG. 3C The above paragraphs describe an example in which the calculation is performed 7 times (i.e., from the zeroth cycle #0 to the sixth cycle #6). However, the embodiments are not limited thereto. In one embodiment, the given number of times the calculation operation is repeated can be predetermined based on the number of digits of the calculation result. For example, the maximum number of digits of the result that can be obtained by a 4-bit multiplication operation can be "8". Therefore, the maximum number of times that the calculation can be performed for a 4-bit multiplication operation can be 8 times. However, the embodiments are not limited thereto. For example, the given number of iterations can be changed or modified differently according to the type / format of the operand or the calculation result value.

[0075] Reference FIG. 3A to FIG. 3CThe described bit serial calculation based on the lookup table for 4-bit multiplication is provided as an example, but the embodiment is not limited thereto. For example, the bit serial calculation based on the lookup table can support various calculations by modifying the mode of the lookup table differently or by the combination of various lookup tables. The range (or size) of the operand can be changed differently by adjusting the number of lookup tables participating in feedforward or feedback or the number of times the calculation is repeated. The position of the bit to be fed back or fed forward for each lookup table or the number of bits to be fed back or fed forward for each lookup table is not limited, and the calculation type or range of the operand can be changed differently by adjusting the position of the bit to be fed back or fed forward for each lookup table or the number of bits to be fed back or fed forward for each lookup table.

[0076] Figure 4A and Figure 4B It is used for describing according to the embodiment Figure 1 Components that are not necessary for describing the computing operation of the memory device 100 are omitted for convenience of description.

[0077] Reference Figure 1 , Figure 4A and Figure 4B , the column calculation control circuit 170 may include a column register REG_COL. The column register REG_COL may be configured to generate a column calculation selection signal CCSL based on an input operand.

[0078] The memory cell array 110 may include a cell array CAR, a bit line sense amplifier BLSA, a column selection circuit CSC, and an input / output sense amplifier IOSA. The cell array CAR may include a plurality of memory cells connected to a plurality of word lines WL0 to WLn. The plurality of memory cells may store a plurality of calculation output patterns LUT_SET. In one embodiment, the plurality of calculation output patterns LUT_SET may refer to data sets for supporting various calculation operations. For example, the plurality of calculation output patterns LUT_SET may include data sets corresponding to reference Figure 3B The data patterns corresponding to the output values ​​of the described lookup tables LUT0 to LUT3 will be described in detail with reference to the accompanying drawings.

[0079] The bit line sense amplifier BLSA may be connected to a plurality of memory cells of the cell array CAR through a plurality of bit lines BL. The bit line sense amplifier BLSA may be configured to sense voltage changes of the plurality of bit lines BL and output the sensed voltage changes.

[0080] In response to the column calculation selection signal CCSL, the column selection circuit CSC may select some of the voltage changes output from the bit line sense amplifier BLSA to be output through the local input / output line LIO. The local input / output line LIO may be connected to the global input / output line GIO.

[0081] The input / output sense amplifier IOSA may sense changes in the global input / output line GIO. Some of the signals (or bits) sensed by the input / output sense amplifier IOSA may be fed back to the column register REG_COL, and other of the signals (or bits) sensed by the input / output sense amplifier IOSA may be fed forward to another column register REG_COL different from the column register REG_COL.

[0082] Bit-serial computation based on a lookup table can be done by Figure 4A For example, for ease of description, assume that Figure 4A The construction shown in corresponds to the reference Figure 3A In this case, one of the plurality of calculation output patterns LUT_SET (eg, a calculation output pattern stored in a memory cell connected to the 0th word line WL0) may include Figure 3B The input operand may correspond to a0, a1, a2, a3, or b0.

[0083] In this case, when the 0th word line WL0 is activated, one calculation output pattern LUT_SET may be provided to the column selection circuit CSC through the bit line sense amplifier BLSA. The column selection circuit CSC may select and output a portion of the one calculation output pattern LUT_SET in response to the column calculation selection signal CCSL. In this case, Figure 4A The column calculation selection signal CCSL shown in may correspond to the 0th input IN[0] to the third input IN[3], and the value output by the column selection circuit CSC may be the 0th output OUT[0] and the first output OUT[1] corresponding to the 0th input IN[0] to the third input IN[3]. In detail, when the column calculation selection signal CCSL is {0000b}, the value output from the column selection circuit CSC may be {10b}; when the column calculation selection signal CCSL is {0001b}, the value output from the column selection circuit CSC may be {01b}.

[0084] The value output from the column selection circuit CSC may be provided to the global input / output line GIO through the local input / output line LIO. The input / output sense amplifier IOSA may sense a voltage change of the global input / output line GIO and may store an output signal. A portion of the output signal sensed by the input / output sense amplifier IOSA may be fed back to the column register REG_COL, and the remaining portion of the output signal sensed by the input / output sense amplifier IOSA may be fed forward to another column register. The portion FF fed forward from the input / output sense amplifier IOSA and the portion FB fed back from the input / output sense amplifier IOSA may be used to generate the column calculation selection signal CCSL in the next iteration.

[0085] Reference Figure 4A The structure described is a structure corresponding to one channel. However, the embodiment is not limited thereto. One memory bank of the memory device 100 may include a plurality of channels, and various types of calculations may be supported by the plurality of channels. For example, Figure 4B As shown in , the memory cell array 110 may include a plurality of cell arrays CAR[0] to CAR[3]. The plurality of cell arrays CAR[0] to CAR[3] may store a plurality of calculation output patterns LUT_SET0 to LUT_SET3, respectively. In one embodiment, the plurality of calculation output patterns LUT_SET0 to LUT_SET3 may be changed or modified differently according to the kind of calculation performed in the memory device 100.

[0086] The plurality of cell arrays CAR[0] to CAR[3] may be connected to the plurality of bit line sense amplifiers BLSA[0] to BLSA[3], respectively. The plurality of bit line sense amplifiers BLSA[0] to BLSA[3] may be connected to the plurality of column selection circuits CSC[0] to CSC[3], respectively. The plurality of column selection circuits CSC[0] to CSC[3] may output output signals OUT0 to OUT3, respectively, in response to the plurality of column calculation selection signals CCSL0 to CCSL3.

[0087] The plurality of input / output sense amplifiers IOSA[0] to IOSA[3] may be configured to amplify a plurality of output signals OUT0 to OUT3 output from a plurality of column selection circuits CSC[0] to CSC[3] through a plurality of global input / output lines GIO1 to GIO3 and output the amplified signals.

[0088] Some of the signals output from the plurality of input / output sense amplifiers IOSA[0] to IOSA[3] may be fed back (FB) or fed forward (FF) to the plurality of column registers REG_COL[0] to REG_COL[3].

[0089] In one embodiment, referring to Figure 2Aand Figure 2B In the read operation of the memory device 100 described above, a column selection signal CSL may be generated based on a column address, and the same column selection signal CSL may be provided to a plurality of column selection circuits CSC[0] to CSC[3]. Figure 4A and Figure 4B In the described computing operation of the memory device 100 , different or independent column computing select signals CCSL0 to CCSL3 may be provided to the plurality of column select circuits CSC[ 0 ] to CSC[ 3 ], respectively.

[0090] For example, the column calculation control circuit 170 may include a first input register REG_IN1 , a second input register REG_IN2 , a preset register REG_PRE, an output register REG_OUT, and a plurality of column registers REG_COL[ 0 ] to REG_COL[ 3 ].

[0091] The first input register REG_IN1 may be configured to store or set information about a first input operand. The second input register REG_IN2 may be configured to store or set information about a second input operand. The preset register REG_PRE may be configured to store or set initial values ​​of a plurality of column registers REG_COL[0] to REG_COL[3] in an initialization phase of a calculation operation of the memory device 100. The output register REG_OUT may be configured to accumulate calculation results. In one embodiment, the first input register REG_IN1 and the output register REG_OUT may be shift registers.

[0092] The plurality of column registers REG_COL[0] to REG_COL[3] may be configured to generate a plurality of column calculation selection signals CCSL0 to CCSL3, respectively, based on the set values. In one embodiment, each of the column calculation selection signals CCSL0 to CCSL3 may be used as an input to a lookup table in a bit serial calculation based on a lookup table. For example, each of the plurality of column calculation selection signals CCSL0 to CCSL3 may correspond to a reference FIG. 3A to FIG. 3C The multiple inputs IN[0] to IN[3] are described. However, the embodiment is not limited thereto. For example, the size and configuration of the column calculation selection signals CCSL0 to CCSL3 may be changed and modified differently according to the calculation type, the structure of the calculation output mode LUT_SET, the size of the operand (e.g., the number of bits), etc. Figures 5 to 6E Detailed description based on Figure 4B The operations performed on the structure.

[0093] According to the above structure, a bit serial calculation based on a lookup table can be performed by a read operation repeatedly performed on the memory device 100. A memory device that provides a related art calculation function (e.g., a process-in-memory (PIM)) provides a calculation function by using an arithmetic processor dedicated to calculation operations in a related art memory device or an arithmetic logic unit (ALU) dedicated to calculation operations in a related art memory device.

[0094] In the case of having an arithmetic processor or ALU in a memory device in the prior art storage device, the arithmetic processor or arithmetic logic unit takes time to perform calculations, and power consumption increases. In addition, the implementation of a separate arithmetic processor or arithmetic logic unit leads to an increase in chip size.

[0095] In contrast, according to various embodiments of the present disclosure, when internal read operations are repeatedly performed in the memory device 100, various computing functions can be supported without a separate arithmetic processor or arithmetic logic unit. Therefore, a memory device that provides computing functions while improving performance and reducing costs is provided.

[0096] Figure 5 It is used to describe the embodiment according to Figure 1 Flowchart of the computing operation of the memory device 100. Figure 1 , Figure 4B and Figure 5 In operation S110, the memory device 100 may load an input operand. For example, the memory device 100 may receive an input operand from an external device (e.g., a memory controller). In some embodiments, the memory device 100 may read an input operand stored in a memory cell under the control of the external device. The memory device 100 may store or set the input operand in the first input register REG_IN1 and the second input register REG_IN2.

[0097] In operation S120, the memory device 100 may set the column register based on the input operand. Figure 4B As shown in , the memory device 100 may set a plurality of column registers REG_COL[0] to REG_COL[3] based on input operands loaded into the first input register REG_IN1 and the second input register REG_IN2. In one embodiment, when the plurality of column registers REG_COL[0] to REG_COL[3] are set, a plurality of column calculation selection signals CCSL0 to CCSL3 may be generated.

[0098] In operation S130, the memory device 100 may perform an internal read operation. For example, the memory device 100 may activate a selected word line. When the selected word line is activated, the calculation output patterns LUT_SET0 to LUT_SET3 stored in the memory cells connected to the selected word line may be provided to a plurality of bit line sense amplifiers BLSA[0] to BLSA[3]. A plurality of column selection circuits CSC[0] to CSC[3] may output a plurality of output signals OUT0 to OUT3, respectively, in response to a plurality of column calculation selection signals CCSL0 to CCSL3. A plurality of input / output sense amplifiers IOSA[0] to IOSA[3] may sense a plurality of output signals OUT0 to OUT3. In one embodiment, the plurality of output signals OUT0 to OUT3 may be signals outputted from a plurality of column selection circuits CSC[0] to CSC[3], respectively. As described above, the memory device 100 may perform an internal read operation for a selected word line based on a plurality of column calculation selection signals CCSL0 to CCSL3 generated by a plurality of column registers REG_COL[0] to REG_COL[3].

[0099] In operation S140, the memory device 100 may update the plurality of column registers REG_COL[0] to REG_COL[3] and the output register REG_OUT based on the result of the internal read operation. For example, through the internal read operation in operation S130, the plurality of input / output sense amplifiers IOSA[0] to IOSA[3] may be in a state of storing the plurality of output signals OUT0 to OUT3. The plurality of output signals OUT0 to OUT3 stored in the plurality of input / output sense amplifiers IOSA[0] to IOSA[3] may be fed back (FB) and fed forward (FF) to the plurality of column registers REG_COL[0] to REG_COL[3], and one output signal (e.g., OUT3) of the plurality of output signals OUT0 to OUT3 may be accumulated in the output register REG_OUT.

[0100] In detail, a portion of the 0th output signal OUT0 stored in the 0th input / output sense amplifier IOSA[0] is fed back to the 0th column register REG_COL[0], and the remaining portion of the 0th output signal OUT0 is fed forward to the first column register REG_COL[1]. A portion of the first output signal OUT1 stored in the first input / output sense amplifier IOSA[1] is fed back to the first column register REG_COL[1], and the remaining portion of the first output signal OUT1 is fed forward to the second column register REG_COL[2]. A portion of the second output signal OUT2 stored in the second input / output sense amplifier IOSA[2] is fed back to the second column register REG_COL[2], and the remaining portion of the second output signal OUT2 is fed forward to the third column register REG_COL[3]. A portion of the third output signal OUT3 stored in the third input / output sense amplifier IOSA[3] is fed back to the third column register REG_COL[3], and the remaining portion of the third output signal OUT3 is accumulated.

[0101] In operation S150, the memory device 100 may determine whether the number of internal read operations is a reference value (i.e., a given number of times). In some embodiments, the reference value may be a maximum value as described above. In one embodiment, the reference number of internal read operations may be set by an external device (e.g., a memory controller). In some embodiments, the reference number of internal read operations may be determined based on the type of target calculation, the size of the operand, etc. When the number of internal read operations is not the reference value (i.e., a given number of times) (operation S150, no), the memory device 100 performs operation S130 again.

[0102] When the number of internal read operations is a reference value (i.e., a given number of times) (operation S150, yes), in operation S160, the memory device 100 may output a calculation result. For example, when the internal read operation is repeatedly performed, the bit value may be accumulated in the output register REG_OUT. The bit value accumulated in the output register REG_OUT may correspond to the calculation result, and the memory device 100 may output the accumulated bit value of the output register REG_OUT as the calculation result.

[0103] FIG. 6A to FIG. 6E is used to describe according to some embodiments Figure 5 For ease of description, it is assumed that the memory device 100 performs the calculation operation of the memory device 100 with reference to FIG. 3A to FIG. 3C The calculation operation described is (ie, 4-bit multiplication operation: "5×7"). However, the embodiments are not limited thereto.

[0104] First, if Fig. 6AAs shown in , the first input operand (ie, 5={0101b}) is set to the first input register REG_IN1, and the second input operand (ie, 7={0111b}) is set to the second input register REG_IN2.

[0105] The least significant bit (LSB) (e.g., a3) (i.e., 1) of the first input register REG_IN1 is set to the 0th input value of each of the 0th column register REG_COL[0] to the third column register REG_COL[3]. The most significant bit (MSB) (e.g., b0) (i.e., 0) of the second input register REG_IN2 is set to the first input value of the 0th column register REG_COL[0], the second MSB (e.g., b1) (i.e., 1) is set to the first input value of the first column register REG_COL[1], the second LSB (e.g., b2) (i.e., 1) is set to the first input value of the second column register REG_COL[2], and the least significant bit (LSB) (e.g., b3) (i.e., 1) is set to the first input value of the third column register REG_COL[3]. The preset register REG_PRE sets the third input value of the 0th column register REG_COL[0] to "1", and sets the remaining input values ​​of the 0th column register REG_COL[0] to the third column register REG_COL[3] to "0".

[0106] In this case, the value set to the 0th column register REG_COL[0] is {1001b}, the value set to the first column register REG_COL[1] is {1100b}, the value set to the second column register REG_COL[2] is {1100b}, and the value set to the third column register REG_COL[3] is {1100b}.

[0107] Next, refer to Figure 6B , when the selected word line WL is activated, the 0th to 3rd calculation output patterns LUT_SET0 to LUT_SET3 stored in the 0th to 3rd cell arrays CAR[0] to CAR[3] may be output through the bit lines BL. The 0th to 3rd bit line sense amplifiers BLSA[0] to BLSA[3] may sense and output the 0th to 3rd calculation output patterns LUT_SET0 to LUT_SET3 through the bit lines BL.

[0108] In response to the 0th column calculation selection signal CCSL0 to the third column calculation selection signal CCSL3, the 0th column calculation selection signal CCSL0 to the third column selection circuit CSC[3] may output some of the outputs of the 0th bit line sense amplifier BLSA[0] to the third bit line sense amplifier BLSA[3] as the 0th output signal OUT0 to the third output signal OUT3. For example, the 0th bit line sense amplifier BLSA[0] to the third bit line sense amplifier BLSA[3] may output the 0th calculation output pattern LUT_SET0 to the third calculation output pattern LUT_SET3, respectively. In this case, the 0th calculation output pattern LUT_SET0 may correspond to Figure 3B The output of the 0th lookup table LUT0, and the first calculation output mode, the second calculation output mode, and the third calculation output mode LUT_SET1 to LUT_SET3 may correspond to the outputs of the first lookup table LUT1, the second lookup table LUT2, and the third lookup table LUT3.

[0109] In this case, in response to the 0th column calculation selection signal CCSL0 of {1001b}, the 0th column selection circuit CSC[0] may output {01b} as the 0th output signal OUT0. In response to the first column calculation selection signal CCSL1 of {1100b}, the first column selection circuit CSC[1] may output {10b} as the first output signal OUT1. In response to the second column calculation selection signal CCSL2 of {1100b}, the second column selection circuit CSC[2] may output {10b} as the second output signal OUT2. In response to the third column calculation selection signal CCSL3 of {1100b}, the third column selection circuit CSC[3] may output {10b} as the third output signal OUT3.

[0110] Next, if Figure 6CAs shown in , the 0th output signal OUT0 to the third output signal OUT3 sensed by the 0th input / output sense amplifier IOSA[0] to the third input / output sense amplifier IOSA[3] may be fed back or fed forward to the 0th column register REG_COL[0] to the third column register REG_COL[3]. For example, the least significant bit (i.e., "1") of the 0th output signal OUT0 of {01b} may be fed back to the third input of the 0th column register REG_COL[0], and the most significant bit (i.e., "0") may be fed forward to the second input of the first column register REG_COL[1]. The least significant bit (i.e., "0") of the first output signal OUT1 of {10b} may be fed back to the third input of the first column register REG_COL[1], and the most significant bit (i.e., "1") may be fed forward to the second input of the second column register REG_COL[2]. The least significant bit (i.e., "0") of the second output signal OUT2 of {10b} may be fed back to the third input of the second column register REG_COL[2], and the most significant bit (i.e., "1") may be fed forward to the second input of the third column register REG_COL[3]. The least significant bit (i.e., "0") of the third output signal OUT3 of {10b} may be fed back to the third input of the third column register REG_COL[3], and the most significant bit (i.e., "1") may be accumulated in the output register REG_OUT.

[0111] The 0th input IN[0] of the 0th to third column registers REG_COL[0] to REG_COL[3] may be updated based on the second LSB (eg, a2) (ie, “0”) of the first input operand output from the first input register REG_IN1.

[0112] In this case, the 0th column register REG_COL[0] is set to {0001b}, the first column register REG_COL[1] is set to {0100b}, the second column register REG_COL[2] is set to {0110b}, and the third column register REG_COL[3] is set to {0110b}.

[0113] Afterwards, if Fig.6D As shown in , when the selected word line WL is activated, the 0th to 3rd calculation output patterns LUT_SET0 to LUT_SET3 stored in the 0th to 3rd cell arrays CAR[0] to CAR[3] of the memory device 100 may be output through the bit lines BL. The 0th to 3rd bit line sense amplifiers BLSA[0] to BLSA[3] may sense and output the 0th to 3rd calculation output patterns LUT_SET0 to LUT_SET3 through the bit lines BL.

[0114] In response to the 0th to the third column calculation selection signal CCSL0 to CCSL3 , the 0th to the third column calculation selection circuits CSC[ 0 ] to CSC[ 3 ] may output the 0th to the third output signals OUT0 to OUT3 .

[0115] For example, in response to the 0th column calculation selection signal CCSL0 of {0001b}, the 0th column selection circuit CSC[0] may output the 0th output signal OUT0 of {01b}. In response to the first column calculation selection signal CCSL1 of {0100b}, the first column selection circuit CSC[1] may output the first output signal OUT1 of {00b}. In response to the second column calculation selection signal CCSL2 of {0110b}, the second column selection circuit CSC[2] may output the second output signal OUT2 of {10b}. In response to the third column calculation selection signal CCSL3 of {0110b}, the third column selection circuit CSC[3] may output the third output signal OUT3 of {10b}.

[0116] Next, if Fig. 6E As shown in , the 0th output signal OUT0 to the third output signal OUT3 sensed by the 0th input / output sense amplifier IOSA[0] to the third input / output sense amplifier IOSA[3] may be fed back or fed forward to the 0th column register REG_COL[0] to the third column register REG_COL[3]. The configuration in which the 0th output signal OUT0 to the third output signal OUT3 are fed back or fed forward to the 0th column register REG_COL[0] to the third column register REG_COL[3] is similar to the configuration in reference to Figure 6C The configuration is described, therefore, additional description will be omitted to avoid redundancy and for brevity.

[0117] As described above, the memory device 100 can perform an internal read operation on a calculation output mode corresponding to a target calculation based on a plurality of column calculation selection signals generated from a plurality of column registers, and can update the plurality of column registers based on the result of the internal read operation. The memory device 100 can perform a target calculation with respect to an input operand by repeatedly performing the above operation.

[0118] Therefore, the calculation operation can be performed within the memory device that does not include a separate arithmetic processor or a separate arithmetic logic unit. In addition, since the calculation operation is performed by repeatedly reading a plurality of calculation output patterns stored in the memory unit, various types of calculations can be supported.

[0119] Figure 7 According to some embodiments, Figure 1 4 to 5 are diagrams showing examples of calculation output modes of the memory device 100. Fig. 6EA case where each of the column calculation selection signals CCSL0 to CCSL3 is a 4-bit signal and each of the 0th to third output signals OUT0 to OUT3 is a 2-bit signal is described However, the embodiment is not limited thereto.

[0120] For example, one column selection circuit CSC may be configured to receive 512 (=2 6 ×8) signals and output eight signals among 512 signals. In this case, the column calculation selection signal CCSL generated by the column register REG_COL may be a 6-bit signal, and the output signal sensed by the input / output sense amplifier IOSA may be an 8-bit signal.

[0121] That is to say, Figure 7 The output values ​​shown in (e.g., x00, x01, ..., x636, and x637) may be stored in a memory cell connected to a word line (e.g., a first word line) among a plurality of memory cells included in the cell array CAR. When an internal read operation is performed for the first word line, an output signal corresponding to the column calculation selection signal CCSL may be output. For example, when the column calculation selection signal CCSL is {000000b}, the output signal of {x00, x01, x02, x03, x04, x05, x06, x07 b} may be output by an internal read operation performed for the first word line; when the column calculation selection signal CCSL is {000001b}, the output signal of {x10, x11, x12, x13, x14, x15, x16, x17 b} may be output by an internal read operation performed for the first word line.

[0122] In one embodiment, the size of the input value and the output value of the lookup table may be determined based on the structure of the memory device 100, the memory cell array 110, or the cell array CAR. For example, the column selection circuit CSC may be implemented as a selection 2 n One of the signal sets, and one signal set may include "m" bits. In this case, the column calculation selection signal CCSL may include "n" bits, and the output signal may include "m" bits. In this way, the calculation output pattern LUT_SET stored in the cell array CAR may correspond to a lookup table that provides an m-bit output with respect to an n-bit input. Wherein, n and m may be positive integers.

[0123] Fig. 8A and Figure 8B According to some embodiments, Figure 1 For convenience of description, components that are not necessary for describing the computing operation of the memory device 100 are omitted for brevity.

[0124] In one embodiment, referring to FIG. 3A to FIG. 7 A lookup table-based bit serial calculation of the memory device 100 is described. However, the embodiment is not limited thereto, and the memory device 100 may perform a lookup table-based calculation.

[0125] For example, Figure 8B As shown in , the column register REG_COL may generate a column calculation selection signal CCSL based on an input operand. The memory cell array 110 may include a cell array CAR, a bit line sense amplifier BLSA, a column selection circuit CSC, and an input / output sense amplifier IOSA. The operations of the column register REG_COL, the cell array CAR, the bit line sense amplifier BLSA, the column selection circuit CSC, and the input / output sense amplifier IOSA are similar to the operations of the column register REG_COL, the cell array CAR, the bit line sense amplifier BLSA, the column selection circuit CSC, and the input / output sense amplifier IOSA described above, and therefore, additional descriptions will be omitted to avoid redundancy and for brevity.

[0126] exist Fig. 8A In the embodiment of the present invention, the memory device 100 may output the output signal OUT of the input / output sense amplifier IOSA as the calculation result without repeatedly performing the internal read operation. In this case, the memory device 100 may perform the internal read operation only once and may output the calculation result based on the lookup table.

[0127] Fig. 8A The calculation of the cell array (CAR) unit can be extended to the memory cell array (110) or the memory cell. For example, Figure 8B As shown in , the column calculation control circuit 160-1 may include a first input register REG_IN1, a second input register REG_IN2, a preset register REG_PRE, an output register REG_OUT, and a plurality of column registers REG_COL[0] to REG_COL[3]. The first input register REG_IN1, the second input register REG_IN2, the preset register REG_PRE, the output register REG_OUT, and the plurality of column registers REG_COL[0] to REG_COL[3] are similar to the first input register REG_IN1, the second input register REG_IN2, the preset register REG_PRE, the output register REG_OUT, and the plurality of column registers REG_COL[0] to REG_COL[3] described above, and therefore, additional description will be omitted to avoid redundancy and for brevity.

[0128] The memory cell array 110 may include a plurality of cell arrays CAR[0] to CAR[3]. The plurality of cell arrays CAR[0] to CAR[3] may store a plurality of calculation output patterns LUT_SET0 to LUT_SET3, respectively. The plurality of cell arrays CAR[0] to CAR[3] may be connected to a plurality of bit line sense amplifiers BLSA[0] to BLSA[3], respectively. The plurality of bit line sense amplifiers BLSA[0] to BLSA[3] may be connected to a plurality of column selection circuits CSC[0] to CSC[3], respectively. The plurality of column selection circuits CSC[0] to CSC[3] may output output signals OUT0 to OUT3, respectively, in response to a plurality of column calculation selection signals CCSL0 to CCSL3.

[0129] The plurality of input / output sense amplifiers IOSA[0] to IOSA[3] may be configured to amplify the plurality of output signals OUT0 to OUT3 output from the plurality of column selection circuits CSC[0] to CSC[3] through the plurality of global input / output lines GIO1 to GIO3 and output the amplified signals. The 0th output OUT0 to the third output OUT3 from the plurality of input / output sense amplifiers IOSA[0] to IOSA[3] may be provided to the output register REG_OUT.

[0130] As described above, the memory device 100 may perform a lookup table based calculation through one internal read operation.

[0131] Fig. 9 is a block diagram showing a memory device according to an embodiment. In one embodiment, for simplicity, Fig. 9 Components that are not necessary for describing the structure of the memory device 200 having a computing function are omitted.

[0132] Reference Fig. 9 , the memory device 200 may include a memory cell array 210, an input / output (I / O) circuit 260, and a plurality of cluster computing control circuits 280 to 283. In one embodiment, the memory device 200 may also include various components such as a CA buffer, an address decoder, a command decoder, and a control logic circuit.

[0133] The memory cell array 210 may include a plurality of memory banks BG0 / BA0 to BG3 / BA3. Each of the plurality of memory banks BG0 / BA0 to BG3 / BA3 may be a reference Figures 1 to 8B The memory cell array 110 or a plurality of cell arrays CAR, a plurality of bit line sense amplifiers, a plurality of column selection circuits, and input / output sense amplifiers are described.

[0134] In one embodiment, each of the plurality of memory banks BG0 / BA0 to BG3 / BA3 may include a reference Figures 1 to 8B That is, each of the plurality of memory banks BG0 / BA0 to BG3 / BA3 may be configured to perform a lookup table-based bit serial calculation or a lookup table-based calculation.

[0135] In one embodiment, when a plurality of memory banks BG0 / BA0 to BG3 / BA3 perform independent calculation operations, the range (or size) of operands may be limited according to the structure of the plurality of memory banks BG0 / BA0 to BG3 / BA3. For example, it is assumed that each of the plurality of memory banks BG0 / BA0 to BG3 / BA3 includes 16 channels. One channel may indicate a unit of data output in response to one column calculation selection signal. That is, one channel may include a unit of data outputted in response to one column calculation selection signal. Figure 4A The described configuration realizes the cell array CAR, the bit line sense amplifier BLSA, the column selection circuit CSC and the input / output sense amplifier IOSA.

[0136] When each of the plurality of memory banks BG0 / BA0 to BG3 / BA3 includes 16 channels, the range of operands that can be calculated in a single memory bank may be limited by the number of channels. In order to increase the range of operands that can be calculated, it is necessary to increase the size of the column calculation selection signal CCSL or the size of the output signal OUT of the column selection circuit CSC. However, the size of the column calculation selection signal CCSL or the size of the output signal OUT of the column selection circuit CSC may be limited according to the structure of the memory device 100, and therefore, the range of operands that can be calculated in a single memory bank may be limited to a specific range.

[0137] exist Fig. 9 In an embodiment of the present invention, the memory device 200 may perform computing operations in units of clusters. A cluster may be a unit in which a plurality of memory banks are included. The 0th cluster may include the 0th memory bank BA0 of the 0th memory bank group BG0, the 0th memory bank BA0 of the first memory bank group BG1, the 0th memory bank BA0 of the second memory bank group BG2, and the 0th memory bank BA0 of the third memory bank group BG3. The first cluster may include the first memory bank BA1 of the 0th memory bank group BG0, the first memory bank BA1 of the first memory bank group BG1, the first memory bank BA1 of the second memory bank group BG2, and the first memory bank BA1 of the third memory bank group BG3. The second cluster may include the second memory bank BA2 of the 0th memory bank group BG0, the second memory bank BA2 of the first memory bank group BG1, the second memory bank BA2 of the second memory bank group BG2, and the second memory bank BA2 of the third memory bank group BG3. The third cluster may include the third memory bank BA3 of the 0th memory bank group BG0 , the third memory bank BA3 of the first memory bank group BG1 , the third memory bank BA3 of the second memory bank group BG2 , and the third memory bank BA3 of the third memory bank group BG3 .

[0138] The 0th cluster computing control circuit 280 may control computing operations of the memory banks included in the 0th cluster. The first cluster computing control circuit 281 may control computing operations of the memory banks included in the first cluster. The second cluster computing control circuit 282 may control computing operations of the memory banks included in the second cluster. The third cluster computing control circuit 283 may control computing operations of the memory banks included in the third cluster.

[0139] In the following, for the convenience of description, the computing operation of the cluster will be described with reference to the 0th cluster and the 0th cluster computing control circuit 280 .

[0140] A feedback operation FB and a feedforward operation FF may be performed between column calculation control circuits of memory banks included in the 0th cluster under the control of the 0th cluster calculation control circuit 280. In detail, a feedback operation FB and a feedforward operation FF may be performed between a column calculation control circuit of the 0th memory bank BA0 of the 0th memory bank group BG0 and a column calculation control circuit of the 0th memory bank BA0 of the first memory bank group BG1. A feedback operation FB and a feedforward operation FF may be performed between a column calculation control circuit of the 0th memory bank BA0 of the first memory bank group BG1 and a column calculation control circuit of the 0th memory bank BA0 of the second memory bank group BG2. A feedback operation FB and a feedforward operation FF may be performed between a column calculation control circuit of the 0th memory bank BA0 of the second memory bank group BG2 and a column calculation control circuit of the 0th memory bank BA0 of the third memory bank group BG3.

[0141] In one embodiment, the 0th cluster calculation control circuit 280 may control the column calculation control circuit included in the memory bank of the 0th cluster based on the 0th file register REF_F0 included in the input / output circuit 260. For example, the 0th file register REF_F0 may include information about the input operand and preset information. The 0th cluster calculation control circuit 280 may set the input operand and the preset information to the column calculation control circuit included in the memory bank of the 0th cluster based on the 0th file register REF_F0.

[0142] In one embodiment, when the storage banks of the 0th cluster perform a computing operation together, the computing unit can be expanded. For example, assume that the operand that can be calculated in a single storage bank is a 16-bit operand. In this case, when the four storage banks of the 0th cluster perform a computing operation together, the size of the operand that can be calculated can be expanded to 64 bits (=16×4). The computing operation of the cluster unit will be described in detail with reference to the following drawings.

[0143] exist Fig. 9In an embodiment of the present invention, the input / output circuit 260 may include a 0th file register REG_F0 to a 3rd file register REG_F3. The 0th file register REG_F0 to the 3rd file register REG_F3 may be configured to store input operands and preset information used by the 0th cluster computing control circuit 280 to the 3rd cluster computing control circuit 283. An embodiment in which the 0th file register REG_F0 to the 3rd file register REG_F3 are accessed by the 0th cluster computing control circuit 280 to the 3rd cluster computing control circuit 283 is shown, but the embodiment is not limited thereto. For example, the 0th file register REG_F0 to the 3rd file register REG_F3 may be shared by the 0th cluster computing control circuit 280 to the 3rd cluster computing control circuit 283.

[0144] Fig.10 and Fig.11 Is used to describe Fig. 9 FIG. 2 is a diagram of a computing operation of a cluster of memory devices 200. For ease of description, components that are not necessary for describing the computing operation of the cluster units are omitted for brevity.

[0145] Reference Fig. 9 , Fig.10 and Fig.11 , each of the 0th memory bank BA0 of the first memory bank group BG1 and the 0th memory bank BA0 of the second memory bank group BG2 may include a plurality of cell arrays CAR, a plurality of bit line sense amplifiers BLSA, a plurality of column selection circuits CSC, a plurality of input / output sense amplifiers IOSA, and a column calculation control circuit. The construction of each of the 0th memory bank BA0 of the first memory bank group BG1 and the 0th memory bank BA0 of the second memory bank group BG2 is similar to that of the reference FIG. 3A to FIG. 8A The configuration described herein, and therefore, additional description will be omitted to avoid redundancy and for the sake of brevity.

[0146] In one embodiment, the memory banks BG0 / BA0, BG1 / BA0, BG2 / BA0, and BG3 / BA0 included in the 0th cluster may perform a calculation operation together. In this case, an input operand may be input to the column calculation control circuits of the memory banks BG0 / BA0, BG1 / BA0, BG2 / BA0, and BG3 / BA0 included in the 0th cluster, and a feedback operation FB and a feedforward operation FF may be performed between the column calculation control circuits of the memory banks BG0 / BA0, BG1 / BA0, BG2 / BA0, and BG3 / BA0 included in the 0th cluster.

[0147] In detail, Fig.11As shown in , the 0th memory bank BA0 of the first memory bank group BG1 may include a column calculation control circuit 271. The column calculation control circuit 271 may include four column registers REG_COL[0] to REG_COL[3], a first input register REG_IN1, a second input register REG_IN2, a preset register REG_PRE, and an output register REG_OUT. The operation of the column calculation control circuit 271 is similar to the operation of the column calculation control circuit described above, and therefore, additional description will be omitted to avoid redundancy and for brevity.

[0148] In one embodiment, when computing operations are performed in clusters, the size of the input operands may be increased. FIG. 4A to FIG. 6E As described above, it is assumed that a 4-bit multiplication operation is performed by a calculation operation of a single memory bank. In this case, each of the four column registers REG_COL[0] to REG_COL[3], the first input register REG_IN1, and the second input register REG_IN2 can be implemented to store four bits. When a calculation operation is performed in a cluster including four memory banks, the number of bits of the operand can be increased to 16 (=4×4). In this case, the 16-bit operand is divided into four 4-bit operands, and the divided operands can be set to the column calculation control circuits of the four memory banks respectively.

[0149] Thereafter, when a calculation operation is performed in units of clusters, the column calculation control circuit 271 performs a feedforward operation FF so that some of the bits from the last input / output sense amplifier are provided to the first column register of the next memory bank. The column calculation control circuit of the last memory bank performs a feedback operation FB so that some of the bits from the last input / output sense amplifier are provided to the output register of the previous memory bank. For example, it is assumed that a calculation operation is performed in the order of the 0th memory bank BA0 of the 0th memory bank group BG0, the 0th memory bank BA0 of the first memory bank group BG1, the 0th memory bank BA0 of the second memory bank group BG2, and the 0th memory bank BA0 of the third memory bank group BG3. In this case, some of the bits of the last input / output sense amplifier of the 0th memory bank BA0 of the 0th memory bank group BG0 are provided to the first column register of the 0th memory bank BA0 of the first memory bank group BG1, some of the bits of the last input / output sense amplifier of the 0th memory bank BA0 of the first memory bank group BG1 are provided to the first column register of the 0th memory bank BA0 of the second memory bank group BG2, and some of the bits of the last input / output sense amplifier of the 0th memory bank BA0 of the third memory bank group BG3 are fed back (FB) to the output register of the 0th memory bank BA0 of the 0th memory bank group BG0, the 0th memory bank BA0 of the first memory bank group BG1 or the 0th memory bank BA0 of the second memory bank group BG2. However, the embodiments are not limited thereto. In one embodiment, some of the bits of the last input / output sense amplifier of the 0th memory bank BA0 of the third memory bank group BG3 are fed back to the output register of the 0th memory bank BA0 of the second memory bank group BG2, some of the bits of the last input / output sense amplifier of the 0th memory bank BA0 of the second memory bank group BG2 are fed back to the output register of the 0th memory bank BA0 of the first memory bank group BG1, and some of the bits of the last input / output sense amplifier of the 0th memory bank BA0 of the first memory bank group BG1 are fed back to the output register of the 0th memory bank BA0 of the 0th memory bank group BG0.

[0150] As described above, the memory device 200 may perform a computing operation in units of clusters including a plurality of memory banks. In a computing operation of a memory bank unit, a computing range may be limited due to the structural characteristics of the memory device 200. However, since the memory device 200 performs a computing operation in units of clusters, the computing range may be expanded differently.

[0151] Fig. 12A and Fig. 12B is a block diagram showing a memory device according to an embodiment. Fig. 12A and Fig. 12B, the memory device 300 may include a memory cell array 310, a CA buffer 320, an address decoder 330, a command decoder 340, a control logic circuit 350, an input / output (I / O) circuit 360, and a column control circuit 370. The memory cell array 310, the CA buffer 320, the address decoder 330, the command decoder 340, the control logic circuit 350, and the input / output circuit 360 are described above, and therefore, additional description will be omitted to avoid redundancy and for brevity.

[0152] Under the control of the control logic circuit 350, the column control circuit 370 may generate a column select signal CSL or a column calculation select signal CCSL. For example, when the memory device 300 operates in the normal mode, the column control circuit 370 may generate a column select signal CSL or a column calculation select signal CCSL as shown in FIG. Figure 2A and Figure 2B The column select signal CSL is generated based on the column address ADDR_COL. When the memory device 300 operates in the calculation mode, the column control circuit 370 may generate the column calculation select signal CCSL based on an input operand or a result of an internal calculation operation.

[0153] In detail, Fig. 12B As shown in , the memory cell array 310 may include a plurality of cell arrays CAR[0] to CAR[3], a plurality of bit line sense amplifiers BLSA[0] to BLSA[3], a plurality of column selection circuits CSC[0] to CSC[3], and a plurality of input / output sense amplifiers IOSA[0] to IOSA[3]. The plurality of cell arrays CAR[0] to CAR[3], the plurality of bit line sense amplifiers BLSA[0] to BLSA[3], the plurality of column selection circuits CSC[0] to CSC[3], and the plurality of input / output sense amplifiers IOSA[0] to IOSA[3] are described above, and therefore, additional description will be omitted to avoid redundancy and for brevity.

[0154] The column control circuit 370 may include a first input register REG_IN1, a second input register REG_IN2, a preset register REG_PRE, an output register REG_OUT, and a plurality of column registers REG_COL[0] to REG_COL[3]. The first input register REG_IN1, the second input register REG_IN2, the preset register REG_PRE, and the output register REG_OUT are described above, and therefore, additional descriptions will be omitted to avoid redundancy and for brevity.

[0155] When the memory device 300 operates in the computing mode, the plurality of column registers REG_COL[0] to REG_COL[3] may be configured as shown in FIG. FIG. 4A to FIG. 11The column calculation selection signals CCSL0 to CCSL3 are generated. In this case, the column calculation selection signals CCSL0 to CCSL3 may have different values ​​according to operands or results of previous internal read operations.

[0156] When the memory device 300 operates in the normal mode, the plurality of column registers REG_COL[0] to REG_COL[3] may generate a column selection signal CSL based on the column address ADDR_COL. In this case, the column selection signals CSL output from the plurality of column registers REG_COL[0] to REG_COL[3] may be identical to each other. That is, when the memory device 300 operates in the normal mode, since the same column selection signal CSL is output from the plurality of column registers REG_COL[0] to REG_COL[3], the memory device 300 may operate normally. In one embodiment, when the memory device 300 operates in the normal mode, the outputs of the input / output sense amplifiers IOSA[0] to IOSA[3] may not be fed back or fed forward to the plurality of column registers REG_COL[0] to REG_COL[3], and may be provided to the input / output circuit 360.

[0157] Fig.13 is a block diagram showing a memory system according to an embodiment. Fig.13 , the memory system 1000 may include a memory device 1100 and a host 1200. Under the control of the host 1200, the memory device 1100 may store data or may output the stored data. In one embodiment, the memory device 1100 may be a memory module including a plurality of memories. The memory module may be implemented with various types of dual in-line memory modules (DIMMs), such as UDIMMs (unbuffered DIMMs), RDIMMs (registered DIMMs), and SODIMMs (small outline DIMMs).

[0158] The host 1200 may be configured to control the memory device 1100. In one embodiment, the host 1200 may include a central processing unit (CPU) or an application processor (AP). For example, the host 1200 may include an application 1210, a kernel 1220, a device driver 1230, and a memory controller 1240. In some embodiments, the application 1210, the kernel 1220, the device driver 1230, and the memory controller 1240 may be executed by the CPU or the AP. In some embodiments, the application 1210, the kernel 1220, the device driver 1230, and the memory controller 1240 may be implemented by hardware control logic. The application 1210 may indicate various programs driven on the host 1200. The application 1210 may be configured to generate various access requests for accessing the memory device 1100.

[0159] The kernel 1220 may control or manage various system resources used in the host 1200. The kernel 1220 may be configured to provide an access request generated by the application 1210 to the device driver 1230. The device driver 1230 may convert the access request from the kernel 1220 into a memory request for accessing the memory device 1100. In one embodiment, the device driver 1230 may be configured to provide various functions for effectively controlling the memory device 1100.

[0160] The memory controller 1240 may be configured to control the memory device 1100 under the control of the device driver 1230. For example, in order to control the memory device 1100, the memory controller 1240 may transmit a clock signal CK and a command / address signal CA to the memory device 1100. The memory controller 1240 may exchange a data signal DQ and a data strobe signal DQS with the memory device 1100. In one embodiment, the memory controller 1240 may communicate with the memory device 1100 through a DDR interface or a LPDDR interface. However, embodiments are not limited thereto. In some embodiments, the memory controller 1240 may communicate with the memory device 1100 based on at least one of various interfaces, such as an ATA (Advanced Technology Attachment) interface, a SATA (Serial ATA) interface, an e-SATA (external SATA) interface, a SCSI (Small Computer Small Form Factor Interface) interface, a SAS (Serial Attached SCSI) interface, a PCI (Peripheral Component Interconnect) interface, a PCIe (PCI Express) interface, an IEEE 1394 interface, a USB (Universal Serial Bus) interface, an SD (Secure Digital) card interface, an MMC (Multimedia Card) interface, an eMMC (embedded Multimedia Card) interface, a UFS (Universal Flash Storage) interface, an eUFS (embedded Universal Flash Storage) interface, a CF (Compact Flash) card interface, and / or a CXL (Compute Express Link) interface.

[0161] In one embodiment, the memory device 1100 may be a reference Figures 1 to 12B One of the memory devices 100, 200, and 300 described above and may be based on reference Figures 1 to 12B The described method of operation provides calculation functionality.

[0162] against Figures 1 to 12B The memory device 1100 can store the calculation output mode LUT_SET. That is, as shown in FIG. Figures 1 to 12B As described above, the lookup table-based bit serial calculation may be performed by repeatedly performing an internal read operation on the calculation output pattern LUT_SET stored in the memory device 1100 .

[0163] In one embodiment, the calculation output mode LUT_SET can be implemented by various combinations. For example, the memory device 1100 can store multiple calculation output modes LUT_SET. Each of the multiple calculation output modes LUT_SET or the combination of at least some of the multiple calculation output modes LUT_SET can support different types of calculations. The combination of the first calculation output mode and the second calculation output mode among the multiple calculation output modes LUT_SET can support a first arithmetic operation or a first logical operation, and the combination of the first calculation output mode and the third calculation output mode among the multiple calculation output modes LUT_SET can support a second arithmetic operation different from the first arithmetic operation or a second logical operation different from the first logical operation. That is, various types of calculations can be supported by various combinations of multiple calculation output modes LUT_SET.

[0164] Fig.14 According to the embodiment shown Fig.13 Flowchart of the operation of the memory system 1000. Fig.13 and Fig.14 In operation S1100, the host 1200 and the memory device 1100 may perform a calculation definition phase. For example, the memory device 1100 may perform a calculation operation by repeatedly performing an internal read operation on the calculation output mode LUT_SET. That is, before the calculation operation is performed in the memory device 1100, a plurality of calculation output modes LUT_SET may be stored in the memory device 1100. The host 1200 may store a plurality of predetermined calculation output modes or a plurality of calculation output modes for supporting various calculations in the memory device 1100. In one embodiment, a plurality of calculation output modes may be stored in a pre-allocated area of ​​the memory device 1100. In one embodiment, the calculation definition phase in operation S1100 may be performed in the initialization phase of the memory device 1100. In some embodiments, the calculation definition phase in operation S1100 may be performed while the memory device 1100 is driven. In one embodiment, through the calculation definition phase in operation S1100, a plurality of calculation output modes may be stored or updated in the memory device 1100.

[0165] In operation S1200, the host 1200 and the memory device 1100 may perform a preparation phase. For example, an operand for a computing operation is used to perform the computing operation in the memory device 1100. The input operand may be a portion of user data stored in the memory device 1100. In some embodiments, the host 1200 may control the memory device 1100 so that a portion of the user data stored in the memory device 1100 is set to a file register (refer to Fig. 9 ) or input register (refer to Figure 4BIn some embodiments, the host 1200 may send an operand to the memory device 1100, and the memory device 1100 may set the operand received from the host 1200 to a file register (see Fig. 9 ) or input register (refer to Figure 4B ).

[0166] In operation S1300, the host 1200 and the memory device 1100 may perform an operation phase. For example, under the control of the host 1200, the memory device 1100 may repeatedly perform an internal read operation on a calculation output pattern stored in a memory cell connected to a selected word line. In this case, as shown in FIG. Figures 1 to 12B As described above, when the internal read operation is repeated, the column register may be updated based on the result of the internal read operation. The memory device 1100 may repeat the internal read operation up to a given number of times.

[0167] In operation S1400, the host 1200 and the memory device 1100 may perform an output phase. For example, through operation S1300, the memory device 300 may perform a computing operation and may store a result of the computing operation. In one embodiment, the result of the computing operation may be set to an output register or a file register of the memory device 1100. In some embodiments, the host 1200 may store the result of the computing operation in a memory unit of the memory device 1100. In some embodiments, the host 1200 may move the result of the computing operation to any other file register. In some embodiments, the host 1200 may receive the result of the computing operation.

[0168] As described above, the host 1200 and the memory device 1100 may perform various computing operations in the memory device 1100 through a definition phase, a preparation phase, an operation phase, and an output phase.

[0169] Fig.15 According to some embodiments, Fig.14 Flowchart of operation S1100. Figures 13 to 15 , operation S1100 may include operations S1110 to S1150.

[0170] In operation S1110, the host 1200 may receive device information from the memory device 1100. For example, the memory device 1100 may include a serial presence detection (SPD) configured to store device information about the memory device 1100. The host 1200 may receive the device information of the SPD of the memory device 1100. In one embodiment, in an initialization operation of the memory device 1100, the host 1200 may receive the device information from the memory device 1100. However, the embodiment is not limited thereto. For example, the location where the device information is stored and the time point at which the device information is obtained may be variously changed or modified.

[0171] In operation S1120, the host 1200 may allocate a memory area for calculating the output pattern LUT_SET. For example, based on the device information, the host 1200 may identify the capacity of the memory device 1100 and identify that the memory device 1100 is a device that supports bit serial calculation based on a lookup table. The host 1200 may allocate a portion of the capacity of the memory device 1100 to the memory area for calculating the output pattern LUT_SET.

[0172] In operation S1130, the host 1200 may prepare a calculation output mode LUT_SET. For example, the memory device 1100 may perform various types of calculations through various combinations of a plurality of calculation output mode LUT_SETs. The host 1200 may prepare a plurality of calculation output mode LUT_SETs based on structural characteristics of the memory device 1100 identified by using device information. In one embodiment, the plurality of calculation output mode LUT_SETs may have a predetermined data structure. In some embodiments, the plurality of calculation output mode LUT_SETs may be generated or changed according to a request of a user or an application.

[0173] In operation S1140, the host 1200 may send a write command WR and the calculation output mode LUT_SET to the memory device 1100. In one embodiment, the write command WR may include an address corresponding to a memory area allocated for the calculation output mode LUT_SET. In operation S1150, the memory device 1100 may store the calculation output mode LUT_SET in the allocated memory area in response to the write command.

[0174] In one embodiment, the host 1200 and the memory device 1100 may repeatedly perform operations S1140 and S1150 according to the size of the calculated output pattern LUT_SET. In one embodiment, the write command used in operation S1140 may be the same as the write command used to perform a normal write operation of the memory device 1100.

[0175] Fig.16 According to some embodiments, Fig.13 1 is a diagram of the storage capacity of a memory device of a memory system 1000. Fig.13 and Fig.16 , the storage space (or memory space) of the memory device 1100 may include a user data area and a lookup table area (LUT area). In one embodiment, the user data area and the lookup table area may be physically or logically distinguished from each other.

[0176] The user data area may be used as an area for the host 1200 to store user data, and the lookup table area may be used to store a calculation output pattern. In one embodiment, the lookup table area may be allocated by the host 1200. In some embodiments, the lookup table area may be a predetermined area.

[0177] Fig.17 According to some embodiments, Fig.16 In one embodiment, the memory cell array of the memory device 1100 may include a plurality of cell arrays CAR, a plurality of bit line sense amplifiers BLSA, a plurality of column selection circuits CSC, and a plurality of input / output sense amplifiers IOSA.

[0178] A plurality of cell arrays CAR may be connected to a plurality of bit line sense amplifiers BLSA, respectively. A plurality of bit line sense amplifiers BLSA may be connected to a plurality of column selection circuits CSC, respectively. A plurality of cell arrays CAR, a plurality of bit line sense amplifiers BLSA, and a plurality of column selection circuits CSC may be arranged in a row direction and a column direction. Cell arrays CAR arranged in the same row may share the same word line WL.

[0179] The column selection circuits CSC arranged in the same column may be connected to the same global input / output line GIO. In one embodiment, when the memory device 1100 performs a computing operation, the column selection circuits arranged in different columns may operate in response to different or independent column computing selection signals CCSL. When the memory device 1100 performs a normal operation, the column selection circuits may operate in response to the same column selection signal CSL.

[0180] The plurality of input / output sense amplifiers IOSA may be connected to the plurality of global input / output lines GIO in units of columns. Depending on the operation mode of the memory device 1100 (i.e., computing mode or normal mode), the plurality of input / output sense amplifiers IOSA may be connected to the column computing control circuit CCCC or the input / output circuit.

[0181] In one embodiment, the multiple cell arrays CAR, the multiple bit line sense amplifiers BLSA, the multiple column selection circuits CSC, and the multiple input / output sense amplifiers IOSA are similar to the multiple cell arrays CAR, the multiple bit line sense amplifiers BLSA, the multiple column selection circuits CSC, and the multiple input / output sense amplifiers IOSA described above, and therefore, additional description will be omitted to avoid redundancy and for brevity.

[0182] In one embodiment, the cell arrays that share a specific word line among the plurality of cell arrays CAR may be allocated to a lookup table area for storing the calculation output pattern LUT_SET. Fig.17 As shown, the calculation output pattern LUT_SET may be stored in the cell array CAR sharing a specific word line WL.

[0183] When the memory device 1100 operates in a computing mode or performs a computing operation, the memory device 1100 may access the cell array CAR connected to a specific word line WL under the control of the host 1200 (or the memory controller 1240 ).

[0184] exist Fig.17 In the embodiment of the present invention, an example in which the calculation output mode LUT_SET is stored in a specific cell array CAR (eg, a cell array CAR sharing a specific word line WL) is described, but the embodiment is not limited thereto. For example, the calculation output mode LUT_SET may be stored in any other cell array CAR.

[0185] Fig.18A and Fig.18B is a detailed illustration according to some embodiments Fig.14 FIG. 1 is a flowchart of operation S1200 of FIG. Fig.13 , Fig.14 and Fig.18A , operation S1200 may include operations S1211 to S1215.

[0186] In operation S1211, the host 1200 may send a load command LOAD to the memory device 1100. For example, the load command LOAD may be a command for loading an input operand stored in the memory device 1100 into a file register (refer to Fig. 9 ). In some embodiments, the load command LOAD may instruct the memory device 1100 to load an input operand into a file register of the memory device 1100. In one embodiment, the load command LOAD may include information about a command delimiter indicating a load command, an address (e.g., a bank address and a column address), whether to perform auto precharge, a cluster number, and a target register.

[0187] In operation S1212, the memory device 1100 may read an input operand stored in a memory cell in response to a load command LOAD. For example, the load command LOAD may include address information. The memory device 1100 may read an input operand from a memory cell corresponding to the address information.

[0188] In operation S1213, the memory device 1100 may set a file register based on the read input operand. For example, the memory device 1100 may store the read input operand in the file register. For example, the load command LOAD may include information about the cluster number and the target register. The memory device 1100 may store the input operand in the file register corresponding to the cluster number and the target register.

[0189] In one embodiment, the memory device 1100 may perform a read operation on a memory cell in response to a load command LOAD, but read data (ie, an input operand) may not be transmitted to the host 1200 .

[0190] In operation S1214, the host 1200 may send a setup command SETUP to the memory device 1100. For example, the setup command SETUP may be a command for setting the input operand stored in the file register to various registers of the column calculation control circuit. In some embodiments, the setup command SETUP may instruct the memory device 1100 to store the input operand stored in the file register to various registers of the column calculation control circuit. In one embodiment, the setup command SETUP may include information about a command delimiter indicating a setup command, a cluster number, a first input register, a second input register, a preset register, the number of internal read operations for calculation operations, and a calculation unit.

[0191] In operation S1215, the memory device 1100 may set the column calculation control circuit based on the input operand stored in the file register in response to the setup command SETUP. For example, the setup command SETUP may include information about the cluster number, the first input register, the second input register, and the preset register. The memory device 1100 may set the first input register, the second input register, and the preset register of the column calculation control circuit corresponding to the information included in the setup command SETUP.

[0192] Next, refer to Fig.13 , Fig.14 and Fig.18B , operation S1200 may include operations S1221 to S1224.

[0193] In operation S1221, the host 1200 may send an input command INPUT and an input operand to the memory device 1100. For example, the input command INPUT may be a command for providing the memory device 1100 with an operand to be used in a calculation operation of the memory device 1100. In one embodiment, the input command INPUT may include information about a command delimiter indicating an input command, an address (e.g., a bank address and a column address), whether to perform auto precharge, a cluster number, and a target register.

[0194] In operation S1222, the memory device 1100 may set a file register based on an input operand received from the host 1200 in response to an input command INPUT. For example, the memory device 1100 may load the input operand into the file register. For example, the input command INPUT may include information about a cluster number and a target register. The memory device 1100 may set a file register and a target register corresponding to the cluster number based on the input operand.

[0195] In operation S1223, the host 1200 may send a setup command SETUP to the memory device 1100. In operation S1224, the memory device 1100 may set the column calculation control circuit based on the input operand stored in the file register in response to the setup command SETUP. Operations S1223 and S1224 are similar to Fig.18A Operation S1214 and operation S1215, therefore, additional description will be omitted to avoid redundancy and for the sake of brevity.

[0196] As described above, the memory device 1100 may set data stored in the memory device 1100 or data received from the host 1200 as an input operand.

[0197] In one embodiment, when operation S1200 is completed, all column registers of the column calculation control circuit of the memory device 1100 may be in an initial setting state.

[0198] Fig.19 According to some embodiments, Fig.14 Flowchart of operation S1300. Fig.13 , Fig.14 and Fig.19 , operation S1300 may include operations S1310 to S1360.

[0199] In operation S1310, the host 1200 may send an execution command EXECUTE to the memory device 1100. The execution command EXECUTE may be a command for repeating an internal read operation for a computing operation in the memory device 1100. In some embodiments, the execution command EXECUTE may command the memory device 1100 to repeat an internal read operation for a computing operation in the memory device 1100. In one embodiment, the execution command EXECUTE may include information about a command delimiter indicating an execution command, a cluster number, and a target register.

[0200] In operation S1320 , the variable “i” is set to “0.” The variable “i” is used to describe an iteration of an internal read operation performed in the memory device 1100 , and embodiments are not limited thereto.

[0201] In operation S1330, the memory device 1100 may perform an i-th internal read operation based on the column register of the column calculation control circuit. For example, after operation S1200 is completed, the column register of the memory device 1100 is set to an initial state for the calculation operation. In this way, the memory device 1100 may perform the operation as described in reference to FIG. 4A to FIG. 12B When the internal read operation is performed, an output signal corresponding to the column calculation selection signal generated from each column register is provided to the input / output sense amplifier.

[0202] In operation S1340, the memory device 1100 may update the column register and the output register based on the internal read operation. FIG. 6A to FIG. 6E The configuration associated with the updating of the column registers and the output registers is described, and therefore, additional description will be omitted to avoid redundancy and for brevity.

[0203] In operation S1350, it is determined whether the variable "i" is a reference value. For example, the setup command SETUP in operation S1214 or operation S1223 may include information about the number of internal read operations. The variable "i" is not a reference value indicating that the internal read operation is not performed up to a given number of times defined by the setup command SETUP. In some embodiments, the reference value may be the maximum value discussed above. When it is determined that the variable "i" is not a reference value (operation S1350, no), the variable "i" is increased by up to "1", and the memory device 1100 performs operation S1330 again.

[0204] When it is determined that the variable "i" is a reference value (operation S1350, yes), the internal read operation is performed up to a given number of times defined by the setup command SETUP, and in operation S1360, the memory device 1100 may set the file register based on the value of the output register. For example, the execution command EXECUTE may include information about the target register. The memory device 1100 may store the calculation result (i.e., the value of the output register) in the file register corresponding to the target register, and the information of the target register is included in the execution command EXECUTE.

[0205] Fig. 20A , Fig. 20B and Fig. 20C According to some embodiments, Fig.14 Flowchart of operation S1400. Fig.13 , Fig.14 and Fig. 20A , operation S1400 may include operation S1411 and operation S1412.

[0206] In operation S1411, the host 1200 may send a storage command STORE to the memory device 1100. For example, the storage command STORE may be a command for storing a result of a computing operation of the memory device 1100 in a memory cell of the memory device 1100. In some embodiments, the storage command STORE may command the memory device 1100 to store the result of the computing operation of the memory device 1100 in the memory cell of the memory device 1100. In one embodiment, the storage command STORE may include information about a command delimiter indicating a storage command, an address (e.g., a bank address and a column address), whether to perform auto precharge, a cluster number, and a source register.

[0207] In operation S1412, the memory device 1100 may write the value of the file register of the memory device 1100 into the memory cell in response to the storage command STORE. For example, when operation S1300 is completed, the calculation result is set to the file register of the memory device 1100. The memory device 1100 may store the value of the file register corresponding to the cluster number in the memory cell corresponding to the address. In this case, information about the cluster number and the address may be included in the storage command STORE.

[0208] according to Fig. 20A , the host 1200 may command the memory device 1100 to directly store the result of the computing operation performed by the memory device 1100 in the memory device 1100.

[0209] Next, refer to Fig.13 , Fig.14 and Fig. 20B , operation S1400 may include operation S1421 and operation S1422.

[0210] In operation S1421, the host 1200 may send a move command MOVE to the memory device 1100. For example, the move command MOVE may be a command for moving a result of a computing operation of the memory device 1100 to any other file register of the memory device 1100. In some embodiments, the move command MOVE may instruct the memory device 1100 to move a result of a computing operation of the memory device 1100 to any other file register of the memory device 1100. In one embodiment, the move command MOVE may include information about a command delimiter indicating a move command, a source cluster number, a source register, a target cluster number, and a target register.

[0211] In operation S1422, the memory device 1100 may move the value of the file register of the memory device 1100 to any other file register in response to the move command MOVE. For example, when operation S1300 is completed, the calculation result is stored in the file register of the memory device 1100. The memory device 1100 may move the value of the file register corresponding to the source cluster number and the source register to the file register corresponding to the target cluster number and the target register. In this case, information about the source cluster number, the source register, the target cluster number, and the target register may be included in the move command MOVE.

[0212] according to Fig. 20B , the host 1200 may instruct the memory device 1100 to move the result of the calculation operation performed by the memory device 1100 to any other file register. In this case, the result of the calculation operation can be used in any other calculation of the memory device 1100.

[0213] Next, refer to Fig.13 , Fig.14 and Fig. 20C , operation S1400 may include operation S1431 and operation S1432.

[0214] In operation S1431, the host 1200 may send an output command OUTPUT to the memory device 1100. For example, the output command OUTPUT may be a command for outputting the result of the computing operation of the memory device 1100 to the host 1200. In some embodiments, the host 1200 may command the memory device 1100 to output the result of the computing operation of the memory device 1100 to the host 1200. In one embodiment, the output command OUTPUT may include information about a command delimiter indicating an output command, a cluster number, and a source register.

[0215] In operation S1432, the memory device 1100 may transmit the calculation result to the host 1200 in response to the output command OUTPUT. For example, when operation S1300 is completed, the calculation result of the memory device 1100 is stored in the file register. The memory device 1100 may transmit the value (ie, the calculation result) stored in the file register corresponding to the cluster number and the source register to the host 1200.

[0216] according to Fig. 20C , the host 1200 may receive the calculation result of the memory device 1100.

[0217] As described above, the memory device 1100 may perform a computing operation under the control of the host 1200. In this case, the memory device 1100 may perform a computing operation based on the reference Figures 1 to 12B The host 1200 may send various commands to the memory device 1100 so that the memory device 1100 performs a computing operation. In other words, the host 1200 may send various commands to command the memory device 1100 to perform a computing operation. For example, the host 1200 may send a load command LOAD, a setup command SETUP, an input command INPUT, an operation command EXECUTE, a storage command STORE, a move command MOVE, and an output command OUTPUT to the memory device 1100. The above commands may be defined by an interface between the memory device 1100 and the host 1200. In one embodiment, the memory device 1100 and the host 1200 may communicate with each other based on a DDR interface. The above commands may be implemented using a combination of various commands defined by the DDR interface, a reserved command, or a vendor command.

[0218] Fig.21 According to some embodiments, Fig.13 A block diagram of a memory controller of a host of a memory system. Fig.13 and Fig.21 The memory controller 1240 may include an address map 1241, a memory bank control circuit 1242, a cluster control circuit 1243, a channel scheduler 1244, a read buffer RB, and a write buffer WB.

[0219] The address map 1241 may be configured to transfer a request provided from the application 1210, the kernel 1220, or the device driver 1230 of the host 1200 to the bank control circuit 1242 and the cluster control circuit 1243. In one embodiment, a request for a normal operation (e.g., a read operation or a write operation) of the memory device 1100 may be provided to the bank control circuit 1242, and a request for a computing operation of the memory device 1100 may be provided to the cluster control circuit 1243.

[0220] The memory bank control circuit 1242 may be configured to control the normal operation of the memory device 1100. For example, the memory bank control circuit 1242 may include a plurality of memory bank queues, a plurality of memory bank schedulers, and a plurality of command registers. Each memory bank queue may be configured to store a request to a corresponding memory bank (i.e., a request to a corresponding memory bank may be added to each memory bank queue). Each memory bank scheduler may be configured to schedule commands stored in a corresponding memory bank queue. Each of the plurality of command registers may be configured to store a command scheduled by a corresponding memory bank scheduler.

[0221] The cluster control circuit 1243 may be configured to control the computing operation of the memory device 1100. For example, the cluster control circuit 1243 may include a plurality of cluster queues, a plurality of cluster schedulers, and a plurality of command registers. Each of the plurality of cluster queues may be configured to store a request for a corresponding cluster (i.e., a request for a corresponding cluster may be added to each of the plurality of cluster queues). Each of the plurality of cluster schedulers may be configured to schedule commands stored in the corresponding cluster queue. Each of the plurality of command registers may store commands scheduled by the corresponding cluster scheduler.

[0222] Through the above configuration, the storage body control circuit 1242 can process requests or commands associated with normal operations (e.g., read operations or write operations), which are associated with multiple storage bodies of the memory device 1100, and the cluster control circuit 1243 can process requests or commands associated with computing operations of the memory device 1100.

[0223] The channel scheduler 1244 may be configured to schedule commands generated by the bank control circuit 1242 and the cluster control circuit 1243. For example, the channel scheduler 1244 may schedule commands generated by the bank control circuit 1242 and the cluster control circuit 1243, and may transmit the scheduled commands to the memory device 1100 via a command address (CA) bus.

[0224] The read buffer RB may be configured to receive data (eg, data signal DQ and data strobe signal DQS) from the memory device 1100 through the data bus and temporarily store the received data. The data temporarily stored in the read buffer RB may be provided to the application 1210 through the device driver 1230.

[0225] The write buffer WB may be configured to receive data from the device driver 1230 and temporarily store the received data. The data (eg, the data signal DQ and the data strobe signal DQS) temporarily stored in the write buffer WB may be transmitted to the memory device 1100 through the data bus.

[0226] In one embodiment, the calculation output pattern LUT_SET for the calculation operation to be stored in the memory device 1100 may be temporarily stored in the write buffer WB and may be sent to the memory device 1100 through a data bus (eg, a data signal DQ and a data strobe signal DQS).

[0227] The computing operation of the memory device 1100 may be supported by the above structure of the memory controller 1240. For example, the CPU or AP of the host 1200 may provide an instruction set for offloading the computing function to the memory device 1100. The application 1210 may request a computing operation from the memory device 1100 by using the instruction set for offloading the computing function. In this case, the above instruction set may be provided to the memory controller 1240, and the memory controller 1240 may process the above instruction set or request by using the cluster control circuit 1243.

[0228] In one embodiment, Fig.21 The configuration of the memory controller 1240 shown in is provided as an example, and the embodiment is not limited thereto. For example, the address map 1241 of the memory controller 1240 may divide the instruction set for the computing function requested from the device driver 1230 in units of memory banks so as to transmit the divided instruction set to the memory bank control circuit 1242. The path scheduler 1244 may process the commands for the computing function to be processed by the memory bank control circuit 1242 simultaneously or in parallel. In this case, the computing function of the memory device 1100 may be supported without the cluster control circuit 1243. In other words, in some embodiments, the cluster control circuit 1243 may be omitted.

[0229] Fig. 22 is a diagram showing a memory module according to an embodiment. Fig. 22 , the memory module 2100 may include a plurality of memory devices MEM0 to MEM8, a register clock driver RCD and a plurality of data buffers DB. In one embodiment, Fig. 22 The memory module 2100 is shown as having a structure of LRDIMM (Load Reduced Dual In-line Memory Module), but the embodiment is not limited thereto. For example, the memory module 2100 may be implemented with various types of memory modules such as UDIMM, RDIMM, SODIMM, and / or NVDIMM (Non-Volatile DIMM).

[0230] The register clock driver RCD may receive a command / address signal CA and a clock signal CK from an external device (eg, a memory controller) and may control a plurality of data buffers DB based on the received signals or may transmit the received signals to a plurality of memory devices MEM0 to MEM8.

[0231] Under the control of the register clock driver RCD, the plurality of data buffers DB may exchange data with external devices through data signals DQ and data strobe signals DQS. In some embodiments, under the control of the register clock driver RCD, the plurality of data buffers DB may exchange data with the plurality of memory devices MEM0 to MEM8.

[0232] The plurality of memory devices MEM0 to MEM8 may operate in response to a received command / address signal CA and a received clock signal CK. In one embodiment, each of the plurality of memory devices MEM0 to MEM8 may include a reference signal. Figures 1 to 21 Each of the plurality of memory devices MEM0 to MEM8 may include a calculation control circuit CCC. The calculation control circuit CCC may include a reference Figures 1 to 21 That is, each of the plurality of memory devices MEM0 to MEM8 may be based on a reference Figures 1 to 21 Describes methods to perform computational operations.

[0233] In one embodiment, at least some of the plurality of memory devices MEM0 to MEM8 may be configured to perform a calculation operation together. For example, it is assumed that the operand that can be calculated in each of the plurality of memory devices MEM0 to MEM8 is an N-bit operand. In this case, when the 0th memory device MEM0 and the first memory device MEM1 perform a calculation operation together, the range of operands that can be calculated can be increased to 2×N bits. To this end, the calculation control circuit CCC of the plurality of memory devices MEM0 to MEM8 may perform a feedback operation FB and a feedforward operation FF. The construction of performing the feedback operation FB and the feedforward operation FF between the memory devices is similar to the above construction of performing the feedback operation FB and the feedforward operation FF between the storage bodies in a single memory device, and therefore, additional description will be omitted to avoid redundancy and for brevity.

[0234] In one embodiment, the plurality of memory devices MEM0 to MEM8 may perform feedback operations FB and feedforward operations FF through separate dedicated lines or separate dedicated buses. In one embodiment, the plurality of memory devices MEM0 to MEM8 may perform feedback operations FB and feedforward operations FF through multiple data buffers DB.

[0235] Fig.23is a block diagram showing a memory system according to an embodiment. Fig.23 , the memory system 2000 may include a CPU 2200 and a plurality of memory modules 2100-1 to 2100-n (eg, DIMM #1 2100-1 to DIMM #n 2100-n). The CPU 2200 may be a reference Fig.13 The host 1200 described in the memory system 1000 of the present invention. The CPU 2200 may control the plurality of memory modules 2100-1 to 2100-n. For example, the CPU 2200 may store data in the plurality of memory modules 2100-1 to 2100-n, or may read data stored in the plurality of memory modules 2100-1 to 2100-n.

[0236] The plurality of memory modules 2100-1 to 2100-n may operate under the control of the CPU 2200. In one embodiment, each of the plurality of memory modules 2100-1 to 2100-n may be a reference Fig. 22 That is, under the control of the CPU 2200, each of the plurality of memory modules 2100-1 to 2100-n may be based on the reference Figures 1 to 22 The described methods perform computational operations.

[0237] In one embodiment, at least some of the multiple memory modules 2100-1 to 2100-n may perform a computing operation together. For example, assume that the operand that can be calculated in each of the multiple memory modules 2100-1 to 2100-n is an M-bit operand. In this case, when the first memory module 2100-1 and the second memory module 2100-2 perform a computing operation together, the range of operands that can be calculated can be increased to 2×M bits. To this end, the computing control circuits of the multiple memory modules 2100-1 to 2100-n may perform a feedback operation FB and a feedforward operation FF. The construction for performing the feedback operation FB and the feedforward operation FF between the memory modules is similar to the construction for performing the feedback operation FB and the feedforward operation FF between the memory devices (refer to Fig. 22 ), therefore, additional description will be omitted to avoid redundancy and for brevity.

[0238] As described above, according to various embodiments of the present disclosure, a memory device may perform a bit-serial calculation based on a lookup table without a separate processor or a separate arithmetic logic unit. For example, the memory device may store a plurality of calculation output patterns, and may perform a target calculation by repeatedly performing an internal read operation on a calculation output pattern corresponding to a target calculation among the plurality of calculation output patterns. In this case, an operand corresponding to the target calculation may be applied to a column selection signal of the memory device.

[0239] In one embodiment, the computing operation according to various embodiments of the present disclosure may be performed in units of a single channel, in units of a memory bank including a plurality of channels, in units of a cluster including a plurality of memory banks, in units of a memory device including a plurality of clusters, in units of a memory module including a plurality of memory devices, or in units of a memory system including a plurality of memory modules. As described above, in order to perform the computing operation by using various units, the components may be implemented so that the feedback operation FB and the feedforward operation FF are performed between the components.

[0240] Fig.24 is a block diagram showing a memory system according to an embodiment. Fig.24 , the memory system 3000 may include a CPU 3100 and a CXL memory 3200. The CPU 3100 may control the overall operation of the memory system 3000. In one embodiment, the CPU 3100 may be a reference Figures 1 to 23 The CPU 3100 is described in Fig.24 , but the embodiment is not limited thereto. For example, CPU 3100 may be replaced by one of various processors (such as a graphics processing unit (GPU), a neural processing unit (NPU) and / or a data processing unit (DPU)). In one embodiment, CPU 3100 may include a single-core processor or a multi-core processor.

[0241] CPU 3100 may be configured to control CXL memory 3200. For example, CPU 3100 may store data in CXL memory 3200 or may read data stored in CXL memory 3200. In one embodiment, CPU 3100 may be configured to request a computing operation to CXL memory 3200.

[0242] The CXL memory 3200 may include a CXL controller 3210 and a memory device 3220. Under the control of the CPU 3100, the CXL controller 3210 may store data in the memory device 3220, or may transmit data stored in the memory device 3220 to the CPU 3100. In one embodiment, the memory device 3220 may include a reference Figures 1 to 23 That is, the memory device 3220 may include a calculation control circuit CCC, and may be based on a reference Figures 1 to 23 Describes methods to perform computational operations.

[0243] In one embodiment, the CPU 3100 and the CXL memory 3200 may communicate with each other based on a CXL (Compute Express Link) interface. The CXL interface may refer to a low-latency and high-bandwidth link that supports dynamic protocol multiplexing of consistency, memory access, and IO protocols to enable various connections between accelerators, memory devices, or various electronic devices.

[0244] The CPU 3100 may send a computing request to the CXL memory 3200 through the CXL interface. The CXL controller 3210 of the CXL memory 3200 may control the memory device 3220 in response to the computing request received through the CXL interface so that the computing operation is performed in the memory device 3220 .

[0245] Fig.25 is a diagram of a data center 4000 to which a memory device is applied according to an embodiment.

[0246] Reference Fig.25 , the data center 4000 may be a facility that collects various types of data and provides services, and is referred to as a data storage center. The data center 4000 may be a system for operating a search engine and a database, and may be a computing system used by a company (such as a bank) or a government agency. The data center 4000 may include application servers 4100 to 4100n (e.g., application server 1 to application server N) and storage servers 4200 to 4200m (e.g., storage server 1 to storage server M). The number of application servers 4100 to 4100n and the number of storage servers 4200 to 4200m may be selected differently according to the embodiment. The number of application servers 4100 to 4100n may be different from the number of storage servers 4200 to 4200m.

[0247] The application server 4100 or the storage server 4200 may include at least one of the processors 4110 and 4210 and the memories 4120 and 4220. The storage server 4200 will now be described as an example. The processor 4210 may control all operations of the storage server 4200, access the memory 4220, and execute instructions and / or data loaded in the memory 4220. The memory 4220 may be a double data rate synchronous DRAM (DDR SDRAM), a high bandwidth memory (HBM), a hybrid memory cube (HMC), a dual in-line memory module (DIMM), an Optane DIMM, and / or a non-volatile DIMM (NVMDIMM). In some embodiments, the number of processors 4210 and memories 4220 included in the storage server 4200 may be selected differently. In one embodiment, the processor 4210 and the memory 4220 may provide a processor-memory pair. In one embodiment, the number of processors 4210 may be different from the number of memories 4220. The processor 4210 may include a single-core processor or a multi-core processor. The above description of the storage server 4200 may be similarly applied to the application server 4100. In some embodiments, the application server 4100 may not include the storage device 4150. The storage server 4200 may include at least one storage device 4250. The number of storage devices 4250 included in the storage server 4200 may be variously selected according to embodiments.

[0248] The application servers 4100 to 4100n can communicate with the storage servers 4200 to 4200m through the network (NT) 4300. The network 4300 can be implemented by using a fiber channel (FC) or Ethernet. In this case, FC can be a medium for relatively high-speed data transmission, and an optical switch with high performance and high availability is used. According to the access method of the network 4300, the storage servers 4200 to 4200m can be provided as a file storage device, a block storage device, or an object storage device.

[0249] In one embodiment, the network 4300 may be a storage-specific network such as a storage area network (SAN). For example, in some embodiments, the SAN may be an FC-SAN implemented using an FC network and according to an FC protocol (FCP). In some embodiments, the SAN may be an Internet Protocol (IP)-SAN implemented using a Transmission Control Protocol (TCP) / IP network and according to a SCSI or Internet SCSI (iSCSI) protocol over TCP / IP. In some embodiments, the network 4300 may be a general-purpose network such as a TCP / IP network. For example, the network 4300 may be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), and NVMe over a network (NVMe-oF).

[0250] Hereinafter, the application server 4100 and the storage server 4200 will be mainly described. The description of the application server 4100 may be applied to another application server 4100n, and the description of the storage server 4200 may be applied to another storage server 4200m.

[0251] The application server 4100 may store data requested to be stored by a user or client in one of the storage servers 4200 to 4200m through the network 4300. The application server 4100 may obtain data requested to be read by a user or client from one of the storage servers 4200 to 4200m through the network 4300. For example, the application server 4100 may be implemented as a network server or a database management system (DBMS).

[0252] The application server 4100 may access a memory 4120n or a storage device 4150n included in another application server 4100n through the network 4300. In some embodiments, the application server 4100 may access a memory 4220 to 4220m or a storage device 4250 to 4250m included in the storage servers 4200 to 4200m through the network 4300. Therefore, the application server 4100 may perform various operations on the data stored in the application servers 4100 to 4100n and / or the storage servers 4200 to 4200m. For example, the application server 4100 may execute an instruction for moving or copying data between the application servers 4100 to 4100n and / or the storage servers 4200 to 4200m. In this case, data may be moved from storage devices 4250 to 4250m of storage servers 4200 to 4200m to storage 4120 to 4120n of application servers 4100 to 4100n directly or through storage 4220 to 4220m of storage servers 4200 to 4200m. Data moved through network 4300 may be data encrypted for security or privacy.

[0253] The storage server 4200 will now be described as an example. The interface (I / F) 4254 may provide a physical connection between the processor 4210 and the controller (CTRL) 4251 and a physical connection between the network interface card (NIC) 4240 and the controller 4251. For example, the interface 4254 may be implemented using a direct attached storage (DAS) solution in which the storage device 4250 is directly connected to a dedicated cable. For example, the interface 4254 may be implemented using various interface solutions (such as ATA, SATA, e-SATA, SCSI, SAS, PCI, PCIe, NVMe, IEEE 1394, USB interface, SD card interface, MMC interface, eMMC interface, UFS interface, eUFS interface, and / or CF card interface).

[0254] The storage server 4200 may further include a switch 4230 and a NIC (Network Interconnect) 4240. The switch 4230 may selectively connect the processor 4210 to the storage device 4250 or selectively connect the NIC 4240 to the storage device 4250 via the control of the processor 4210. In one embodiment, the switches 4130 to 4130n included in the application servers 4100 to 4100n may be configured similarly to the switch 4230, and the NICs 4140 to NIC4140n included in the application servers 4100 to 4100n may be configured similarly to the NICs 4240 to NIC 4240m included in the storage servers 4200 to 4200m.

[0255] In one embodiment, NIC 4240 may include a network interface card and a network adapter. NIC 4240 may be connected to network 4300 through a wired interface, a wireless interface, a Bluetooth interface, or an optical interface. NIC 4240 may include an internal memory, a digital signal processor (DSP), and a host bus interface, and is connected to processor 4210 and / or switch 4230 through the host bus interface. The host bus interface may be implemented as one of the above examples of interface 4254. In one embodiment, NIC 4240 may be integrated with at least one of processor 4210, switch 4230, and storage device 4250.

[0256] In the storage servers 4200 to 4200m or the application servers 4100 to 4100n, the processor may send a command to the storage devices 4150 to 4150n and 4250 to 4250m or the memories 4120 to 4120n and 4220 to 4220m, and program or read data. In this case, the data may be data whose errors are corrected by the ECC engine. The data may be data on which a data bus inversion (DBI) operation or a data mask (DM) operation is performed, and may include cyclic redundancy code (CRC) information. The data may be data encrypted for security or privacy.

[0257] The storage devices 4150 to 4150n and 4250 to 4250m may send control signals and command / address signals to nonvolatile memory devices (NVM) (e.g., NAND flash memory devices) 4252 to 4252m in response to a read command received from a processor. Therefore, when data is read from the NAND flash memory devices 4252 to 4252m, an input read enable (RE) signal may be input as a data output control signal, and thus, the data may be output to the DQ bus. The data strobe signal DQS may be generated using the RE signal. The command and address signals may be latched in the page buffer according to the rising edge or falling edge of the write enable (WE) signal.

[0258] The controller 4251 may control all operations of the storage device 4250. In one embodiment, the controller 4251 may include an SRAM. The controller 4251 may write data to the NAND flash memory device 4252 in response to a write command, or read data from the NAND flash memory device 4252 in response to a read command. For example, a write command and / or a read command may be provided from the processor 4210 of the storage server 4200, the processor 4210m of another storage server 4200m, or the processors 4110 and 4110n of the application servers 4100 and 4100n. The DRAM 4253 may temporarily store (or buffer) data to be written to the NAND flash memory device 4252 or data read from the NAND flash memory device 4252. The DRAM 4253 may store metadata. Here, the metadata may be user data or data generated by the controller 4251 to manage the NAND flash memory device 4252. The storage device 4250 may include a secure element (SE) for security or privacy. In one embodiment, interfaces 4254 to 4254 m , DRAMs 4253 to 4253 m , and controllers 4251 to 4251 m included in storage devices 4250 to 4250 m may be similarly configured, respectively.

[0259] In one embodiment, the memory 4120 to 4120n of the application server 4100 to 4100n or the memory 4220 to 4220m of the storage server 4200 to 4200m may be referred to as Figures 1 to 24 The memory device or memory module described above can be implemented or can be based on the reference Figures 1 to 24 The method described above is used to perform a computing operation. In one embodiment, at least some of the memories 4120 to 4120n of application servers 4100 to 4100n or at least some of the memories 4220 to 4220m of storage servers 4200 to 4200m may be configured to perform a computing operation together. For example, the memories 4120 and 4120m of application servers 4100 and 4100m may be configured to perform the same computing operation together. In this case, as described above, the range of operands that can be calculated may be increased. For this reason, feedback operations and feedforward operations may be performed between the memories 4120 to 4120n of application servers 4100 to 4100n or the memories 4220 to 4220m of storage servers 4200 to 4200m.

[0260] According to the present disclosure, a memory device repeatedly performs an internal read operation on a calculation output mode. In this case, the internal read operation is performed based on a column calculation selection signal, the column calculation selection signal is generated based on an operand, and when the internal read operation is performed, the column calculation selection signal is updated. When the memory device performs the above operation, the result of the calculation operand can be obtained. That is, the memory device can perform various types of calculation operations without a separate arithmetic processor. Therefore, a storage device and an operating method thereof that provide a calculation function while improving performance and reducing costs are provided.

[0261] While the present disclosure has been described with reference to various embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the following claims.

Claims

1. A memory device having a computing function, the memory device comprising: a first cell array including first memory cells connected to a plurality of word lines; a second cell array comprising second memory cells connected to the plurality of word lines; a first bit line sense amplifier configured to sense a first voltage of a first bit line connected to a first memory cell and output the first voltage; a second bit line sense amplifier configured to sense a second voltage of a second bit line connected to a second memory cell and output the second voltage; a first column selection circuit configured to output a first output signal among first voltages output by the first bit line sense amplifier based on a first column calculation selection signal; a second column selection circuit configured to output a second output signal among the second voltages output by the second bit line sense amplifier based on a second column calculation selection signal different from the first column calculation selection signal; as well as The column calculation control circuit is configured to generate a first column calculation selection signal and a second column calculation selection signal.

2. The memory device according to claim 1, further comprising: a first input / output sense amplifier configured to sense a first output signal; as well as The second input / output sense amplifier is configured to sense the second output signal.

3. The memory device according to claim 1, wherein: The column calculation control circuit includes: a first column register configured to generate a first column calculation selection signal based on an input operand; and The second column register is configured to generate a second column calculation selection signal based on the input operand.

4. The memory device according to claim 3, wherein: The first column register is updated based on the first portion of the first output signal and the input operand, and The second column register is updated based on the second portion of the first output signal, the first portion of the second output signal, and the input operand.

5. The memory device according to claim 4, wherein: The column calculation control circuit also includes: An output register is configured to accumulate a second portion of the second output signal.

6. The memory device according to claim 5, wherein: A memory cell connected to the first word line among the first memory cells stores a first calculation output pattern, wherein a memory cell connected to the second word line among the first memory cells stores a second calculation output pattern, wherein a memory cell connected to the first word line among the second memory cells stores a third calculation output pattern, and Among the second memory cells, the memory cells connected to the second word line store a fourth calculation output pattern.

7. The memory device according to claim 6, wherein: When the internal read operation is repeated for the first word line, the value accumulated in the output register corresponds to the result of the first type of computational operation on the input operand, and Wherein, when the internal read operation is repeated for the second word line, the value accumulated in the output register corresponds to the result of the second type of computational operation on the input operand.

8. The memory device according to claim 1, wherein: The first cell array and the second cell array are included in the same memory bank.

9. The memory device according to claim 1, wherein: The first cell array and the second cell array are included in different memory banks.

10. The memory device according to any one of claims 1 to 9, further comprising: a column decoder configured to generate a common column select signal based on a column address, In the read operation of the memory device, The first column selection circuit outputs first read data among the outputs of the first bit line sense amplifier based on the common column selection signal, and The second column selection circuit outputs second read data among outputs of the second bit line sense amplifier based on the common column selection signal.

11. A method for operating a memory device having a computing function, the method comprising: Load input operands; Setting a plurality of column registers based on an input operand; performing a first internal read operation on memory cells of a memory device with respect to a first word line based on a plurality of first column calculation selection signals respectively generated from the plurality of column registers; updating the plurality of column registers and the output register based on a result of the first internal read operation; as well as A second internal read operation is performed on memory cells of the memory device with respect to the first word line based on a plurality of second column calculation selection signals respectively generated from the plurality of column registers that have been updated.

12. The operating method according to claim 11, wherein: The plurality of first column calculation selection signals are independent of one another, and the plurality of second column calculation selection signals are independent of one another.

13. The operating method according to claim 11, wherein: The steps to load the input operands are: receiving a load command from a controller; and Reading an input operand stored in a memory cell based on a load command, and The input operands are not output to the controller.

14. The operating method according to claim 11, wherein: The step of setting the plurality of column registers based on the input operand comprises: receiving a setup command from a controller; and Based on the set command, the plurality of column registers are set based on the input operand.

15. The operating method according to claim 11, further comprising: receiving a storage command from a controller; as well as The value of the output register is stored in the memory cell based on the store command.

16. The operating method according to any one of claims 11 to 15, further comprising: In an initialization operation of the memory device, a calculation output pattern is stored in a memory cell connected to a first word line.

17. A memory device having a computing function, the memory device comprising: a first cell array configured to store a first computation output pattern; a first bit line sense amplifier configured to sense a first voltage of a first bit line connected to the first cell array and output the first voltage; a first column selection circuit configured to output a first output signal among first voltages output by the first bit line sense amplifier based on a first column calculation selection signal; as well as A first column calculation control circuit is configured to generate a first column calculation selection signal based on an input operand, When the internal read operation of the first calculation output mode is repeatedly performed, the first column calculation control circuit updates the first column calculation selection signal.

18. The memory device of claim 17, further comprising: a second cell array configured to store a second computation output pattern; a second bit line sense amplifier configured to sense a second voltage of a second bit line connected to the second cell array and output the second voltage; as well as a second column selection circuit configured to output a second output signal among the second voltages output by the second bit line sense amplifier based on the second column calculation selection signal, wherein the first column calculation control circuit is configured to generate a second column calculation selection signal based on an input operand, and When the internal read operation is repeatedly performed on both the first calculation output mode and the second calculation output mode, the first column calculation control circuit updates the first column calculation selection signal and the second column calculation selection signal.

19. The memory device of claim 18, wherein: The first column calculation selection signal is updated based on the output of the first column selection circuit, and The second column calculation selection signal is updated based on the output of the first column selection circuit and the output of the second column selection circuit.

20. The memory device of claim 17, further comprising: a second cell array configured to store a second computation output pattern; a second bit line sense amplifier configured to sense a second voltage of a second bit line connected to the second cell array and output the second voltage; a second column selection circuit configured to output a second output signal among the second voltages output by the second bit line sense amplifier based on the second column calculation selection signal; as well as A second column calculation control circuit is configured to generate a second column calculation selection signal based on an input operand, and When the internal read operation for the second calculation output mode is repeatedly performed, the second column calculation control circuit is further configured to update the second column calculation selection signal based on the result of the internal read operation and the information fed forward from the first column calculation control circuit.

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