Preparation method of semiconductor device and semiconductor device

Abstract

The invention relates to the technical field of semiconductors, and discloses a preparation method of a semiconductor device and the semiconductor device. The preparation method of the semiconductor device comprises the following steps: sequentially forming a seed layer and a welding body at a to-be-interconnected position on a first device part; in the process of forming the welding body, atoms in the welding body and atoms in the seed layer are mutually diffused, and an eutectic film is formed on the side wall of the welding body; performing etching treatment on the eutectic film, and removing the eutectic film; and after the eutectic film is etched, the to-be-interconnected position on the second device part is interconnected with the to-be-interconnected position on the first device part through the welding body. The reliability of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor device and a semiconductor device. Background Art

[0002] Semiconductor device packaging technology is a major obstacle to increasing the integration density of semiconductor devices. One of the semiconductor device packaging processes involves connecting various device components using a flip-chip interconnection process, forming an interconnect structure at the desired location on at least one device component.

[0003] In related art, the steps for forming an interconnect structure include sequentially forming a seed layer and a solder body at the desired interconnection location on the device portion. The process temperature for forming the solder body is relatively high, exceeding the melting point of the solder body. Therefore, during the formation of the solder body, solid-liquid diffusion occurs between atoms in the solder body and atoms in the seed layer, forming a eutectic film on the sidewalls of the solder body.

[0004] However, the stress generated by the formation of the eutectic film leads to poor reliability of the semiconductor device. Summary of the Invention

[0005] The purpose of the present invention is to at least provide a method for preparing a semiconductor device and a semiconductor device, which can at least solve the problem of poor reliability of the semiconductor device and at least achieve the effect of improving the reliability of the semiconductor device.

[0006] In order to solve the above technical problems, the present invention provides a method for preparing a semiconductor device, comprising: sequentially forming a seed layer and a welding body at a position to be interconnected on a first device part; in the process of forming the welding body, atoms in the welding body and atoms in the seed layer diffuse with each other, and a eutectic film is formed on the side wall of the welding body; the eutectic film is etched to remove the eutectic film; after the eutectic film is etched, the position to be interconnected on the second device part is interconnected with the position to be interconnected on the first device part through the welding body.

[0007] The method for preparing a semiconductor device provided by the present invention generates a certain tensile stress on the first device part during the process of forming the eutectic film. By etching the eutectic film on the side wall of the welding body to remove the eutectic film, the tensile stress generated by the eutectic film on the first device part can be released, the adhesion of the seed layer at the position to be interconnected is improved, and the contact ability between the first device part and the seed layer is enhanced. At the same time, a clean interface is provided for interconnecting the position to be interconnected on the second device part and the position to be interconnected on the first device part, thereby improving the stability of the interconnection and making the reliability of the semiconductor device high.

[0008] In addition, the process for etching the eutectic film includes a dry etching process. The steps of etching the eutectic film include: using a rotating member to drive the first device portion, the seed layer, and the solder body to rotate circumferentially around the central axis of the first device portion; and simultaneously irradiating an ion beam toward the surface of the first device portion having the eutectic film. The dry etching process has the characteristics of smooth surface, high uniformity, strong stability, and manufacturability, and can improve the accuracy of etching the eutectic film. During the process of the first device portion, the seed layer, and the solder body rotating together, the ion beam can be uniformly irradiated to the surface of the eutectic film to etch the eutectic film.

[0009] Furthermore, irradiating the ion beam toward the surface of the first device portion having the eutectic film includes irradiating the ion beam toward the surface of the eutectic film from a side of the first device portion having the eutectic film, with the ion beam offset from the central axis by an angle less than 90 degrees. This can increase the probability of the ion beam irradiating the surface of the eutectic film, enhance the etching effect on the eutectic film, and improve the ability of the to-be-interconnected position on the second device portion to be interconnected with the to-be-interconnected position on the first device portion via the solder body.

[0010] In addition, the deviation angle is 1° to 75°, which can simultaneously meet the requirements of high probability of ion beam irradiation to the eutectic film surface and low process difficulty.

[0011] In addition, the current for forming the ion beam is 10 mA to 300 mA, and the voltage is 100 V to 2000 V. This can simultaneously meet the requirements of good removal of the eutectic film, low production cost, and high efficiency of interconnecting the locations to be interconnected on the second device part with the locations to be interconnected on the first device part through the solder body.

[0012] In addition, the first device portion is a detection chip, and the second device portion is a readout circuit; or the first device portion is a readout circuit, and the second device portion is a detection chip.

[0013] In addition, when the first device portion is a detection chip, an electrode is provided on one side surface of the first device portion, and the position to be interconnected on the first device portion is located on the electrode of the first device portion. The electrode is used for signal transmission in the semiconductor device.

[0014] Furthermore, the process for forming the electrode on the first device portion includes: sequentially forming a stacked initial first electrode layer, an initial second electrode layer, and an initial third electrode layer at the location where the electrode is to be formed in the first device portion; patterning the initial second electrode layer and the initial third electrode layer to form a second electrode and a third electrode; and, during an etching process of the eutectic film, removing a portion of the initial first electrode layer to form a first electrode at the location where the electrode is to be formed; wherein the location to be interconnected is located on the third electrode. The first electrode is an ohmic contact layer that contacts the surface of a pixel in the detection chip; the second electrode is an intermediate transmission layer for transmitting signals generated by the first electrode; and the third electrode is an interconnection layer. The initial first electrode layer is set on the entire surface, which can avoid direct tensile stress on the picture elements of the detection chip during the formation of the eutectic film, thereby protecting the picture elements of the detection chip; at the same time, it improves the adhesion of the electrode on the surface of the picture element and enhances the contact ability between the electrode and the picture element; in the process of etching the eutectic film, part of the initial first electrode layer is removed, so that the dimensions of the formed first electrode, the second electrode and the third electrode along the surface direction of the detection chip are consistent, thereby improving the signal transmission efficiency of the semiconductor device; and reducing the production process and reducing production costs.

[0015] In addition, a number of picture elements are arranged inside the detection chip; the picture elements are arranged opposite to the positions to be interconnected and are connected to the electrodes.

[0016] In addition, the spacing between adjacent pixels is 1 μm to 15 μm. Using pixel sizes of the above size, more pixels can be integrated while keeping the area of ​​the detection chip 1 unchanged, which is beneficial for preparing semiconductor devices with high pixel density, improving the resolution of semiconductor devices and reducing production costs.

[0017] In addition, the method for manufacturing a semiconductor device further includes: before interconnecting the position to be interconnected on the second device portion with the position to be interconnected on the first device portion via the soldering body, sequentially forming a seed layer and a soldering body at the position to be interconnected on the second device portion, wherein during the formation of the soldering body, atoms in the soldering body and atoms in the seed layer diffuse with each other, forming a eutectic film on the sidewalls of the soldering body; etching the eutectic film to remove the eutectic film; and interconnecting the position to be interconnected on the second device portion with the position to be interconnected on the first device portion via the soldering body, including: interconnecting the soldering body at the position to be interconnected on the second device portion with the soldering body at the position to be interconnected on the first device portion. This can further enhance the interconnection between the position to be interconnected on the second device portion and the position to be interconnected on the first device portion.

[0018] The eutectic film etching process includes a dry etching process. The steps of etching the eutectic film include: using a rotating member to drive the second device portion, the seed layer, and the solder body to rotate circumferentially around the central axis of the second device portion; and simultaneously irradiating an ion beam toward the surface of the second device portion having the eutectic film. The ion beam can evenly etch the eutectic film, improving the accuracy of the etching process.

[0019] Furthermore, irradiating the ion beam toward the surface of the second device portion having the eutectic film includes irradiating the ion beam toward the surface of the eutectic film from a side of the second device portion having the eutectic film, with the ion beam offset from the central axis by an angle less than 90°. This can increase the probability of the ion beam irradiating the surface of the eutectic film, enhance the etching effect on the eutectic film, and improve the ability of the to-be-interconnected position on the second device portion to be interconnected with the to-be-interconnected position on the first device portion via the solder body.

[0020] In addition, the deviation angle is 1° to 75°, which can simultaneously meet the requirements of high probability of ion beam irradiation to the eutectic film surface and low process difficulty.

[0021] In addition, the current for forming the ion beam is 10 mA to 300 mA, and the voltage is 100 to 2000 V. This can simultaneously meet the requirements of good removal of the eutectic film, low production cost, and high efficiency of interconnecting the locations to be interconnected on the second device part with the locations to be interconnected on the first device part through the solder body.

[0022] Furthermore, the total height of the solder body is 2 μm to 20 μm. When the spacing between adjacent pixels is 1 μm to 15 μm, the solder body adopting this height range can reduce the degree of lateral deformation of the solder body during the interconnection process, avoid contact between adjacent solder bodies, and prevent series connection between pixels, thereby preventing semiconductor device failure and improving semiconductor device reliability. In addition, it provides a larger space for subsequent packaging with filler, and the sufficient flow of filler reduces the generation of bubbles, thereby improving the yield rate of semiconductor devices.

[0023] The present invention also provides a semiconductor device, which is prepared by the method for preparing the semiconductor device of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0025] Figure 1 A flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0026] Figures 2 to 10 A schematic structural diagram of a semiconductor device manufacturing process according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present invention more apparent, various embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in various embodiments of the present invention to help readers better understand the present invention. However, even without these technical details and various variations and modifications based on the following embodiments, the technical solutions claimed in the present invention can still be implemented.

[0028] An embodiment of the present invention provides a method for preparing a semiconductor device, referring to Figure 1 ,include:

[0029] Step S1: forming a seed layer and a solder body in sequence at a location to be interconnected on the first device portion; during the process of forming the solder body, atoms in the solder body and atoms in the seed layer diffuse into each other, forming a eutectic film on the sidewall of the solder body;

[0030] Step S2: etching the eutectic film to remove the eutectic film;

[0031] Step S3: After etching the eutectic film, interconnect the locations to be interconnected on the second device portion with the locations to be interconnected on the first device portion via a soldering body.

[0032] In this embodiment, since a certain tensile stress is generated on the first device part during the process of forming the eutectic film, the eutectic film on the side wall of the welding body is etched to remove the eutectic film, which can release the tensile stress generated by the eutectic film on the first device part, improve the adhesion of the seed layer at the position to be interconnected, and enhance the contact ability between the first device part and the seed layer. At the same time, a clean interface is provided for the interconnection between the position to be interconnected on the second device part and the position to be interconnected on the first device part, thereby improving the stability of the interconnection and making the reliability of the semiconductor device high.

[0033] In one embodiment, the process for etching the eutectic film includes a dry etching process, such as an ion beam etching process. Dry etching processes have the advantages of smooth surface, high uniformity, strong stability, and manufacturability, and can improve the accuracy of etching the eutectic film. In other embodiments, the process for etching the eutectic film includes a wet etching process.

[0034] Ion etching is a method of processing the surface of a eutectic film using a high-energy ion beam. The ion beam is generated by an ion source, accelerated and focused by an accelerator into a high-speed ion beam, which then bombards the surface of the eutectic film. The ion beam bombards the surface of the eutectic film, sputtering atoms from the surface and achieving the desired etching effect.

[0035] Specifically, the step of etching the eutectic film includes: using a rotating member to drive the first device portion, the seed layer, and the solder body to rotate circumferentially around the central axis of the first device portion; and simultaneously irradiating an ion beam toward the surface of the first device portion having the eutectic film. The ion beam can evenly irradiate the surface of the eutectic film to etch the eutectic film, thereby improving the accuracy of the etching process.

[0036] In one embodiment, the rotation speed is 1 r / min to 20 r / min, for example, 1 r / min, 5 r / min, 10 r / min, 15 r / min or 20 r / min. If the rotation speed is less than 1 r / min, the etching time is too long and the production efficiency is low; if the rotation speed is greater than 20 r / min, the etching rate of the eutectic film in the middle area of ​​the first device part and the edge area will be greatly different. Therefore, a rotation speed of 1 r / min to 20 r / min can simultaneously meet the requirements of high production efficiency and consistent etching rate. It should be noted that the rotation speed is not limited to this.

[0037] In one embodiment, irradiating the ion beam toward the surface of the first device portion having the eutectic film includes irradiating the ion beam toward the surface of the eutectic film from a side of the first device portion having the eutectic film, with the ion beam offset from the central axis and at an angle less than 90°. This can increase the probability of the ion beam irradiating the surface of the eutectic film, enhance the etching effect on the eutectic film, and improve the ability of the to-be-interconnected position on the second device portion to be interconnected with the to-be-interconnected position on the first device portion via the solder body.

[0038] In one embodiment, the first device part, the seed layer and the welding body can be controlled to rotate together, the ion beam can be controlled to rotate, or the first device part, the seed layer and the welding body can be controlled to rotate together while the ion beam is controlled to rotate, as long as the ion beam is irradiated from the side of the first device having the eutectic film in a direction that deviates from the center axis by less than 90°.

[0039] In one embodiment, the size of the deviation angle is 1° to 75°, for example, 1°, 10°, 30°, 60° or 75°. If the size of the deviation angle is less than 1°, the effect of increasing the probability of the ion beam irradiating the surface of the eutectic film is small, and the process difficulty is high; if the size of the deviation angle is greater than 75°, the range of the ion beam irradiating the surface of the eutectic film becomes narrower, and the effect of increasing the probability of the ion beam irradiating the surface of the eutectic film is small. Therefore, the size of the deviation angle of 1° to 75° can simultaneously take into account the requirements of a high probability of the ion beam irradiating the surface of the eutectic film and a low process difficulty. It should be noted that the size of the deviation angle is not limited to this.

[0040] In one embodiment, the current for forming the ion beam is 10mA to 300mA, for example, 10mA, 50mA, 100mA, 200mA or 300mA. If the current for forming the ion beam is less than 10mA, the time for forming the ion beam is long, the production cost is high, and the ion beam bombards the surface of the eutectic film, causing the atoms on the surface of the eutectic film to sputter. If the current for forming the ion beam is greater than 300mA, the energy of the ion beam irradiating the surface of the eutectic film is large, which easily leads to the separation of the seed layer and the weld body. Therefore, the current for forming the ion beam is 10mA to 300mA, which can simultaneously take into account the requirements of good effect of removing the eutectic film, low production cost and high effect of interconnecting the position to be interconnected on the second device part with the position to be interconnected on the first device part through the weld body. It should be noted that the current for forming the ion beam is not limited to this.

[0041] In one embodiment, the voltage for forming the ion beam is 100V to 2000V, for example, 100V, 500V, 1000V, 1500V or 2000V. If the voltage for forming the ion beam is less than 100V, the time for forming the ion beam is long, the production cost is high, and the ion beam bombards the surface of the eutectic film, causing the atoms on the surface of the eutectic film to sputter. If the voltage for forming the ion beam is greater than 2000V, the energy of the ion beam irradiating the surface of the eutectic film is large, which easily leads to the separation of the seed layer and the weld body. Therefore, the voltage for forming the ion beam is 100V to 2000V, which can simultaneously take into account the requirements of good effect of removing the eutectic film, low production cost and high effect of interconnecting the position to be interconnected on the second device part with the position to be interconnected on the first device part through the weld body. It should be noted that the voltage for forming the ion beam is not limited to this.

[0042] In one embodiment, the first device section is a detection chip and the second device section is a readout circuit; alternatively, the first device section is a readout circuit and the second device section is a detection chip. In other embodiments, the first device section is another semiconductor device or another circuit and the second device section is another semiconductor device or another circuit.

[0043] In one embodiment, when the first device portion is a detection chip, an electrode is provided on one side surface of the first device portion, and the position to be interconnected on the first device portion is located on the electrode of the first device portion. The electrode is used for signal transmission in the semiconductor device.

[0044] In one embodiment, the process of forming the electrode on the first device portion includes: sequentially forming a stack of an initial first electrode layer, an initial second electrode layer, and an initial third electrode layer at the location where the electrode is to be formed in the first device portion; patterning the initial second electrode layer and the initial third electrode layer to form a second electrode and a third electrode; and, during an etching process of the eutectic film, removing a portion of the initial first electrode layer to form a first electrode at the location where the electrode is to be formed; wherein the location to be interconnected is located on the third electrode. The first electrode is an ohmic contact layer that contacts the surface of a pixel in the detection chip; the second electrode is an intermediate transmission layer for transmitting signals generated by the first electrode; and the third electrode is an interconnection layer. The initial first electrode layer is set on the entire surface, which can avoid direct tensile stress on the picture elements of the detection chip during the formation of the eutectic film, thereby protecting the picture elements of the detection chip; at the same time, it improves the adhesion of the electrode on the surface of the picture element and enhances the contact ability between the electrode and the picture element; in the process of etching the eutectic film, part of the initial first electrode layer is removed, so that the dimensions of the formed first electrode, the second electrode and the third electrode along the surface direction of the detection chip are consistent, thereby improving the signal transmission efficiency of the semiconductor device; and reducing the production process and reducing production costs.

[0045] In other embodiments, after the initial first electrode layer, the initial second electrode layer and the initial third electrode layer are stacked in sequence at the position where the electrode is to be formed in the first device part, the initial third electrode layer is patterned, and then, in the process of etching the eutectic film, part of the initial first electrode layer and the initial second electrode layer are removed; the initial first electrode layer, the initial second electrode layer and the initial third electrode layer can also be patterned at the same time.

[0046] In other embodiments, the electrodes are provided in a single layer. The number of electrode layers can be selected according to actual needs, and can also be two layers or more than three layers, which is not limited here.

[0047] In one embodiment, the cross-sectional shape of the electrode along a direction perpendicular to the surface of the detection chip includes but is not limited to a square.

[0048] In another embodiment, when the second device portion is a detection chip, the method includes forming an electrode at a location on the second device portion where the electrode is to be formed. The electrode structure includes one of a single-layer structure, a stacked structure, and a tubular structure. The electrode structure is tubular, and when the location to be interconnected on the second device portion is interconnected with the location to be interconnected on the first device portion, the weld body is located within the tubular structure, thereby reducing the pressure applied during the interconnection process and reducing the degree of lateral deformation of the weld body.

[0049] In one embodiment, a plurality of pixels (not shown) are disposed inside the detection chip, the pixels are disposed opposite to the positions to be interconnected and are connected to the electrodes. In this embodiment, the pixels are connected to the first electrode.

[0050] Several pixels may be arranged in an array, but are not limited thereto.

[0051] In one embodiment, the spacing between adjacent pixels is 1 μm to 15 μm, for example, 1 μm, 5 μm, 7.5 μm, 10 μm or 15 μm. The spacing between adjacent pixels can represent the size of the pixel along the arrangement direction of the pixel, that is, the size of the pixel along the arrangement direction of the pixel is 1 μm to 15 μm. By using pixels of the above size, more pixels can be integrated while the area of ​​the detection chip remains unchanged, which is conducive to the preparation of semiconductor devices with high-density pixels, improving the resolution of semiconductor devices and reducing production costs. In other embodiments, the spacing between adjacent pixels can be greater than 15 μm. The arrangement direction of the pixels is parallel to the surface direction of the detection chip.

[0052] In one embodiment, the method for preparing a semiconductor device further includes: before interconnecting the position to be interconnected on the second device portion with the position to be interconnected on the first device portion via a soldering body, sequentially forming a seed layer and a soldering body at the position to be interconnected on the second device portion; during the process of forming the soldering body, atoms in the soldering body and atoms in the seed layer diffuse with each other, forming a eutectic film on the sidewalls of the soldering body; and etching the eutectic film to remove the eutectic film. Interconnecting the position to be interconnected on the second device portion with the position to be interconnected on the first device portion via the soldering body includes: interconnecting the soldering body at the position to be interconnected on the second device portion with the soldering body at the position to be interconnected on the first device portion. This can further enhance the effect of interconnecting the position to be interconnected on the second device portion with the position to be interconnected on the first device portion.

[0053] In one embodiment, the total height of the solder body is 2 μm to 20 μm, for example, 2 μm, 4 μm, 10 μm, 15 μm, or 20 μm. When the spacing between adjacent pixels is 1 μm to 15 μm, the solder body adopting the above height range can reduce the degree of lateral deformation of the solder body during the interconnection process, avoid contact between adjacent solder bodies, and prevent series connection between pixels, thereby preventing semiconductor device failure and improving semiconductor device reliability. In addition, it provides a larger space for subsequent packaging using underfill, and the sufficient flow of underfill reduces the generation of bubbles, thereby improving the yield rate of semiconductor devices.

[0054] It should be noted that in this embodiment, preferably, a seed layer and a soldering body are sequentially formed at the location to be interconnected on the first device portion, and a seed layer and a soldering body are simultaneously sequentially formed at the location to be interconnected on the second device portion. The total height of the soldering body is the sum of the height of the soldering body at the location to be interconnected on the second device portion and the height of the soldering body at the location to be interconnected on the first device portion.

[0055] In one embodiment, etching the eutectic film includes: using a rotating member to drive the second device portion, the seed layer, and the solder body to rotate circumferentially around a central axis of the second device portion; and simultaneously irradiating an ion beam toward a surface of the second device portion having the eutectic film. The ion beam can uniformly etch the eutectic film, improving the accuracy of the etching process.

[0056] In one embodiment, the process of etching the eutectic film includes a dry etching process, such as an ion beam etching process. In other embodiments, the process of etching the eutectic film includes a wet etching process.

[0057] In one embodiment, irradiating the ion beam toward the surface of the second device portion having the eutectic film includes irradiating the ion beam toward the surface of the eutectic film from a side of the second device portion having the eutectic film, with the ion beam offset from the central axis and at an angle less than 90°. This can increase the probability of the ion beam irradiating the surface of the eutectic film, enhance the etching effect on the eutectic film, and improve the ability of the to-be-interconnected position on the second device portion to be interconnected with the to-be-interconnected position on the first device portion via the solder body.

[0058] In one embodiment, the second device part, the seed layer and the welding body can be controlled to rotate together, the ion beam can be controlled to rotate, or the second device part, the seed layer and the welding body can be controlled to rotate together while the ion beam is controlled to rotate, as long as the ion beam is irradiated from the side of the second device having the eutectic film in a direction that deviates from the center axis by less than 90°.

[0059] In one embodiment, the offset angle is 1° to 75°, for example, 1°, 10°, 30°, 60°, or 75°. An offset angle of 1° to 75° can simultaneously meet the requirements of a high probability of the ion beam irradiating the eutectic film surface and a low process difficulty. It should be noted that the offset angle is not limited to this.

[0060] In one embodiment, the current for forming the ion beam is 10 mA to 300 mA, and the voltage is 100 to 2000 V. This current of 10 mA to 300 mA and the voltage of 100 to 2000 V can simultaneously achieve good removal of the eutectic film, low production costs, and high efficiency in interconnecting the locations to be interconnected on the second device portion with the locations to be interconnected on the first device portion via the solder body. It should be noted that the current for forming the ion beam is not limited to this.

[0061] The following embodiments are described as examples in which the first device part is a detection chip, the second device part is a readout circuit, a seed layer and a solder body are sequentially formed at the position to be interconnected on the first device part, and a seed layer and a solder body are sequentially formed at the position to be interconnected on the second device part.

[0062] Reference below Figures 2 to 10 , which introduces the preparation process of semiconductor devices in detail.

[0063] refer to Figure 2 A substrate 100 is provided; a plurality of pixels are formed on the substrate 100, and a passivation layer (not shown) is formed between adjacent pixels. The passivation layer can reduce signal interference between the pixels. The surface of the pixel is provided as the location where the electrode is to be formed. In other embodiments, the passivation layer may not be formed.

[0064] In one embodiment, the material of the substrate 100 includes cadmium zinc telluride, the material of the pixel includes mercury cadmium telluride, and the detection chip includes a mercury cadmium telluride chip.

[0065] Regarding the spacing between adjacent picture elements, refer to the description of the aforementioned embodiment.

[0066] refer to Figure 3 An initial first electrode layer 200 a , an initial second electrode layer 210 a , and an initial third electrode layer 220 a are sequentially formed on the surface of the pixel and the substrate 100 .

[0067] In one embodiment, the process for forming the initial first electrode layer 200a includes a deposition process, which includes one or a combination of ion beam deposition process, magnetron sputtering process, and thermal evaporation deposition process; the process for forming the initial second electrode layer 210a includes a deposition process, which includes one or a combination of ion beam deposition process, magnetron sputtering process, and thermal evaporation deposition process; the process for forming the initial third electrode layer 220a includes a deposition process, which includes one or a combination of ion beam deposition process, magnetron sputtering process, and thermal evaporation deposition process.

[0068] In one embodiment, the thickness of the initial first electrode layer 200a is 1 nm to 500 nm, for example, 1 nm, 150 nm, 300 nm, 350 nm, or 500 nm. The total thickness of the initial second electrode layer 210a and the initial third electrode layer 220a is 0.1 μm to 10 μm, for example, 0.1 μm, 3 μm, 5 μm, 7 μm, or 10 μm. The thickness directions of the initial first electrode layer 200a, the initial second electrode layer 210a, and the initial third electrode layer 220a are all perpendicular to the surface of the substrate 100. It should be noted that the thickness of the initial first electrode layer 200a and the total thickness of the initial second electrode layer 210a and the initial third electrode layer 220a are not limited thereto.

[0069] In one embodiment, the material of the initial first electrode layer 200a includes one or a combination of chromium and tin; the material of the initial second electrode layer 210a includes one or a combination of chromium, titanium, palladium, platinum, titanium nitride, and tungsten; and the material of the initial third electrode layer 220a includes one or a combination of aluminum, silver, copper, and gold. In other embodiments, the materials of the initial first electrode layer, the initial second electrode layer, and the initial third electrode layer may also include other metallic conductive materials.

[0070] In one embodiment, during the formation of the initial first electrode layer 200a, the initial second electrode layer 210a and the initial third electrode layer 220a, the temperature of the detection chip is 1°C to 200°C, for example, 50°C, 100°C, 150°C or 200°C.

[0071] refer to Figure 4 The initial second electrode 210a and the initial third electrode layer 220a are patterned at the same time to form the second electrode 210 and the third electrode 220. The surface of the third electrode 220 is the location to be interconnected.

[0072] In this embodiment, after an initial first electrode layer 200a, an initial second electrode layer 210a, and an initial third electrode layer 220a are sequentially formed on the surface of the pixel and the substrate 100, a first photoresist (not shown) is formed on the surface of the initial third electrode layer 220a facing away from the substrate 100; the first photoresist is exposed; the first photoresist is developed; and portions of the initial second electrode layer 210a and the initial third electrode layer 220a are etched away using the remaining first photoresist as a mask, and then the first photoresist is removed.

[0073] During the process of etching away a portion of the initial second electrode layer 210a and the initial third electrode layer 220a using the remaining first photoresist as a mask, an element detector is used for detection to ensure that the etching stops at the surface of the initial first electrode layer 200a.

[0074] In one embodiment, the process of etching and removing part of the initial second electrode layer 210a and the initial third electrode layer 220a includes an ion beam etching process, and the current for forming the ion beam is 10mA to 300mA, for example, 10mA, 50mA, 100mA, 200mA or 300mA; the voltage is 100V to 2000V, for example, 100V, 500V, 1000V, 1500V or 2000V.

[0075] In one embodiment, during the process of etching away a portion of the initial second electrode layer 210 a and the initial third electrode layer 220 a , the temperature of the detection chip is 1° C. to 100° C., for example, 30° C., 50° C., 70° C., or 100° C.

[0076] In one embodiment, the process of forming the first photoresist includes a spin coating process, and the rotation speed is 1000 r / min to 6000 r / min, for example, 1000 r / min, 3000 r / min, 5000 r / min or 6000 r / min.

[0077] In one embodiment, the thickness of the first photoresist is 1 μm to 10 μm, for example, 1 μm, 3 μm, 5 μm, 7 μm or 10 μm; the exposure processing time is 1s to 60s, for example, 10s, 30s, 50s or 60s; the development processing time is 1s to 60s, for example, 10s, 30s, 50s or 60s.

[0078] In one embodiment, after developing the first photoresist, the process further includes baking the first photoresist. This process is intended to dry out moisture from the first photoresist and solidify the first photoresist. In one embodiment, the baking process lasts from 1 minute to 20 minutes, for example, 3 minutes, 5 minutes, 10 minutes, 15 minutes, or 20 minutes.

[0079] refer to Figure 5 and Figure 6 , a seed layer 300 and a welding body 400 are sequentially formed on the surface of the third electrode 220 ; in the process of forming the welding body 400 , atoms in the welding body 400 and atoms in the seed layer 300 diffuse with each other, and a eutectic film 500 is formed on the side wall of the welding body 400 .

[0080] In one embodiment, the steps of sequentially forming the seed layer 300 and the solder body 400 on the surface of the third electrode 220 include: forming a patterned photoresist 600 (refer to FIG. Figure 5 ), the patterned photoresist 600 exposes the surface of the third electrode 220; a seed layer 300 and an initial welding body 400a are formed in sequence on the surface of the third electrode 220 (continued to refer to Figure 5 ); thereafter, removing the patterned photoresist 600; stripping the initial welding body 400a; and performing a heat treatment to form a welding body 400 (reference Figure 6 ).

[0081] In one embodiment, the step of forming the seed layer 300 includes a deposition process, and the deposition process includes one or a combination of ion beam deposition process, magnetron sputtering process, and thermal evaporation deposition process.

[0082] In one embodiment, the seed layer has a thickness of 1 nm to 500 nm, such as 50 nm, 100 nm, 150 nm, 300 nm, 400 nm or 500 nm. In one embodiment, the weld body 400 has a height of 1 μm to 10 μm, such as 1 μm, 3 μm, 5 μm, 7 μm or 10 μm.

[0083] In one embodiment, the shape of the cross section of the welding body 400 along the direction perpendicular to the surface of the substrate 100 includes a circle or an ellipse. When the shape of the cross section of the welding body 400 along the direction perpendicular to the surface of the substrate 100 includes a circle, the diameter of the welding body 400 is 1 μm to 15 μm, for example, 1 μm, 5 μm, 7.5 μm, 10 μm or 15 μm.

[0084] In one embodiment, the material of the seed layer 300 includes one or a combination of gold, silver, and copper. In other embodiments, the material of the seed layer includes other metal materials.

[0085] In one embodiment, the material of the solder body 400 includes, but is not limited to, indium.

[0086] In one embodiment, the step of forming a patterned photoresist 600 on the surface of the initial first electrode layer 200a and the third electrode 220 includes: forming an initial photoresist (not shown) on the surface of the initial first electrode layer 200a and the third electrode 220; exposing the initial photoresist; and then developing the initial photoresist.

[0087] In one embodiment, the process of forming the initial photoresist includes a spin coating process, with a rotation speed of 1 r / min to 6000 r / min, for example, 1 r / min, 1000 r / min, 3000 r / min, 5000 r / min or 6000 r / min.

[0088] In one embodiment, the thickness of the initial photoresist is 1 μm to 10 μm, for example, 1 μm, 3 μm, 5 μm, 7 μm or 10 μm; the exposure processing time is 1s to 60s, for example, 10s, 30s, 50s or 60s; the development processing time is 1s to 60s, for example, 10s, 30s, 50s or 60s.

[0089] In one embodiment, after developing the initial photoresist, the process further includes baking the initial photoresist. This process is intended to dry out moisture from the initial photoresist and solidify the initial photoresist. In one embodiment, the baking time is 1 to 20 minutes, for example, 3 minutes, 5 minutes, 10 minutes, 15 minutes, or 20 minutes.

[0090] In one embodiment, the dimension of the third electrode 220 exposed by the patterned photoresist 600 parallel to the surface of the substrate 100 is 1 μm to 15 μm, for example, 1 μm, 5 μm, 7.5 μm, 10 μm, or 15 μm. That is, the dimension of the third electrode 220 in the semiconductor device parallel to the surface of the substrate 100 is 1 μm to 15 μm, representing the dimension of the position of the electrode to be formed in the first device portion parallel to the surface of the substrate 100.

[0091] refer to Figure 7 , the eutectic film 500 is etched to remove the eutectic film 500 .

[0092] The description of the etching process for the eutectic film 500 refers to the description of the previous embodiment.

[0093] In this embodiment, during the etching process of the eutectic film 500 , a portion of the initial first electrode layer 200 a is removed to form the first electrode 200 at the location where the electrode is to be formed.

[0094] refer to Figure 8, a readout circuit 700 is provided, and a seed layer 300 and a welding body 400 are sequentially formed on the surface of the readout circuit 700; in the process of forming the welding body 400, atoms in the welding body 400 and atoms in the seed layer 300 diffuse with each other, and a eutectic film 500 is formed on the side wall of the welding body 400.

[0095] Part of the surface of the readout circuit 700 is set as a location to be interconnected with the readout circuit 700.

[0096] In one embodiment, the steps of sequentially forming a seed layer 300 and a welding body 400 on the surface of the readout circuit 700 include: forming a second photoresist (not shown) on the surface of the readout circuit 700; exposing the second photoresist; developing the second photoresist so that the second photoresist exposes the surface of the readout circuit 700, and sequentially forming a seed layer 300 and a welding body 400 on the surface of the readout circuit 700; and then removing the second photoresist.

[0097] Regarding the process description and thickness description of forming the seed layer 300 , and the process description, thickness description, and shape description of the welding body, reference is made to the description of the aforementioned embodiment.

[0098] In one embodiment, the process of forming the second photoresist includes a spin coating process, with a rotation speed of 1 r / min to 6000 r / min, for example, 1 r / min, 1000 r / min, 3000 r / min, 5000 r / min or 6000 r / min.

[0099] In one embodiment, the thickness of the second photoresist is 1 μm to 10 μm, for example, 1 μm, 3 μm, 5 μm, 7 μm or 10 μm; the exposure processing time is 1s to 60s, for example, 10s, 30s, 50s or 60s; the development processing time is 1s to 60s, for example, 10s, 30s, 50s or 60s.

[0100] In one embodiment, after developing the second photoresist, the process further includes baking the second photoresist. This process is intended to dry out moisture from the second photoresist and stabilize the second photoresist. In one embodiment, the baking time is 1 to 20 minutes, for example, 3 minutes, 5 minutes, 10 minutes, 15 minutes, or 20 minutes.

[0101] In one embodiment, the second photoresist exposes a surface of the readout circuit 700 with a size of 1 μm to 15 μm, such as 1 μm, 5 μm, 7.5 μm, 10 μm, or 15 μm. That is, the size of the seed layer 300 and the solder body 400 in the semiconductor device parallel to the surface of the readout circuit 700 is 1 μm to 15 μm, representing the size of the second device portion parallel to the surface of the readout circuit 700 at the location to be interconnected.

[0102] In one embodiment, before the seed layer 300 is sequentially formed on the surface of the readout circuit 700, a photolithography process is performed on the readout circuit 700. The readout circuit 700 is divided into a plurality of sub-circuits, and the plurality of sub-circuits are arranged in a one-to-one correspondence with the plurality of pixels.

[0103] refer to Figure 9 , the eutectic film 500 is etched to remove the eutectic film 500 .

[0104] In this embodiment, the description of the steps of etching the eutectic film 500 refers to the description of the previous embodiment.

[0105] refer to Figure 10 , the position to be interconnected on the readout circuit 700 is interconnected with the position to be interconnected on the third electrode 220 through the welding body 400.

[0106] The steps of interconnecting the position to be interconnected on the readout circuit 700 with the position to be interconnected on the third electrode 220 through the welding body 400 include: arranging the detection chip and the readout circuit 700 relative to each other; applying pressure to the side of the readout circuit 700 facing away from the detection chip and / or the side of the detection chip facing away from the readout circuit 700; and performing reflow soldering on the welding body 400 and the third electrode 220.

[0107] In one embodiment, the pressure applied to the side of the readout circuit 700 facing away from the detection chip and / or the side of the detection chip facing away from the readout circuit 700 is 1×10 3 Pa~1x10 7 Pa, for example, 1x10 3 Pa, 1x10 4 Pa, 1x10 5 Pa or 1x10 7 Pa. In other embodiments, the pressure may be adjusted according to the size of the detection chip and / or the readout circuit.

[0108] In one embodiment, the reflow soldering process temperature is 100° C. to 300° C., such as 100° C., 200° C. or 300° C., and the reflow soldering process time is 1 hour to 24 hours, such as 1 hour, 5 hours, 10 hours, 17 hours or 24 hours.

[0109] In one embodiment, before applying pressure to the side of the readout circuit 700 facing away from the detection chip and / or the side of the detection chip facing away from the readout circuit 700, the method further includes heating the detection chip and the readout circuit 700. During the heating process of the detection chip and the readout circuit 700, the solder body 400 becomes softer, which facilitates closer contact between the solder body 400 and the third electrode 220 during the subsequent application of pressure.

[0110] In one embodiment, the temperature of the heating treatment is 1° C. to 300° C., for example, 1° C., 50° C., 100° C., 200° C., or 300° C. The temperature of the heating treatment should not be too high to avoid excessive deformation of the weld body.

[0111] In other embodiments, the temperature raising process may not be performed.

[0112] Another embodiment of the present invention further provides a semiconductor device, which is manufactured using the method for manufacturing the semiconductor device provided in the above embodiment.

[0113] In one embodiment, the semiconductor device includes a detector, wherein the detector includes a focal plane detector, wherein the focal plane detector includes an infrared focal plane detector, and wherein the infrared focal plane detector includes a cooled infrared focal plane detector.

[0114] It should be understood that the expressions "mechanism", "device", "component" and the like used in this application are merely a method for distinguishing different components, elements, parts, portions or assemblies at different levels. However, if other expressions can achieve the same purpose, they may be replaced by other expressions.

[0115] Those skilled in the art will understand that the above-mentioned embodiments are specific examples for realizing the present invention, and in actual applications, the technical features of the above-mentioned embodiments can be arbitrarily combined. In order to make the description concise, not all possible combinations of the technical features in the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification, and various changes can be made to them in form and details without departing from the spirit and scope of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: A seed layer and a solder body are sequentially formed at a position to be interconnected on the first device portion; in the process of forming the solder body, atoms in the solder body and atoms in the seed layer diffuse with each other, and a eutectic film is formed on the side wall of the solder body; Performing etching on the eutectic film to remove the eutectic film; After the eutectic film is etched, the position to be interconnected on the second device portion is interconnected with the position to be interconnected on the first device portion through the soldering body.

2. The method for preparing a semiconductor device according to claim 1, wherein: The process for etching the eutectic film includes a dry etching process; wherein, the step of etching the eutectic film includes: using a rotating part to drive the first device part, the seed layer and the welding body to rotate circumferentially around the central axis of the first device part; at the same time, irradiating the ion beam toward the surface of the first device part having the eutectic film.

3. The method for preparing a semiconductor device according to claim 2, characterized in that: The step of irradiating the ion beam toward a surface of the first device portion having the eutectic film includes: The ion beam is irradiated from the side of the first device having the eutectic film toward the surface of the eutectic film in a direction deviated from the central axis with a deviation angle of less than 90°.

4. The method for preparing a semiconductor device according to claim 3, characterized in that: The deviation angle is between 1° and 75°.

5. The method for preparing a semiconductor device according to claim 2, characterized in that: The current for forming the ion beam is 10mA-300mA, and the voltage is 100V-2000V.

6. The method for preparing a semiconductor device according to claim 1, wherein: The first device section is a detection chip, and the second device section is a readout circuit; or, the first device section is a readout circuit, and the second device section is a detection chip.

7. The method for preparing a semiconductor device according to claim 6, characterized in that: In the case where the first device part is a detection chip, an electrode is provided on one side surface of the first device part, and the position to be interconnected on the first device part is located on the electrode of the first device part.

8. The method for preparing a semiconductor device according to claim 7, characterized in that: The process of forming the electrode on the first device portion includes: Sequentially forming a stacked initial first electrode layer, an initial second electrode layer and an initial third electrode layer at the position where the electrode is to be formed in the first device portion; patterning the initial second electrode layer and the initial third electrode layer to form a second electrode and a third electrode; During the etching process of the eutectic film, a portion of the initial first electrode layer is removed to form a first electrode at the position where the electrode is to be formed; wherein the position to be interconnected is located on the third electrode.

9. The method for preparing a semiconductor device according to claim 7, characterized in that: A plurality of picture elements are arranged inside the detection chip; the picture elements are arranged opposite to the positions to be interconnected and are connected to the electrodes.

10. The method for preparing a semiconductor device according to claim 9, characterized in that: The distance between adjacent picture elements is 1 μm to 15 μm.

11. The method for preparing a semiconductor device according to claim 1 or 6, characterized in that: The method further comprises: Before interconnecting the position to be interconnected on the second device part with the position to be interconnected on the first device part through the welding body, the seed layer and the welding body are sequentially formed at the position to be interconnected on the second device part, and in the process of forming the welding body, atoms in the welding body and atoms in the seed layer diffuse with each other to form a eutectic film on the side wall of the welding body; the eutectic film is etched to remove the eutectic film; The method of interconnecting the position to be interconnected on the second device part with the position to be interconnected on the first device part through the welding body comprises: The soldering body at the position to be interconnected on the second device portion is interconnected with the soldering body at the position to be interconnected on the first device portion.

12. The method for preparing a semiconductor device according to claim 11, characterized in that: The process for etching the eutectic film includes a dry etching process; wherein, the step of etching the eutectic film includes: using a rotating part to drive the second device part, the seed layer and the welding body to rotate circumferentially around the central axis of the second device part; at the same time, irradiating the ion beam toward the surface of the second device part having the eutectic film.

13. The method for preparing a semiconductor device according to claim 12, characterized in that: The step of irradiating the ion beam toward a surface of the second device portion having the eutectic film includes: The ion beam is irradiated from the side of the second device having the eutectic film toward the surface of the eutectic film in a direction deviated from the central axis with an angle smaller than 90°.

14. The method for preparing a semiconductor device according to claim 13, characterized in that: The deviation angle is between 1° and 75°.

15. The method for preparing a semiconductor device according to claim 12, characterized in that: The current for forming the ion beam is 10mA-300mA, and the voltage is 100-2000V.

16. The method for preparing a semiconductor device according to claim 11, characterized in that: The total height of the welded body is 2 μm to 20 μm.

17. A semiconductor device, characterized in that: The semiconductor device is prepared by the method for preparing the semiconductor device according to any one of claims 1 to 16.

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