Method for monitoring performance of SiGe channel
By using zero-marking layer patterns and incisive marking to monitor the thermal annealing temperature during the SiGe channel formation process, the problem of the inability to effectively monitor and adjust the thermal annealing temperature uniformity of the SiGe channel in the prior art is solved, and the silicon germanium channel is realized Performance improvement.
Patent Information
- Application Number
- CN202411524824.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-29
- Publication Date
- 2025-02-14
AI Technical Summary
The prior art cannot effectively monitor and adjust the thermal annealing temperature uniformity of SiGe channels during the formation process, resulting in difficulty in adjusting the performance of SiGe channels in a timely manner.
By forming a zero mark layer pattern and inscribed mark on the silicon substrate on the insulator, the stress effect and thermal annealing temperature change of the silicon germanium channel are monitored using the deviation values of both, and the thermal annealing temperature is adjusted.
Real-time monitoring and adjustment of the thermal annealing temperature of silicon germanium channels is achieved to ensure temperature uniformity and thus improve product performance.
Smart Images
Figure CN119446948A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the field of semiconductor technology, and in particular to a method for monitoring SiGe channel performance. Background Art
[0002] In order to improve the performance of PMOS, the channel of PMOS devices with buried silicon on interlayer (SOI) structure has gradually evolved from Si to SiGe channel. At present, SiGe channel is mainly formed by epitaxial growth of SiGe on SOI in the PMOS region, followed by thermal annealing process. Among them, how to ensure the temperature uniformity of thermal annealing process and prevent stress relaxation of SiGe during the formation of SiGe channel becomes the key technology.
[0003] Currently, the industry mainly evaluates the performance of SiGe channels by evaluating the performance of devices that can be accepted for testing on wafers or by observing whether there are defects in the SiGe channels through transmission electron microscope (TEM) slices. However, this method cannot adjust the SiGe channel performance in a timely manner.
[0004] In order to solve the above problems, a new method for monitoring SiGe channel performance needs to be proposed. Summary of the invention
[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for monitoring SiGe channel performance, so as to solve the problem that the prior art cannot monitor SiGe channel performance.
[0006] To achieve the above objectives and other related objectives, the present invention provides a method for monitoring SiGe channel performance, comprising:
[0007] Step 1, providing a silicon-on-insulator substrate, which is composed of a silicon base layer, a buried layer and a thin silicon layer stacked in sequence from bottom to top, and forming a zero mark layer pattern on the silicon-on-insulator substrate;
[0008] Step 2: forming a silicon germanium epitaxial layer on the thin silicon layer, and forming the thin silicon layer into a silicon germanium channel by thermal annealing;
[0009] Step three, forming an overlay mark on the zero mark layer pattern, and using the deviation value between the two to monitor the stress effect of SiGe and the influence of thermal annealing temperature change on the formation of SiGe channel in the product wafer, so as to adjust the corresponding thermal annealing temperature.
[0010] Preferably, the method for forming the zero mark layer pattern in step one includes: forming a hard mask layer on the thin silicon layer; forming a first photoresist layer on the hard mask layer; photolithographically opening the first photoresist layer to define the formation position of the zero mark layer pattern; forming a groove on the silicon substrate on the insulator by etching; removing the first photoresist layer, and forming a filling layer to fill the groove by deposition and grinding; and removing the hard mask layer.
[0011] Preferably, the material of the hard mask layer in step 1 is silicon nitride.
[0012] Preferably, the hard mask layer in step 1 has a thickness of 50 to 100 angstroms.
[0013] Preferably, the thickness of the first photoresist layer in step 1 is 8000 to 25000 angstroms.
[0014] Preferably, the shape of the zero mark layer pattern in step one is a plurality of squares.
[0015] Preferably, the side length of the square of the zero mark layer pattern in step one is 10 to 18 um.
[0016] Preferably, the depth of the groove in step 1 is 1000 to 3000 angstroms.
[0017] Preferably, the material of the filling layer in step one is an oxide layer.
[0018] Preferably, after depositing the filling layer in step 1, a high temperature annealing step is further included, and the temperature range of the high temperature annealing treatment is 900-1200° C. and the time is 0.5-2 hours.
[0019] Preferably, the grinding method in step one is chemical mechanical planarization grinding.
[0020] Preferably, in step 2, the germanium silicon epitaxial layer is grown by epitaxial growth method, the growth Ge concentration is 10%-50%, and the thickness of the germanium silicon epitaxial layer is 15-50nm.
[0021] Preferably, the thermal annealing in step 2 is performed at a temperature ranging from 900 to 1200° C. for a time ranging from 2 to 60 min; and the gases used are oxygen and inert gas.
[0022] Preferably, the method for forming the overlay mark in step three comprises: forming a second photoresist layer covering the zero mark layer pattern; and photolithographically patterning the second photoresist layer to form an overlay mark located on the zero mark layer pattern.
[0023] Preferably, the thickness of the second photoresist layer in step three is 1500 to 3500 angstroms.
[0024] Preferably, the shape of the overlay mark in step three is a plurality of squares whose side lengths are smaller than the side lengths of the zero mark layer pattern.
[0025] Preferably, the side length of the square in the overlay mark in step three is 6 to 10 um.
[0026] As described above, the method for monitoring SiGe channel performance of the present invention has the following beneficial effects:
[0027] The present invention monitors the thermal annealing temperature of the SiGe channel according to the deviation value of the zero mark layer pattern and the overlay mark, monitors the influence of the thermal annealing temperature change in the wafer on the formation of the SiGe channel in the product wafer, and timely adjusts the uniformity of the thermal annealing temperature for forming the SiGe channel, thereby improving product performance. BRIEF DESCRIPTION OF THE DRAWINGS
[0028] Figure 1 Shown is a schematic diagram of the process flow of the present invention;
[0029] Figure 2 It is a schematic diagram showing the formation of a hard mask layer according to the present invention;
[0030] Figure 3 It is a schematic diagram showing the photolithography opening of the first photoresist layer of the present invention;
[0031] Figure 4 It is a schematic diagram of forming a groove by etching according to the present invention;
[0032] Figure 5 Shown is a schematic diagram of the deposited filling layer of the present invention;
[0033] Figure 6 Shown is a schematic diagram of the grinding filling layer of the present invention;
[0034] Figure 7 Shown is a schematic diagram of removing the hard mask layer of the present invention;
[0035] Figure 8 It is a schematic diagram of forming a germanium silicon epitaxial layer according to the present invention;
[0036] Fig. 9 It is a schematic diagram of forming a germanium silicon channel by annealing according to the present invention;
[0037] Fig.10 Shown is a schematic diagram of forming an overlay mark according to the present invention;
[0038] Fig.11 Shown is a top view schematic diagram of a zero mark layer pattern and an overlay mark according to an embodiment of the present invention. DETAILED DESCRIPTION
[0039] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0040] See also Figure 1 The present invention provides a method for monitoring SiGe channel performance, comprising:
[0041] Step 1: providing a silicon-on-insulator substrate, which is composed of a silicon base layer 101, a buried layer 102 and a thin silicon layer 103 stacked in sequence from bottom to top, and forming a zero mark layer pattern 111 on the silicon-on-insulator substrate;
[0042] In some embodiments, the method for forming the zero mark layer pattern 111 in step 1 includes: forming a hard mask layer 104 on the thin silicon layer 103, and the hard mask layer 104 can be formed by low pressure chemical vapor deposition. Figure 2 The structure shown; forming a first photoresist layer 105 on the hard mask layer 104; photolithography opens the first photoresist layer 105 to define the formation position of the zero mark layer pattern 111, forming as Figure 3 The structure shown in FIG. 1 is a structure in which a groove is formed on a silicon-on-insulator substrate by etching to form a groove. Figure 4 The structure shown in the figure is usually etched by dry etching; the first photoresist layer 105 is removed, and the photoresist layer can usually be removed by wet cleaning, and a filling layer 106 for filling the groove is formed by deposition and grinding, that is, the filling layer 106 is first deposited to form a filling layer 106 as shown in the figure. Figure 5 The structure shown in FIG. 1 is then ground onto the filling layer 106 onto the hard mask layer 104 to form a Figure 6 Remove the hard mask layer 104 to form a Figure 7 In the structure shown, the hard mask layer 104 can be removed by wet etching, and the remaining filling layer 106 serves as the zero mark layer pattern 111.
[0043] In some embodiments, the material of the hard mask layer 104 in step 1 is silicon nitride.
[0044] In some embodiments, the hard mask layer 104 in step 1 has a thickness of 50 to 100 angstroms.
[0045] In some embodiments, the thickness of the first photoresist layer 105 in step 1 is 8000-25000 angstroms.
[0046] In some embodiments, the zero mark layer pattern 111 in step 1 is disposed at various locations of the SiGe channel 109 to monitor the uniformity of the annealing temperature, and is in the shape of a plurality of squares. In other embodiments, the shape of the zero mark layer pattern 111 may also be other shapes.
[0047] In some embodiments, the side length of the square of the zero mark layer pattern 111 in step 1 is 10 to 18 um.
[0048] In some embodiments, the depth of the groove in step 1 is 1000-3000 angstroms.
[0049] In some embodiments, the material of the filling layer 106 in step 1 is an oxide layer.
[0050] In some embodiments, after depositing the filling layer 106 in step 1, a high temperature annealing step is further included, and the temperature range of the high temperature annealing is 900-1200° C. and the time is 0.5-2 hours.
[0051] In some embodiments, the polishing method in step 1 is chemical mechanical planarization polishing.
[0052] Step 2: forming a silicon germanium epitaxial layer 107 on the thin silicon layer 103, forming a silicon germanium epitaxial layer 107 as shown in FIG. Figure 8 The structure shown in FIG. 1 is formed by thermal annealing the thin silicon layer 103 into a germanium silicon channel 109, and the germanium diffuses downward, and the thin silicon layer 103 is formed into a thermal oxide layer 108, forming a Fig. 9 The structure shown;
[0053] In some embodiments, in step 2, the germanium-silicon epitaxial layer 107 is grown by epitaxial growth, the germanium concentration is 10%-50%, and the thickness of the germanium-silicon epitaxial layer 107 is 15-50 nm.
[0054] In some embodiments, the temperature range of the thermal annealing in step 2 is 900-1200° C., and the time is 2-60 min; the gases used are oxygen and inert gas.
[0055] Step 3: forming an overlay mark 110 on the zero mark layer pattern 111, forming Fig.10 The structure shown uses the deviation value of the two to monitor the stress effect of SiGe and the influence of the thermal annealing temperature change on the formation of the SiGe channel 109 of the product wafer, so as to adjust the corresponding thermal annealing temperature.
[0056] In some embodiments, the method for forming the overlay mark 110 in step three includes: forming a second photoresist layer covering the zero mark layer pattern 111 ; and photolithographically patterning the second photoresist layer to form the overlay mark 110 located on the zero mark layer pattern 111 .
[0057] In some embodiments, the thickness of the second photoresist layer in step three is 1500-3500 angstroms.
[0058] In some embodiments, the shape of the overlay mark 110 in step 3 is a plurality of squares whose side lengths are smaller than the side lengths of the zero mark layer pattern 111. In other embodiments, the shape of the overlay mark 110 may also be other shapes.
[0059] In some embodiments, the side length of the square in the overlay mark 110 in step three is 6 to 10 um.
[0060] See also Fig.10 The shapes of the overlay mark 110 and the zero mark layer pattern 111 are preferably squares. By measuring the deviation values of the two in the X / Y direction, the thermal annealing temperature of the germanium silicon channel 109 is monitored, and the influence of the thermal annealing temperature change in the chip on the formation of the germanium silicon channel 109 in the product chip is monitored. The uniformity of the thermal annealing temperature of the germanium silicon channel 109 is adjusted in time, thereby improving product performance.
[0061] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner. Therefore, the drawings only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.
[0062] In summary, the present invention monitors the thermal annealing temperature of the SiGe channel according to the deviation value of the zero mark layer pattern and the overlay mark, monitors the influence of the change of the thermal annealing temperature in the wafer on the formation of the SiGe channel of the product wafer, and timely adjusts the uniformity of the thermal annealing temperature of the SiGe channel formation, thereby improving the product performance. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0063] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.
Claims
1. A method for monitoring SiGe channel performance, characterized in that: include: Step 1, providing a silicon-on-insulator substrate, which is composed of a silicon base layer, a buried layer and a thin silicon layer stacked in sequence from bottom to top, and forming a zero mark layer pattern on the silicon-on-insulator substrate; Step 2: forming a silicon germanium epitaxial layer on the thin silicon layer, and forming the thin silicon layer into a silicon germanium channel by thermal annealing; Step three, forming an overlay mark on the zero mark layer pattern, and using the deviation value between the two to monitor the stress effect of SiGe and the influence of thermal annealing temperature change on the formation of SiGe channel in the product wafer, so as to adjust the corresponding thermal annealing temperature.
2. The method for monitoring SiGe channel performance according to claim 1, characterized in that: The method for forming the zero mark layer pattern in step one includes: forming a hard mask layer on the thin silicon layer; forming a first photoresist layer on the hard mask layer; photolithographically opening the first photoresist layer to define the formation position of the zero mark layer pattern; using etching to form a groove on the silicon substrate on the insulator; removing the first photoresist layer, and forming a filling layer to fill the groove by deposition and grinding; and removing the hard mask layer.
3. The method for monitoring SiGe channel performance according to claim 2, characterized in that: The material of the hard mask layer in step 1 is silicon nitride.
4. The method for monitoring SiGe channel performance according to claim 2, characterized in that: The thickness of the hard mask layer in step 1 is 50 to 100 angstroms.
5. The method for monitoring SiGe channel performance according to claim 2, characterized in that: The thickness of the first photoresist layer in step 1 is 8000 to 25000 angstroms.
6. The method for monitoring SiGe channel performance according to claim 2, characterized in that: The shape of the zero mark layer pattern in step 1 is a plurality of squares.
7. The method for monitoring SiGe channel performance according to claim 6, characterized in that: The side length of the square of the zero mark layer pattern in step 1 is 10 to 18 um.
8. The method for monitoring SiGe channel performance according to claim 2, characterized in that: The depth of the groove in step 1 is 1000 to 3000 angstroms.
9. The method for monitoring SiGe channel performance according to claim 2, characterized in that: The material of the filling layer in step 1 is an oxide layer.
10. The method for monitoring SiGe channel performance according to claim 9, characterized in that: After depositing the filling layer in step 1, a high temperature annealing step is also included. The temperature range of the high temperature annealing treatment is 900-1200° C. and the time is 0.5-2 hours.
11. The method for monitoring SiGe channel performance according to claim 2, characterized in that: The grinding method in step 1 is chemical mechanical planarization grinding.
12. The method for monitoring SiGe channel performance according to claim 2, characterized in that: In step 2, the germanium silicon epitaxial layer is grown by epitaxial growth method, the growth Ge concentration is 10%-50%, and the thickness of the germanium silicon epitaxial layer is 15-50nm.
13. The method for monitoring SiGe channel performance according to claim 2, characterized in that: The temperature range of the thermal annealing in step 2 is 900-1200° C., and the time is 2-60 min; the gases used are oxygen and inert gas.
14. The method for monitoring SiGe channel performance according to claim 1, characterized in that: The method for forming the overlay mark in step three includes: forming a second photoresist layer covering the zero mark layer pattern; and photolithographically patterning the second photoresist layer to form an overlay mark located on the zero mark layer pattern.
15. The method for monitoring SiGe channel performance according to claim 14, characterized in that: The thickness of the second photoresist layer in step three is 1500 to 3500 angstroms.
16. The method for monitoring SiGe channel performance according to claim 6 or 7, characterized in that: The shape of the overlay mark in step three is a plurality of squares whose side lengths are smaller than the side lengths of the zero mark layer pattern.
17. The method for monitoring SiGe channel performance according to claim 16, characterized in that: The side length of the square in the overlay mark in step three is 6 to 10 um.