Semiconductor package and manufacturing method thereof
By designing slots on the packaging substrate of the semiconductor package and setting the semiconductor wafer to face the slots, the problem that existing semiconductor packages are difficult to detect internally is solved, and more efficient experimental design and manufacturing is achieved.
Patent Information
- Application Number
- CN202311230699.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2023-08-02
- Filing Date
- 2023-09-22
- Publication Date
- 2025-02-14
AI Technical Summary
Existing semiconductor packages are difficult to detect internally, limiting the efficiency of experimental design and manufacturing.
A semiconductor package is designed, wherein the package substrate has slot holes, and the semiconductor wafer is arranged on the package substrate, and has a wafer circuit facing the slot holes. Through the slots of the package substrate, the wafer circuit of the semiconductor wafer can be detected, repaired or modified.
The detection, repair or modification of semiconductor wafers can be conveniently performed through the slots of the packaging substrate, improving the internal accessibility of the packaging and manufacturing efficiency.
Smart Images
Figure CN119447044A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to a semiconductor package and a manufacturing method thereof. Background Art
[0002] Design of experiment (DOE) is a widely used method in the design and manufacture of semiconductor packages. In order to facilitate the implementation of DOE, semiconductor packages should be designed to facilitate internal probing. Summary of the invention
[0003] One aspect of the present disclosure is to provide a semiconductor package that is easy to perform internal detection and a method for manufacturing the semiconductor package.
[0004] According to some embodiments of the present disclosure, a semiconductor package includes a package substrate, a semiconductor chip, a plurality of conductive bumps, and a molding material. The package substrate has a first surface, a second surface opposite to the first surface, and at least one slot extending from the first surface to the second surface. The semiconductor chip is disposed on the package substrate and includes a chip circuit, which faces the slot of the package substrate. The conductive bump is located between the package substrate and the semiconductor chip, and the conductive bump electrically connects the semiconductor chip to the package substrate. The molding material covers the semiconductor chip and the conductive bump.
[0005] In one or more embodiments of the present disclosure, a vertical projection of the slot on the semiconductor wafer at least partially overlaps with the wafer circuit.
[0006] In one or more embodiments of the present disclosure, the semiconductor chip has a central portion, the chip circuit is located in the central portion, and the semiconductor chip further includes a plurality of bonding pads, which are arranged around the central portion and connected to the conductive bumps.
[0007] In one or more embodiments of the present disclosure, the package substrate has a central portion, the slot is located in the central portion, and the package substrate includes a plurality of first conductive pads, which are arranged around the central portion and connected to the conductive bumps.
[0008] In one or more embodiments of the present disclosure, the package substrate further includes a plurality of second conductive pads and a plurality of conductive lines. The first conductive pad is located on the first surface, and the second conductive pad is located on the second surface. The conductive line electrically connects the first conductive pad to the second conductive pad. The second conductive pad and the conductive line are arranged around the central portion.
[0009] In one or more embodiments of the present disclosure, the semiconductor package further comprises a plurality of external connection terminals, which are attached to a second surface of the package substrate away from the semiconductor chip. The package substrate has a central portion, the slot is located in the central portion, and the external connection terminals are arranged around the central portion.
[0010] In one or more embodiments of the present disclosure, the chip circuit includes at least one of a detection circuit and a data signal circuit.
[0011] In one or more embodiments of the present disclosure, the semiconductor wafer has a first width, and the slot has a second width greater than the first width.
[0012] In one or more embodiments of the present disclosure, the slot portion is located outside the vertical projection of the semiconductor chip onto the packaging substrate.
[0013] In one or more embodiments of the present disclosure, the molding compound fills the slot.
[0014] According to some embodiments of the present disclosure, a method for manufacturing a semiconductor package includes: providing a packaging substrate, the packaging substrate having a first surface, a second surface opposite to the first surface, and at least one slot extending from the first surface to the second surface; disposing a semiconductor chip on the packaging substrate through a flip chip bonding process so that the chip circuit of the semiconductor chip faces the slot; and encapsulating the semiconductor chip with a molding mold.
[0015] In summary, in the semiconductor package disclosed herein, the package substrate has a slot, the semiconductor chip is disposed on the package substrate, and has a chip circuit facing the slot. Through the above configuration, the chip circuit of the semiconductor chip can be used through the slot of the package substrate. The chip circuit can include a detection circuit so that the detection of the semiconductor chip can be performed through the slot of the package substrate. The chip circuit can include a data signal circuit, and the data signal circuit can be modified or repaired through the slot of the package substrate.
[0016] It should be understood that the foregoing general description and the following detailed description are merely exemplary, and are intended to provide further explanation of the invention claimed in this case. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] In order to make the above and other objects, features, advantages and implementation methods of the present disclosure more obvious and understandable, the accompanying drawings are described as follows:
[0018] Figure 1 A schematic cross-sectional view of a semiconductor package according to an embodiment of the present disclosure is shown;
[0019] Figure 2 To illustrate Figure 1 A schematic bottom view of the semiconductor package shown; and
[0020] Figure 3 FIG. 4 is a schematic bottom view of a semiconductor package according to another embodiment of the present disclosure. DETAILED DESCRIPTION
[0021] The following is a detailed description of the embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings. In the drawings and the specification, the same reference numerals are used to represent the same or similar parts as much as possible. However, the specific structural and functional details disclosed herein are only used to describe the exemplary embodiments, and therefore, may be implemented in a variety of alternative forms and should not be considered to be limited to the exemplary embodiments described herein. It should be understood that it is not intended to limit the exemplary embodiments to the specific forms disclosed, but rather to cover all modifications, equivalents and alternatives that fall within the scope of the present disclosure.
[0022] Please refer to Figure 1 as well as Figure 2 . Figure 1 To illustrate a schematic cross-sectional view of a semiconductor package 10 according to an embodiment of the present disclosure, Figure 2 To illustrate Figure 1 FIG. 1 is a schematic bottom view of a semiconductor package 10 shown in FIG. Figure 1 and Figure 2 As shown, the semiconductor package 10 includes a package substrate 20 and a semiconductor chip 30 disposed on the package substrate 20. Specifically, the semiconductor chip 30 is disposed on the package substrate 20 by a flip-chip bonding process. The semiconductor chip 30 adopts a "face-down" configuration, in other words, the semiconductor chip 30 includes a plurality of bonding pads 31, which are disposed on a lower surface 32 of the semiconductor chip 30 and electrically coupled to the package substrate 20.
[0023] like Figure 1 and Figure 2 As shown, the semiconductor package 10 further includes a plurality of conductive bumps 40, which are located between the package substrate 20 and the semiconductor chip 30 and electrically connect the semiconductor chip 30 to the package substrate 20. The conductive bumps 40 can provide signal and power transmission between the semiconductor chip 30 and the package substrate 20. The conductive bumps 40 can be fixed to the bonding pads 31.
[0024] In some embodiments, the semiconductor package 10 is a memory package, such as a DDR5 synchronous dynamic memory (SDRAM) package, and the semiconductor chip 30 is a dynamic memory chip. In some embodiments, the package substrate 20 is a circuit board with circuits arranged thereon. In some embodiments, the conductive bump 40 may include tin (Sn), lead (Pb), nickel (Ni), gold (Au), silver (Ag), copper (Cu), bismuth (Bi), other suitable conductive materials, or any combination of the above materials. In some embodiments, the conductive bump 40 may include a solder ball or a copper pillar.
[0025] In some embodiments, the semiconductor package 10 is a flip-chip package, and the semiconductor chip 30 is electrically connected to the package substrate 20 only through the conductive bumps 40 (that is, the semiconductor package 10 does not have any bonding wires connecting the semiconductor chip 30 and the package substrate 20). Figure 1 The semiconductor package 10 is shown as having a single semiconductor chip, but it should be understood that in other embodiments, the semiconductor package 10 may include more than one semiconductor chip. For example, one or more additional semiconductor chips may be stacked on the semiconductor chip 30, and the one or more additional semiconductor chips stacked on the semiconductor chip 30 may be connected to the semiconductor chip 30 or the package substrate 20 through structures such as conductive bumps, through-silicon vias (TSVs), and bonding wires.
[0026] like Figure 1 and Figure 2 As shown, the semiconductor package 10 further includes a molding compound 50, and the molding compound 50 covers the semiconductor chip 30 and the conductive bumps 40. In other words, the semiconductor chip 30 and the conductive bumps 40 are embedded in the molding compound 50. In some embodiments, the molding compound 50 can cover the top surface of the package substrate 20 and the side and top surfaces of the semiconductor chip 30, and the molding compound 50 can also fill the gap between the semiconductor chip 30 and the package substrate 20. In some embodiments, the molding compound 50 can include polyimide (PI), epoxy, other suitable materials, or any combination of the above materials.
[0027] like Figure 1 and Figure 2As shown, the semiconductor package 10 further includes a plurality of external connection terminals 60, and the external connection terminals 60 are disposed on the package substrate 20. Specifically, the package substrate 20 has a first surface 21 and a second surface 22, and the semiconductor chip 30 is disposed on the first surface 21 of the package substrate 20. The second surface 22 of the package substrate 20 is opposite to the first surface 21, so the second surface 22 is farther away from the semiconductor chip 30 than the first surface 21. The external connection terminals 60 are disposed on the second surface 22 of the package substrate 20, and the external connection terminals 60 are electrically coupled to the semiconductor chip 30 through the circuits of the package substrate 20 and the conductive bumps 40.
[0028] The external connection terminals 60 serve as external connection interfaces of the semiconductor package 10. For example, the external connection terminals 60 may include solder balls, which may be connected to external electronic components (e.g., printed circuit boards) to allow data transmission and power transmission between the semiconductor package 10 and the external electronic components. The external connection terminals 60 may be in the form of a ball grid array (BGA) and may be soldered to an external electronic component such as a printed circuit board. In other embodiments, the external connection terminals 60 may form a fine-pitch ball grid array (FBGA) or a land grid array (LGA). In some embodiments, the external connection terminals 60 may include tin (Sn), lead (Pb), nickel (Ni), gold (Au), silver (Ag), copper (Cu), bismuth (Bi), other suitable conductive materials, or any combination of the above materials.
[0029] like Figure 1 and Figure 2 As shown, the package substrate 20 has at least one slot 23, and the slot 23 extends from the first surface 21 of the package substrate 20 to the second surface 22 (in other words, the slot 23 penetrates the package substrate 20). The semiconductor chip 30 has a chip circuit 35, and the chip circuit 35 is arranged on the lower surface 32 of the semiconductor chip 30 and faces the slot 23 of the package substrate 20. Through the above configuration, the chip circuit 35 of the semiconductor chip 30 can be exposed through the slot 23 of the package substrate 20, and various operations can be performed through the slot 23 of the package substrate 20, such as measuring the signal of the semiconductor chip 30, repairing the circuit of the semiconductor chip 30, or modifying the circuit of the semiconductor chip 30.
[0030] In some embodiments, the chip circuit 35 of the semiconductor chip 30 includes a detection circuit, and the detection circuit can be used to perform signal measurement of the semiconductor chip 30 to facilitate the DOE design of the semiconductor package. In some embodiments, the chip circuit 35 of the semiconductor chip 30 includes a data signal circuit. When the problem of the semiconductor package 10 is found, the data signal circuit can be repaired or modified through the slot 23 of the package substrate 20. In some embodiments, other circuits (for example, a power supply circuit) can also be configured to face the slot 23 of the package substrate 20.
[0031] In some embodiments, the detection or circuit modification of the semiconductor wafer 30 can be performed by a focused ion beam (FIB) technique. The focused ion beam technique can perform etching or deposition at a target location. For example, the focused ion beam technique can be used to cut off unwanted circuits in the semiconductor wafer 30. For example, the focused ion beam technique can be used to deposit conductive materials to form circuits in the semiconductor wafer 30.
[0032] like Figure 1 and Figure 2 As shown, in some embodiments, the vertical projection of the slot 23 projected on the lower surface 32 of the semiconductor chip 30 at least partially overlaps with the chip circuit 35. In other words, the chip circuit 35 partially or completely falls within the vertical projection of the slot 23 projected on the lower surface 32 of the semiconductor chip 30, so that the chip circuit 35 can be conveniently used through the slot 23 of the package substrate 20. In some embodiments, the chip circuit 35 includes at least one of a detection circuit and a data signal circuit. In some embodiments, the detection circuit and the data signal circuit include conductive structures, such as conductive pads and wires.
[0033] In some embodiments, the molding material 50 may be formed by injecting a resin material from the bottom of the packaging substrate 20 (ie, a side of the packaging substrate 20 away from the semiconductor wafer 30 ) through the slot 23 .
[0034] like Figure 1 and Figure 2 As shown, in some embodiments, the semiconductor chip 30 has a first width W1, and the slot 23 of the package substrate 20 has a second width W2 greater than the first width W1, so that the slot 23 partially extends beyond the side of the semiconductor chip 30 in the lateral direction D1, wherein the lateral direction D1 is a direction perpendicular to the stacking direction D2 of the package substrate 20 and the semiconductor chip 30. In other words, in the stacking direction D2, the slot 23 of the package substrate 20 is partially not covered by the semiconductor chip 30. Therefore, the resin material used to form the molding mold 50 can more easily flow to the side and top of the semiconductor chip 30 to cover the semiconductor chip 30.
[0035] like Figure 1 and Figure 2 As shown, in some embodiments, the slot 23 is partially located outside the vertical projection of the semiconductor chip 30 projected on the packaging substrate 20. In some embodiments, the slot 23 has two opposite ends, and at least one of the two opposite ends of the slot 23 is located outside the vertical projection of the semiconductor chip 30 projected on the packaging substrate 20.
[0036] like Figure 1 and Figure 2 As shown, in some embodiments, the molding material 50 fills the slot 23 of the package substrate 20. In some embodiments, the molding material 50 extends beyond the second surface 22 of the package substrate 20 and covers the area around the slot 23. The molding material 50 can provide protection for the chip circuit 35. Before performing internal detection on the semiconductor package 10, the portion of the molding material 50 filled in the slot 23 can be removed to expose the chip circuit 35. In some embodiments, the molding material 50 can be removed by etching.
[0037] like Figure 1 and Figure 2 As shown, in some embodiments, the package substrate 20 has a central portion C1. The package substrate 20 includes a plurality of first conductive pads 25, which are located on the first surface 21 of the package substrate 20 and connected to the conductive bumps 40. The first conductive pads 25 are arranged around the central portion C1, and the slot 23 is located in the central portion C1. Through the above configuration, the slot 23 can be opened on the package substrate 20 without making a significant modification to the circuit layout of the package substrate 20.
[0038] like Figure 1 and Figure 2 As shown, in some embodiments, the package substrate 20 further includes a plurality of second conductive pads 26, which are located on the second surface 22 of the package substrate 20 and connected to the external connection terminals 60. The second conductive pads 26 are arranged around the central portion C1, and the slot 23 is located in the central portion C1.
[0039] like Figure 1 and Figure 2 As shown, in some embodiments, the package substrate 20 further includes a plurality of conductive lines 29, and the conductive lines 29 electrically connect the first conductive pad 25 to the second conductive pad 26. The conductive lines 29 are arranged around the central portion C1, and the slot 23 is located in the central portion C1. In some embodiments, the conductive lines 29 may include one or more conductive wires, one or more conductive via structures, or a combination thereof.
[0040] like Figure 1 and Figure 2As shown, in some embodiments, the semiconductor wafer 30 has a central portion C2. The bonding pads 31 are disposed around the central portion C2 of the semiconductor wafer 30 and connected to the conductive bumps 40. The wafer circuit 35 is located in the central portion C2 of the semiconductor wafer 30 to face the slot 23.
[0041] In some embodiments, the slot 23 may be located below the semiconductor chip 30 but away from the center of the package substrate 20. For example, the slot 23 may be formed between adjacent first conductive pads 25 (or between adjacent second conductive pads 26) and separated from any conductive trace 29. Similarly, the chip circuit 35 may be located away from the center of the semiconductor chip 30 (e.g., between adjacent bonding pads 31) and facing the slot 23.
[0042] Please refer to Figure 3 . Figure 3 FIG. 1 is a schematic bottom view of a semiconductor package 12 according to another embodiment of the present disclosure. The semiconductor package 12 includes a package substrate 20A, a semiconductor chip 30 disposed on the package substrate 20A, a plurality of conductive bumps 40 (not visible in the bottom view of this figure) connecting the semiconductor chip 30 to the package substrate 20A, and a molding material 50 ( Figure 3 The present embodiment is a semiconductor package 12 of the embodiment of the present invention. The semiconductor package 12 of the embodiment of the present invention is provided with a plurality of slots 23A in the package substrate 20A, and the chip circuit 35 of the semiconductor chip 30 faces the plurality of slots 23A in the package substrate 20. In some embodiments, the vertical projection of the plurality of slots 23A in the package substrate 20 onto the semiconductor chip 30 at least partially overlaps with the chip circuit 35.
[0043] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor package (for example, for manufacturing the aforementioned semiconductor package 10 or 12) includes: (a) providing a package substrate 20 or 20A, wherein the package substrate 20 or 20A has a first surface 21, a second surface 22 opposite to the first surface 21, and at least one slot 23 or 23A extending from the first surface 21 to the second surface 22; (b) placing a semiconductor chip 30 on the package substrate 20 or 20A through a flip chip bonding process, so that the semiconductor chip (c) encapsulating the semiconductor chip 30 with a molding mold 50 (e.g., injecting a resin material from the bottom of the package substrate 20 or 20A through the slot 23 or 23A, and then curing the resin material). In some embodiments, the method for manufacturing a semiconductor package further includes: fixing a plurality of external connection terminals 60 to the second surface 22 of the package substrate 20 or 20A (e.g., thereby forming a ball grid array).
[0044] In summary, in the semiconductor package disclosed herein, the package substrate has a slot, the semiconductor chip is disposed on the package substrate, and has a chip circuit facing the slot. Through the above configuration, the chip circuit of the semiconductor chip can be used through the slot of the package substrate. The chip circuit can include a detection circuit so that the detection of the semiconductor chip can be performed through the slot of the package substrate. The chip circuit can include a data signal circuit, and the data signal circuit can be modified or repaired through the slot of the package substrate.
[0045] Although the present disclosure has been described in detail with reference to certain embodiments, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described herein.
[0046] It is obvious to those skilled in the art that various changes and variations can be made to the structure of the present disclosure without departing from the scope or spirit of the present disclosure. In view of this, the present disclosure is intended to cover the changes and variations that fall within the claims.
[0047]
Explanation of symbols
[0048] 10,12:Semiconductor packaging
[0049] 20,20A:Packaging substrate
[0050] 21: First surface
[0051] 22: Second surface
[0052] 23,23A: Slot
[0053] 25: First conductive pad
[0054] 26: Second conductive pad
[0055] 29: Conductive circuit
[0056] 30: Semiconductor wafer
[0057] 31: Bonding pad
[0058] 32: Lower surface
[0059] 35:Chip Circuit
[0060] 40: Conductive bump
[0061] 50: Molding material
[0062] 60: External connection terminal
[0063] C1, C2: Central part
[0064] D1: Lateral direction
[0065] D2: Stacking direction
[0066] W1: First width
[0067] W2: Second width.
Claims
1. A semiconductor package, characterized in that: Include: A packaging substrate having a first surface, a second surface opposite to the first surface, and at least one slot extending from the first surface to the second surface; A semiconductor chip is disposed on the package substrate and includes a chip circuit, wherein the chip circuit faces the slot of the package substrate; A plurality of conductive bumps are located between the packaging substrate and the semiconductor chip, wherein the plurality of conductive bumps electrically connect the semiconductor chip to the packaging substrate; as well as The molding mold covers the semiconductor wafer and the plurality of conductive bumps.
2. The semiconductor package according to claim 1, wherein: A vertical projection of the slot on the semiconductor wafer at least partially overlaps with the wafer circuit.
3. The semiconductor package according to claim 1, wherein: The semiconductor chip has a central part, the chip circuit is located in the central part, and the semiconductor chip further comprises a plurality of bonding pads, which are arranged around the central part and connected to the plurality of conductive bumps.
4. The semiconductor package according to claim 1, wherein: The packaging substrate has a central part, the slot is located in the central part, and the packaging substrate includes a plurality of first conductive pads, which are arranged around the central part and connected to the plurality of conductive bumps.
5. The semiconductor package according to claim 4, wherein: The packaging substrate further includes a plurality of second conductive pads and a plurality of conductive circuits, wherein the plurality of first conductive pads are located on the first surface, the plurality of second conductive pads are located on the second surface, and the plurality of conductive circuits electrically connect the plurality of first conductive pads to the plurality of second conductive pads, wherein the plurality of second conductive pads and the plurality of conductive circuits are arranged around the central portion.
6. The semiconductor package according to claim 1, wherein: It further comprises a plurality of external connection terminals, which are attached to the second surface of the packaging substrate away from the semiconductor chip, wherein the packaging substrate has a central portion, the slot is located in the central portion, and the plurality of external connection terminals are arranged around the central portion.
7. The semiconductor package according to claim 1, wherein: The chip circuit includes at least one of a detection circuit and a data signal circuit.
8. The semiconductor package according to claim 1, wherein: The semiconductor wafer has a first width, and the slot has a second width, which is greater than the first width.
9. The semiconductor package according to claim 1, wherein: The slot portion is located outside the vertical projection of the semiconductor chip onto the packaging substrate.
10. The semiconductor package according to claim 1, wherein: The molding compound fills the slot.
11. A method for manufacturing a semiconductor package, characterized in that: Include: A packaging substrate is provided, wherein the packaging substrate has a first surface, a second surface opposite to the first surface, and at least one slot extending from the first surface to the second surface; Disposing a semiconductor chip on the package substrate by a flip chip bonding process so that a chip circuit of the semiconductor chip faces the slot; as well as The semiconductor wafer is encapsulated with a molding compound.
12. The method for manufacturing a semiconductor package according to claim 11, wherein: A vertical projection of the slot on the semiconductor wafer at least partially overlaps with the wafer circuit.
13. The method for manufacturing a semiconductor package according to claim 11, wherein: The chip circuit includes at least one of a detection circuit and a data signal circuit.