Multi-die packaging structure and chip thereof

Abstract

The present disclosure provides a multi-die package structure and a chip thereof, the multi-die package structure comprising: a first die at least comprising a second conductive layer; a second die; the isolation structure is located on the first tube core and electrically connected with the second tube core, and the isolation structure comprises an insulating dielectric layer; the first conducting layer is positioned above the insulating dielectric layer; at least one of a first conductive layer in the isolation structure and a second conductive layer in the first tube core forms at least one of an isolation inductor, an isolation capacitor and an isolation transformer. The isolation structure electrically connected with the second tube core is arranged on the first tube core, and the first conductive layer in the isolation structure is separated from the second conductive layer in the first tube core through the insulating dielectric layer in the isolation structure, so that the connection and isolation requirements among the multiple tube cores are met, and the isolation voltage-resistant performance of each tube core is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor devices, and in particular to a multi-die packaging structure and a chip thereof. Background Art

[0002] Multi-die packaging is an integrated circuit packaging technology in which multiple dies, each containing a specific functional module or part of the circuit, are manufactured independently and then combined together in the packaging process to form a complete chip.

[0003] In multi-die packaging, the high-voltage die needs to be isolated from the low-voltage die to improve the stability and safety of the circuit. Common high- and low-voltage isolation technologies mainly include magnetic isolation, capacitive isolation, and inductive isolation. For example, two dies made of a silicon substrate are stacked and packaged, and the two stacked dies are connected by organic materials. The conductive layers in the two dies and the organic materials form an isolator to achieve high and low voltage isolation. However, the silicon substrate located between the two conductive layers is a semiconductor material rather than an insulating material. Therefore, the coupling performance of the isolator is poor, and because the thickness uniformity of the organic material is difficult to control and holes are easily formed, the overall voltage resistance performance of the isolator and the stacked die is not stable.

[0004] Therefore, a new multi-die packaging structure and chip thereof need to be proposed to solve the above problems. Summary of the invention

[0005] In view of the above problems, the purpose of the present disclosure is to provide a multi-die packaging structure and a chip thereof, by providing an isolation structure electrically connected to the second die on the first die, and separating the first conductive layer in the isolation structure from the second conductive layer in the first die by an insulating medium layer in the isolation structure, which not only meets the connection and isolation requirements between the multiple die, but also improves the isolation voltage resistance performance of each die.

[0006] According to one aspect of the present disclosure, there is provided a multi-die packaging structure, comprising:

[0007] A first tube core including at least a second conductive layer;

[0008] a second die; and

[0009] an isolation structure, located on the first tube core and electrically connected to the second tube core,

[0010] Wherein, the isolation structure comprises:

[0011] Insulating dielectric layer;

[0012] a first conductive layer located above the insulating dielectric layer; and

[0013] an adhesive layer located below the insulating dielectric layer,

[0014] At least one of the first conductive layer in the isolation structure and the second conductive layer in the first tube core forms at least one of an isolation inductor, an isolation capacitor, and an isolation transformer.

[0015] Optionally, the first tube core is one of a high voltage tube core and a low voltage tube core, and the second tube core is the other of the high voltage tube core and the low voltage tube core, and the isolation structure is used to improve the voltage resistance performance of the first tube core and the second tube core.

[0016] Optionally, the second conductive layer is a top metal layer of the first die or a plurality of conductive stacked layers in the first die.

[0017] Optionally, the first die further includes a semiconductor layer, and the second conductive layer is located above the semiconductor layer.

[0018] Optionally, the material of the insulating medium layer includes at least one of glass, pre-impregnated resin glass fiber cloth, and an adhesive film.

[0019] Optionally, the isolation structure further includes a connection layer, located between the insulating medium layer and the first conductive layer, and used for fixedly connecting the insulating medium layer and the first conductive layer.

[0020] Optionally, the material of the connection layer includes a titanium compound, the first conductive layer is a metal electroplating layer, and the connection layer is a seed layer of the metal electroplating layer.

[0021] Optionally, the first conductive layer is a single conductive layer or a plurality of conductive stacked layers.

[0022] Optionally, the isolation structure further includes an interlayer isolation layer and an interlayer connection layer.

[0023] In the first conductive layer, the interlayer isolation layer and the interlayer connection layer are located between two adjacent conductive stacked layers.

[0024] Optionally, the isolation structure further includes a metal coating layer located on a surface of the first conductive layer.

[0025] Optionally, the material of the adhesive layer includes at least one of mounting glue, polyimide, and pre-impregnated resin glass fiber cloth, and the isolation structure and the first tube core are mounted and fixed via the adhesive layer.

[0026] Optionally, a packaging frame is further included, and the first tube core and the second tube core are respectively fixed on the packaging frame.

[0027] Optionally, the pads on the packaging structure are electrically connected to the first conductive layer of the isolation structure through wire bonding, or the second die includes a third conductive layer, and the third conductive layer is electrically connected to the first conductive layer of the isolation structure through wire bonding.

[0028] Optionally, a packaging layer is further included, for covering the first tube core, the second tube core and the isolation structure.

[0029] According to another aspect of the present disclosure, a chip is provided, comprising the multi-die package structure as described above.

[0030] One of the above technical solutions has the following beneficial effects:

[0031] An isolation structure is provided on the first tube core, and the isolation structure is electrically connected to the second tube core, wherein the first conductive layer and the insulating dielectric layer in the isolation structure and the second conductive layer in the first tube core constitute an isolator structure, for example, forming at least one of an isolation inductor, an isolation capacitor, and an isolation transformer, thereby meeting the connection and signal isolation transmission requirements between the first tube core and the second tube core. At the same time, the first conductive layer and the second conductive layer are separated by the insulating dielectric layer in the isolation structure. Compared with the solution of stacking packaging of two tube cores made of a silicon substrate, the use of the insulating dielectric layer can improve the coupling performance of the isolator and the overall withstand voltage performance of the first tube core and the second tube core. Furthermore, in the isolation structure, an adhesive layer is provided under the insulating dielectric layer, and the isolation structure is bonded and fixed to the first tube core by the adhesive layer. That is to say, the first tube core and the isolation structure can be manufactured separately, which reduces the manufacturing difficulty of the first tube core and the isolation structure and improves the yield rate.

[0032] In some embodiments, by reusing the top metal layer or multiple conductive stacks in the first die as one of the conductive layers (the second conductive layer) constituting the isolator, materials can be greatly saved and the process steps in production can be reduced.

[0033] In some embodiments, the insulating medium layer used to isolate the first conductive layer from the second conductive layer is made of glass. The material of glass is hard and the uniformity of its thickness is easy to control. It is not easy to have holes, so it can improve the overall pressure resistance performance of the packaging structure. In addition, the price of glass is relatively cheap, which can reduce the manufacturing cost of the packaging structure and its chip.

[0034] In some embodiments, the insulating dielectric layer used to isolate the first conductive layer from the second conductive layer is composed of a pre-impregnated resin glass fiber cloth material or an adhesive film, wherein the pre-impregnated resin glass fiber cloth material can withstand a voltage of up to 160V / μm, greatly enhancing the overall voltage resistance of the packaging structure. In addition, since the pre-impregnated resin glass fiber cloth and the adhesive film have good toughness and are not easy to break, the yield rate and service life of the packaging structure and its chip are improved.

[0035] It should be noted that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0037] Figure 1 A schematic diagram of a multi-die packaging structure in the related art is shown;

[0038] Figure 2 A schematic structural diagram of an isolation structure according to a first embodiment of the present disclosure is shown;

[0039] Figure 3 A schematic structural diagram of a first tube core according to a first embodiment of the present disclosure is shown;

[0040] Figure 4 A schematic diagram of the structure after the isolation structure and the first tube die are fixed in the first embodiment of the present disclosure is shown;

[0041] Figure 5 A structural schematic diagram showing a first packaging method of a multi-die packaging structure according to a first embodiment of the present disclosure is shown;

[0042] Figure 6 A structural schematic diagram showing a second packaging method of the multi-die packaging structure of the first embodiment of the present disclosure is shown;

[0043] Figure 7 A schematic structural diagram of an isolation structure according to a second embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0044] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, the same elements or modules are represented by the same or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0045] The present disclosure will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are represented by similar reference numerals. For the sake of clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown. For the sake of simplicity, the semiconductor structure obtained after several steps can be described in one figure.

[0046] It should be understood that when describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or another region, it may mean that it is directly on the other layer or another region, or that other layers or regions are included between it and the other layer or another region. Furthermore, if the device is turned over, the layer or a region will be "below" or "beneath" another layer or another region.

[0047] If the purpose is to describe the situation of being directly on another layer or another area, this article will use expressions such as "directly on..." or "on... and adjacent to...".

[0048] Many specific details of the present disclosure are described below, such as device structure, materials, dimensions, processing technology and techniques, so as to more clearly understand the present disclosure. However, as those skilled in the art will appreciate, the present disclosure may not be implemented in accordance with these specific details.

[0049] At the same time, certain words are used in this patent specification and claims to refer to specific components. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same component. This patent specification and claims do not use differences in names as a way to distinguish components, but rather use differences in components' functions as the criteria for distinction.

[0050] In addition, it should be noted that, in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the process, method, article or equipment including the elements.

[0051] Figure 1 A schematic structural diagram of a multi-die packaging structure in the related art is shown.

[0052] like Figure 1 As shown, in the related art, the multi-die package structure includes a first die 10, a second die 20 and a dielectric layer 30. The first die 10 includes a silicon substrate 11 and a FAB top metal 12 located on the silicon substrate 11. The second die 20 includes a silicon substrate 21 and a FAB top metal 22 located on the silicon substrate 21, wherein the FAB top metal is a metal layer added in the last stage of the manufacturing process of the die. The die is a crystal grain before the chip is packaged, which is a small piece cut from a wafer.

[0053] The first tube core 10 and the second tube core 20 are stacked and packaged, and the dielectric layer 30 is located between the FAB top metal 12 and the silicon substrate 21, and is used to fix the stacked first tube core 10 and the second tube core 20. The material of the dielectric layer 30 is pre-impregnated resin fiberglass cloth (prepreg, PP), which is an organic insulating material, and serves as an electrical isolation medium between the FAB top metal 12 and the FAB top metal 22.

[0054] See also Figure 1 In addition to the electrical isolation medium composed of PP material, there is also a silicon substrate 21 between the FAB top metal 12 and the FAB top metal 22. The thickness of the silicon substrate 21 increases the distance between the FAB top metal 12 and the FAB top metal 22. Moreover, the silicon substrate 21 is a semiconductor material and is also conductive, resulting in poor coupling performance of the isolator. In addition, since the PP material is an organic material, its thickness uniformity is difficult to control and it is easy to form holes. If the withstand voltage of the isolator is required to reach 3000V, the holes or process impurities in the PP material can easily cause the area to be easily broken down, resulting in the overall withstand voltage performance of the isolator being unstable.

[0055] In view of the above problems, the purpose of the present disclosure is to provide a multi-die packaging structure and a chip thereof, by providing an isolation structure electrically connected to the second die on the first die, and separating the first conductive layer in the isolation structure from the second conductive layer in the first die by an insulating medium layer in the isolation structure, which not only meets the connection and isolation requirements between the multiple die, but also improves the voltage resistance performance of each die.

[0056] Figure 2 A schematic structural diagram of the isolation structure of the first embodiment of the present disclosure is shown. Figure 3 FIG. 1 shows a schematic structural diagram of a first tube core according to a first embodiment of the present disclosure. Figure 4 A schematic diagram of the structure after the isolation structure and the first tube core are fixed in the first embodiment of the present disclosure is shown.

[0057] like Figures 2 to 4As shown, in this embodiment, the isolation structure 100 includes an insulating dielectric layer 110, a connecting layer 120, a first conductive layer 130 and a metal coating layer 140. Along the thickness direction of the insulating dielectric layer 110, the connecting layer 120, the first conductive layer 130 and the metal coating layer 140 are sequentially stacked on the first surface of the insulating dielectric layer 110. The isolation structure 100 also includes an adhesive layer 101, which is located on the second surface of the insulating dielectric layer 110, wherein the first surface of the insulating dielectric layer 110 is opposite to the second surface. The material of the insulating dielectric layer 110 includes at least one of glass, pre-impregnated resin glass fiber cloth (PP), and adhesive film (ABF), and the adhesive film is usually made of polyimide and / or other high-temperature adhesives. The material of the connecting layer 120 includes titanium compounds, such as TiW, TiCu, etc., and the first conductive layer 130 is a metal layer, such as Cu, Al, Ag, etc. The material of the adhesive layer 101 includes at least one of insulating film adhesive, polyimide, and pre-impregnated resin glass fiber cloth.

[0058] During the manufacturing process of the isolation structure 100, the connection layer 120 is formed on the first surface of the insulating dielectric layer 110 by a deposition process, and then the first conductive layer 130 is formed on the connection layer 120 by an electroplating process. Since metal materials are not easy to directly adhere to glass, PP, and ABF materials, the connection layer 120 serves as a seed layer for electroplating the first conductive layer 130, and the first conductive layer 130 of the auxiliary metal material is fixedly connected to the insulating dielectric layer 110 of the glass, PP, and ABF material.

[0059] The metal coating layer 140 is, for example, Ni, Au, etc. When the material of the first conductive layer 130 is Cu, since Cu is very hard and not conducive to the subsequent wire bonding process, it is necessary to form the metal coating layer 140 on the surface of the first conductive layer 130. If the material of the first conductive layer 130 is Al, which is a softer material, the metal coating layer 140 may not be provided.

[0060] However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may make other arrangements for the materials of the connection layer 120 , the first conductive layer 130 , the adhesive layer 101 , and the metal plating layer 140 as needed.

[0061] like Figure 3 and Figure 4As shown, the first tube core 200 includes a semiconductor layer 210 and a second conductive layer 221 located on the semiconductor layer 210, a pad 222 and an isolation layer 230. The semiconductor layer 210 is, for example, a Si or SiC substrate or a stacked structure composed of a substrate and an epitaxial layer, wherein a CMOS circuit is formed by processes such as doping. The second conductive layer 221 can be a FAB top metal layer, or a stack of multiple conductive layers located on the semiconductor layer 210. The materials of the multiple conductive layers can be metal or polysilicon, etc. The multiple conductive layers are separated by an isolation layer 230, and the material of the isolation layer 230 is, for example, silicon oxide, silicon nitride, etc.

[0062] In some optional embodiments, the adhesive layer 101 is attached to the second surface of the insulating medium layer 110, and a protective film is covered on the adhesive layer 101. When fixedly connected with the first tube core 200, the protective film can be torn off, and the isolation structure 100 and the first tube core 200 are mounted and fixed through the adhesive layer 101, so that the insulating medium layer 110 in the isolation structure 100 and the second conductive layer 221 in the first tube core 200 are fixedly connected through the adhesive layer 101.

[0063] In some other optional embodiments, the adhesive layer 101 may also be attached to the surface of the second conductive layer 221, and a protective film may be covered on the adhesive layer 101. After the protective film is removed, the isolation structure 100 and the first tube core 200 may be mounted and fixed.

[0064] like Figure 4 As shown, after the isolation structure 100 and the first tube core 200 are mounted and fixed by the adhesive layer 101, the first conductive layer 130, the insulating dielectric layer 110 in the isolation structure 100 and the second conductive layer 221 in the first tube core 200 constitute an isolator, wherein the first conductive layer 130 and the second conductive layer 221 are electrically isolated by the insulating dielectric layer 110. At least one of the first conductive layer 130 and the second conductive layer 221 forms at least one of an isolation inductor, an isolation capacitor, and an isolation transformer. In some specific embodiments, the first conductive layer 130 and the second conductive layer 221 are respectively two plates of the isolation capacitor, or the first conductive layer 130 and the second conductive layer 221 are respectively two inductor coils of the isolation transformer.

[0065] Figure 5 A structural schematic diagram of a first packaging method of a multi-die packaging structure of the first embodiment of the present disclosure is shown.

[0066] like Figure 5As shown, the multi-die package structure of the first embodiment of the present disclosure includes an isolation structure 100, a first die 200, a second die 400, a package frame 500 and a package layer (not shown). Among them, the second die 400 includes a semiconductor layer 410 and a third conductive layer 421, a pad 422 and an isolation layer 430 located on the semiconductor layer 410, and the third conductive layer 421 and the pad 422 are the FAB top metal of the second die 400. Pads 510 and 520 are arranged on the package frame 500, the first die 200 carries the isolation structure 100, and the first die 200 and the second die 400 are respectively located on the package frame 500, and the metal plating layer 140 and the third conductive layer 421 are connected, the pad 422 and the pad 510 are connected, and the pad 222 and the pad 520 are connected by a wire bonding process. The package layer is used to cover the first die 200, the second die 400 and the isolation structure 100.

[0067] Figure 6 A structural schematic diagram of a second packaging method of the multi-die packaging structure of the first embodiment of the present disclosure is shown.

[0068] like Figure 6 As shown, the same points as the first packaging method are not repeated here, and the difference is that the packaging frame of the second packaging method includes a first packaging frame 501 and a second packaging frame 502. The first tube core 200 carries the isolation structure 100, the first tube core 200 is located on the packaging frame 501, and the pad 222 is connected to the pad 510 on the packaging frame 501 by wire bonding. The second tube core 400 is located on the packaging frame 502, and the second tube core 400 is electrically connected to the pad 520 through the wiring on the packaging frame 502, and the pad 520 on the packaging frame 502 is connected to the metal coating layer 140 of the isolation structure 100 by wire bonding.

[0069] The present disclosure also provides a chip having the following Figure 5 and Figure 6 In the multi-die packaging structure shown, the high and low voltage isolation circuit of the chip is generally composed of a transmitting end, a receiving end and an isolator. The transmitting end is composed of a circuit in the first die 200, and the receiving end is composed of a circuit in the second die 400. The first die 200 is one of the high voltage die and the low voltage die, and the second die 400 is the other of the high voltage die and the low voltage die. The types of the first die 200 and the second die 400 are not limited here, and technicians in this field can set them according to the specific requirements of the circuit function.

[0070] However, the embodiments of the present disclosure are not limited thereto, and those skilled in the art may make other arrangements for the connection between the lead frame, the first tube core 200 and the second tube core 400 as needed.

[0071] In this embodiment, the first conductive layer 130 and the second conductive layer 221 are electrically isolated directly through the insulating dielectric layer 110. Compared with the situation where there is a semiconductor material such as a silicon substrate between the two conductive layers, the electrical isolation of the two conductive layers directly through the insulating dielectric layer 110 can greatly improve the coupling performance of the isolator.

[0072] The pressure resistance of the glass material can reach 35V / μm, and the insulating dielectric layer 110 of the glass is hard and the thickness uniformity is easy to control, and it is not easy to have holes, so it can improve the overall pressure resistance performance of the isolator, and then improve the pressure resistance performance of the first tube core 200 and the second tube core 400 respectively electrically connected to the isolator. In addition, the price of glass is relatively cheap, which can reduce the manufacturing cost of the multi-die packaging structure and its chip.

[0073] The withstand voltage of the insulating dielectric layer 110 made of pre-impregnated resin glass fiber cloth can reach 160V / μm, which greatly enhances the overall withstand voltage performance of the isolator, and further enhances the withstand voltage performance of the first tube core 200 and the second tube core 400 respectively electrically connected to the isolator. In addition, since the pre-impregnated resin glass fiber cloth and the adhesive film have good toughness and are not easy to break, the yield rate and service life of the multi-tube core packaging structure and its chips are improved.

[0074] Figure 7 A schematic structural diagram of an isolation structure according to a second embodiment of the present disclosure is shown.

[0075] like Figure 7 As shown, the similarities between the isolation structure 101a of the second embodiment of the present disclosure and the isolation structure 100 of the first embodiment are not repeated here. The difference is that the stacked structure 102 of the isolation structure 101a is located on the connection layer 120, and the stacked structure 102 is composed of alternating conductive layers 131, interlayer isolation layers 151 and interlayer connection layers 161, and the top layer of the stacked structure 102 is the conductive layer 131. The metal plating layer 140 is located on the surface of the top conductive layer 131 of the stacked structure 102. Among them, the conductive layer 131 is a metal material, such as Cu, Al, Ag, etc., the interlayer isolation layer 151 is, for example, PP material, ABF material, and the interlayer connection layer 161 is a titanium compound, such as TiCu, TiW, etc. The multiple conductive layers 131 stacked in the stacked structure 102 of this embodiment can replace the first conductive layer 130 of the first embodiment, or the first conductive layer 130 includes multiple conductive stacks, and the multiple conductive stacks serve as one of the plates of the isolation capacitor or one of the inductor coils of the isolation transformer.

[0076] According to the embodiments of the present disclosure as above, these embodiments do not describe all the details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and changes can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present disclosure, so that those skilled in the art can make good use of the present disclosure and the modifications based on the present disclosure. The scope of protection of the present disclosure shall be based on the scope defined by the claims of the present disclosure and their equivalents.

Claims

1. A multi-die packaging structure, comprising: A first tube core including at least a second conductive layer; A second tube core; as well as an isolation structure, located on the first tube core and electrically connected to the second tube core, Wherein, the isolation structure comprises: Insulating dielectric layer; a first conductive layer located above the insulating dielectric layer; and an adhesive layer located below the insulating dielectric layer, At least one of the first conductive layer in the isolation structure and the second conductive layer in the first tube core forms at least one of an isolation inductor, an isolation capacitor, and an isolation transformer.

2. The multi-die package structure according to claim 1, wherein: The first tube core is one of a high voltage tube core and a low voltage tube core, and the second tube core is the other of the high voltage tube core and the low voltage tube core. The isolation structure is used to improve the voltage resistance performance of the first tube core and the second tube core.

3. The multi-die package structure according to claim 1, wherein: The second conductive layer is a top metal layer of the first die or a plurality of conductive stacked layers in the first die.

4. The multi-die package structure according to claim 3, wherein: The first die also includes a semiconductor layer, and the second conductive layer is located above the semiconductor layer.

5. The multi-die package structure according to claim 1, wherein: The material of the insulating medium layer includes at least one of glass, pre-impregnated resin glass fiber cloth, and adhesive film.

6. The multi-die package structure according to claim 5, wherein: The isolation structure further includes a connection layer, which is located between the insulating medium layer and the first conductive layer and is used for fixedly connecting the insulating medium layer and the first conductive layer.

7. The multi-die package structure according to claim 6, wherein: The material of the connection layer includes a titanium compound, the first conductive layer is a metal electroplating layer, and the connection layer is a seed layer of the metal electroplating layer.

8. The multi-die package structure according to claim 1, wherein: The first conductive layer is a single conductive layer or a plurality of conductive stacked layers.

9. The multi-die package structure according to claim 8, wherein: The isolation structure also includes an interlayer isolation layer and an interlayer connection layer. In the first conductive layer, the interlayer isolation layer and the interlayer connection layer are located between two adjacent conductive stacked layers.

10. The multi-die package structure according to claim 1, wherein: The isolation structure further includes a metal coating layer located on the surface of the first conductive layer.

11. The multi-die package structure according to claim 1, wherein: The material of the adhesive layer includes at least one of mounting glue, polyimide, and pre-impregnated resin glass fiber cloth, and the isolation structure and the first tube core are mounted and fixed through the adhesive layer. 12 . The multi-die packaging structure according to claim 1 , further comprising a packaging frame, wherein the first die and the second die are respectively fixed on the packaging frame.

13. The multi-die package structure according to claim 12, wherein: The pads on the packaging structure are electrically connected to the first conductive layer of the isolation structure through wire bonding, or the second die includes a third conductive layer, and the third conductive layer is electrically connected to the first conductive layer of the isolation structure through wire bonding. 14 . The multi-die package structure according to claim 1 , further comprising a packaging layer for covering the first die, the second die and the isolation structure.

15. A chip comprising the multi-die package structure according to any one of claims 1 to 14.

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