Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. A recess in the substrate; the multiple stand columns are arranged at the bottom of the groove in a protruding mode, and the multiple stand columns are separated from one another; according to the multiple stacked electrode layers, the bottommost electrode layer covers all the surfaces of the groove and all the surfaces of the stand column, the other electrode layers are sequentially stacked on the bottommost electrode layer, and the part, located on the side wall of the stand column, of the topmost electrode layer serves as a side wall electrode; the dielectric layers are located between the adjacent electrode layers; and the gaps are positioned between any adjacent side wall electrodes. The invention is beneficial to the performance stabilization of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Deep Trench Capacitor (DTC) is widely used in antenna matching, RF filtering and IC decoupling, especially in applications with height and volume restrictions. It has very high stability and extremely low leakage current under high bias voltage, and plays a vital role in some industrial fields.

[0003] Silicon-based capacitors are replacing ceramic capacitors in the smartphone AP and PMIC terminal markets with their irreplaceable advantages such as miniaturization, high stability, and low ESR / ESL. High-density DTCs increase the effective area of ​​capacitors through three-dimensional structural design, thereby increasing capacitance density.

[0004] The most common design at present is a planar structure with vertical slots parallel or perpendicular to each other. The area of ​​the capacitor unit cell is changed by changing the length of the vertical slots, and then the structure with different customer requirements is constructed by connecting the unit cells in parallel. In this structural design, the interconnect plug (CT) is generally located outside the cell by etching the electrode plate to expose the lower electrode plate for leading out the CT.

[0005] As the number of DTC layers increases, the number of electrode layers will also increase, and the design of CT leads with multiple electrode layers will become difficult. Summary of the invention

[0006] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, which is beneficial to stabilizing the performance of the semiconductor structure.

[0007] To solve the above problems, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a groove located in the substrate; a plurality of pillars protruding from the bottom of the groove, and the plurality of pillars are separated from each other; a plurality of stacked electrode layers, wherein the bottom electrode layer covers various surfaces of the groove and various surfaces of the pillars, and the remaining electrode layers are stacked in sequence on the bottom electrode layer, wherein the portion of the top electrode layer located on the side wall of the pillar serves as a sidewall electrode; a dielectric layer located between adjacent electrode layers; and a gap located between any adjacent sidewall electrodes.

[0008] Optionally, the bottom of the column is connected to the base to form an integrated structure.

[0009] Optionally, the top surface of the post is flush with the top of the groove.

[0010] Optionally, the shape of the column includes a cylindrical shape.

[0011] Optionally, a plurality of columns extending along a first direction constitute a column group, the number of column groups is multiple and they are arranged in parallel along a second direction, in adjacent column groups, the plurality of columns are staggered in the second direction, and the first direction is perpendicular to the second direction; the side wall electrodes on the side walls of three adjacent columns arranged in a triangle form a gap.

[0012] Optionally, the total thickness of the multi-layer stacked electrode layer and dielectric layer satisfies the formula Wherein, T represents the total thickness of the multi-layer stacked electrode layer and dielectric layer, L represents the distance between the centers of adjacent columns arranged in a triangle, and r represents the radius of the column.

[0013] Optionally, the semiconductor structure further includes: a sealing layer, located at the top of the gap and sealing the top of the gap.

[0014] Optionally, the material of the sealing layer includes silicon oxide.

[0015] Optionally, the substrate includes a device area and a lead area adjacent to the device area; the groove is located in the device area; the electrode layer is also located on the top of the substrate in the lead area, and in the lead area, any electrode layer exposes another adjacent electrode layer located therebelow.

[0016] Optionally, the lead area is located on both sides of the device area; the multilayer electrode layer includes alternately stacked first electrode layers and second electrode layers, in any lead area, the first electrode layer exposes the surface of the second electrode layer, and in another lead area, the second electrode layer exposes the surface of the first electrode layer.

[0017] Optionally, the semiconductor structure also includes: a first interconnect plug, located in the lead area and on each exposed electrode layer and electrically connected to the corresponding electrode layer, the number of first interconnect plugs on each electrode layer is multiple and arranged along the extension direction of the lead area, and the extension direction is perpendicular to the direction from the lead area to the device area; multiple first interconnect lines, each first interconnect line corresponds to a first interconnect plug located on the same electrode layer, and is electrically connected to the corresponding multiple first interconnect plugs.

[0018] Optionally, the semiconductor structure further includes: electrode openings, which are respectively located in each electrode layer except the bottom electrode layer and penetrate the electrode layers, wherein the electrode openings of each electrode layer are located at different pillar tops.

[0019] Optionally, a plurality of columns extending along the first direction constitute a column group, the number of column groups is multiple and arranged in parallel along the second direction; the number of electrode layers is n, and the electrode openings of the same electrode layer are located at the top of the columns of the same column group and correspond one-to-one to the columns; along the second direction and according to a preset period, the electrode openings of each electrode layer are distributed in sequence at the top of the columns of different column groups, and each preset period has n adjacent column groups, and the first direction is perpendicular to the second direction.

[0020] Optionally, the semiconductor structure also includes: a plurality of second interconnect plugs, each located on the electrode layer exposed at the bottom of the electrode opening and electrically connected to the corresponding electrode layer; a plurality of second interconnect lines, the second interconnect lines extending along the first direction and located at the top of the second interconnect plugs on the corresponding column group, and the second interconnect lines located at the top of the second interconnect plugs on the same electrode layer are connected in parallel.

[0021] Optionally, among the plurality of second interconnection lines, the second interconnection lines located on top of the second interconnection plugs in the odd-numbered electrode layers are connected in parallel, and the second interconnection lines located on top of the second interconnection plugs in the even-numbered electrode layers are connected in parallel.

[0022] Optionally, the semiconductor structure further includes: a through-hole interconnect structure that passes through the substrate; a groove that surrounds the through-hole interconnect structure and includes a plurality of sub-grooves that are connected in sequence along the circumferential direction; and in each sub-groove, a plurality of columns form a hexagonal column unit.

[0023] Optionally, the material of the electrode layer includes one or more of Si, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al; the material of the dielectric layer includes HfO 2 、HfSiO、TiO 2 , HfZrO, HfSiON, HfTaO, HfTiO, Ta 2 O 5 、ZrO 2 、ZrSiO 2 、Al 2 O 3 、SrTiO 3 , BaSrTiO and SiN.

[0024] Correspondingly, an embodiment of the present invention also provides a method for forming a semiconductor structure, including: providing a substrate; forming a groove in the substrate; forming a column protruding from the bottom of the groove, wherein the plurality of columns are separated from each other; forming a multi-layer stacked electrode layer and a dielectric layer, wherein the bottom electrode layer covers various surfaces of the groove and various surfaces of the column, and the remaining electrode layers are stacked in sequence on the bottom electrode layer, wherein the portion of the top electrode layer located on the side wall of the column serves as a sidewall electrode, and there is a gap between any adjacent sidewall electrodes.

[0025] Optionally, the steps of forming a groove in the substrate and forming a pillar protruding from the bottom of the groove include: patterning the substrate, forming a groove in the substrate and a plurality of pillars protruding from the bottom of the groove.

[0026] Optionally, in the step of forming a column protruding from the bottom of the groove, the shape of the column includes a cylindrical shape.

[0027] Optionally, in the step of forming columns, a plurality of columns extending along a first direction constitute a column group, the number of column groups is multiple and they are arranged in parallel along a second direction, and in adjacent column groups, a plurality of columns are staggered in the second direction, and the first direction is perpendicular to the second direction; in the step of forming an electrode layer, side wall electrodes on the side walls of three adjacent columns arranged in a triangle form a gap.

[0028] Optionally, in the step of forming the electrode layer, the total thickness of the multi-layer stacked electrode layer and the dielectric layer satisfies the formula Wherein, T represents the total thickness of the multi-layer stacked electrode layer and dielectric layer, L represents the distance between the centers of adjacent columns arranged in a triangle, and r represents the radius of the column.

[0029] Optionally, after forming the electrode layer and the dielectric layer, the forming method further includes: forming a sealing layer on the top of the sealing gap.

[0030] Optionally, in the step of providing a substrate, the substrate includes a device area and a lead area adjacent to the device area; in the step of forming a groove, the groove is located in the device area; in the step of forming an electrode layer, the electrode layer is also located on the top of the substrate in the lead area, and in the lead area, any electrode layer exposes another adjacent electrode layer located therebelow.

[0031] Optionally, in the step of providing a substrate, the lead areas are located on both sides of the device area; in the step of forming the electrode layer, the multilayer electrode layer includes alternately stacked first electrode layers and second electrode layers, and in any lead area, the first electrode layer exposes the surface of the second electrode layer, and in another lead area, the second electrode layer exposes the surface of the first electrode layer.

[0032] Optionally, after forming a multi-layer stacked electrode layer and a dielectric layer, the formation method also includes: forming a first interconnect plug electrically connected to the corresponding electrode layer on each electrode layer exposed in the lead area, the number of the first interconnect plugs on each electrode layer is multiple and arranged along the extension direction of the lead area, and the extension direction is perpendicular to the direction from the lead area to the device area; forming multiple first interconnect lines, each first interconnect line corresponds to a first interconnect plug on the same electrode layer, and is electrically connected to the corresponding multiple first interconnect plugs.

[0033] Optionally, in the step of forming electrode layers, electrode openings are formed in the electrode layers except the bottommost electrode layer, and the electrode openings penetrate the electrode layers, wherein the electrode openings of the electrode layers are located at different pillar tops.

[0034] Optionally, in the step of forming columns, a plurality of columns extending along the first direction constitute a column group, the number of column groups is multiple and arranged in parallel along the second direction; in the step of forming electrode layers, the number of electrode layers is n, and electrode openings of the same electrode layer are located at the tops of columns of the same column group and correspond one-to-one to the columns; in the step of forming electrode layers, along the second direction and according to a preset period, the electrode openings of each electrode layer are sequentially distributed at the tops of columns of different column groups, and each preset period has n adjacent column groups, and the first direction is perpendicular to the second direction.

[0035] Optionally, after forming a multi-layer stacked electrode layer and a dielectric layer, the formation method also includes: forming second interconnect plugs on the electrode layers exposed at the bottom of the electrode openings, respectively, the second interconnect plugs being electrically connected to the corresponding electrode layers; forming a plurality of second interconnect lines on top of the second interconnect plugs, the second interconnect lines extending along the first direction and being located at the top of the second interconnect plugs on the corresponding column group, and the interconnect lines located at the top of the second interconnect plugs on the same electrode layer are connected in parallel.

[0036] Optionally, in the step of forming a plurality of second interconnection lines, the second interconnection lines on top of the second interconnection plugs located in odd-numbered electrode layers are connected in parallel, and the second interconnection lines on top of the second interconnection plugs located in even-numbered electrode layers are connected in parallel.

[0037] Optionally, in the step of providing a substrate, a through-hole interconnection structure penetrating the substrate is formed in the substrate; in the step of forming a groove, the groove surrounds the through-hole interconnection structure and includes a plurality of sub-grooves connected in sequence along the circumferential direction; in the step of forming a column, in each sub-groove, a plurality of columns constitute a hexagonal column unit.

[0038] Optionally, in the step of forming a multi-layer stack of electrode layers and dielectric layers, a furnace tube process is used to form each electrode layer and dielectric layer.

[0039] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0040] In the semiconductor structure provided by the embodiment of the present invention, a plurality of pillars protrude from the bottom of the groove, and the plurality of pillars are separated from each other. The electrode layers are stacked in multiple layers, and the bottom electrode layer covers each surface of the groove and each surface of the pillars. The remaining electrode layers are stacked in sequence on the bottom electrode layer, wherein the portion of the top electrode layer located on the side wall of the pillar serves as a side wall electrode, and the gap is located between any adjacent side wall electrodes. In the embodiment of the present invention, by using the separated pillars, each side surface of the pillar is exposed in the groove, which is conducive to making the stress direction generated by the multi-layer stacked electrode layers in the groove be along the direction perpendicular to each side surface of the pillar. That is, the distribution of stress is more dispersed, thereby improving the problem of stress concentration and reducing the impact of stress on the semiconductor structure. Moreover, there is a gap between any adjacent sidewall electrodes, which is conducive to the release of stress in the gap, and in the subsequent thermal process, the gap can also provide a certain space for the expansion of the film layer, which is beneficial to the stability of the performance of the semiconductor structure. At the same time, the arrangement of columns is adopted, and the remaining space in the groove is used to accommodate the electrode layer and the dielectric layer to form a capacitor. Compared with the traditional use of separate vertical grooves to provide space for forming capacitors, the structural design of this solution is more flexible and compact, which is conducive to improving the integration of the semiconductor structure.

[0041] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a groove is formed in a substrate, and a column protruding from the bottom of the groove is formed. The plurality of columns are separated from each other to form a multi-layer stacked electrode layer and a dielectric layer. In the multi-layer electrode layer, the bottom electrode layer covers each surface of the groove and each surface of the column, and the remaining electrode layers are stacked in sequence on the bottom electrode layer, wherein the portion of the top electrode layer located on the side wall of the column serves as a side wall electrode, and there is a gap between any adjacent side wall electrodes; in the embodiment of the present invention, by using the separated columns, each side of the column is exposed in the groove, which is conducive to making the stress direction generated by the multi-layer stacked electrode layer in the groove along the The direction perpendicular to the sides of the pillars, that is, the distribution of stress is more dispersed, thereby improving the problem of stress concentration and reducing the influence of stress on the semiconductor structure. Moreover, there is a gap between any adjacent sidewall electrodes, which is conducive to the release of stress in the gap, and in the subsequent thermal process, the gap can also provide a certain space for the expansion of the film layer, which is beneficial to the stability of the performance of the semiconductor structure. At the same time, the arrangement of the pillars is adopted, and the remaining space in the groove is used to accommodate the electrode layer and the dielectric layer to form a capacitor. Compared with the traditional use of separate vertical grooves to provide space for forming capacitors, the structural design of this solution is more flexible and compact, which is conducive to improving the integration of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 to Figure 2 It is a schematic diagram of the structure of a semiconductor structure;

[0043] Figures 3 to 6 is a schematic structural diagram of an embodiment of a semiconductor structure of the present invention;

[0044] Figure 7 is a schematic structural diagram of another embodiment of the semiconductor structure of the present invention;

[0045] Figures 8 to 14 is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention;

[0046] Fig.15 It is a schematic structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0047] At present, the performance stability of semiconductor structures needs to be improved. Now, the reasons why the performance stability needs to be improved are analyzed in combination with a semiconductor structure.

[0048] Figure 1 to Figure 2 It is a structural diagram of a semiconductor structure.

[0049] Combined with reference Figure 1 and Figure 2 , Figure 2 for Figure 1 The cross-sectional view of a groove in the semiconductor structure includes: a substrate 10; a plurality of discrete square grooves 20, which are located in the substrate 10; a plurality of stacked electrode layers 11, wherein the bottom electrode layer 11 covers each surface of the groove 20, and the remaining electrode layers 11 are stacked in sequence on the bottom electrode layer 11; and a dielectric layer, which is located between adjacent electrode layers 11.

[0050] In the step of forming a plurality of stacked electrode layers 11 and a dielectric layer between adjacent electrode layers 11 in the square groove 20, due to factors such as different expansion coefficients of different film layers, the plurality of film layers stacked in the groove 20 are prone to generate large stress during the process, and the stress direction is perpendicular to the direction of the side wall of the groove 20, such as Figure 2 The dotted arrows in the middle show tensile stress and compressive stress. The side wall of the square groove 20 is susceptible to greater stress. Figure 1 As shown, the arrangement of the grooves 20 in the substrate 10 is parallel to the X direction and the Y direction. Due to the arrangement of the grooves 20, the stress direction is mainly along the X direction and the Y direction, which can easily lead to a large warping of the substrate 10, affecting the subsequent process of the semiconductor structure and causing the performance of the semiconductor structure to be unstable.

[0051] In order to solve the technical problem, an embodiment of the present invention provides a semiconductor structure, including: a substrate; a groove located in the substrate; a plurality of pillars protruding from the bottom of the groove, and the plurality of pillars are separated from each other; a plurality of stacked electrode layers, the bottom electrode layer covers various surfaces of the groove and various surfaces of the pillars, and the remaining electrode layers are stacked in sequence on the bottom electrode layer, wherein the portion of the top electrode layer located on the side wall of the pillar serves as a sidewall electrode; a dielectric layer located between adjacent electrode layers; and a gap located between any adjacent sidewall electrodes.

[0052] In the embodiment of the present invention, by adopting mutually separate columns, each side of the column is exposed in the groove, which is conducive to making the stress direction generated by the multi-layer stacked electrode layer in the groove along the direction perpendicular to the each side of the column, that is, the distribution of stress is more dispersed, thereby improving the problem of stress concentration and reducing the influence of stress on the semiconductor structure. Moreover, there is a gap between any adjacent sidewall electrodes, which is conducive to the release of stress in the gap, and in the subsequent thermal process, the gap can also provide a certain space for the expansion of the film layer, which is conducive to the stability of the performance of the semiconductor structure. At the same time, the arrangement of the columns is adopted, and the remaining space in the groove is used to accommodate the electrode layer and the dielectric layer to form a capacitor. Compared with the traditional use of separate vertical grooves to provide space for forming capacitors, the structural design of this solution is more flexible and compact, which is conducive to improving the integration of the semiconductor structure.

[0053] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present invention more obvious and easy to understand, the specific embodiments of the present invention are described in detail below with reference to the accompanying drawings. Figures 3 to 6 , showing a schematic structural diagram of an embodiment of a semiconductor structure of the present invention.

[0054] Combined with reference Figures 3 to 6 The semiconductor structure includes: a substrate 100; a groove 200, located in the substrate 100; a plurality of pillars 110, protruding from the bottom of the groove 200, and the plurality of pillars 110 are separated from each other; a plurality of stacked electrode layers 201, the bottom electrode layer 201 covers various surfaces of the groove 200 and various surfaces of the pillars 110, and the remaining electrode layers 210 are stacked in sequence on the bottom electrode layer 210, wherein the portion of the top electrode layer 210 located on the side wall of the pillar 110 serves as the sidewall electrode 101; a dielectric layer (not shown), located between adjacent electrode layers 201; and a gap 200s, located between any adjacent sidewall electrodes 202.

[0055] The substrate 100 is used to provide a process platform for forming a semiconductor structure.

[0056] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0057] In this embodiment, the substrate 100 includes a device region 100A and a lead region 100B adjacent to the device region 100A.

[0058] The device region 100A is used to form a capacitor structure, and the lead region 100B is used to electrically lead out the electrode layer 201 .

[0059] Specifically, in this embodiment, the lead area 100B is located on both sides of the device area 100A, so that the multi-layer electrode layer 201 can be distributed in the lead areas 100B on both sides, and the two adjacent electrode layers 201 are electrically connected from the lead areas 100B on both sides, so that the electrical connection lines of the electrode layers 201 are simplified and easy to implement.

[0060] In this embodiment, the semiconductor structure further includes: a through-hole interconnection structure (not shown) penetrating the substrate 100 .

[0061] The through-hole interconnection structure is used to realize longitudinal electrical connection of wafers and realize longitudinal stacking of wafers. In this embodiment, the through-hole interconnection structure is a through-silicon-via (TSV) structure.

[0062] In this embodiment, the groove 200 is used to provide a spatial position for the formation of the electrode layer 210 and the dielectric layer.

[0063] Accordingly, in this embodiment, the groove 200 is located in the device region 100A.

[0064] In this embodiment, the groove 200 surrounds the through-hole interconnection structure and includes a plurality of sub-grooves (not shown) that are connected in sequence along the circumferential direction; in each sub-groove, a plurality of columns 110 constitute a hexagonal column unit.

[0065] Compared with a square structure in which a plurality of square grooves form a surrounding through-hole interconnection structure, in the present embodiment, a plurality of pillars 110 form a hexagonal honeycomb-shaped pillar unit, and a plurality of pillar units form a ring structure surrounding the through-hole interconnection structure. The honeycomb-shaped pillar units are arranged more compactly, and the ring structure formed by a plurality of pillar units saves more occupied area, which is beneficial to improving the integration of the semiconductor structure.

[0066] In this embodiment, the pillars 110 are used to form the electrode layer 210 on the sidewalls thereof, thereby providing support for the formation of the sidewall electrodes 202 .

[0067] In this embodiment, the pillar 110 is obtained by patterning the substrate 100 , and therefore, the bottom of the pillar 110 is connected to the substrate 100 to form an integrated structure, making it easier to obtain the pillar.

[0068] Moreover, in this embodiment, the groove 200 and the pillar 110 protruding from the bottom of the groove 200 are simultaneously obtained by patterning the substrate 100 , so that the top surface of the pillar 110 is flush with the top of the groove 200 , which is correspondingly beneficial to the formation of the electrode layer 210 .

[0069] In this embodiment, the shape of the pillar 110 includes a cylindrical shape.

[0070] refer to Figure 4 If the pillar 110 is cylindrical, the sidewall electrode 202 located on the sidewall of the pillar 110 is also cylindrical, so that the cross-sections of the sidewall electrodes 202 on the sidewalls of adjacent pillars 110 are in contact, and the corresponding multiple contacting surfaces can form a gap 200s.

[0071] Combined with reference Figure 4 and Figure 5 , Figure 5 for Figure 4 In the cross-sectional view along the AA direction, the pillar 110 is cylindrical, which is conducive to making the stress direction generated by the multi-layer stacked electrode layer 201 in the groove 200 along the diameter direction of the pillar 110 (such as Figure 5 As shown by the dashed arrow in the figure, the stress distribution is more dispersed, thereby improving the problem of stress concentration and reducing the influence of stress on the semiconductor structure.

[0072] In this embodiment, along the first direction (such as Figure 3 A plurality of columns 110 extending and arranged in a second direction (as shown in the X direction) form a column group 111. The number of the column group 111 is multiple and along the second direction (as shown in the X direction) Figure 3 In the adjacent column groups 111, the plurality of columns 110 are staggeredly distributed in the second direction, and the first direction is perpendicular to the second direction.

[0073] A plurality of columns 110 extending and arranged along the first direction constitute a column group 111. The number of column groups 111 is plural and they are arranged in parallel along the second direction. That is to say, the arrangement regularity of the columns 110 is good, and the remaining space in the groove 200 except for the columns 110 is relatively regular, which is conducive to the formation of the electrode layer 210, so that the electrical properties of the capacitor structure formed by the electrode layer 210 are relatively stable.

[0074] In adjacent column groups 111, multiple columns 110 are staggered in the second direction, which means that in adjacent column groups 111, a column 110 in one column group 111 is located at the interval between adjacent columns 110 in another column group 111 in the second direction, so that the column 110 and the adjacent column 110 at the corresponding interval can enclose a gap of 200s.

[0075] The multi-layer electrode layer 201 is used to form a capacitor structure. Specifically, the multi-layer electrode layer 201 stacked in the groove 200 is used to form a deep trench capacitor (DTC) structure.

[0076] In this embodiment, the material of the electrode layer 201 includes one or more of Si, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0077] As an example, in this embodiment, the material of the electrode layer 201 is polysilicon. Using polysilicon to form the electrode layer 201 is beneficial to the operation of the patterning process of the electrode layer 201.

[0078] The dielectric layer serves as an insulating layer in the formed capacitor structure and is used to isolate adjacent electrode layers 201 .

[0079] In this embodiment, the material of the dielectric layer is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. The use of a high-k dielectric material is conducive to increasing the capacitance value of the capacitor structure and correspondingly increasing the capacitance density.

[0080] Specifically, the dielectric layer is a high-k dielectric layer formed by stacking, that is, the dielectric layer is a high-k composite dielectric layer. When the thickness of the high-k dielectric layer reaches a certain value, its formation quality is likely to deteriorate. Therefore, by using a high-k composite dielectric layer, the thickness of the dielectric layer can meet the process requirements while having better formation quality. To this end, the high-k dielectric material includes HfO 2 、HfSiO、TiO 2 , HfZrO, HfSiON, HfTaO, HfTiO, Ta 2 O 5 、ZrO 2 、ZrSiO 2 、Al 2 O 3 、SrTiO 3 , BaSrTiO and SiN.

[0081] In this embodiment, the dielectric layer is a ZAZ layer. The ZAZ layer includes a first ZrO 2 Layer, Al 2 O3 Layer and second ZrO 2 In other embodiments, according to process requirements, the material of the dielectric layer may also be one or more of silicon oxide, silicon oxynitride and silicon nitride.

[0082] In this embodiment, the gap 200s surrounded by the sidewall electrodes 202 is used to release the stress generated by the film layers stacked in the groove 200, and is also used to provide space for the expansion of the film layers in the subsequent thermal process.

[0083] Combined with reference Figure 3 , Figure 4 and Figure 6 , Figure 4 for Figure 3 A partial enlarged view of the middle triangle area 100t, Figure 6 for Figure 4 In the cross-sectional view along the BB direction, the sidewall electrodes 202 on the sidewalls of three adjacent pillars 110 arranged in a triangle form a gap 200s.

[0084] In this embodiment, in adjacent column groups 111, multiple columns 110 are staggered in the second direction, and the sidewall electrodes 202 of the side walls of three adjacent columns 110 arranged in a triangle are in contact with each other, and a gap 200s is correspondingly formed at the center of the triangular area 100t. At the same time, the sidewall electrodes 202 of the side walls of three adjacent columns 110 in this arrangement can form a gap 200s, which is conducive to obtaining more gaps 200s, and is more conducive to alleviating the stress generated by the stacked film layers in the groove 200, and providing more space for the expansion of the film layers in the subsequent thermal process.

[0085] In this embodiment, the total thickness of the multi-layer stacked electrode layer 201 and the dielectric layer satisfies the formula Wherein, T represents the total thickness of the multi-layer stacked electrode layer 201 and dielectric layer, L represents the distance between the centers of adjacent columns 110 arranged in a triangle, and r represents the radius of the column 110 .

[0086] The minimum spacing between the side walls of adjacent pillars 110 arranged in a triangle is L-2r. When the total thickness of the electrode layer 201 and the dielectric layer on the side walls of the pillars 110 is (L-2r) / 2, the film layer formed by the electrode layer 201 and the dielectric layer on the side walls of adjacent pillars 110 is just in contact with each other, and the side wall electrodes 202 on the side walls of three adjacent pillars 110 just enclose a gap of 200s. Among the three pillars 110 arranged in a triangle, the distance from the center of each pillar 110 to the center point of the triangle formed by the centers of the three pillars 110 is That is, when the thickness of the film formed by the electrode layer 201 and the dielectric layer on the side wall of the pillar 110 is When , the electrode layer 201 on the side walls of the three pillars 110 and the film layer formed by the dielectric layer are just in contact at the center point of the triangle, and the gap 200s disappears at this time. Therefore, in this embodiment, the total thickness of the multi-layer stacked electrode layer 201 and the dielectric layer satisfies the formula

[0087] refer to Figure 3 The electrode layer 201 is also located on the top of the substrate 100 in the lead area 100B, and in the lead area 100B, any electrode layer 201 exposes another adjacent electrode layer 201 located therebelow.

[0088] The exposed electrode layers 201 are used for electrical connection with the outside, so that corresponding electrical signals are loaded to each electrode layer 201 .

[0089] Specifically, in this embodiment, the multilayer electrode layer 201 includes alternately stacked first electrode layers 210 and second electrode layers 220. In any lead area 100B, the first electrode layer 210 exposes the surface of the second electrode layer 220, and in another lead area 100B, the second electrode layer 220 exposes the surface of the first electrode layer 210.

[0090] In any lead area 100B, the first electrode layer 210 exposes the surface of the second electrode layer 220, and the corresponding second electrode layers 220 are electrically connected from the lead area 100B. In another lead area 100B, the second electrode layer 220 exposes the surface of the first electrode layer 210, and the corresponding first electrode layers 210 are electrically connected from the lead area 100B, so that the electrical connection lines between the first electrode layer 210 and the second electrode layer 220 are regularly arranged, and the electrical connection between the first electrode layer 210 and the second electrode layer 220 is easy to achieve.

[0091] In this embodiment, the semiconductor structure further includes: a sealing layer 700 located on the top of the gap 200s and sealing the top of the gap 200s.

[0092] The sealing layer 700 is used to seal the gap 200s so that the film layer in the subsequent process will not fill in the gap 200s and provide a relatively flat process platform for the subsequent process.

[0093] In this embodiment, the material of the sealing layer 700 includes silicon oxide.

[0094] Silicon oxide can seal the gap 200s well and will not fill in the gap 200s as much as possible.

[0095] In this embodiment, the semiconductor structure also includes: a first interconnect plug 300, which is located in the lead area 100B and is located on each exposed electrode layer 201 and is electrically connected to the corresponding electrode layer. The number of the first interconnect plugs 300 on each electrode layer 201 is multiple and is arranged along the extension direction of the lead area 100B, and the extension direction is perpendicular to the direction from the lead area 100B to the device area 100A.

[0096] The first interconnect plug 300 is used to realize the electrical connection between the electrode layer 201 and the outside, so as to load the electrical signal to the electrode layer 201. There are multiple first interconnect plugs 300 on each electrode layer 201 and they are arranged along the extension direction of the lead area 100B, which is conducive to making the loading of the electrical signal to each electrode layer 201 more uniform.

[0097] In this embodiment, the material of the first interconnection plug 300 includes Cu, Co or W.

[0098] In this embodiment, the semiconductor structure further includes: a plurality of first interconnection lines 400 , each of which is located on a corresponding first interconnection plug 300 on the same electrode layer 201 and is electrically connected to the corresponding plurality of first interconnection plugs 300 .

[0099] The first interconnection line 400 is used to electrically connect the corresponding plurality of first interconnection plugs 300 , so as to load an electrical signal to the corresponding electrode layer 201 .

[0100] In this embodiment, the material of the first interconnection line 400 includes Cu, Co or W.

[0101] Figure 7 It is a schematic structural diagram of another embodiment of the semiconductor structure of the present invention.

[0102] The similarities between this embodiment and the above embodiment are not described in detail here. The difference between this embodiment and the above embodiment is that the circuit structure for loading the electrical signal to the electrode layer is different.

[0103] refer to Figure 7 The semiconductor structure further includes: electrode openings 204, which are respectively located in the remaining electrode layers 203 except the bottom electrode layer 203, and penetrate the electrode layers 203, wherein the electrode openings 204 of each electrode layer 203 are located at the top of different pillars 112.

[0104] The electrode opening 204 is used to expose the corresponding electrode layer 203 , so that electrical connection of the exposed electrode layer 203 is achieved through the electrode opening 204 .

[0105] In this embodiment, the electrode openings 204 of each electrode layer 203 are located at the top of different pillars 112, that is, the electrical signal loading of each electrode layer 203 can be achieved above the pillars 112 without requiring additional area for electrical connection of the electrode layer 203, which is beneficial to saving occupied area.

[0106] In this embodiment, the number of electrode layers 203 is n, and the electrode openings 204 of the same electrode layer 203 are located at the tops of the pillars 112 of the same pillar group 113 and correspond one-to-one to the pillars 112 .

[0107] The plurality of columns 112 are regularly arranged into a plurality of column groups 113, the electrode openings 204 above the columns 112 of each column group 113 expose the same electrode layer 203, and the columns 112 in each column group 113 are arranged and extended in the same direction. The electrode layers 203 on the columns 112 of each column group 113 are easy to be electrically connected to the interconnection lines extending in the same direction at the same time, and the connection method is simple, which is conducive to the realization of the capacitor structure.

[0108] In this embodiment, along the second direction and according to a preset period, the electrode openings 204 of each electrode layer 203 are sequentially distributed on the tops of the columns 112 of different column groups 113 . In each preset period, there are n adjacent column groups 113 , and the first direction is perpendicular to the second direction.

[0109] Among the n adjacent column groups 113, the surfaces of the 1st to nth electrode layers 203 are exposed in sequence on the column groups 113 arranged in sequence along the second direction, so the arrangement of the electrode layers 203 exposed on the column groups 113 is regular, which is conducive to the regular arrangement of the interconnection lines and the electrode layers 203 corresponding to the formation above the column groups 113, so that the semiconductor structure has a regular structure, and the structural design and formation are easy to achieve.

[0110] In this embodiment, the semiconductor structure further includes: a plurality of second interconnect plugs 301 , which are respectively located on the electrode layer 203 exposed at the bottom of the electrode opening 204 and are electrically connected to the corresponding electrode layer 203 .

[0111] The second interconnection plug 301 is used to load an electrical signal to the corresponding electrode layer 203 .

[0112] In this embodiment, the plurality of second interconnection plugs 301 are located on the electrode layer 203 exposed on the pillars 112 , so there is no need to form an additional area to etch the electrode layer 203 specifically for forming the second interconnection plugs 301 , which is beneficial to saving the occupied area of ​​the semiconductor structure.

[0113] In this embodiment, the material of the second interconnection plug 301 is tungsten. In other embodiments, the material of the second interconnection plug may also be cobalt or ruthenium.

[0114] In this embodiment, the semiconductor structure also includes: a plurality of second interconnection lines 401, the second interconnection lines 401 extending along the first direction and located on top of the second interconnection plugs 301 on the corresponding column group 113, and the second interconnection lines 401 located on top of the second interconnection plugs 301 on the same electrode layer 203 are connected in parallel.

[0115] The second interconnection line 401 is used to be electrically connected to the second interconnection plug 301 , so as to load an electrical signal to the corresponding electrode layer 203 through the second interconnection plug 301 .

[0116] In this embodiment, the second interconnection line 401 extends along the first direction and is located on the top of the second interconnection plug 301 on the corresponding column group 113. The columns 112 of the same column group 113 expose the same electrode layer 203, so that the same second interconnection line 401 can load electrical signals for the same electrode layer 203. Moreover, the second interconnection lines 401 located on the top of the second interconnection plug 301 on the same electrode layer 203 are connected in parallel, so that the same electrode layer 203 in the multiple electrode layers 203 can be loaded with the same electrical signal, thereby realizing the basic function of the deep trench capacitor structure.

[0117] In this embodiment, the material of the second interconnection line 401 is tungsten. In other embodiments, the material of the second interconnection line may also be cobalt or ruthenium.

[0118] In this embodiment, among the plurality of second interconnection lines 401, the second interconnection lines 401 located on top of the second interconnection plugs 301 in the odd-numbered electrode layers 203 are connected in parallel, and the second interconnection lines 401 located on top of the second interconnection plugs 301 in the even-numbered electrode layers 203 are connected in parallel.

[0119] The second interconnection lines 401 at the top of the second interconnection plugs 301 of the electrode layers 203 located in odd layers are connected in parallel, and the second interconnection lines 401 at the top of the second interconnection plugs 301 of the electrode layers 203 located in even layers are connected in parallel, so that the electrode layers 203 in odd layers are loaded with the same electrical signal, and the electrode layers 203 in even layers are loaded with the same electrical signal, thereby achieving a potential difference between adjacent electrode layers 203 and simplifying the electrical connection lines of the multi-layer electrode layers 203, so that the electrical connection structure of the multi-layer electrode layers 203 is simple and easy to implement, which is beneficial to saving the formation cost of the semiconductor structure.

[0120] Correspondingly, the present invention also provides a method for forming a semiconductor structure. Figures 8 to 14 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention.

[0121] The method for forming the semiconductor structure of this embodiment is described in detail below with reference to the accompanying drawings.

[0122] refer to Figure 8, providing a substrate 100.

[0123] The substrate 100 is used to provide a process platform for forming a semiconductor structure.

[0124] In this embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium, and the substrate may also be other types of substrates such as silicon on insulator substrate or germanium on insulator substrate. The material of the substrate may be a material suitable for process requirements or easy to integrate.

[0125] In this embodiment, the substrate 100 includes a device region 100A and a lead region 100B adjacent to the device region 100A.

[0126] The device region 100A is used to form a capacitor structure, and the lead region 100B is used to subsequently electrically lead out the electrode layer.

[0127] Specifically, in this embodiment, the lead area 100B is located on both sides of the device area 100A, so that the subsequently formed multi-layer electrode layer can be distributed in the lead areas 100B on both sides, and the two adjacent electrode layers are electrically connected from the lead areas 100B on both sides, so that the electrical connection lines of the electrode layers are simplified and easy to implement.

[0128] In this embodiment, the semiconductor structure further includes: a through-hole interconnection structure (not shown) penetrating the substrate 100 .

[0129] The through-hole interconnection structure is used to realize longitudinal electrical connection of wafers and realize longitudinal stacking of wafers. In this embodiment, the through-hole interconnection structure is a through-silicon-via (TSV) structure.

[0130] Combined with reference Fig. 9 and Fig.10 , Fig.10 for Fig. 9 A cross-sectional view of a partial column, a groove 200 is formed in the base 100; a column 110 is formed protruding from the bottom of the groove 200, and a plurality of columns 110 are separated from each other.

[0131] In this embodiment, the groove 200 is used to provide a spatial position for the subsequent formation of an electrode layer and a dielectric layer.

[0132] Accordingly, in this embodiment, the groove 200 is located in the device region 100A.

[0133] In this embodiment, the groove 200 surrounds the through-hole interconnection structure and includes a plurality of sub-grooves (not shown) that are connected in sequence along the circumferential direction; in each sub-groove, a plurality of columns 110 constitute a hexagonal column unit.

[0134] Compared with a square structure in which a plurality of square grooves form a surrounding through-hole interconnection structure, in the present embodiment, a plurality of pillars 110 form a hexagonal honeycomb-shaped pillar unit, and a plurality of pillar units form a ring structure surrounding the through-hole interconnection structure. The honeycomb-shaped pillar units are arranged more compactly, and the ring structure formed by a plurality of pillar units saves more occupied area, which is beneficial to improving the integration of the semiconductor structure.

[0135] In this embodiment, the pillars 110 are used to form a subsequently formed electrode layer on the sidewalls thereof, thereby providing support for the formation of the sidewall electrodes.

[0136] In this embodiment, the steps of forming the groove 200 in the substrate 100 and forming the pillars 110 protruding from the bottom of the groove 200 include: patterning the substrate 100, forming the groove 200 in the substrate 100, and a plurality of pillars 110 protruding from the bottom of the groove 200.

[0137] The pillar 110 is obtained by patterning the substrate 100, and therefore, the bottom of the pillar 110 is connected to the substrate 100 to form an integrated structure, which makes it easier to obtain the pillar. Moreover, in this embodiment, the groove 200 and the pillar 110 protruding from the bottom of the groove 200 are obtained by patterning the substrate 100 at the same time, so that the top surface of the pillar 110 is flush with the top of the groove 200, which is correspondingly conducive to the formation of the electrode layer 210.

[0138] In this embodiment, in the step of forming the pillar 110 protruding from the bottom of the groove 200 , the shape of the pillar 110 includes a cylindrical shape.

[0139] The pillar 110 is cylindrical, and the sidewall electrodes subsequently formed on the sidewalls of the pillars 110 are also cylindrical, so that the sidewall electrode cross-sections of the sidewalls of adjacent pillars 110 are in contact, and correspondingly multiple contacting surfaces can form a gap.

[0140] In this embodiment, in the step of forming the pillar 110, the pillars 110 are formed along the first direction (eg Fig. 9 A plurality of columns 110 extending and arranged in a second direction (as shown in the X direction) form a column group 111. The number of the column group 111 is multiple and along the second direction (as shown in the X direction) Fig. 9 In the adjacent column groups 111, the plurality of columns 110 are staggeredly distributed in the second direction, and the first direction is perpendicular to the second direction.

[0141] A plurality of columns 110 extending along the first direction constitute a column group 111. The number of column groups 111 is plural and they are arranged in parallel along the second direction. That is to say, the arrangement regularity of the columns 110 is good, so the remaining space in the groove 200 except for the columns 110 is relatively regular, which is conducive to the formation of the subsequent electrode layer, so that the electrical properties of the capacitor structure formed by the electrode layer are relatively stable.

[0142] In adjacent column groups 111, multiple columns 110 are staggered in the second direction, which means that in adjacent column groups 111, a column 110 in one column group 111 is located at the interval between adjacent columns 110 in another column group 111 in the second direction, so that the column 110 and the adjacent column 110 at the corresponding interval can enclose a gap.

[0143] Combined with reference Figures 11 to 14 , forming a multi-layer stacked electrode layer 201 and a dielectric layer (not shown), in which the bottom electrode layer 201 covers the surfaces of the groove 200 and the surfaces of the pillar 110, and the remaining electrode layers 201 are stacked in sequence on the bottom electrode layer 201, wherein the top electrode layer 201 located on the side wall of the pillar 110 serves as a sidewall electrode 202, and there is a gap 200s between any adjacent sidewall electrodes 202.

[0144] The multi-layer electrode layer 201 is used to form a capacitor structure. Specifically, the multi-layer electrode layer 201 stacked in the groove 200 is used to form a deep trench capacitor (DTC) structure.

[0145] Specifically, in conjunction with reference Fig.12 and Fig.13 , Fig.13 for Fig.12 In the cross-sectional view along the AA direction, the pillar 110 is cylindrical, which is conducive to making the stress direction generated by the multi-layer stacked electrode layer 201 in the groove 200 along the diameter direction of the pillar 110 (such as Fig.13 As shown by the dashed arrow in the figure, the stress distribution is more dispersed, thereby improving the problem of stress concentration and reducing the influence of stress on the semiconductor structure.

[0146] In this embodiment, the material of the electrode layer 201 includes one or more of Si, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al.

[0147] As an example, in this embodiment, the material of the electrode layer 201 is polysilicon. Using polysilicon to form the electrode layer 201 is beneficial to the operation of the patterning process of the electrode layer 201.

[0148] The dielectric layer serves as an insulating layer in the formed capacitor structure and is used to isolate adjacent electrode layers 201 .

[0149] In this embodiment, the material of the dielectric layer is a high-k dielectric material, wherein the high-k dielectric material refers to a dielectric material having a relative dielectric constant greater than that of silicon oxide. The use of a high-k dielectric material is conducive to increasing the capacitance value of the capacitor structure and correspondingly increasing the capacitance density.

[0150] Specifically, the dielectric layer is a high-k dielectric layer formed by stacking, that is, the dielectric layer is a high-k composite dielectric layer. When the thickness of the high-k dielectric layer reaches a certain value, its formation quality is likely to deteriorate. Therefore, by using a high-k composite dielectric layer, the thickness of the dielectric layer can meet the process requirements while having better formation quality. To this end, the high-k dielectric material includes HfO 2 、HfSiO、TiO 2 , HfZrO, HfSiON, HfTaO, HfTiO, Ta 2 O 5 、ZrO 2 、ZrSiO 2 、Al 2 O 3 、SrTiO 3 , BaSrTiO and SiN.

[0151] In this embodiment, the dielectric layer is a ZAZ layer. The ZAZ layer includes a first ZrO 2 Layer, Al 2 O 3 Layer and second ZrO 2 In other embodiments, according to process requirements, the material of the dielectric layer may also be one or more of silicon oxide, silicon oxynitride and silicon nitride.

[0152] In this embodiment, in the step of forming the multi-layer stacked electrode layer 201 and dielectric layer, a furnace tube process is used to form each electrode layer 201 and dielectric layer.

[0153] The furnace tube process is used to form each electrode layer 201 and dielectric layer, which is beneficial for the electrode layer 201 and dielectric layer to be well formed on the side wall of the pillar 110 and will not fill the gap 200s as much as possible.

[0154] In other embodiments, each electrode layer and each dielectric layer may be formed by chemical vapor deposition process.

[0155] In this embodiment, the gap 200s surrounded by the sidewall electrodes 202 is used to release the stress generated by the film layers stacked in the groove 200, and is also used to provide space for the expansion of the film layers in the subsequent thermal process.

[0156] Combined with reference Fig.11 , Fig.12 and Fig.14 , Fig.12 for Fig.11 A partial enlarged view of the middle triangle area 100t, Fig.14 for Fig.12In the cross-sectional view along the BB direction, in the step of forming the electrode layer 201 , the sidewall electrodes 202 on the sidewalls of three adjacent pillars 110 arranged in a triangle form a gap 200s.

[0157] In this embodiment, in adjacent column groups 111, multiple columns 110 are staggered in the second direction, and the sidewall electrodes 202 of the side walls of three adjacent columns 110 arranged in a triangle are in contact with each other, and a gap 200s is correspondingly formed at the center of the triangular area 100t. At the same time, the sidewall electrodes 202 of the side walls of three adjacent columns 110 in this arrangement can form a gap 200s, which is conducive to obtaining more gaps 200s, and is more conducive to alleviating the stress generated by the stacked film layers in the groove 200, and providing more space for the expansion of the film layers in the subsequent thermal process.

[0158] In this embodiment, in the step of forming the electrode layer 201, the total thickness of the multi-layer stacked electrode layer 201 and the dielectric layer satisfies the formula Wherein, T represents the total thickness of the multi-layer stacked electrode layer 201 and dielectric layer, L represents the distance between the centers of adjacent columns 110 arranged in a triangle, and r represents the radius of the column 110 .

[0159] The minimum spacing between the side walls of adjacent pillars 110 arranged in a triangle is L-2r. When the total thickness of the electrode layer 201 and the dielectric layer on the side walls of the pillars 110 is (L-2r) / 2, the film layer formed by the electrode layer 201 and the dielectric layer on the side walls of adjacent pillars 110 is just in contact with each other, and the side wall electrodes 202 on the side walls of three adjacent pillars 110 just enclose a gap of 200s. Among the three pillars 110 arranged in a triangle, the distance from the center of each pillar 110 to the center point of the triangle formed by the centers of the three pillars 110 is That is to say, when the thickness of the film formed by the electrode layer 201 and the dielectric layer on the side wall of the pillar 110 is When , the electrode layer 201 on the side walls of the three pillars 110 and the film layer formed by the dielectric layer are just in contact at the center point of the triangle, and the gap 200s disappears at this time. Therefore, in this embodiment, the total thickness of the multi-layer stacked electrode layer 201 and the dielectric layer satisfies the formula

[0160] refer to Fig.11 In the step of forming the electrode layer 201, the electrode layer 201 is also located on the top of the substrate 100 in the lead area 100B, and in the lead area 100B, any electrode layer 201 exposes another adjacent electrode layer 201 located therebelow.

[0161] The exposed electrode layers 201 are used for electrical connection with the outside, so that corresponding electrical signals are loaded to each electrode layer 201 .

[0162] Specifically, in the present embodiment, in the step of forming the electrode layer 201, the multilayer electrode layer 201 includes alternately stacked first electrode layers 210 and second electrode layers 220, and in any lead area 100B, the first electrode layer 210 exposes the surface of the second electrode layer 220, and in another lead area 100B, the second electrode layer 220 exposes the surface of the first electrode layer 210.

[0163] In any lead area 100B, the first electrode layer 210 exposes the surface of the second electrode layer 220, and the corresponding second electrode layers 220 are electrically connected from the lead area 100B. In another lead area 100B, the second electrode layer 220 exposes the surface of the first electrode layer 210, and the corresponding first electrode layers 210 are electrically connected from the lead area 100B, so that the electrical connection lines between the first electrode layer 210 and the second electrode layer 220 are regularly arranged, and the electrical connection between the first electrode layer 210 and the second electrode layer 220 is easy to achieve.

[0164] In this embodiment, after forming the electrode layer 201 and the dielectric layer, the forming method further includes: forming a sealing layer 700 at the top of the sealing gap 200s.

[0165] The sealing layer 700 is used to seal the gap 200s so that the film layer in the subsequent process will not fill in the gap 200s and provide a relatively flat process platform for the subsequent process.

[0166] In this embodiment, the material of the sealing layer 700 includes silicon oxide.

[0167] Silicon oxide can seal the gap 200s well and will not fill in the gap 200s as much as possible.

[0168] In the present embodiment, after forming a multi-layer stacked electrode layer 201 and a dielectric layer, the formation method further includes: forming a first interconnect plug 300 electrically connected to the corresponding electrode layer 201 on each electrode layer 201 exposed in the lead area 100B, and the number of the first interconnect plugs 300 on each electrode layer 201 is multiple and arranged along the extension direction of the lead area 100B, and the extension direction is perpendicular to the direction of the lead area 100B pointing to the device area 100A.

[0169] The first interconnect plug 300 is used to realize the electrical connection between the electrode layer 201 and the outside, so as to load the electrical signal to the electrode layer 201. There are multiple first interconnect plugs 300 on each electrode layer 201 and they are arranged along the extension direction of the lead area 100B, which is conducive to making the loading of the electrical signal to each electrode layer 201 more uniform.

[0170] In this embodiment, the material of the first interconnection plug 300 includes Cu, Co or W.

[0171] In this embodiment, a plurality of first interconnection lines 400 are formed, each of which is located on a corresponding first interconnection plug 300 on the same electrode layer 201 and is electrically connected to the corresponding plurality of first interconnection plugs 300 .

[0172] The first interconnection line 400 is used to electrically connect the corresponding plurality of first interconnection plugs 300 , so as to load an electrical signal to the corresponding electrode layer 201 .

[0173] In this embodiment, the material of the first interconnection line 400 includes Cu, Co or W.

[0174] Fig.15 It is a schematic structural diagram corresponding to each step in another embodiment of the method for forming a semiconductor structure of the present invention.

[0175] The similarities between this embodiment and the above embodiment are not described in detail here. The difference between this embodiment and the above embodiment is that the circuit structure for loading the electrical signal to the electrode layer is different.

[0176] refer to Fig.15 In the step of forming the electrode layer 203 , electrode openings 204 are formed in the electrode layers 203 except the bottom electrode layer 203 , and the electrode openings 204 penetrate the electrode layers 203 , wherein the electrode openings 204 of each electrode layer 203 are located at the tops of different pillars 112 .

[0177] The electrode opening 204 is used to expose the corresponding electrode layer 203 , so that electrical connection of the exposed electrode layer 203 is achieved through the electrode opening 204 .

[0178] In this embodiment, the electrode openings 204 of each electrode layer 203 are located at the top of different pillars 112, that is, the electrical signal loading of each electrode layer 203 can be achieved above the pillars 112 without requiring additional area for electrical connection of the electrode layer 203, which is beneficial to saving occupied area.

[0179] In this embodiment, in the step of forming the electrode layer 203 , the number of electrode layers 203 is n, and the electrode openings 204 of the same electrode layer 203 are located at the tops of the columns 112 of the same column group 113 and correspond one-to-one to the columns 112 .

[0180] The plurality of columns 112 are regularly arranged into a plurality of column groups 113, the electrode openings 204 above the columns 112 of each column group 113 expose the same electrode layer 203, and the columns 112 in each column group 113 are arranged and extended in the same direction. The electrode layers 203 on the columns 112 of each column group 113 are easy to be electrically connected to the interconnection lines extending in the same direction at the same time, and the connection method is simple, which is conducive to the realization of the capacitor structure.

[0181] In this embodiment, in the step of forming the electrode layer 203, the electrode openings 204 of each electrode layer 203 are sequentially distributed on the tops of the columns 112 of different column groups 113 along the second direction and according to a preset period, and in each preset period there are n adjacent column groups 113, and the first direction is perpendicular to the second direction.

[0182] Among the n adjacent column groups 113, the surfaces of the 1st to nth electrode layers 203 are exposed in sequence on the column groups 113 arranged in sequence along the second direction, so the arrangement of the electrode layers 203 exposed on the column groups 113 is regular, which is conducive to the regular arrangement of the interconnection lines and the electrode layers 203 corresponding to the formation above the column groups 113, so that the semiconductor structure has a regular structure, and the structural design and formation are easy to achieve.

[0183] In this embodiment, after forming the multi-layer stacked electrode layer 203 and dielectric layer, the forming method further includes: forming second interconnect plugs 301 on the electrode layer 203 exposed at the bottom of the electrode opening 204 , respectively, and the second interconnect plugs 301 are electrically connected to the corresponding electrode layer 203 .

[0184] The second interconnection plug 301 is used to load an electrical signal to the corresponding electrode layer 203 .

[0185] In this embodiment, the plurality of second interconnection plugs 301 are located on the electrode layer 203 exposed on the pillars 112 , so there is no need to form an additional area to etch the electrode layer 203 specifically for forming the second interconnection plugs 301 , which is beneficial to saving the occupied area of ​​the semiconductor structure.

[0186] In this embodiment, the material of the second interconnection plug 301 is tungsten. In other embodiments, the material of the second interconnection plug may also be cobalt or ruthenium.

[0187] In this embodiment, a plurality of second interconnection lines 401 are formed on top of the second interconnection plugs 301. The second interconnection lines 401 extend along the first direction and are located on top of the second interconnection plugs 301 on the corresponding column groups 113. The second interconnection lines 401 located on top of the second interconnection plugs 301 on the same electrode layer 203 are connected in parallel.

[0188] The second interconnection line 401 is used to be electrically connected to the second interconnection plug 301 , so as to load an electrical signal to the corresponding electrode layer 203 through the second interconnection plug 301 .

[0189] In this embodiment, the second interconnection line 401 extends along the first direction and is located on the top of the second interconnection plug 301 on the corresponding column group 113. The columns 112 of the same column group 113 expose the same electrode layer 203, so that the same second interconnection line 401 can load electrical signals for the same electrode layer 203. Moreover, the second interconnection lines 401 located on the top of the second interconnection plug 301 on the same electrode layer 203 are connected in parallel, so that the same electrode layer 203 in the multiple electrode layers 203 can be loaded with the same electrical signal, thereby realizing the basic function of the deep trench capacitor structure.

[0190] In this embodiment, the material of the second interconnection line 401 is tungsten. In other embodiments, the material of the second interconnection line may also be cobalt or ruthenium.

[0191] In this embodiment, in the step of forming a plurality of second interconnection lines 401, the second interconnection lines 401 on top of the second interconnection plugs 301 located in odd-numbered electrode layers 203 are connected in parallel, and the second interconnection lines 401 on top of the second interconnection plugs 301 located in even-numbered electrode layers 203 are connected in parallel.

[0192] The second interconnection lines 401 at the top of the second interconnection plugs 301 of the electrode layers 203 located in odd layers are connected in parallel, and the second interconnection lines 401 at the top of the second interconnection plugs 301 of the electrode layers 203 located in even layers are connected in parallel, so that the electrode layers 203 in odd layers are loaded with the same electrical signal, and the electrode layers 203 in even layers are loaded with the same electrical signal, thereby achieving a potential difference between adjacent electrode layers 203 and simplifying the electrical connection lines of the multi-layer electrode layers 203, so that the electrical connection structure of the multi-layer electrode layers 203 is simple and easy to implement, which is beneficial to saving the formation cost of the semiconductor structure.

[0193] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A semiconductor structure, characterized in that: include: substrate; a groove located in the substrate; A plurality of columns protruding from the bottom of the groove, and the plurality of columns are separated from each other; A plurality of stacked electrode layers, wherein the bottom electrode layer covers each surface of the groove and each surface of the pillar, and the remaining electrode layers are stacked in sequence on the bottom electrode layer, wherein the portion of the top electrode layer located on the side wall of the pillar serves as a side wall electrode; A dielectric layer, located between adjacent electrode layers; A gap is located between any adjacent sidewall electrodes.

2. The semiconductor structure according to claim 1, wherein: The bottom of the column is connected to the base to form an integrated structure.

3. The semiconductor structure according to claim 1, wherein: The top surface of the column is flush with the top of the groove.

4. The semiconductor structure according to claim 1, wherein: The shape of the pillar includes a cylindrical shape.

5. The semiconductor structure according to claim 4, characterized in that A plurality of columns extending and arranged along the first direction constitute a column group, the number of the column groups is plural and they are arranged in parallel along the second direction, in adjacent column groups, the plurality of the columns are staggered in the second direction, and the first direction is perpendicular to the second direction; The side wall electrodes on the side walls of three adjacent columns arranged in a triangle form the gap.

6. The semiconductor structure according to claim 5, characterized in that The total thickness of the multi-layer stacked electrode layer and dielectric layer satisfies the formula Wherein, T represents the total thickness of the multi-layer stacked electrode layer and dielectric layer, L represents the distance between the centers of adjacent columns arranged in a triangle, and r represents the radius of the column.

7. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes a sealing layer located on the top of the gap and sealing the top of the gap.

8. The semiconductor structure according to claim 7, wherein: The sealing layer is made of silicon oxide.

9. The semiconductor structure according to any one of claims 1 to 8, characterized in that: The substrate includes a device area and a lead area adjacent to the device area; The groove is located in the device area; The electrode layer is also located on the top of the substrate in the lead area, and in the lead area, any electrode layer exposes another adjacent electrode layer located therebelow.

10. The semiconductor structure according to claim 9, wherein: The lead area is located on both sides of the device area; The multi-layer electrode layer includes a first electrode layer and a second electrode layer that are alternately stacked. In any one of the lead areas, the first electrode layer exposes a surface of the second electrode layer, and in another of the lead areas, the second electrode layer exposes a surface of the first electrode layer.

11. The semiconductor structure according to claim 9, wherein: The semiconductor structure further includes: a first interconnect plug located in the lead region and located on each of the exposed electrode layers and electrically connected to the corresponding electrode layer, wherein the number of the first interconnect plugs on each of the electrode layers is plural and arranged along the extension direction of the lead region, wherein the extension direction is perpendicular to the direction from the lead region to the device region; A plurality of first interconnection lines, each of which is located on a corresponding first interconnection plug on the same electrode layer and is electrically connected to the corresponding plurality of first interconnection plugs.

12. The semiconductor structure according to any one of claims 1 to 8, characterized in that: The semiconductor structure further includes: electrode openings, which are respectively located in the remaining electrode layers except the bottom electrode layer and penetrate the electrode layers, wherein the electrode openings of each electrode layer are located at the top of different pillars.

13. The semiconductor structure according to claim 12, wherein: A plurality of the columns extending and arranged along the first direction constitute a column group, and the column group is multiple in number and arranged in parallel along the second direction; The number of electrode layers is n, and the electrode openings of the same electrode layer are located at the tops of the columns of the same column group and correspond one to one with the columns; Along the second direction and according to a preset period, the electrode openings of each electrode layer are sequentially distributed on the tops of columns of different column groups. There are n adjacent column groups in each preset period, and the first direction is perpendicular to the second direction.

14. The semiconductor structure according to claim 13, wherein: The semiconductor structure further comprises: a plurality of second interconnect plugs, each of which is located on the electrode layer exposed at the bottom of the electrode opening and is electrically connected to the corresponding electrode layer; A plurality of second interconnection lines extend along the first direction and are located on top of second interconnection plugs on corresponding pillar groups, and the second interconnection lines located on top of second interconnection plugs on the same electrode layer are connected in parallel.

15. The semiconductor structure according to claim 14, wherein: Among the plurality of second interconnection lines, the second interconnection lines located on top of the second interconnection plugs in the odd-numbered electrode layers are connected in parallel, and the second interconnection lines located on top of the second interconnection plugs in the even-numbered electrode layers are connected in parallel.

16. The semiconductor structure according to claim 1, wherein: The semiconductor structure further includes: a through-hole interconnect structure penetrating the substrate; The groove surrounds the through-hole interconnection structure and includes a plurality of sub-grooves connected in sequence along the circumferential direction; In each of the sub-grooves, a plurality of the columns form a hexagonal column unit.

17. The semiconductor structure according to claim 1, wherein: The material of the electrode layer includes one or more of Si, W, Cu, Co, TiN, Ti, Ta, TaN, Ru, RuN and Al; the material of the dielectric layer includes one or more of HfO2, HfSiO, TiO2, HfZrO, HfSiON, HfTaO, HfTiO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, BaSrTiO and SiN.

18. A method for forming a semiconductor structure, characterized in that: include: providing a substrate; forming a groove in the substrate; Forming a column protruding from the bottom of the groove, wherein a plurality of the columns are separated from each other; A multi-layer stacked electrode layer and a dielectric layer are formed, wherein the bottom electrode layer covers the surfaces of the grooves and the surfaces of the pillars, and the remaining electrode layers are stacked in sequence on the bottom electrode layer, wherein the top electrode layer is located on the side wall of the pillar as a side wall electrode, and there is a gap between any adjacent side wall electrodes.

19. The method for forming a semiconductor structure according to claim 18, wherein: The steps of forming a groove in the substrate and forming a column protruding from the bottom of the groove include: patterning the substrate, forming a groove in the substrate and a plurality of columns protruding from the bottom of the groove.

20. The method for forming a semiconductor structure according to claim 18, wherein: In the step of forming a column protruding from the bottom of the groove, the shape of the column includes a cylindrical shape.

21. The method for forming a semiconductor structure according to claim 20, wherein: In the step of forming the columns, a plurality of columns extending and arranged along the first direction constitute a column group, the number of the column groups is multiple and they are arranged in parallel along the second direction, in adjacent column groups, a plurality of the columns are staggered in the second direction, and the first direction is perpendicular to the second direction; In the step of forming the electrode layer, the sidewall electrodes on the sidewalls of three adjacent columns arranged in a triangle form the gap.

22. The method for forming a semiconductor structure according to claim 21, wherein: In the step of forming the electrode layer, the total thickness of the multi-layer stacked electrode layer and the dielectric layer satisfies the formula Wherein, T represents the total thickness of the multi-layer stacked electrode layer and dielectric layer, L represents the distance between the centers of adjacent columns arranged in a triangle, and r represents the radius of the column.

23. The method for forming a semiconductor structure according to claim 18, wherein: After forming the electrode layer and the dielectric layer, the forming method further comprises: forming a sealing layer for sealing the top of the gap.

24. The method for forming a semiconductor structure according to any one of claims 18 to 23, characterized in that: In the step of providing the substrate, the substrate includes a device area and a lead area adjacent to the device area; In the step of forming the groove, the groove is located in the device area; In the step of forming the electrode layer, the electrode layer is also located on the top of the substrate in the lead area, and in the lead area, any electrode layer exposes another adjacent electrode layer located therebelow.

25. The method for forming a semiconductor structure according to claim 24, wherein: In the step of providing the substrate, the lead area is located on both sides of the device area; In the step of forming the electrode layer, the multilayer electrode layer includes alternately stacked first electrode layers and second electrode layers, in any lead area, the first electrode layer exposes the surface of the second electrode layer, and in another lead area, the second electrode layer exposes the surface of the first electrode layer.

26. The method for forming a semiconductor structure according to claim 24, wherein: After forming a multi-layer stack of electrode layers and dielectric layers, the formation method further comprises: forming a first interconnect plug electrically connected to the corresponding electrode layer on each electrode layer exposed in the lead area, wherein the number of the first interconnect plugs on each electrode layer is multiple and arranged along the extension direction of the lead area, and the extension direction is perpendicular to the direction from the lead area to the device area; A plurality of first interconnection lines are formed, each of which is located on a corresponding first interconnection plug on the same electrode layer and is electrically connected to the corresponding plurality of first interconnection plugs.

27. The method for forming a semiconductor structure according to any one of claims 18 to 23, characterized in that: In the step of forming the electrode layers, electrode openings are formed in the electrode layers except the bottom electrode layer, and the electrode openings penetrate the electrode layers, wherein the electrode openings of the electrode layers are located at different pillar tops.

28. The method for forming a semiconductor structure according to claim 27, wherein: In the step of forming the pillars, a plurality of the pillars extending and arranged along the first direction constitute a pillar group, and the number of the pillar groups is plural and they are arranged in parallel along the second direction; In the step of forming the electrode layer, the number of the electrode layers is n, and the electrode openings of the same electrode layer are located at the tops of the columns of the same column group and correspond one to one with the columns; In the step of forming the electrode layer, the electrode openings of each electrode layer are sequentially distributed on the tops of columns of different column groups along the second direction and according to a preset period. There are n adjacent column groups in each preset period, and the first direction is perpendicular to the second direction.

29. The method for forming a semiconductor structure according to claim 28, wherein: After forming a multi-layer stack of electrode layers and dielectric layers, the forming method further comprises: forming second interconnect plugs on the electrode layers exposed at the bottom of the electrode openings, respectively, the second interconnect plugs being electrically connected to the corresponding electrode layers; A plurality of second interconnection lines are formed on the top of the second interconnection plugs. The second interconnection lines extend along the first direction and are located on the top of the second interconnection plugs on the corresponding pillar groups. The interconnection lines on the top of the second interconnection plugs on the same electrode layer are connected in parallel.

30. The method for forming a semiconductor structure according to claim 29, wherein: In the step of forming a plurality of second interconnection lines, the second interconnection lines on top of the second interconnection plugs in the odd-numbered electrode layers are connected in parallel, and the second interconnection lines on top of the second interconnection plugs in the even-numbered electrode layers are connected in parallel.

31. The method for forming a semiconductor structure according to claim 18, wherein: In the step of providing the substrate, a through-hole interconnection structure penetrating the substrate is formed in the substrate; In the step of forming the groove, the groove surrounds the through-hole interconnection structure and includes a plurality of sub-grooves that are connected in sequence along the circumferential direction; In the step of forming the pillars, in each of the sub-grooves, a plurality of the pillars form a hexagonal pillar unit.

32. The method for forming a semiconductor structure according to claim 18, wherein: In the step of forming a multi-layer stack of electrode layers and dielectric layers, a furnace tube process is used to form each of the electrode layers and dielectric layers.

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