Three-dimensional packaging chip and manufacturing method thereof

Abstract

The invention provides a three-dimensional packaging chip and a manufacturing method thereof, the three-dimensional packaging chip comprises a first chip and a second chip, and the second chip is bonded with the first chip; the at least one concave part is arranged on the surface, close to the second chip, of the first chip; the at least one concave part is arranged on the surface, close to the first chip, of the second chip, and the convex part and the concave part are nested in an aligned manner; the first metal layer is laid on the surface, close to the second chip, of the first chip, and the first metal layer covers the concave part; the second metal layer is laid on the surface, close to the first chip, of the second chip, and the second metal layer covers the convex part; and an insulating layer disposed between the first metal layer and the second metal layer, and the first metal layer, the insulating layer, and the second metal layer forming a capacitor device. According to the three-dimensional packaging chip and the manufacturing method thereof provided by the invention, the problem that a capacitor on a circuit board cannot meet the requirements of an on-chip system on the capacity and the position of the capacitor can be solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of integrated circuit manufacturing, and in particular relates to a three-dimensional packaged chip and a manufacturing method thereof. Background Art

[0002] When packaging the chip, the chip of each module will be packaged independently, and the packaged multiple chips will be laid flat on a circuit board and connected into a system on chip through the circuit board. And for capacitors, which are larger in structure, they are laid on the circuit board together with the packaged chips.

[0003] However, as the integration of the system on chip increases, two-dimensional packaging can no longer meet the volume requirements of the system on chip. Furthermore, the system on chip with increased integration requires larger current support, which in turn requires larger capacitors. And as the voltage switching frequency of the power chip continues to increase, the capacitor needs to be as close to the power network as possible. However, the capacitor set on the circuit board cannot meet the system on chip's requirements for the capacity and location of the capacitor. Summary of the invention

[0004] The object of the present invention is to provide a three-dimensional packaged chip and a manufacturing method thereof, which can solve the problem that the capacitors on the circuit board cannot meet the requirements of the system on chip for the capacity and position of the capacitors.

[0005] To achieve the above object, the present invention provides a three-dimensional packaged chip, comprising at least:

[0006] A first chip and a second chip, wherein the second chip is bonded to the first chip;

[0007] At least one recessed portion is disposed on a surface of the first chip close to the second chip;

[0008] At least one concave portion is arranged on a surface of the second chip close to the first chip, and the convex portion is aligned and nested with the concave portion;

[0009] A first metal layer is laid on a surface of the first chip close to the second chip, and the first metal layer covers the concave portion;

[0010] A second metal layer is laid on a surface of the second chip close to the first chip, and the second metal layer covers the protrusion; and

[0011] The insulating layer is disposed between the first metal layer and the second metal layer, and the first metal layer, the insulating layer and the second metal layer form a capacitor device.

[0012] In an embodiment of the present invention, a through silicon via structure is provided in the first chip and the second chip.

[0013] In one embodiment of the present invention, a recess is provided on a surface of the first chip close to the second chip and between two adjacent through-silicon via structures; and a protrusion is provided on a surface of the second chip close to the first chip and between two adjacent through-silicon via structures.

[0014] In one embodiment of the present invention, two or more recesses are provided on the surface of the first chip close to the second chip and between two adjacent through-silicon via structures; and two or more protrusions are provided on the surface of the second chip close to the first chip and between two adjacent through-silicon via structures.

[0015] In one embodiment of the present invention, the concave portion and the convex portion are arranged in a rectangular, pentagonal, hexagonal shape, or a rectangular, pentagonal, or hexagonal shape with rounded corners.

[0016] In one embodiment of the present invention, the first metal layer includes a first capacitor metal layer, which covers the concave portion; the second metal layer includes a second capacitor metal layer, which covers the convex portion, and the second capacitor metal layer and the first capacitor metal layer are arranged in alignment.

[0017] In one embodiment of the present invention, the first metal layer includes a first contact metal layer, and the first contact metal layer is arranged on both sides of the first capacitor metal layer; the second metal layer includes a second contact metal layer, and the second contact metal layer is arranged on both sides of the second capacitor metal layer, and the second contact metal layer and the first contact metal layer are arranged in alignment.

[0018] In one embodiment of the present invention, the sum of the thicknesses of the first contact metal layer and the second contact metal layer is equal to the sum of the thicknesses of the first capacitor metal layer, the second capacitor metal layer and the insulating layer.

[0019] In an embodiment of the present invention, the first metal layer includes one first capacitor metal layer and two first contact metal layers, and the second metal layer includes one second capacitor metal layer and two second contact metal layers.

[0020] In one embodiment of the present invention, the first metal layer includes at least two first capacitor metal layers, at least two of the first capacitor metal layers are laid on the surface of the first chip, and each of the first capacitor metal layers covers one of the recessed portions, and a gap is provided between two adjacent first capacitor metal layers; the second metal layer includes at least two second capacitor metal layers, at least two of the second capacitor metal layers are laid on the surface of the second chip, and each of the second capacitor metal layers covers one of the protruding portions, and a gap is provided between two adjacent second capacitor metal layers.

[0021] In one embodiment of the present invention, the three-dimensional packaged chip further includes:

[0022] A third chip is disposed on a side of the first chip away from the second chip; and

[0023] The fourth chip is arranged on a side of the first chip away from the second chip, and the second chip and the third chip are arranged side by side.

[0024] In one embodiment of the present invention, the second chip is a power chip

[0025] The present invention also provides a method for manufacturing a three-dimensional packaged chip, which comprises at least the following steps:

[0026] providing a first chip and a second chip;

[0027] Etching a surface of the first chip close to the second chip to form at least one concave portion;

[0028] Etching the surface of the second chip close to the first chip to form at least one convex portion, wherein the convex portion is aligned and nested with the concave portion;

[0029] Laying a first metal layer on a surface of the first chip close to the second chip, wherein the first metal layer covers the concave portion;

[0030] Laying a second metal layer on the surface of the second chip close to the first chip, wherein the second metal layer covers the protrusion;

[0031] The second chip is bonded to the first chip, and an insulating layer is disposed between the first metal layer and the second metal layer, and the first metal layer, the insulating layer and the second metal layer form a capacitor device.

[0032] In summary, the present invention provides a three-dimensional packaged chip and a manufacturing method thereof, which adopts a system-level packaging structure, and chips with multiple functions are concentrated in one package, so that the system is more integrated and smaller in size. And an advanced three-dimensional core particle structure is adopted to integrate capacitor devices in a three-dimensional direction, so as to ensure that the package size is smaller, the system is more integrated, and the device performance is more superior. Through chip bonding between chips, a large capacitor device is formed, and the entire system is the same size as the chip, with a smaller size and a lower thickness. Compared with surface-mount capacitors, the capacitor structure provided by the present application is closer to the device itself, which can better improve the performance of the device. At the same time, an electrode sheet of a capacitor device is formed on the bonding surface of two working chips, which greatly increases the area of ​​the capacitor device and improves the capacitance of the capacitor device. Further, the capacitor is designed to be tooth-shaped, which effectively increases the capacitor area and further improves the capacitance value, thereby greatly improving the system performance. Furthermore, the present application realizes three-dimensional docking on two active chips, and the chips are interconnected with each other to realize the function of the entire system. Therefore, relative to SIP packaging, this packaging structure has a reduced size and a better market prospect. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0034] Figure 1 It is a schematic diagram of the structure of the first chip in one embodiment of the present application.

[0035] Figure 2 It is a schematic diagram of the structure of the second chip in one embodiment of the present application.

[0036] Figure 3 It is a schematic diagram of a structure in which a recess is formed on a first chip in one embodiment of the present application.

[0037] Figure 4 It is a schematic diagram of a structure in which a convex portion is formed on a second chip in one embodiment of the present application.

[0038] Figure 5 It is a structural schematic diagram of forming a first metal layer on a concave portion of a first chip in one embodiment of the present application.

[0039] Figure 6 It is a schematic structural diagram of forming a second metal layer on the protrusion of the second chip in one embodiment of the present application.

[0040] Figure 7 It is a schematic diagram of the structure of bonding the first chip and the second chip in one embodiment of the present application.

[0041] Figure 8 It is a schematic diagram of the structure of packaging a first chip and a second chip in one embodiment of the present application.

[0042] Fig. 9 It is a schematic diagram of the structure in which the third chip and the fourth chip are integrated and packaged in one embodiment of the present application.

[0043] Description of labels:

[0044] 100, first chip; 101, through silicon via structure; 102, first input-output interface; 103, recess; 104, first metal layer; 1041, first capacitor metal layer; 1042, first contact metal layer; 105, insulating layer; 106, first connection metal layer; 107, protective layer; 1071, first protective layer; 1072, second protective layer; 200, second chip; 201, second input-output interface; 202, metal pad; 203, protrusion; 204, second metal layer; 2041, second capacitor metal layer; 2042, second contact metal layer; 205, second connection metal layer; 206, solder ball; 300, third chip; 400, fourth chip. DETAILED DESCRIPTION

[0045] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are given in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thoroughly and comprehensively understood.

[0046] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0047] In the description of the present invention, it should be understood that the orientations or positional relationships indicated by the terms "center", "upper", "lower", "front", "back", "left", "right", etc. are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance.

[0048] In some embodiments, when forming an integrated circuit, working modules of various functions are independently packaged to form independent working chips, and then the working chips and capacitor devices are laid flat on a circuit board, and the working chips and capacitors are interconnected through the circuit board to form a two-dimensional system on chip. As the integration of the system on chip continues to increase, more and more working chips need to be integrated on the circuit board. Therefore, in one embodiment of the present invention, a three-dimensional packaged chip is provided, and the working chips and capacitor devices are integrated in a three-dimensional direction, so that working chips with multiple functions are concentrated in one package, which can ensure that the package size is smaller, the system is more integrated, and the device performance is more superior.

[0049] See also Figure 8 and Fig. 9 As shown, in one embodiment of the present invention, the three-dimensional packaged chip provided by the present application includes two or more working chips and a capacitive device arranged between two of the working chips. Wherein. The working chips are stacked in the thickness direction thereof, and the capacitive device is integrated between the two working chips stacked in the thickness direction. In some embodiments of the present invention, the three-dimensional packaged chip includes a first chip 100, a second chip 200, a third chip 300 and a fourth chip 400 arranged in the thickness direction, and a capacitive device is arranged between the first chip 100 and the second chip 200 to form a complete three-dimensional three-dimensional packaged chip. In other embodiments, the three-dimensional packaged chip includes only a first chip 100 and a second chip 200, and a capacitive device arranged between the first chip 100 and the second chip 200. In other embodiments, the three-dimensional packaged chip may also include at least two first chips 100, at least two second chips 200, at least two third chips 300 and at least two fourth chips 400 arranged in the thickness direction.

[0050] It should be noted that the three-dimensional packaged chip in the present application includes two or more working chips, and the two or more working chips will be stacked in the thickness direction of the working chip to form a three-dimensional packaged chip. The present application does not limit the specific number of working chips in the three-dimensional packaged chip and the functions of the working chips. The role of each working chip can be the same or different, depending on whether the function of the three-dimensional packaged chip can be realized. Similarly, the present application does not limit the number of capacitors formed between two adjacent working chips. One capacitor can be formed between two working chips, or two or more capacitors can be formed between two working chips. It can be determined based on the capacitance of the required capacitor and the area occupied by the capacitor between the two working chips. Combined with Figure 8 and Fig. 9As shown, in the present invention, two working chips and four working chips are provided in the three-dimensional packaged chip for explanation, that is, in one embodiment, the three-dimensional packaged chip includes a first chip 100 and a second chip 200, and a capacitor device is formed between the first chip 100 and the second chip 200. In another embodiment, the three-dimensional packaged chip includes a first chip 100, a second chip 200, a third chip 300 and a fourth chip 400, and a capacitor device is formed between the first chip 100 and the second chip 200.

[0051] See also Figure 8 and Fig. 9 As shown, in the present invention, the first chip 100 is a memory chip, and the second chip 200 is a power chip. When the first chip 100 and the second chip 200 are bonded, a complete system can be formed. The third chip 300 and the fourth chip 400 are arranged on the side of the first chip 100 away from the second chip 200, and the third chip 300 and the fourth chip 400 can be memory chips, or they can be any type of chips such as a central processing unit chip, a communication chip, a sensor, etc. In some embodiments, on the side of the first chip 100 away from the second chip 200, a fifth chip and a sixth chip, etc. can also be arranged at the same layer or higher layer as the third chip 300 and the fourth chip 400.

[0052] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, a through silicon via (TSV) structure 101 is provided in the first chip 100 and the second chip 200, and the through silicon via structure 101 extends from the first surface of the first chip 100 and the second chip 200 to the inside of the first chip 100 and the second chip 200. Among them, the first surface and the second surface of the first chip 100 and the second chip 200 are two opposite surfaces of the first chip 100 and the second chip 200 in the thickness direction, and an input and output interface is provided on the first surface of the first chip 100 and the second chip 200, and the input and output interface is connected to the through silicon via structure 101, which is the input interface or output interface of the first chip 100 and the second chip 200 signal. Therefore, the first surface of the working chip can be used as the front of the chip, and the second surface of the chip is used as the back of the working chip.

[0053] See also Figure 1 and Figure 2As shown, in one embodiment of the present invention, the through silicon via structure 101 extends from the first surface of the first chip 100 and the second chip 200 to the inside of the first chip 100 and the second chip 200. When forming the through silicon via structure 101 in the first chip 100 and the second chip 200, the through silicon via can be formed in the first chip 100 and the second chip 200 first. The present invention does not limit the depth of the through silicon via, which is specifically based on the effective working area through the first chip 100 and the second chip 200. In this embodiment, the depth of the through silicon via refers to the depth of the contact hole buried in the first chip 100 and the second chip 200. Specifically, the through silicon via can be formed in the first chip 100 and the second chip 200 from the first surface of the first chip 100 and the second chip 200 by means of etching process, and the through silicon via passes through the effective working area of ​​the first chip 100. Among them, all semiconductor devices in the first chip 100 and the second chip 200 are concentrated in the effective working area. After forming the TSV, a conductive material, such as a metal material such as copper, aluminum, gold, or an alloy of two or three of these metal materials, is deposited in the TSV to form a TSV structure 101 .

[0054] It should be noted that the working chip includes a substrate and semiconductor devices disposed on the substrate, wherein the semiconductor devices are electrically connected to each other. When forming a through silicon via, the through silicon via passes through the substrate of the working chip, but does not damage the semiconductor devices in the effective working area.

[0055] See also Figure 1 and Figure 2 As shown, in one embodiment of the present invention, after forming the through silicon via structure 101, an organic material, metal or an organic composite material such as polyester, glass fiber or ceramic material may be disposed at the position of the through silicon via structure 101 to form an input-output interface. The input-output interface formed on the surface of the first chip 100 is the first input-output interface 102, and the input-output interface formed on the surface of the second chip 200 is the second input-output interface 201.

[0056] See also Figure 2 As shown, in one embodiment of the present invention, after the input-output interface is formed, a metal pad 202 is formed on the first surface of the second chip 200. Specifically, after the second input-output interface 201 is formed on the surface of the second chip 200, a conductive metal material, such as copper, aluminum, gold or an alloy of two or three of these metal materials, can be deposited on the second input-output interface 201 to form the metal pad 202.

[0057] See also Figures 1 to 4As shown, in one embodiment of the present invention, after forming a first input-output interface 102 on the first surface of the first chip 100, and forming a second input-output interface 201 and a metal pad 202 on the first surface of the second chip 200, the second surfaces of the first chip 100 and the second chip 200 are thinned until the through silicon via structure 101 is exposed from the second surfaces of the first chip 100 and the second chip 200. Specifically, the second surfaces of the first chip 100 and the second chip 200 can be polished by a chemical mechanical polishing (CMP) method to thin the first chip 100 and the second chip 200.

[0058] Please note that, see Figures 1 to 4 As shown, thinning the first chip 100 and the second chip 200 also thins the substrates in the first chip 100 and the second chip 200. After thinning, the first chip 100 and the second chip 200 retain a complete effective working area, that is, the thinning does not cause any damage to the semiconductor devices and their connections in the first chip 100 and the second chip 200. After thinning the first chip 100 and the second chip 200, a temporary carrier (not shown in the figure) is set on the first surface of the first chip 100 and the second chip 200 to enhance the mechanical strength of the first chip 100 and the second chip 200. After the first chip 100 and the second chip 200 are bonded, the temporary carrier is removed.

[0059] See also Figures 1 to 4 As shown, in one embodiment of the present invention, after the second surfaces of the first chip 100 and the second chip 200 are thinned, the second surfaces of the first chip 100 and the second chip 200 are etched to form a recess 103 on the second surface of the first chip 100, and a protrusion 203 on the second surface of the second chip 200, and the recess 103 on the second surface of the first chip 100 and the protrusion 203 on the second surface of the second chip 200 are correspondingly nested.

[0060] See also Figures 1 to 4 As shown, in one embodiment of the present invention, when etching the second surface of the first chip 100 and the second chip 200, the first chip 100 and the second chip 200 can be etched according to the materials of the first chip 100 and the second chip 200. In some embodiments, the substrate of the second surface of the first chip 100 and the second chip 200 is, for example, a silicon substrate, and hydrogen fluoride (HF) can be used to dry-etch the first chip 100 and the second chip 200. The first chip 100 and the second chip 200 can also be wet-etched using solutions such as hydrofluoric acid (HF) or nitric acid (HNO3). In other embodiments, the substrate of the first chip 100 and the second chip 200 can also be a substrate of other materials, and etching can be performed according to the specific materials of the first chip 100 and the second chip 200.

[0061] See also Figure 3 to Figure 4 As shown, in one embodiment of the present invention, on the second surface of the first chip 100, the recess 103 formed is located between adjacent through silicon via structures 101, and the recess 103 between the multiple through silicon via structures 101 forms a tooth-like structure. On the second surface of the second chip 200, the protrusion 203 formed is located between adjacent through silicon via structures 101, and the protrusion 203 between the multiple through silicon vias forms a tooth-like structure. The present application does not specifically limit the positions of the recess 103 on the second surface of the first chip 100 and the protrusion 203 on the second surface of the second chip 200, so that the recess 103 on the second surface of the first chip 100 and the protrusion 203 on the second surface of the second chip 200 can be arranged in alignment and nested, that is, when the first chip 100 and the second chip 200 are bonded, the protrusion 203 on the second surface of the second chip 200 is nested in the recess 103 on the second surface of the first chip 100.

[0062] It should be noted that if Figure 3 to Figure 4 As shown, the concave portion 103 and the convex portion 202 do not need to be disposed between every two adjacent TSV structures 101. The concave portion 103 or the convex portion 202 may be disposed between the TSV structures 101 according to specific requirements, so that there is a spacing between the concave portion 103 or the convex portion 202 and the TSV structure 101.

[0063] Combination Figures 5 and 6 As shown, in the subsequent process of the present invention, a metal layer will be deposited on the concave portion 103 on the second surface of the first chip 100 and the convex portion 203 on the second surface of the second chip 200, thereby forming two electrode plates of the capacitor device. Therefore, the surface area of ​​the concave portion 103 on the second surface of the first chip 100 and the convex portion 203 on the second surface of the second chip 200 is related to the capacitance value of the formed capacitor device. In order to match the capacitance value of the formed capacitor device, the number of the concave portion 103 on the second surface of the first chip 100 and the convex portion 203 on the second surface of the second chip 200 can be adaptively adjusted. In some embodiments, a concave portion 103 is set between two adjacent through silicon via structures 101 on the second surface of the first chip 100, and a convex portion 203 is set between two adjacent through silicon via structures 101 on the second surface of the second chip 200. In other embodiments, two, three or more concave portions 103 are provided between two adjacent TSV structures 101 on the second surface of the first chip 100, and two, three or more convex portions 203 are provided between two adjacent TSV structures 101 on the second surface of the second chip 200. By increasing the number of concave portions 103 and convex portions 203 between two adjacent TSV structures 101, the surface area of ​​the second surface of the first chip 100 and the second chip 200 can be increased, thereby increasing the area size of the two electrode plates of the capacitor device and changing the capacitance of the capacitor device.

[0064] See also Figure 3 to Figure 4 As shown, the present application does not limit the shape of the concave portion 103 on the second surface of the first chip 100 and the convex portion 203 on the second surface of the second chip 200. In some embodiments, the concave portion 103 on the second surface of the first chip 100 and the convex portion 203 on the second surface of the second chip 200 are arranged in a rectangular shape. In other embodiments, the concave portion 103 on the second surface of the first chip 100 can be arranged in a pentagon, hexagon, or a rectangle, pentagon, hexagon, etc. with rounded corners, and the convex portion 203 on the second surface of the second chip 200 is correspondingly arranged in a pentagon, hexagon, or a rectangle, pentagon, hexagon, etc. with rounded corners. After the metal layer and the insulating layer 105 are deposited on the second surface of the first chip 100 and the second surface of the second chip 200, the second surface of the first chip 100 and the second surface of the second chip 200 can be seamlessly bonded.

[0065] See also Figures 3 to 6 As shown, in one embodiment of the present invention, after a concave portion 103 is formed on the second surface of the first chip 100 and a convex portion 203 is formed on the second surface of the second chip 200, a conductive metal material is deposited on the second surface of the first chip 100 to form a first metal layer 104. A conductive metal material is deposited on the second surface of the second chip 200 to form a second metal layer 204. The first metal layer 104 covers the concave portion 103 on the second surface of the first chip 100, and the second metal layer 204 covers the convex portion 203 on the second surface of the second chip 200. The conductive metal material is, for example, a metal material such as copper, aluminum, gold, or an alloy of two or three of these metal materials.

[0066] See also Figure 5 and Figure 6 As shown, in one embodiment of the present invention, the first metal layer 104 includes a first capacitor metal layer 1041 and a first contact metal layer 1042. The second metal layer 204 includes a second capacitor metal layer 2041 and a second contact metal layer 2042. The first capacitor metal layer 1041 covers the concave portion 103 of the second surface of the first chip 100, and the second capacitor metal layer 2041 covers the convex portion 203 of the second surface of the second chip 200. The first contact metal layer 1042 is arranged on both sides of the first capacitor metal layer 1041, and has a spacing with the first capacitor metal layer 1041. The second contact metal layer 2042 is arranged on both sides of the second capacitor metal layer 2041, and has a spacing with the second capacitor metal layer 2041. The first contact metal layer 1042 is connected to the silicon through hole structure 101 in the first chip 100, and the second contact metal layer 2042 is connected to the silicon through hole structure 101 in the second chip 200, and the transmission of signals is realized after the first chip 100 and the second chip 200 are bonded.

[0067] See also Figure 5 and Figure 6 As shown, in one embodiment of the present invention, the first capacitor metal layer 1041 and the second capacitor metal layer 2041 are arranged in alignment, and the first contact metal layer 1042 and the second contact metal layer 2042 are arranged in alignment. And the thickness of the first contact metal layer 1042 is greater than the thickness of the first capacitor metal layer 1041, and the thickness of the second contact metal layer 2042 is greater than the thickness of the second capacitor metal layer 2041. More specifically, the sum of the thickness of the first contact metal layer 1042 and the second contact metal layer 2042 is equal to the sum of the thickness of the first capacitor metal layer 1041, the second capacitor metal layer 2041, and the subsequent filling of the insulating layer 105 between the first capacitor metal layer 1041 and the second capacitor metal layer 2041. The thickness of the insulating layer 105 is determined by the capacity of the capacitor device to be formed. In one embodiment of the present invention, the thickness of the first capacitor metal layer 1041 and the second capacitor metal layer 2041 is, for example, 2um to 5um, specifically, for example, 3um, 4um or 5um. The thickness of the first contact metal layer 1042 and the second contact metal layer 2042 is, for example, 8 um to 15 um, specifically, 10 um, 11 um, or 13 um.

[0068] See also Figure 5 and Figure 6 As shown, in one embodiment of the present invention, after the first chip 100 and the second chip 200 are bonded, the first contact metal layer 1042 and the second contact metal layer 2042 are connected, and the first capacitor metal layer 1041 and the second capacitor metal layer 2041 correspond in position. That is, after the first chip 100 and the second chip 200 are bonded, in the thickness direction of the first chip 100 and the second chip 200, the first contact metal layer 1042 and the second contact metal layer 2042 are aligned, and the first capacitor metal layer 1041 and the second capacitor metal layer 2041 are aligned. After the first chip 100 and the second chip 200 are bonded, the connection between the first contact metal layer 1042 and the second contact metal layer 2042 realizes the bonding and signal transmission between the first chip 100 and the second chip 200. The first capacitor metal layer 1041 forms one electrode plate of the capacitor device, and the second capacitor metal layer 2041 forms another electrode plate of the capacitor device.

[0069] See also Figure 5 and Figure 6As shown, in one embodiment of the present invention, the first metal layer 104 includes a first capacitor metal layer 1041 and two first contact metal layers 1042 arranged on both sides of the first capacitor metal layer 1041. The second metal layer 204 includes a second capacitor metal layer 2041 and two second contact metal layers 2042 arranged on both sides of the second capacitor metal layer 2041. At this time, a capacitor device can be formed in a subsequent process. In some other embodiments of the present invention, the first metal layer 104 includes at least two first capacitor metal layers 1041, at least two first capacitor metal layers 1041 are tiled on the second surface of the first chip 100, each first capacitor metal layer 1041 covers at least one recess 103, and two adjacent first capacitor metal layers 1041 are provided with a gap. Correspondingly, the second metal layer 204 includes at least two second capacitor metal layers 2041, at least two second capacitor metal layers 2041 are tiled on the second surface of the second chip 200, at least two second capacitor metal layers 2041 are tiled on the second surface of the second chip 200, each second capacitor metal layer 2041 covers at least one convex portion 203, and two adjacent second capacitor metal layers 2041 are provided with intervals. In other embodiments of the present invention, the first metal layer 104 includes a plurality of first contact metal layers 1042, and the second metal layer 204 includes a plurality of second contact metal layers 2042. A plurality of first contact metal layers 1042 are distributed on the second surface of the first chip 100, and a plurality of second metal layers 204 are distributed on the second surface of the second chip 200. After the first chip 100 and the second chip 200 are bonded, each first contact metal layer 1042 is connected to a second contact metal layer 2042. At this time, the number of capacitor devices formed is equal to the number of capacitor metal layers. Every two first capacitor metal layers 1041 and second capacitor metal layers 1042 arranged in opposite positions and the insulating layer 107 arranged between the first capacitor metal layer 1041 and the second capacitor metal layer 1042 form a capacitor device.

[0070] See also Figures 5 to 7As shown, in one embodiment of the present invention, after forming a first metal layer 104 on the second surface of the first chip 100 and forming a second metal layer 204 on the second surface of the second chip 200, the first chip 100 and the second chip 200 are bonded. When bonding the first chip 100 and the second chip 200, an insulating material is filled between the first metal layer 104 and the second metal layer 204, and between the first chip 100 and the second chip 200, to form an insulating layer 105. The material of the insulating layer 105 is a thermoplastic profile with a high dielectric constant, such as ABF (Ajinomoto Build-up Film) material, chip low filling glue, etc. The insulating layer 105 with a high dielectric constant can isolate the two electrode sheets of the capacitor device, and then cooperate with the first metal layer 104 and the second metal layer 204 to form a capacitor device. When the insulating layer 105 is disposed between the first chip 100 and the second chip 200, the thermoplastic profile with a high dielectric constant may be heated first to make it fluid, and then the thermoplastic profile may be used to fill the gap between the first chip 100 and the second chip 200. After the gap between the first chip 100 and the second chip 200 is filled, the thermoplastic profile is cooled and solidified to form the insulating layer 105.

[0071] See also Figure 7 As shown, in one embodiment of the present invention, after the first chip 100 and the second chip 200 are bonded, the tooth-shaped structure formed by the concave portion 103 on the second surface of the first chip 100 and the tooth-shaped structure formed by the convex portion 203 on the second surface of the second chip 200 are aligned and nested. The insulating layer 105 fills the gap between the first capacitor metal layer 1041 and the second capacitor metal layer 2041 to form a capacitor device. At the same time, the first contact metal layer 1042 and the second contact metal layer 2042 are connected, and the insulating layer 105 fills the gap on both sides of the first contact metal layer 1042 and the second contact metal layer 2042, playing a supporting role between the first chip 100 and the second chip 200.

[0072] See also Figures 7 and 8As shown, in one embodiment of the present invention, after forming the capacitor device, a conductive metal material, such as copper, aluminum, gold or an alloy of two or three of these metal materials, is deposited on the first surface of the first chip 100 to form a first connection metal layer 106. A conductive metal material, such as copper, aluminum, gold or an alloy of two or three of these metal materials, is deposited on the first surface of the second chip 200 to form a second connection metal layer 205. The first connection metal layer 106 covers all or part of the first input-output interface 102 on the first surface of the first chip 100, and the second connection metal layer 205 covers the metal pad 202 on the first surface of the second chip 200. The first connection metal layer 106 leads out the signal of the first chip 100, and the second connection metal layer 205 leads out the signal of the second chip 200, so that the signals are connected to each other.

[0073] See also Figure 8 As shown, in one embodiment of the present invention, after forming the first connection metal layer 106 on the first surface of the first chip 100, an insulating material is deposited on the first connection metal layer 106 to form a protective layer 107. After forming the second connection metal layer 205 on the first surface of the second chip 200, a solder ball 206 can be formed on the second connection metal layer 205 by reflow soldering. Then, the packaging of the first chip 100 and the second chip 200 is completed. Among them, the material of the protective layer 107 can be a common epoxy molding compound, silicone gel or plastic packaging material.

[0074] See also Figures 7 to 9 As shown, in another embodiment of the present invention, after forming the capacitor device, the third chip 300 and the fourth chip 400 are welded on the first surface of the first chip 100, and an insulating material is deposited on the third chip 300 and the fourth chip 400 to form a protective layer 107. A solder ball 206 is formed on the metal pad 202 on the first surface of the second chip 200 by reflow soldering. Then the packaging of the first chip 100, the second chip 200, the third chip 300 and the fourth chip 400 is completed. In this embodiment, the protective layer 107 includes a first protective layer 1071 and a second protective layer 1072. The first protective layer 1071 is arranged between the third chip 300 and the first chip 100, and between the fourth chip 400 and the first chip 100, filling the gap between the third chip 300, the fourth chip 400 and the first chip 100. The second protective layer 1072 is arranged on the third chip 300 and the fourth chip 400, covering the third chip 300 and the fourth chip 400. In this embodiment, the particle size of the first protective layer 1071 is smaller than that of the second protective layer 1072. The first protective layer 1071 is made of, for example, a resin material with a smaller particle size, and the second protective layer 1072 is made of, for example, an organic plastic material with a larger particle size.

[0075] In summary, the present invention provides a three-dimensional packaged chip and a manufacturing method thereof, wherein a first chip and a second chip with different functions or the same function are integrated in the chip thickness direction, and at least one recess is formed on the surface of the first chip close to the second chip, and at least one recess is formed on the surface of the second chip close to the first chip, and the protrusions are aligned and nested with the recesses. Afterwards, a first metal layer is laid on the surface of the first chip close to the second chip, and the first metal layer covers the recesses; a second metal layer is laid on the surface of the second chip close to the first chip, and the second metal layer covers the protrusions. Finally, the first chip and the second chip are bonded, and an insulating layer is provided between the first metal layer and the second metal layer, and the first metal layer, the insulating layer and the second metal layer form a capacitor device. Capacitor devices are integrated in the three-dimensional packaged chip, and the capacitor structure is placed close to the power supply network.

[0076] The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims

1. A three-dimensional packaged chip, characterized in that: At least: A first chip and a second chip, wherein the second chip is bonded to the first chip; At least one recessed portion is disposed on a surface of the first chip close to the second chip; At least one concave portion is arranged on a surface of the second chip close to the first chip, and the convex portion is aligned and nested with the concave portion; A first metal layer is laid on a surface of the first chip close to the second chip, and the first metal layer covers the concave portion; A second metal layer is laid on a surface of the second chip close to the first chip, and the second metal layer covers the protrusion; as well as The insulating layer is disposed between the first metal layer and the second metal layer, and the first metal layer, the insulating layer and the second metal layer form a capacitor device.

2. The three-dimensional packaged chip according to claim 1, characterized in that: A through silicon via structure is provided in the first chip and the second chip.

3. The three-dimensional packaged chip according to claim 2, characterized in that: A concave portion is provided on a surface of the first chip close to the second chip and between two adjacent through silicon via structures; a convex portion is provided on a surface of the second chip close to the first chip and between two adjacent through silicon via structures.

4. The three-dimensional packaged chip according to claim 2, characterized in that: Two or more recesses are provided on a surface of the first chip close to the second chip and between two adjacent through silicon via structures; two or more protrusions are provided on a surface of the second chip close to the first chip and between two adjacent through silicon via structures.

5. The three-dimensional packaged chip according to claim 1, characterized in that: The concave portion and the convex portion are arranged in a rectangular, pentagonal, hexagonal shape or in a rectangular, pentagonal, or hexagonal shape with rounded corners.

6. The three-dimensional packaged chip according to claim 1, characterized in that: The first metal layer includes a first capacitor metal layer, which covers the concave portion; the second metal layer includes a second capacitor metal layer, which covers the convex portion, and the second capacitor metal layer and the first capacitor metal layer are arranged in alignment.

7. The three-dimensional packaged chip according to claim 6, characterized in that: The first metal layer includes a first contact metal layer, which is arranged on both sides of the first capacitor metal layer; the second metal layer includes a second contact metal layer, which is arranged on both sides of the second capacitor metal layer, and the second contact metal layer and the first contact metal layer are arranged in alignment.

8. The three-dimensional packaged chip according to claim 7, characterized in that: The sum of the thicknesses of the first contact metal layer and the second contact metal layer is equal to the sum of the thicknesses of the first capacitor metal, the second capacitor metal layer and the insulating layer.

9. The three-dimensional packaged chip according to claim 7, characterized in that: The first metal layer includes one first capacitor metal layer and two first contact metal layers, and the second metal layer includes one second capacitor metal layer and two second contact metal layers.

10. The three-dimensional packaged chip according to claim 7, characterized in that: The first metal layer includes at least two first capacitor metal layers, at least two of the first capacitor metal layers are laid on the surface of the first chip, and each of the first capacitor metal layers covers one of the recessed portions, and a gap is set between two adjacent first capacitor metal layers; the second metal layer includes at least two second capacitor metal layers, at least two of the second capacitor metal layers are laid on the surface of the second chip, and each of the second capacitor metal layers covers one of the protruding portions, and a gap is set between two adjacent second capacitor metal layers.

11. The three-dimensional packaged chip according to claim 1, characterized in that: The three-dimensional packaged chip further comprises: A third chip is disposed on a side of the first chip away from the second chip; and The fourth chip is arranged on a side of the first chip away from the second chip, and the second chip and the third chip are arranged side by side.

12. The three-dimensional packaged chip according to claim 1, characterized in that: The second chip is a power chip.

13. A method for manufacturing a three-dimensional packaged chip, characterized in that: At least the following steps are included: providing a first chip and a second chip; Etching a surface of the first chip close to the second chip to form at least one concave portion; Etching the surface of the second chip close to the first chip to form at least one convex portion, wherein the convex portion is aligned and nested with the concave portion; Laying a first metal layer on a surface of the first chip close to the second chip, wherein the first metal layer covers the concave portion; Laying a second metal layer on the surface of the second chip close to the first chip, wherein the second metal layer covers the protrusion; The second chip is bonded to the first chip, and an insulating layer is disposed between the first metal layer and the second metal layer, and the first metal layer, the insulating layer and the second metal layer form a capacitor device.

Images